Manufacturing method for semiconductor device and semiconductor device

Abstract

To suppress PID during the manufacturing of a semiconductor device.SOLUTION: A manufacturing method for a semiconductor device includes the steps of forming a gate insulating film on the surface of a semiconductor substrate, forming wiring made of a conductor electrically connected to the gate insulating film, forming a first insulating film that covers the wiring using a film formation method that does not use plasma, and, after forming the first insulating film, forming a second insulating film that covers the first insulating film by plasma CVD.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed technology relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] The following techniques are known as techniques related to manufacturing methods of semiconductor devices. For example, Patent Document 1 describes a manufacturing method of a semiconductor device, which includes the steps of forming a first insulating film on a semiconductor substrate, forming a metal plug in the first insulating film to connect to the semiconductor substrate, forming a second insulating film on the first insulating film with the metal plug formed therein, forming a third insulating film on the second insulating film, and forming an upper wiring layer on or in the third insulating film, wherein the step of forming the second insulating film uses a deposition method that does not use high-density plasma, and the step of forming the third insulating film uses a deposition method that uses high-density plasma. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-39964 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, in a semiconductor device including wiring connected to a gate insulating film via a gate electrode and contacts, and an insulating film covering the wiring, if the insulating film covering the wiring is formed using HDP-CVD (High Density Plasma Chemical Vapor Deposition), charges in the plasma flow into the gate insulating film via the wiring, contacts, and gate electrode and accumulate in the gate insulating film. Excessive charge on the gate insulating film can degrade its characteristics and, in the worst case, can even destroy the gate insulating film. Damage to insulating films caused by plasma used in semiconductor device manufacturing is called PID (Plasma Induced Damage), and is particularly problematic in recent miniaturized devices with extremely thin gate insulating films.

[0005] The disclosed technology has been made in view of the above points, and aims to suppress PID during the manufacture of semiconductor devices. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor device according to the disclosed technology includes the steps of forming a gate insulating film on a surface of a semiconductor substrate, forming wiring connected to the gate insulating film via a conductor, forming a first insulating film covering the wiring using a film formation technique that does not use plasma, and, after forming the first insulating film, forming a second insulating film covering the first insulating film by plasma CVD.

[0007] The semiconductor device according to the disclosed technique includes a gate insulating film provided on a surface of a semiconductor substrate, a wiring connected to the gate insulating film via a conductor, and a first insulating film covering the wiring. and a second insulating film covering the first insulating film. [Effects of the Invention]

[0008] According to the present invention, it is possible to suppress PID during the manufacture of semiconductor devices. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view showing an example of a configuration of a semiconductor device according to an embodiment of the disclosed technique; [Figure 2A] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technique. [Figure 2B] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technique. [Figure 2C] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technique. [Figure 2D] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technique. [Figure 2E]1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technique. [Figure 2F] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technique. [Figure 2G] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technique. [Figure 3A] FIG. 10 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a comparative example. [Figure 3B] FIG. 10 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a comparative example. [Figure 4] 1 is a cross-sectional view showing a state during the formation of an interlayer insulating film in a semiconductor device 1 according to an embodiment of the disclosed technique. [Figure 5A] 10A to 10C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to another embodiment of the disclosed technique. [Figure 5B] 10A to 10C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to another embodiment of the disclosed technique. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the disclosed technology will be described with reference to the drawings. In each drawing, substantially the same or equivalent components or parts are denoted by the same reference numerals.

[0011] [First embodiment] 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to an embodiment of the disclosed technique. The semiconductor device 1 includes a semiconductor substrate 10, a gate insulating film 11, a gate electrode 20, an underlying insulating film 12, contacts 13, wiring 14, a charge trapping insulating film 15, and an interlayer insulating film 16.

[0012] The semiconductor substrate 10 is made of a semiconductor such as silicon. The gate insulating film 11 is made of an insulator such as SiO2 and is provided on the surface of the semiconductor substrate 10. The gate electrode 20 is made of a conductor such as polysilicon and covers the gate insulating film 11. The base insulating film 12 is made of an insulator such as NSG (Non-doped Silicate Glass) and covers the gate electrode 20. The contact 13 is made of a conductor such as tungsten and penetrates the base insulating film 12 to reach the gate electrode 20. The wiring 14 is made of a conductor such as aluminum and is provided on the surface of the base insulating film 12 so as to be connected to the contact 13. In other words, the wiring 14 is connected to the gate insulating film 11 via conductors including the contact 13 and the gate electrode 20.

[0013] The charge trapping insulating film 15 is made of an insulator such as SiO2 and covers the upper and side surfaces of the wiring 14 and the surface of the base insulating film 12. The charge trapping insulating film 15 serves to capture charges in the plasma irradiated when forming the interlayer insulating film 16. The charge trapping insulating film 15 is formed using a film formation method that does not use plasma. The charge trapping insulating film 15 can be formed, for example, by low-pressure CVD (LP-CVD) using TEOS (Si(OC2H5)4) and O3. The charge trapping insulating film 15 is an example of a "first insulating film" in the disclosed technology.

[0014] The interlayer insulating film 16 is made of an insulator such as SiO2 and covers the charge trapping insulating film 15. The interlayer insulating film 16 is formed using the HDP-CVD method. The charge trapping insulating film 15 is formed to a thickness that does not expose the top and side surfaces of the wiring 14. The thickness of the charge trapping insulating film 15 is thinner than the thickness of the interlayer insulating film 16. The interlayer insulating film 16 is an example of a "second insulating film" in the disclosed technology.

[0015] The following describes a method for manufacturing the semiconductor device 1. Figures 2A to 2G are cross-sectional views showing an example of a method for manufacturing the semiconductor device 1.

[0016] First, a semiconductor substrate 10 such as a silicon substrate is prepared (FIG. 2A). Next, a gate insulating film 11 made of an insulator such as SiO2 is formed on the surface of the semiconductor substrate 10 using, for example, thermal oxidation (FIG. 2B). Next, a gate electrode 20 made of a conductor such as polysilicon is formed on the surface of the gate insulating film 11 using CVD (FIG. 2B). Next, a base insulating film 12 made of an insulator such as NSG is formed on the surface of the gate electrode 20 using CVD (FIG. 2C). Next, contact holes (not shown) reaching the gate electrode 20 are formed at predetermined positions in the base insulating film 12 by dry etching. Next, a conductor such as tungsten is filled into the contact holes using CVD, forming contacts 13 that penetrate the base insulating film 12 and reach the gate electrode 20 (FIG. 2D).

[0017] Next, a conductive film made of a conductor such as Al is formed on the surface of the base insulating film by sputtering or vapor deposition, and this conductive film is patterned using photolithography to form wiring 14 connected to contacts 13 on the surface of base insulating film 12 (FIG. 2E). Wiring 14 is connected to gate insulating film 11 via contact 13 and gate electrode 20.

[0018] Next, a plasma-free film formation method is used to form a charge trapping insulating film 15 made of an insulator such as SiO2, which covers the wiring 14. The top and side surfaces of the wiring 14 and the surface of the base insulating film 12 are covered with the charge trapping insulating film 15 (FIG. 2F). The charge trapping insulating film 15 can be formed, for example, by low-pressure CVD (LP-CVD) using TEOS and O3.

[0019] Next, an interlayer insulating film 16 made of an insulator such as SiO2 is formed by HDP-CVD to cover the charge trapping insulating film 15 (FIG. 2G).

[0020] 3A and 3B are cross-sectional views showing an example of the configuration of a semiconductor device 1X according to a comparative example. The semiconductor device 1X according to the comparative example differs from the semiconductor device 1 according to the embodiment of the disclosed technique in that it does not have a charge trapping insulating film. FIG. 3A shows a state in the middle of forming an interlayer insulating film 16 using the HDP-CVD method, and FIG. 3B shows a state after the formation of the interlayer insulating film 16 has been completed.

[0021] In the HDP-CVD method, high-density plasma is irradiated. In the semiconductor device 1X according to the comparative example, the wiring 14 is exposed during the formation of the interlayer insulating film 16, so charges in the plasma flow into the gate insulating film 11 via the wiring 14, the contact 13, and the gate electrode 20, and are accumulated in the gate insulating film 11. As shown in FIG. 3B, the charges that flowed into the gate insulating film 11 remain in the gate insulating film 11 even after the plasma irradiation is completed. If the amount of charge on the gate insulating film 11 becomes excessive, the characteristics will deteriorate, and in the worst case, the gate insulating film 11 may be destroyed.

[0022] 4 is a cross-sectional view showing a state during the formation of the interlayer insulating film 16 in the semiconductor device 1 according to the embodiment of the disclosed technique. According to the semiconductor device 1 according to the embodiment of the disclosed technique, charges in the plasma irradiated when forming the interlayer insulating film 16 are trapped by the charge trap insulating film 15 and accumulated in the charge trap insulating film 15. This makes it possible to prevent charges in the plasma from flowing into the gate insulating film 11 via the wiring 14, the contact 13, and the gate electrode 20 and accumulating in the gate insulating film 11. The charge trap insulating film 15 is formed by a film formation method that does not use plasma (for example, a low-pressure CVD method using TEOS and O3), so no charges flow into the gate insulating film 11 when forming the charge trap insulating film 15.

[0023] As described above, according to the semiconductor device 1 according to the embodiment of the disclosed technique, the accumulation of charge in the gate insulating film 11 due to the plasma used in the manufacturing process is suppressed, thereby making it possible to suppress PID such as characteristic degradation and destruction of the gate insulating film 11.

[0024] [Second embodiment] 5A and 5B are cross-sectional views showing an example of a method for manufacturing a semiconductor device 1 according to a second embodiment of the disclosed technique. The manufacturing method according to the second embodiment is the same as the manufacturing method according to the first embodiment up to the step of forming a charge trap insulating film 15 (FIG. 2F).

[0025] After the charge trapping insulating film 15 is formed, it is etched back by RIE (reactive ion etching). This removes the portion of the charge trapping insulating film 15 that covers the underlying insulating film 12 while leaving the portion that covers the top and side surfaces of the interconnects 14. That is, a structure is formed in which the charge trapping insulating film 15 covers the interconnects 14 in the form of sidewalls (FIG. 5A). The charge trapping insulating film 15 is etched back to a thickness that does not expose the surface of the interconnects 14. After the formation of the charge trapping insulating film 15, the ratio (T1:T2:T3) of the thickness T1 of the portion that covers the top surface of the interconnects 14, the thickness T2 of the portion that covers the surface of the underlying insulating film 12, and the thickness T3 of the portion that covers the side surfaces of the interconnects 14 is 10:8:4. Because RIE is anisotropic, it is possible to remove the portion of the charge trapping insulating film 15 that covers the underlying insulating film 12 while leaving the portion that covers the top and side surfaces of the interconnects 14.

[0026] After the etch-back process of the charge trapping insulating film 15 is completed, the interlayer insulating film 16 made of an insulator such as SiO 2 is formed to cover the charge trapping insulating film 15 using the HDP-CVD method (FIG. 5B).

[0027] According to the manufacturing method of the second embodiment, the charge trapping insulating film 15 covering the wiring 14 in a sidewall shape suppresses the inflow and accumulation of charges into the gate insulating film 11 due to plasma, making it possible to suppress PID such as characteristic degradation and destruction of the gate insulating film 11.

[0028] In narrow slot wiring where the spacing between the wirings 14 is narrow, it is difficult for the interlayer insulating film 16 to enter the region between the wirings 14, and there is a risk of voids occurring in this region. By forming a structure in which the charge trapping insulating film 15 covers the wirings 14 like a sidewall, it becomes easier for the interlayer insulating film 16 to enter the region between the wirings 14, and it becomes possible to reduce the risk of voids occurring in this region. [Explanation of symbols]

[0029] 1. 1X Semiconductor Device 10. Semiconductor substrate 11 Gate insulating film 12 Undercoat insulating film 13 Contact 14 Wiring 15 Charge trapping insulating film 16 Interlayer insulating film

Claims

1. forming a gate insulating film on a surface of a semiconductor substrate; forming wiring connected to the gate insulating film via a conductor; forming a first insulating film covering the wiring using a film formation method that does not use plasma; forming a second insulating film covering the first insulating film by plasma CVD after forming the first insulating film; A method for manufacturing a semiconductor device comprising:

2. The first insulating film is formed by a method using TEOS and O ３ It is a low pressure CVD method using The method of claim 1.

3. forming a gate electrode covering the gate insulating film before forming the wiring; forming a third insulating film covering the gate electrode; forming a contact made of a conductor that penetrates the third insulating film and reaches the gate electrode; Further comprising: The wiring is formed on the surface of the third insulating film so as to be connected to the contact. The method according to claim 1 or 2.

4. The method further includes a step of removing a portion of the first insulating film that covers the third insulating film while leaving a portion of the first insulating film that covers the top and side surfaces of the wiring, before forming the second insulating film. The method of claim 3.

5. a gate insulating film provided on a surface of a semiconductor substrate; a wiring connected to the gate insulating film via a conductor; a first insulating film covering the wiring; a second insulating film covering the first insulating film; A semiconductor device comprising:

6. the first insulating film is a film formed using a film formation method that does not use plasma, The second insulating film is a film formed by plasma CVD. The semiconductor device according to claim 5 .

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