Multilayer ceramic electronic component, manufacturing method thereof, circuit module, and electronic apparatus

Abstract

To provide a multilayer ceramic electronic component capable of making compatible improvement of connectivity between an internal electrode layer and an external electrode and improvement of reliability, and a method of manufacturing a multilayer ceramic electronic component.SOLUTION: A multilayer ceramic electronic component comprises: an element assembly including a plurality of dielectric layers laminated along a first axis and a plurality of internal electrode layers each disposed between the dielectric layers which are adjacent along the first axis; and a pair of external electrodes provided on a surface of the element assembly and electrically connected with the internal electrode layers. The dielectric layer contains a compound which is expressed by a general formula: ABO3-α (0≤α≤1) and has a perovskite structure. The internal electrode layer contains a first phase containing nickel and copper and a co-material. An interface between the first phase and the co-material includes a first segregation part where copper is segregated. A concentration of copper in the first segregation part is higher than a concentration of copper in the first phase, and the external electrode contains nickel.SELECTED DRAWING: Figure 14A

Description

[Technical Field]

[0001] The present disclosure relates to a multilayer ceramic electronic component, a manufacturing method thereof, a circuit module, and an electronic device. [Background technology]

[0002] Multilayer ceramic electronic components such as multilayer ceramic capacitors (MLCCs) are being developed for incorporation into a variety of electronic devices, including smartphones and personal computers. As electronic devices become more multifunctional and performant, and as batteries become larger in capacity, there is a growing demand for smaller, higher-capacity multilayer ceramic electronic components.

[0003] To increase the capacitance of ceramic electronic components, various measures have been taken, such as examining the material composition to increase the dielectric constant of the dielectric material used and thinning the dielectric layers. Another effective approach is to increase the number of layers by thinning the internal electrode layers. However, thinning the internal electrode layers can lead to over-sintering of the internal electrode layers, resulting in a decrease in the continuity ratio due to the difference in the densification temperature range between the dielectric layers and the internal electrode layers during the sintering process. This can lead to poor connectivity between the internal electrode layers and the external electrodes, potentially preventing the desired characteristics from being achieved.

[0004] Therefore, for example, Patent Document 1 discloses a multilayer capacitor that includes a main body including internal electrodes arranged alternately with dielectric layers, and external electrodes that are arranged on the main body and connected to the internal electrodes, where the internal electrodes include Ni crystal grains, ceramic distributed inside the Ni crystal grains, a first coating layer surrounding the Ni crystal grains, and a second coating layer surrounding the ceramic. The multilayer capacitor suppresses the external growth of the internal electrodes, and the coated ceramic present inside the Ni crystal grains suppresses the movement of Ni, thereby suppressing the spheroidization and breakage of the internal electrodes, thereby having little thickness variation despite its thin thickness and excellent connectivity.

[0005] Patent Document 2 also discloses that a ceramic electronic component can maintain connectivity between the internal electrode layers and the external electrodes, the ceramic electronic component comprising a laminated chip having a roughly rectangular parallelepiped shape in which a plurality of dielectric layers primarily composed of ceramic and a plurality of internal electrode layers primarily composed of Ni are alternately stacked and formed so that the plurality of internal electrode layers are alternately exposed on two opposing end faces of the roughly rectangular parallelepiped shape, and external electrodes provided on the two end faces and primarily composed of Ni, the plurality of internal electrode layers containing added metal elements other than Ni and common materials, and the concentration of the added metal elements being higher in the internal electrode layers than in the external electrodes. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2019-176117 [Patent Document 2] Japanese Patent Application Publication No. 2023-136776 Summary of the Invention [Problem to be solved by the invention]

[0007] In conventional multilayer ceramic electronic components, the common material is left in the internal electrode layers to delay sintering of the internal electrode layers and prevent over-sintering of the internal electrode layers even when sintered at the sintering temperature of the dielectric layers. This prevents a decrease in the continuity ratio of the internal electrode layers, thereby preventing a decrease in the connectivity between the internal electrode layers and the external electrodes. However, the remaining common material in the internal electrode layers increases the resistance of the internal electrode layers, resulting in a problem of reduced reliability.

[0008] An object of the present disclosure is to provide a multilayer ceramic electronic component and a method for manufacturing a multilayer ceramic electronic component that can achieve both improved connectivity between internal electrode layers and external electrodes and improved reliability. [Means for solving the problem]

[0009] According to one aspect of the present disclosure, there is provided an element body having a plurality of dielectric layers stacked along a first axis and a plurality of internal electrode layers respectively disposed between the dielectric layers adjacent to each other along the first axis, and a pair of external electrodes provided on a surface of the element body and electrically connected to the internal electrode layers, wherein the dielectric layers are represented by a general formula ABO 3-α The multilayer ceramic electronic component contains a compound having a perovskite structure represented by (0≦α≦1), the internal electrode layers contain a first phase containing nickel and copper and a common material, and have a first segregation portion where copper is segregated at the interface between the first phase and the common material, the copper concentration in the first segregation portion being higher than the copper concentration in the first phase, and the external electrodes contain nickel. [Effects of the Invention]

[0010] According to the present disclosure, it is possible to provide a multilayer ceramic electronic component and a method for manufacturing a multilayer ceramic electronic component that can achieve both improved connectivity between internal electrode layers and external electrodes and improved reliability. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a partial cross-sectional perspective view illustrating a multilayer ceramic capacitor according to one embodiment of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view illustrating a cross section taken along line AA in FIG. [Figure 3] FIG. 3 is a cross-sectional view illustrating a cross section taken along line BB in FIG. [Figure 4] FIG. 4 is a partial enlarged cross-sectional view of the dielectric layers, internal electrode layers, and oxide layers in region D of element body 10 in FIG. [Figure 5] FIG. 5 is an enlarged partial cross-sectional view of the dielectric layer and the internal electrode layer. [Figure 6A] FIG. 6A is an explanatory diagram of a method for measuring the copper concentration in the first segregation portion. [Figure 6B] FIG. 6B is an enlarged view of region A in FIG. 5, and is an explanatory view showing the measurement direction in measuring the copper concentration in the first segregation portion. [Figure 7A]FIG. 7A is an explanatory diagram of a method for measuring the copper concentration in the second segregation portion. [Figure 7B] FIG. 7B is an enlarged view of region B in FIG. 5, and is an explanatory view showing the measurement direction in measuring the copper concentration in the second segregation portion. [Figure 8] FIG. 8 is a flowchart of a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present disclosure. [Figure 9A] FIG. 9A is a diagram illustrating an internal electrode layer pattern forming step in a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present disclosure. [Figure 9B] FIG. 9B is a diagram illustrating a laminate forming step in the method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present disclosure. [Figure 10] 10 is a graph showing the results of elemental analysis by STEM in Example 1. The vertical axis represents the Cu concentration (at %) or the Ba concentration (at %), and the horizontal axis represents the measurement distance (nm). [Figure 11A] FIG. 11A is a trace of a BF-STEM image of the XZ plane of measurement sample 2 of Comparative Example 1. [Figure 11B] FIG. 11B is a trace of a BF-STEM image of the XZ plane of measurement sample 2 in Example 1. [Figure 11C] FIG. 11C is a trace of a BF-STEM image of the XZ plane of measurement sample 2 of Comparative Example 4. [Figure 12A] FIG. 12A is a diagram showing the frequency of the total area of ​​the common material in three layers obtained from a BF-STEM image of the internal electrode layer in the XZ plane of measurement sample 2 of Comparative Example 1. [Figure 12B] FIG. 12B is a diagram showing the frequency of the total area of ​​the common material in three layers obtained from the BF-STEM image of the internal electrode layer in the XZ plane of measurement sample 2 in Example 1. [Figure 12C] FIG. 12C is a diagram showing the frequency of the total area of ​​the common material in three layers obtained from a BF-STEM image of the internal electrode layer in the XZ plane of measurement sample 2 of comparative example 4. [Figure 13]FIG. 13 is a diagram showing the common material area ratio (%) in three layers obtained from BF-STEM images of the internal electrode layers in the XZ plane of measurement sample 2 of Example 1 and Comparative Examples 1 and 4. [Figure 14A] 14A is a diagram showing the results of the ratio (at%) of the number of Cu atoms when Ti is taken as 100 at% by semi-quantitative analysis using the glass standard material of Example 1. The vertical axis represents the ratio (at%) of the number of Cu atoms when Ti is taken as 100 at%, and the horizontal axis represents the distance (μm) from the internal electrode layer. [Figure 14B] 14B is a diagram showing the results of the ratio (at%) of the number of Au atoms when Ti is taken as 100 at% by semi-quantitative analysis using the glass standard material of Comparative Example 4. The vertical axis represents the ratio (at%) of the number of Au atoms when Ti is taken as 100 at%, and the horizontal axis represents the distance (μm) from the internal electrode layer. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present disclosure will be described in detail. Note that the embodiments are not limited by the following description and can be modified as appropriate within the scope of the present disclosure. In this specification, unless otherwise specified, the symbol "to" indicating a numerical range means that the numerical values ​​before and after it are included as the lower limit and upper limit.

[0013] Furthermore, in this specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals, and redundant description may be omitted. Furthermore, in this specification and drawings, the number, position, size, shape, etc. of each component are not limited to the embodiments of the present disclosure, and may be any number, position, size, shape, etc. that is preferable for implementing the embodiments of the present disclosure. Furthermore, the drawings appropriately show mutually orthogonal X-, Y-, and Z-axes. The X-, Y-, and Z-axes define a fixed coordinate system fixed with respect to a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component. If the outer shape of a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component, is approximately rectangular, the X-, Y-, and Z-axes may correspond to the length, width, and height of the capacitor.

[0014] [Multilayer ceramic electronic components] The multilayer ceramic electronic component of this embodiment includes an element body having a plurality of dielectric layers stacked along a first axis and a plurality of internal electrode layers respectively disposed between the dielectric layers adjacent to each other along the first axis, and a pair of external electrodes provided on a surface of the element body and electrically connected to the internal electrode layers. The multilayer ceramic electronic component of this embodiment may further include other layers or members as necessary.

[0015] (1) Structure of multilayer ceramic electronic components Fig. 1 is a partial cross-sectional perspective view illustrating a multilayer ceramic capacitor 100 according to one embodiment of the present disclosure. Figs. 2 and 3 are cross-sectional views illustrating the multilayer ceramic capacitor. Fig. 2 is a cross-sectional view illustrating a cross section taken along line AA in Fig. 1. Fig. 3 is a cross-sectional view illustrating a cross section taken along line BB in Fig. 1. Fig. 4 is a partial cross-sectional enlarged view of dielectric layers, internal electrode layers, and oxide layers in region D of the element body 10 in Fig. 3.

[0016] The multilayer ceramic capacitor 100 includes an element body 10 having a substantially rectangular parallelepiped shape, and a pair of external electrodes 20, namely, a first external electrode 20a and a second external electrode 20b.

[0017] In the element body 10, two opposing surfaces are referred to as the top surface and the bottom surface, and the four surfaces connecting the top surface and the bottom surface are referred to as side surfaces. Typically, when the multilayer ceramic capacitor 100 is mounted on a circuit board, the surface facing the board is referred to as the bottom surface, but this is not limited to this. In the example shown in FIGS. 1 to 3 , a first external electrode 20a and a second external electrode 20b are provided on two opposing side surfaces of the element body 10, namely, a first side surface 10a and a second side surface 10b. The first external electrode 20a extends from the first side surface 10a to four adjacent surfaces. The second external electrode 20b extends from the second side surface 10b to four adjacent surfaces. However, the first external electrode 20a and the second external electrode 20b are spaced apart from each other. The external electrodes may be provided on any surface of the element body 10, not limited to two opposing side surfaces.

[0018] The stacking direction in which the dielectric layers 11 and the internal electrode layers 12 are stacked is the first axis, and in Figures 1 to 3, the first axis, which is the stacking direction in which the dielectric layers 11 and the internal electrode layers 12 are stacked, is the Z axis, which is the direction in which the internal electrode layers face each other.

[0019] The axis perpendicular to the first axis, which is the stacking direction, is the second axis. In Figures 1 to 3, the second axis perpendicular to the first axis, which is the stacking direction, is the X-axis. The second axis is along the length direction of the element body 10, and is the axis along the direction in which the first side surface 10a and the second side surface 10b of the element body 10 face each other, and the direction in which the first external electrode 20a and the second external electrode 20b face each other.

[0020] The third axis is an axis perpendicular to the first axis, which is the stacking direction, and perpendicular to the second axis. The third axis is an axis along the width of the internal electrode layer 12. In Figures 1 to 3, the third axis, which is an axis perpendicular to the first axis, which is the stacking direction, and perpendicular to the second axis, is the Y axis, which is an axis along the direction in which the third side surface 10c and the fourth side surface 10d, which are the two side surfaces other than the first side surface 10a and the second side surface 10b, of the four side surfaces of the element body 10, face each other (see Figure 3). The X axis, Y axis, and Z axis are orthogonal to each other.

[0021] The stacking direction is not limited to the Z-axis direction and can be any direction. For example, the first axis, which is the stacking direction, may be the X-axis in the X-direction or the Y-axis in the Y-direction.

[0022] In the present application, for the purpose of explaining general embodiments, figures illustrating a specific embodiment may be used, and the content described using the coordinate axis system used in the embodiment is applied to the general embodiment by replacing it with a general coordinate system in which the stacking direction is the first axis. For example, the X-axis, Y-axis, and Z-axis used in Figures 1 to 3 in the specific embodiment, in which the stacking direction coincides with the Z-axis direction, can be replaced with the second axis, third axis, and first axis in the general embodiment.

[0023] The element body 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 are alternately stacked. The internal electrode layers 12 include a plurality of first internal electrode layers 12a and a plurality of second internal electrode layers 12b. The first internal electrode layers 12a and the second internal electrode layers 12b are alternately stacked. The edges of the first internal electrode layers 12a extend to the surface of the element body 10 on which the first external electrode 20a is provided, that is, the first side surface 10a in the examples of FIGS. 1 to 3. The edges of the second internal electrode layers 12b extend to the surface of the element body 10 on which the second external electrode 20b is provided, that is, the second side surface 10b in the examples of FIGS. 1 to 3. As a result, the first internal electrode layers 12a and the second internal electrode layers 12b are alternately electrically connected to the first external electrode 20a and the second external electrode 20b. Therefore, the multilayer ceramic capacitor 100 has a configuration in which capacitor units are stacked.

[0024] In addition, in a laminate of dielectric layers 11 and internal electrode layers 12, the internal electrode layers 12 are arranged as the outermost layers in the lamination direction, and the outer surfaces of the laminate in the lamination direction, i.e., the upper and lower surfaces in the examples of FIGS. 1 to 3, are covered with cover layers 13. The cover layers 13 are mainly composed of a ceramic material. For example, the composition of the cover layers 13 may be the same as or different from that of the dielectric layers 11. Note that the configuration is not limited to that shown in FIGS. 1 to 3 as long as the first internal electrode layers 12a and the second internal electrode layers 12b are exposed in different regions on the surface of the laminate and are conductive to different external electrodes. The different regions on the surface of the laminate may be respective surface regions on opposing surfaces of the laminate, respective surface regions on adjacent surfaces of the laminate, or different surface regions on the same surface of the laminate. As long as the different external electrodes are spaced apart from each other, the first internal electrode layers 12a and the second internal electrode layers 12b may extend from the surfaces exposed in the surface regions of the laminate to other surfaces.

[0025] Although details will be described later, the element body 10 preferably has second segregation portions 40 (see FIG. 4) in which copper is segregated at the interfaces between the dielectric layers 11 and the internal electrode layers 12. The second segregation portions 40 are not shown in FIGS. 1 to 3.

[0026] The size of the multilayer ceramic capacitor 100 is not particularly limited, and may be, for example, 0.25 mm long, 0.125 mm wide, and 0.125 mm high; 0.4 mm long, 0.2 mm wide, and 0.2 mm high; 0.6 mm long, 0.3 mm wide, and 0.3 mm high; 1.0 mm long, 0.5 mm wide, and 0.5 mm high; 3.2 mm long, 1.6 mm wide, and 1.6 mm high; or 4.5 mm long, 3.2 mm wide, and 2.5 mm high. However, the above-listed sizes of the multilayer ceramic capacitor 100 are merely examples, and the multilayer ceramic capacitor 100 is not limited to these sizes. The size of the multilayer ceramic capacitor 100 may be, for example, length > width ≥ height; width > length ≥ height; height > length ≥ width; or height > width ≥ length. Note that, for example, length represents the size in the X-axis direction, width represents the size in the Y-axis direction, and height represents the size in the Z-axis direction.

[0027] As described above, the multilayer ceramic capacitor 100 of this embodiment has a plurality of dielectric layers 11 stacked along the Z-axis, which is the first axis, a plurality of internal electrode layers 12 arranged between adjacent dielectric layers 11 along the first axis, and a pair of external electrodes 20 provided on the surface of the element body 10 and electrically connected to the internal electrode layers 12. The dielectric layers 11, the internal electrode layers 12, the second segregation portion 40, and the external electrodes 20 will be described below.

[0028] (2) Dielectric layer (2-1) Components contained in the dielectric layer The dielectric layer 11 is a compound represented by the general formula ABO 3-α It contains a compound having a perovskite structure represented by (0≦α≦1). The dielectric layer 11 may further contain an additive, if necessary.

[0029] <Compounds with perovskite structure> When a compound having a perovskite structure has a stoichiometric composition, α, which indicates the amount of deviation from the stoichiometric composition, is 0 and is represented by the general formula ABO3. In the compound having a perovskite structure represented by the general formula, α may be greater than 0 and equal to or less than 1. In other words, the compound having a perovskite structure represented by the general formula may have more oxygen deficiencies than the stoichiometric composition.

[0030] The general formula ABO 3-α In the general formula ABO, it is preferable that "A" is one or more elements selected from the group consisting of Ba (barium), Sr (strontium), Ca (calcium), and Mg (magnesium). 3-α In the general formula ABO, it is preferable that "B" is one or more elements selected from the group consisting of Ti (titanium), Zr (zirconium), and Hf (hafnium). 3-α In the compound having a perovskite structure represented by the formula (I), the elements "A" and "B" are located at the A site and the B site of the perovskite structure, respectively.

[0031] Specific examples of compounds having a perovskite structure include barium titanate (BaTiO3), calcium zirconate (CaZrO3), calcium titanate (CaTiO3), strontium titanate (SrTiO3), magnesium titanate (MgTiO3), and BaTiO3, which forms a perovskite structure. 1-x-y Ca x Sr y Ti 1-z Zr z O3 (0≦x≦1, 0≦y≦1, 0≦z≦1).

[0032] Ba 1-x-y Ca x Sr y Ti 1-z Zr zExamples of O3 include barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate, and barium calcium titanate zirconate. Note that any compound having a perovskite structure may contain oxygen deficiencies.

[0033] The dielectric layer 11 preferably contains barium titanate as a compound having a perovskite structure, as this compound has particularly excellent dielectric properties. The dielectric layer 11 may contain barium titanate as a main component, or may be composed solely of barium titanate. Barium titanate has excellent dielectric properties, such as an extremely high relative permittivity and low dielectric loss. Therefore, when the dielectric layer 11 contains barium titanate as a compound having a perovskite structure, the capacitance of the multilayer ceramic capacitor 100 can be increased.

[0034] In this specification, the term "main component" refers to the component that is contained in the largest proportion of the substance amount among the components contained.

[0035] Furthermore, the compound having a perovskite structure may be contained as a main component in the dielectric layer 11. For example, the dielectric layer 11 may contain 50 mol % or more, or 90 mol % or more of the compound having a perovskite structure, or may consist solely of the compound having a perovskite structure.

[0036] <Additives> The dielectric layer 11 may contain an additive as an optional component.

[0037] The additive contained in the dielectric layer 11 is not particularly limited, and examples thereof include zirconium (Zr), magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (scandium (Sc), cerium (Ce), neodymium (Nd), yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), Examples of the oxide include an oxide containing one or more elements selected from the group consisting of thulium (Tm), and ytterbium (Yb); or an oxide containing one or more elements selected from the group consisting of cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), and silicon (Si); or a glass containing one or more elements selected from the group consisting of cobalt, nickel, lithium, boron, sodium, potassium, and silicon.

[0038] (2-2) Average thickness of the dielectric layer The average thickness of the dielectric layers 11 is not particularly limited, but from the viewpoint of enabling an increase in capacitance by increasing the number of layers while miniaturizing the multilayer ceramic capacitor 100, it is preferably, for example, 1.0 μm or less, more preferably 0.8 μm or less, and even more preferably 0.5 μm or less. From the viewpoint of improving productivity and yield, the average thickness of the dielectric layers 11 is preferably, for example, 0.2 μm or more, and even more preferably 0.4 μm or more. The lower and upper limits of the average thickness of the dielectric layers 11 can be appropriately combined, and are preferably 0.2 μm or more and 1.0 μm or less, more preferably 0.2 μm or more and 0.8 μm or less, even more preferably 0.4 μm or more and 0.8 μm or less, and particularly preferably 0.4 μm or more and 0.5 μm or less.

[0039] 1 and 2, a sample is prepared by polishing a multilayer ceramic capacitor 100 along the Y axis up to the center along the Y axis, thereby exposing the XZ plane where the dielectric layers 11 and internal electrode layers 12 are laminated. Two dielectric layers 11 located in the center along the Z axis, which is the first axis, are selected from the exposed XZ plane, and two dielectric layers 11 located at the top and bottom along the Z axis, which is the first axis, are further selected. The selected dielectric layers 11 are selected from within the capacitive section 14.

[0040] Then, for the selected dielectric layer 11, the thickness is measured at the center along the X-axis, which is the second axis, and this is defined as the thickness of the dielectric layer 11. Using the same procedure, the thicknesses of the dielectric layers 11 are measured for all six selected dielectric layers 11, and the average value is calculated. This average value is defined as the average thickness of the dielectric layers 11 in the multilayer ceramic capacitor 100. The thickness of the dielectric layers 11 can be measured using, for example, an SEM (Scanning Electron Microscope) or an STEM (Scanning Transmission Electron Microscope). The dielectric layers 11 and the internal electrode layers 12 have different compositions, and therefore can be distinguished by differences in brightness when observed in electron beam images.

[0041] (3) Internal electrode layers 2, the region where the first internal electrode layer 12a connected to the first external electrode 20a and the second internal electrode layer 12b connected to the second external electrode 20b face each other is a region where capacitance is generated in the multilayer ceramic capacitor 100. Therefore, the region where capacitance is generated is referred to as a capacitance portion 14. In other words, the capacitance portion 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes 20 face each other.

[0042] The region where the first internal electrode layers 12a connected to the first external electrode 20a face each other in the stacking direction without the second internal electrode layer 12b connected to the second external electrode 20b intervening therebetween is referred to as the first end margin 15a. The region where the second internal electrode layers 12b connected to the second external electrode 20b face each other in the stacking direction without the first internal electrode layer 12a connected to the first external electrode 20a intervening therebetween is referred to as the second end margin 15b. The first end margin 15a and the second end margin 15b are regions where the internal electrode layers 12 connected to the same external electrode 20 face each other in the stacking direction without the internal electrode layer 12 connected to a different external electrode 20 intervening therebetween. The first end margin 15a and the second end margin 15b are regions where no capacitance is generated.

[0043] The side margin 16 is a region provided outside the capacitive section 14 in a direction along the Y-axis in the example of Fig. 3, which is a third axis perpendicular to the stacking direction and perpendicular to the second axis. In other words, the side margin 16 is an outer region adjacent to the capacitive section 14 when viewed from the stacking direction, and is an outer region adjacent to the capacitive section 14 on the side where the internal electrode layer 12 is not drawn out. The side margin 16 is also a region that does not generate electrical capacitance.

[0044] (3-1) Components contained in the internal electrode layer 5 is an enlarged partial cross-sectional view of the dielectric layer 11 and the internal electrode layer 12. The internal electrode layer 12 contains a first phase 17 containing nickel (Ni) and copper (Cu) and a common material 18, and has a first segregation portion 50 at the interface between the first phase 17 and the common material 18, where copper, which is a metal added to the internal electrode layer 12, is segregated. The copper concentration in the first segregation portion 50 is higher than the copper concentration in the first phase 17.

[0045] <First Phase> The first phase 17 of the internal electrode layer 12 preferably contains nickel as a main component, as this has excellent electrical properties and allows costs to be reduced.

[0046] The copper content in the first phase 17 of the internal electrode layer 12 is not particularly limited, but from the viewpoint of connectivity between the internal electrode layer 12 and the external electrode 20, the copper content relative to nickel is preferably 1 at% or more and 11 at% or less, and more preferably 1 at% or more and 6 at% or less. From the viewpoint of reliability, the copper content relative to nickel in the first phase 17 of the internal electrode layer 12 is preferably 1 at% or more and 11 at% or less, and more preferably 3 at% or more and 11 at% or less. From the viewpoint of overall connectivity and reliability between the internal electrode layer 12 and the external electrode 20, the copper content relative to nickel in the first phase 17 of the internal electrode layer 12 is further preferably 3 at% or more and 6.0 at% or less. The copper content relative to nickel is the atomic ratio of copper when nickel is 100 at%.

[0047] The first phase 17 of the internal electrode layer 12 may contain, in addition to nickel and copper, other components generally used in the internal electrode layers of multilayer ceramic capacitors. Examples of other components used in the internal electrode layers of multilayer ceramic capacitors include base metals such as tin (Sn) or alloys containing such base metals; precious metals such as platinum (Pt), palladium (Pd), silver (Ag), and gold (Au), or alloys containing such base metals. These may be used alone or in combination of two or more.

[0048] If the content of other components other than nickel and copper in the first phase 17 of the internal electrode layer 12 is large, it becomes difficult for copper in the internal electrode layer 12 to diffuse into the external electrode 20, which may result in poor connectivity and reliability between the internal electrode layer 12 and the external electrode 20. Therefore, in the first phase 17 of the internal electrode layer 12, the content of other components relative to nickel is preferably 0.5 at% or less, more preferably 0.1 at% or less, and even more preferably 0 at%. The content of other components relative to nickel is the atomic ratio of the other components when nickel is 100 at%.

[0049] The contents of nickel, copper, and other components in the first phase 17 of the internal electrode layer 12 can be confirmed by performing elemental analysis of the internal electrode layer 12 using various measuring instruments and calculating the atomic ratio of each component to all detected elements. Measuring instruments that can be used for elemental analysis include an energy dispersive X-ray spectrometer (EDS) or wavelength dispersive X-ray spectrometer (WDS) attached to a scanning electron microscope (SEM) or a scanning transmission electron microscope (STEM), an electron probe micro analyzer (EPMA), a laser irradiation inductively coupled plasma mass spectrometer (LA-ICP-MS), and the like.

[0050] <Common materials> The common material 18 is not particularly limited, and may be, for example, the same ceramic material as the main component of the dielectric layer 11. The common material 18 may be a ceramic material represented by the general formula ABO 3-α It is preferable to contain a compound having a perovskite structure represented by (0≦α≦1).

[0051] Specific examples of the co-material 18 include barium titanate (BaTiO3), calcium zirconate (CaZrO3), calcium titanate (CaTiO3), strontium titanate (SrTiO3), magnesium titanate (MgTiO3), and BaTiO3, which forms a perovskite structure. 1-x-y Ca x Sr y Ti 1-z Zr z O3 (0≦x≦1, 0≦y≦1, 0≦z≦1).

[0052] Ba 1-x-y Ca x Sr y Ti 1-z Zrz Examples of O3 include barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate, and barium calcium titanate zirconate. Note that any compound having a perovskite structure may contain oxygen deficiencies.

[0053] The particle size of the common material 18 is not particularly limited, but is preferably smaller than the thickness of the internal electrode layer 12, and from the viewpoint of thinning the internal electrode layer 12, is more preferably 10 nm to 100 nm, and further preferably 10 nm to 50 nm.

[0054] The content of the common material 18 in the internal electrode layer 12 is not particularly limited, but is preferably 2% by mass or more, more preferably 5% by mass or more, and even more preferably 7% by mass or more. When the content of the common material 18 in the internal electrode layer 12 is 2% by mass or more, a sintering retardation effect of the internal electrode layer 12 can be obtained. In addition, the upper limit of the content of the common material 18 in the internal electrode layer 12 is not particularly limited, but is preferably 20% by mass or less, more preferably 15% by mass or less, and even more preferably 12% by mass or less. When the content of the common material 18 in the internal electrode layer 12 is 20% by mass or less, the common material is suitably diffused from the internal electrode layer 12 to the dielectric layer 11 during the sintering process, improving reliability. The upper and lower limits of the content of the common material 18 in the internal electrode layer 12 can be appropriately combined, but is preferably 2% by mass or more to 20% by mass, more preferably 5% by mass or more to 15% by mass or less, and even more preferably 7% by mass or more to 12% by mass or less. The content of the common material 18 in the internal electrode layer 12 is the mass ratio of the common material when the content of nickel in the internal electrode layer 12 is 100 mass %. The content of the common material 18 in the internal electrode layer 12 can be calculated from the amount of raw material charged when the internal electrode layer 12 is produced.

[0055] The area ratio of the common material 18 can also be used as an index for the amount of the common material 18 remaining in the internal electrode layer 12. For example, it can be determined from the cross-sectional area of ​​the common material 18 relative to the cross-sectional area of ​​the internal electrode layer 12 in an XZ cross-section, which is a cross-section in the first axis direction of the multilayer ceramic capacitor 100 as shown in FIG. 2. Specifically, an arbitrary region in one arbitrarily selected layer in the cross-section in the first axis direction of the internal electrode layer 12 is observed with a BF-STEM (BRIGHT Field Scanning Transmission Electron Microscopy) at a magnification of 80,000 times, and the total area of ​​one internal electrode layer 12 in the field of view of the BF-STEM observation image is determined. This is similarly performed for arbitrary regions in two other arbitrarily selected layers in the cross-section in the first axis direction of the internal electrode layer 12, to determine the total area of ​​three internal electrode layers 12. In addition, the diameters of the common materials 18 in the three internal electrode layers 12 are measured from the BF-STEM observation image of the same region, the area of ​​one common material is calculated from the diameter of the common material 18, and the total area of ​​the multiple common materials 18 in the three internal electrode layers 12 is calculated. From these calculated values, the common material area ratio is calculated based on the following formula. Common material area ratio (%) = total area of ​​common material 18 / total area of ​​internal electrode layer 12 × 100

[0056] The common material area ratio is not particularly limited, but is preferably 3% or less, more preferably 2% or less, and even more preferably 1.5% or less. When the common material area ratio is 3% or less, the common material diffuses favorably from the internal electrode layer 12 to the dielectric layer 11 during the sintering process, improving reliability. The lower limit of the common material area ratio is also not particularly limited, but is preferably 0.5% or more, more preferably 0.75% or more, and even more preferably 1% or more. When the common material area ratio is 0.5% or less, the common material diffuses favorably from the internal electrode layer 12 to the dielectric layer 11 during the sintering process, improving reliability. The upper and lower limits of the common material area ratio can be appropriately combined, but is preferably 0.5% to 3%, more preferably 0.75% to 2%, and even more preferably 1% to 1.5%.

[0057] <First segregation area> The first segregation portion 50 is a region where copper, which is a metal added to the internal electrode layer 12, is segregated at the interface between the first phase 17 and the common material 18 in the internal electrode layer 12. When the internal electrode layer 12 is manufactured, copper, preferably copper oxide, is added, thereby forming the first segregation portion 50 at the interface between the first phase 17 and the common material 18.

[0058] The capacitance of the multilayer ceramic capacitor 100 is expressed by the following equation: Therefore, in order to achieve a smaller size and a larger capacitance of the multilayer ceramic capacitor 100, it is conceivable to increase the capacitance per unit volume by thinning the dielectric layers 11 and the internal electrode layers 12, or to increase the number of laminated dielectric layers 11 and internal electrode layers 12.

[0059]

number

[0060] However, conventionally, the sintering temperature of the dielectric layers is higher than that of the internal electrode layers. Therefore, when the internal electrode layers are thinned, the continuity of the internal electrode layers decreases when sintered in a temperature range where the dielectric layers are densified. When the continuity of the internal electrode layers decreases, the connectivity between the internal electrode layers and the external electrodes decreases, resulting in poor conduction and making it difficult to obtain desired characteristics.

[0061] In contrast, in the multilayer ceramic capacitor 100 of the present disclosure, the internal electrode layers 12 contain the common material 18, which delays sintering of the internal electrode layers 12. Meanwhile, the remaining common material 18 in the internal electrode layers 12 can increase the resistance of the internal electrode layers 12 and reduce reliability. However, in the multilayer ceramic capacitor 100 of the present disclosure, the internal electrode layers 12 contain copper in addition to nickel, which is the main component. More specifically, the internal electrode layers 12 are manufactured using a metal paste containing copper oxide in addition to nickel. This allows the common material 18 to be efficiently discharged from the internal electrode layers 12 during sintering. This is believed to be due to the presence of first segregation portions 50, in which highly diffusible copper segregates, around the particles of the common material 18, i.e., at the interface between the first phase 17 and the common material 18 in the internal electrode layers 12. Due to the diffusivity of copper, the common material 18 containing the first segregation portions 50 diffuses from the internal electrode layers 12 toward the external electrode 20 during sintering, causing the common material 18 to be discharged to the external electrode 20. At this time, copper flows, improving the connectivity between the internal electrode layers 12 and the external electrodes 20. As a result, the connectivity between the internal electrode layers 12 and the external electrodes 20 improves, and the capacitance increases. Furthermore, the amount of common material 18 remaining in the internal electrode layers 12 decreases, improving reliability. Therefore, the multilayer ceramic capacitor 100 of the present disclosure can achieve both improved connectivity between the internal electrode layers 12 and the external electrodes 20 and improved reliability.

[0062] The presence of the first segregation portion 50 at the interface between the first phase 17 and the co-material 18 can be confirmed by observing the concentration of copper at the interface between the first phase 17 and the co-material 18 using an energy dispersive X-ray spectrometer (EDS) or wavelength dispersive X-ray spectrometer (WDS) attached to a scanning transmission electron microscope (STEM), an electron probe microanalyzer (EPMA), a laser irradiation inductively coupled plasma mass spectrometry (LA-ICP-MS), or the like.

[0063] The copper concentration in the first segregation portion 50 is higher than the copper concentration in the first phase 17. The copper concentrations in the first segregation portion 50 and the first phase 17 are measured by elemental analysis using a scanning transmission electron microscope (STEM).

[0064] FIG. 6A is an explanatory diagram of a method for measuring the copper concentration in the first segregation region 50. FIG. 6B is an enlarged view of region A in FIG. 5 and is an explanatory diagram showing the measurement direction for measuring the copper concentration in the first segregation region 50. The method for measuring the copper concentration in the first segregation region 50 will be described with reference to FIG. 6A, using an example in which the main component of the common material 18 is barium titanate. As shown in FIGS. 1 and 2, a multilayer ceramic capacitor 100 is polished along the Y axis until it is at the center along the Y axis, thereby preparing a sample in which the XZ plane where the dielectric layers 11 and the internal electrode layers 12 are laminated is exposed. The interface between the first phase 17 and the common material 18 in the exposed XZ plane within the internal electrode layer 12 is measured using a STEM from the first phase 17 side in the internal electrode layer 12 toward the common material 18 side (the direction of the arrow in FIG. 6B) for elemental analysis. Based on the profile data obtained by elemental analysis from the first phase 17 side in the copper internal electrode layer 12 toward the common material 18 side, if the end position where measurement of the first phase 17 side in the internal electrode layer 12 begins is defined as position A, and the distance from position A to an arbitrary position x is defined as measurement distance d(x) nm, then the measurement distance at position A is expressed as d(A) nm = 0 nm. The measurement distance from position A to position B where the Cu concentration has decreased to baseline B is expressed as d(B) nm. Next, if the end position where the measurement in Figure 6A ends is defined as position C, then that measurement distance is expressed as d(C) nm. The average Cu concentration in the range from position B to position C, i.e., the range from measurement distance d(B) nm to measurement distance d(C) nm, is defined as the Cu concentration of baseline B. This allows the average Cu concentration of the common material 18 to be calculated. Next, if the position moved 3 nm toward position A from position B is defined as position (B-3), the peak Cu concentration c(A) is measured in the range from position (B-3) to position B, i.e., the range from measurement distance d(B-3) nm to d(B) nm, thereby determining the peak Cu concentration in the first segregation portion 50.

[0065] In the present disclosure, the position (A+0.5) is defined as the position 0.5 nm from position A, which is the end position at which measurement on the first phase 17 side in the internal electrode layer 12 begins, and the average value of the Cu concentration in the range from position A to position (A+0.5), i.e., the range from d(A) nm to d(A+0.5) nm, is defined as the "copper concentration of the first phase 17," and the peak concentration c(A) of the Cu concentration in the aforementioned range from d(B-3) nm to d(B) nm is defined as the "copper concentration of the first segregation portion 50." That is, in the present disclosure, when the copper concentration of the first segregation portion 50 is expressed as being "higher" than the copper concentration of the first phase 17, it means that the peak Cu concentration c(A) in the range from d(B-3) nm to d(B) nm is higher than the average value of the Cu concentration from the end d(A) nm to d(A+0.5) nm where measurement begins on the first phase 17 side within the internal electrode layer 12.

[0066] When the Cu concentration of baseline B is taken as 100%, the peak concentration c(A) of the Cu concentration is not particularly limited as long as it exceeds 100%, but is preferably 120% or more, and more preferably 130% or more. When the Cu concentration of baseline B is taken as 100%, the upper limit of the peak concentration c(A) of the Cu concentration is not particularly limited, but is more preferably 200% or less.

[0067] The peak concentration c(A) of the Cu concentration is not particularly limited as long as it is higher than the peak concentration of Cu concentration in the first phase 17, but is preferably 1.20 at% or more, and more preferably 4.0 at% or more. The upper limit of the peak concentration c(A) of the Cu concentration is not particularly limited, but is more preferably 16 at% or less.

[0068] The first segregation portions 50 may be disposed at the interface between the first phase 17 and the common material 18, i.e., at least a part of the periphery of the common material 18. Therefore, the first segregation portions 50 may be disposed continuously or discontinuously at the interface between the first phase 17 and the common material 18.

[0069] (3-2) Average thickness of internal electrode layers The average thickness of the internal electrode layers 12 is not particularly limited, but from the viewpoint of increasing the number of layers and increasing the capacitance while miniaturizing the multilayer ceramic capacitor 100, it is preferably 0.8 μm or less, more preferably 0.6 μm or less, and even more preferably 0.4 μm or less. Furthermore, from the viewpoint of improving productivity and yield, the average thickness of the internal electrode layers 12 is preferably 0.2 μm or more, and more preferably 0.3 μm or more. The upper and lower limits of the average thickness of the internal electrode layers 12 can be appropriately combined, but it is preferably 0.2 μm or more and 0.8 μm or less, more preferably 0.2 μm or more and 0.6 μm or less, more preferably 0.3 μm or more and 0.4 μm or less.

[0070] 1 and 2, a sample is prepared by polishing a multilayer ceramic capacitor 100 along the Y axis up to the center along the Y axis, exposing the XZ plane where the dielectric layers 11 and the internal electrode layers 12 are laminated. Two internal electrode layers 12 are selected from the exposed XZ plane, which are located in the center along the Z axis, which is the first axis, and two internal electrode layers 12 are selected from the top and bottom along the Z axis, which is the first axis. The selected internal electrode layers 12 are selected from within the capacitive section 14.

[0071] Then, for the selected internal electrode layer 12, the thickness is measured at the center along the X-axis, which is the second axis, and this is defined as the thickness of the internal electrode layer 12. Using the same procedure, the thicknesses of the internal electrode layers 12 are measured for all six selected internal electrode layers 12, and an average value is calculated. This average value is defined as the average thickness of the internal electrode layers 12 in the multilayer ceramic capacitor 100. The thickness of the internal electrode layers 12 can be measured, for example, with an SEM (Scanning Electron Microscope) or a STEM (Scanning Transmission Electron Microscope).

[0072] (4) Second segregation area The second segregation portion 40 is a region where copper, a metal added to the internal electrode layer 12, segregates at the interface between the dielectric layer 11 and the internal electrode layer 12. More specifically, it is a region where copper, a metal added to the internal electrode layer 12, segregates at the interface between the dielectric layer 11 and the first phase 17 in the internal electrode layer 12. By adding copper, preferably copper oxide, during the manufacturing of the internal electrode layer 12, a first segregation portion 50 is formed at the interface between the first phase 17 and the common material 18, and a second segregation portion 40 is also preferably formed at the interface between the dielectric layer 11 and the internal electrode layer 12. By having the second segregation portion 40, the multilayer ceramic capacitor 100 of the present disclosure can preferably discharge the common material 18 to the dielectric layer 11 during sintering, thereby further improving reliability.

[0073] The presence of the second segregation portion 40 at the interface between the dielectric layer 11 and the internal electrode layer 12 can be confirmed by observing the concentration of copper at the interface between the dielectric layer 11 and the internal electrode layer 12 using an energy dispersive X-ray spectrometer (EDS) or wavelength dispersive X-ray spectrometer (WDS) attached to a scanning transmission electron microscope (STEM), an electron probe microanalyzer (EPMA), a laser irradiation inductively coupled plasma mass spectrometry (LA-ICP-MS), or the like.

[0074] The copper concentration in the second segregation portions 40 is higher than the copper concentration in the first phases 17 of the internal electrode layers 12. The copper concentrations in the second segregation portions 40 and the first phases 17 are measured by elemental analysis using a scanning transmission electron microscope (STEM).

[0075] FIG. 7A is an explanatory diagram of a method for measuring the copper concentration in the second segregation region 40. FIG. 7B is an enlarged view of region B in FIG. 5 and is an explanatory diagram showing the measurement direction for measuring the copper concentration in the second segregation region 40. The method for measuring the copper concentration in the second segregation region 40 will be described with reference to FIG. 7A, taking as an example a case where the main component of the dielectric layer 11 is barium titanate. As shown in FIGS. 1 and 2, a multilayer ceramic capacitor 100 is polished along the Y axis until it is at the center along the Y axis, thereby preparing a sample in which the XZ plane where the dielectric layers 11 and the internal electrode layers 12 are laminated is exposed. The interface between the first phase 17 in the internal electrode layer 12 and the dielectric layer 11 on the exposed XZ plane is measured using a STEM from the side of the first phase 17 in the internal electrode layer 12 toward the dielectric layer 11 (the direction of the arrow in FIG. 7B) to perform elemental analysis. Based on the profile data obtained by elemental analysis from the first phase 17 side in the copper internal electrode layer 12 toward the dielectric layer 11 side, if the end position where measurement of the first phase 17 side in the internal electrode layer 12 begins is defined as position D, and the distance from position D to an arbitrary position x is defined as measurement distance d(x) nm, then the measurement distance at position D is expressed as d(D) nm = 0 nm. The measurement distance from position D to position E where the Cu concentration has decreased to baseline E is expressed as d(E) nm. Next, if the end position where the measurement in Figure 7A ends is defined as position F, then that measurement distance is expressed as d(F) nm. The average value of the Cu concentration in the range from position E to position F, i.e., the range from measurement distance d(E) nm to measurement distance d(F) nm, is defined as the Cu concentration of baseline E. This allows the average value of the Cu concentration in the dielectric layer 11 to be determined. Next, if the position moved 3 nm toward position D from position E is defined as position (D-3), the peak Cu concentration c(B) is measured in the range from position (D-3) to position D, i.e., the range from measurement distance d(D-3) nm to d(D) nm, thereby determining the peak Cu concentration in the second segregation portion 40.

[0076] In the present disclosure, the position (D+0.5) is defined as the position 0.5 nm from position D, which is the end position at which measurement on the first phase 17 side in the internal electrode layer 12 begins, and the average value of the Cu concentration in the range from position D to position (D+0.5), i.e., the range from d(D) nm to d(D+0.5) nm, is defined as the "copper concentration of the first phase 17," and the peak concentration c(B) of the Cu concentration in the aforementioned range from d(E-3) nm to d(E) nm is defined as the "copper concentration of the second segregation portion 40." That is, in the present disclosure, when the copper concentration of the second segregation portion 40 is expressed as being "higher" than the copper concentration of the first phase 17, it means that the peak Cu concentration c(B) in the range from d(E-3) nm to d(E) nm is higher than the average value of the Cu concentration from the end d(D) nm to d(D+0.5) nm where measurement begins on the first phase 17 side within the internal electrode layer 12.

[0077] When the Cu concentration of the baseline E is taken as 100%, the peak concentration c(B) of the Cu concentration is not particularly limited as long as it exceeds 100%, but is preferably 120% or more, and more preferably 130% or more. When the Cu concentration of the baseline E is taken as 100%, the upper limit of the peak concentration c(B) of the Cu concentration is not particularly limited, but is more preferably 200% or less.

[0078] The peak concentration c(B) of the Cu concentration is not particularly limited as long as it is higher than the peak concentration of Cu concentration in the first phase 17, but is preferably 1.20 at% or more, and more preferably 3.0 at% or more. The upper limit of the peak concentration c(B) of the Cu concentration is not particularly limited, but is more preferably 15 at% or less.

[0079] The second segregation portions 40 may be disposed in at least a part of the interface between the dielectric layer 11 and the first phase 17 in the internal electrode layer 12. Therefore, the second segregation portions 40 may be disposed continuously or discontinuously in the interface between the dielectric layer 11 and the first phase 17 in the internal electrode layer 12.

[0080] (5) External electrodes The external electrodes 20 are provided on the first side surface 10a and the second side surface 10b of the element body 10, and are electrically connected to the internal electrode layers 12. The external electrodes 20 may have one or more plating layers on the surface opposite to the side on which the element body 10 is disposed.

[0081] (5-1) Components contained in external electrodes The external electrodes 20 preferably contain Ni as a main component. In addition to nickel, the external electrodes 20 may contain other components used in the external electrodes 20 of the multilayer ceramic capacitor 100. Examples of other components used in the external electrodes 20 of the multilayer ceramic capacitor 100 include base metals such as tin (Sn) or alloys containing such base metals; and noble metals such as copper (Cu), platinum (Pt), palladium (Pd), silver (Ag), and gold (Au), or alloys containing such noble metals. These may be used alone or in combination of two or more.

[0082] When the external electrode 20 contains copper, it is preferable to have a difference in copper concentration between the external electrode 20 and the region of the internal electrode layer 12 close to the external electrode 20, in order to promote the discharge of the common material 18 in the internal electrode layer 12 to the external electrode 20 during sintering, and therefore it is preferable that the copper concentration of the external electrode 20 is lower than the copper concentration in the first end margin 15a and the second end margin 15b of the internal electrode layer 12.

[0083] The ratio of the copper concentration in the external electrode 20 to the copper concentration in the internal electrode layer 12 is not particularly limited, but the ratio [copper concentration in the external electrode 20 / copper concentration in the internal electrode layer 12] is preferably 0.3 or more and 0.5 or less, more preferably 0.2 or more and 0.4 or less, and even more preferably 0.1 or more and 0.2 or less.

[0084] The external electrode 20 may also contain a common material of ceramic particles. The common material in the external electrode 20 may be the same as the common material 18 in the internal electrode layer 12, and may be represented by the general formula ABO 3-αIt is preferable to contain a compound having a perovskite structure represented by (0≦α≦1).

[0085] The content of the common material in the external electrode 20 is not particularly limited, but is preferably 5% by mass or more, more preferably 10% by mass or more, and even more preferably 15% by mass or more. The upper limit of the content of the common material in the external electrode 20 is also not particularly limited, but is preferably 40% by mass or less, more preferably 35% by mass or less, and even more preferably 30% by mass or less. The upper and lower limits of the content of the common material in the external electrode 20 can be appropriately combined, but is preferably 5% by mass or more and 40% by mass or less, more preferably 10% by mass or more and 35% by mass or less, and even more preferably 15% by mass or more and 30% by mass or less. The content of the common material in the external electrode 20 is the mass ratio of the common material when the nickel content in the external electrode 20 is taken as 100% by mass. The content of the common material in the external electrode 20 can be calculated from the amounts of raw materials charged when the external electrode 20 is produced.

[0086] The multilayer ceramic electronic component of this embodiment can be suitably manufactured by a manufacturing method for a multilayer ceramic electronic component of this embodiment, which will be described later.

[0087] [Manufacturing method for multilayer ceramic capacitors] The method for manufacturing a multilayer ceramic electronic component according to the present disclosure includes an internal electrode layer pattern forming step, a laminate forming step, an external electrode precursor forming step, a first heating step, and a second heating step. The method for manufacturing a multilayer ceramic electronic component according to the present disclosure may further include other steps such as a raw material powder preparing step, a slurry preparing step, a coating step, a compression bonding step, a singulation step, a reoxidation treatment step, and a plating treatment step.

[0088] FIG. 8 is a flowchart of a method for manufacturing the multilayer ceramic capacitor 100 according to one embodiment of the present disclosure.

[0089] (1) Raw material powder preparation process (S1) In the raw material powder preparation step (S1), a ceramic raw material powder is prepared as a dielectric material for forming the dielectric layer 11. The dielectric layer 11 is formed of a ceramic material represented by the general formula ABO 3-α Since it contains a compound with a perovskite structure represented by the general formula ABO 3-α The material from which a ceramic containing a compound having a perovskite structure represented by the following formula can be obtained is used as the raw ceramic powder.

[0090] For example, barium titanate (BaTiO3) is a tetragonal compound with a perovskite structure and exhibits a high dielectric constant. Barium titanate is generally obtained by reacting a titanium source such as titanium dioxide with a barium source such as barium carbonate.

[0091] Various methods have been known for synthesizing ceramic raw material powders, such as a solid phase method, a sol-gel method, a hydrothermal method, etc. Any of these methods can be used in this embodiment.

[0092] From the viewpoint of thinning the dielectric layer 11, the number average particle size of the ceramic raw material powder is preferably 50 nm to 200 nm.

[0093] In the raw material powder preparation step (S1), predetermined additives can be added to the ceramic raw material powder depending on the purpose. The additive compounds include one or more elements selected from the group consisting of zirconium (Zr), niobium (Nb), molybdenum (Mo), tantalum (Ta), tungsten (W), magnesium (Mg), manganese (Mn), vanadium (V), and chromium (Cr); scandium (Sc), yttrium (Y), cerium (Ce), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), and erbium (Er). Examples of suitable sintering aids include oxides containing one or more rare earth elements selected from the group consisting of thulium (Tm), ytterbium (Yb), cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), and silicon (Si); and glasses containing one or more elements selected from the group consisting of cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), and silicon (Si). These may be used alone or in combination. Among these, silicon dioxide (SiO), which is primarily an oxide of silicon (Si), functions favorably as a sintering aid.

[0094] In the raw material powder preparation step (S1), for example, a raw material powder of ceramic can be prepared by wet-mixing a compound containing additives and additive compounds as needed, followed by drying and pulverization. Furthermore, after drying and pulverization, the raw material powder can be further pulverized as needed to adjust the particle size, or the particle size can be adjusted by combining with a classification process. The raw material powder as a dielectric material can be obtained by the above steps.

[0095] (2) Slurry preparation step (S2) In the slurry preparation step (S2), a slurry containing the raw material powder obtained in the raw material powder preparation step (S1) is prepared.

[0096] The slurry may contain, in addition to the raw material powder obtained in the raw material powder preparation step (S1), an organic binder, an organic solvent, a plasticizer, etc. The organic binder is not particularly limited, and known resins such as polyvinyl butyral (PVB) resin can be used. The organic solvent is not particularly limited, and examples thereof include ethanol and toluene.

[0097] The method for preparing the slurry is not particularly limited, and examples thereof include a method in which raw material powder, an organic binder, an organic solvent, and a plasticizer are added and wet mixed. Note that when the ceramic raw material powder and the like are mixed in the raw material powder preparation step (S1), an organic binder and the like may also be added and wet mixed.

[0098] (3) Coating process (S3) In the coating step (S3), the slurry prepared in the slurry preparation step (S2) is coated onto a substrate.

[0099] In the coating step (S3), the obtained slurry can be coated on a substrate by, for example, a die coater method or a doctor blade method. This forms a dielectric layer precursor sheet 71. An example of the dielectric layer precursor sheet 71 is a ceramic precursor sheet. The thickness of the dielectric layer precursor sheet 71 can be appropriately selected depending on the average thickness of the desired dielectric layer 11.

[0100] The substrate is not particularly limited, but is preferably made of a material from which the dielectric layer precursor sheet 71 can be peeled off, and an example of this is a polyethylene terephthalate (PET) film.

[0101] In the coating step (S3), the slurry may be coated onto the substrate and then dried. An example of the coating step (S3) is omitted in the drawings.

[0102] (4) Internal electrode layer pattern formation process (S4) In the internal electrode layer pattern forming process (S4), 3-αAn internal electrode layer pattern 72 is formed on a dielectric layer precursor sheet 71 containing a raw material powder of a ceramic containing a compound having a perovskite structure represented by (0≦α≦1) using a first metal paste containing nickel (Ni), copper oxide (CuO), and a common material 18. Specifically, the internal electrode layer pattern 72 is formed on the dielectric layer precursor sheet 71 obtained in the coating step (S3) using the first metal paste containing nickel, copper oxide, and the common material 18.

[0103] FIG. 9A is a diagram illustrating an internal electrode layer pattern forming step in a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present disclosure.

[0104] The particle size of copper oxide (CuO) is not particularly limited, but is preferably smaller than the thickness of the internal electrode layer 12, and from the viewpoint of thinning the internal electrode layer 12, is more preferably 10 nm to 100 nm.

[0105] The content of copper oxide (CuO) in the first metal paste is not particularly limited, but from the viewpoint of the connectivity between the internal electrode layer 12 and the external electrode 20, the content of copper (Cu) relative to nickel (Ni) in the internal electrode layer 12 is preferably 1 at% to 11 at% and more preferably 1 at% to 6 at%. Furthermore, from the viewpoint of reliability, the content of copper oxide (CuO) in the first metal paste is preferably 1 at% to 11 at% and more preferably 3 at% to 11 at%. Furthermore, from the viewpoint of overall connectivity and reliability between the internal electrode layer 12 and the external electrode 20, the content of copper oxide (CuO) in the first metal paste is more preferably 3 at% to 6.0 at% and more preferably 3 at% to 11 at%. When copper oxide (CuO) is added, it may be dispersed in advance in an organic solvent such as terpineol.

[0106] As described above, the first internal electrode layer 12a and the second internal electrode layer 12b can be mainly composed of nickel (Ni) or an alloy containing nickel (Ni). The first metal paste may further contain a base metal such as tin (Sn) or an alloy containing this; a noble metal such as platinum (Pt), palladium (Pd), silver (Ag), or gold (Au) or an alloy containing these.

[0107] The first internal electrode layer pattern 72a in the first internal electrode layer 12a and the second internal electrode layer pattern 72b in the second internal electrode layer 12b may be formed using a metal paste of the same composition or different compositions, as long as the first metal paste contains nickel, copper oxide, and the common material 18. That is, the main component of the first internal electrode layer 12a and the main component of the second internal electrode layer 12b may be the same or different. As an example, the main component of both the first internal electrode layer 12a and the second internal electrode layer 12b may be the same, that is, nickel.

[0108] In the internal electrode layer pattern forming step (S4), the metal paste can be prepared by kneading nickel, copper oxide, and the common material 18, and further, if necessary, other metals or alloys, or common materials.

[0109] In the internal electrode layer pattern forming step (S4), as illustrated in Fig. 9A, a first metal paste containing nickel, copper oxide, and a common material 18 can be printed on the surface of the dielectric layer precursor sheet 71 by a printing method such as screen printing or gravure printing. In addition, the method for forming the internal electrode layer pattern in the internal electrode layer pattern forming step (S4) is not limited to the printing method, and a plating method, a vacuum deposition method, a sputtering method, or a CVD method may also be used. As a result, a first internal electrode layer pattern 72a for the first internal electrode layer 12a or a second internal electrode layer pattern 72b for the second internal electrode layer 12b is formed on the surface of the dielectric layer precursor sheet 71.

[0110] Alternatively, a dielectric pattern paste for the reverse pattern layer can be obtained by adding an organic binder such as an ethyl cellulose-based binder and an organic solvent such as a terpineol-based binder to the raw material powder obtained in the raw material powder preparation step (S1) and kneading them in a roll mill. As illustrated in Fig. 9A, a dielectric pattern paste may be formed in a peripheral region on a dielectric layer precursor sheet 71 where the first internal electrode layer pattern 72a and the second internal electrode layer pattern 72b are not formed, thereby arranging the dielectric pattern 73 and filling in the step between the first internal electrode layer pattern 72a and the second internal electrode layer pattern 72b. The dielectric layer precursor sheet 71 on which the internal electrode layer pattern 72 and the dielectric pattern 73 are formed is referred to as a lamination unit.

[0111] (5) Laminate formation process (S5) In the laminate formation process (S5), a laminate is formed by stacking multiple dielectric layer precursor sheets 71, each having an internal electrode layer pattern 72 formed thereon, along a first axis so that the internal electrode layer patterns 72 are alternately exposed on two opposing end faces.

[0112] FIG. 9B is a diagram illustrating a laminate forming step in the method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present disclosure.

[0113] 9B, the dielectric layer precursor sheet 71 on which the first internal electrode layer pattern 72a and the dielectric pattern 73 are formed and the dielectric layer precursor sheet 71 on which the second internal electrode layer pattern 72b and the dielectric pattern 73 are formed are laminated in this order while peeling off the base material from the dielectric layer precursor sheet 71. At this time, it is preferable to laminate the lamination units so that the internal electrode layers 12 and the dielectric layers 11 are alternately arranged and so that the edges of the internal electrode layers 12 are alternately exposed on both end faces in the length direction of the dielectric layer 11 and are alternately drawn out to a pair of external electrodes.

[0114] The number of layers in the laminate unit is not particularly limited and can be appropriately selected depending on the purpose, and can be, for example, 100 to 500 layers.

[0115] Furthermore, cover layers 13 may be further laminated on the upper and lower surfaces of the laminate of dielectric layer precursor sheets 71. The number of cover layers 13 to be laminated is not particularly limited and can be appropriately selected depending on the purpose, and can be, for example, 2 to 10 layers. The cover layers 13 may have the same components as the dielectric layer precursor sheets 71, or may contain different additive compounds.

[0116] In the laminate formation step (S5), the laminate obtained as described above, preferably a laminate of dielectric layer precursor sheets 71 covered on the upper and lower surfaces with cover layers 13, is thermocompressed to form a laminate.

[0117] (6) Singulation process (S6) In the singulation step (S6), the laminate obtained in the laminate formation step (S5) is singulated.

[0118] In the singulation step (S6), the method of singulation is not particularly limited, and existing methods such as dicing using a dicer or laser cutting can be used.

[0119] The size of the individual pieces is not particularly limited and can be selected appropriately depending on the desired size of the multilayer ceramic capacitor 100 .

[0120] (7) External electrode precursor formation step (S7) In the external electrode precursor forming step (S7), a second metal paste containing nickel is applied by an appropriate method to the surface of the singulated laminate to form an external electrode precursor. When external electrodes 20 are provided on two end faces of the element body 10, it is preferable that in the external electrode precursor forming step (S7), the second metal paste containing nickel is applied by an appropriate method to two opposing side faces, that is, a first side face 10a and a second side face 10b, of the singulated laminate to form an external electrode precursor.

[0121] As described above, the external electrode 20 can be primarily composed of nickel (Ni) or an alloy containing nickel (Ni). The second metal paste may further contain powder of an additive metal element, such as a base metal such as tin (Sn) or an alloy containing it; or a noble metal such as copper (Cu), platinum (Pt), palladium (Pd), silver (Ag), or gold (Au), or an alloy containing these. The second metal paste may also contain a co-material or glass component. When the second metal paste contains other components, such as powder of an additive metal element or a co-material, the concentration of the other components relative to nickel is reduced. The inclusion of a glass component can reduce voids within the external electrode and increase its strength.

[0122] In the external electrode precursor forming step (S7), the second metal paste can be prepared by kneading nickel and, if necessary, other metals, alloys, or co-materials. When copper is added to the second metal paste, the copper may be added in the form of a simple substance or a compound.

[0123] The second metal paste used in the external electrode precursor forming step (S7) may have the same composition as or different from the first metal paste used in the internal electrode layer pattern forming step (S4), for example.

[0124] The method for applying the second metal paste to the surface of the laminate is not particularly limited, and examples thereof include a dipping method and a transfer method.

[0125] In the external electrode precursor forming step (S7), the second metal paste may be applied to the surface of the laminate and then dried.

[0126] (8) First heating step (S8) In the first heating step (S8), the laminate with the external electrode precursor formed thereon obtained in the external electrode precursor forming step (S7) is heated at 800°C or higher and 1000°C or lower.

[0127] The heating time in the first heating step (S8) is not particularly limited, but is preferably maintained for 3 minutes to 5 minutes. Among these, in the first heating step (S8), it is preferable to maintain the laminate at a temperature of 800°C to 1000°C for 3 minutes to 5 minutes, since this facilitates the formation of first segregation portions 50 at the interface between first phase 17 and common material 18.

[0128] Organic binders are generally burned away at approximately 500°C. Therefore, the organic binder can be degreased in the first heating step (S8). Although this increases the number of process steps, the degreasing step can be separated from the first heating step (S8) and performed between the first heating step (S8) and the external electrode precursor forming step (S7), which is the preceding step, or can be performed within the external electrode precursor forming step (S7).

[0129] Conventionally, by sintering a laminate having an external electrode precursor formed thereon at a high heating rate, the metal paste is sintered before the common material 18 is expelled from the metal paste in the internal electrode layer pattern 72, so that the common material 18 remains in the internal electrode layer 12. On the other hand, the manufacturing method of the multilayer ceramic electronic component of the present disclosure includes the first heating step (S8), thereby expelling the common material 18 appropriately to the external electrode 20.

[0130] The laminate may be gradually heated from room temperature until the heating temperature reaches 800° C. In this case, the average heating rate from room temperature until 800° C. is not particularly limited, but if the average heating rate is too high, the organic binder in the first metal paste in the internal electrode layer pattern 72 may not be sufficiently degreased, which may cause problems such as cracks occurring in the second heating step, so the average heating rate is preferably 80° C. / min or less, and more preferably 65° C. / min or less.

[0131] In addition, even when the degreasing step is separated from the first heating step (S8) and is performed between the preceding external electrode precursor forming step (S7) or within the external electrode precursor forming step (S7), the average temperature rise rate in the degreasing step itself from room temperature to 500°C is preferably 80°C / min or less, and more preferably 65°C / min or less. When the degreasing step is separated from the first heating step (S8), the average temperature rise rate in the first heating step (S8) can be 200°C / min or more and 500°C / min or less, and by setting it to 300°C / min or more and 500°C / min, it is possible to easily form the first segregation portion 50 at the interface between the first phase 17 and the common material 18.

[0132] The oxygen partial pressure in the first heating step (S8) is not particularly limited, but is preferably 10 -10 atm over 10 -7 atm or less is preferable, and 10 -9 atm over 10 -7 atm or less is preferable, and 10 -8 atm over 10 -7 Atm or less is more preferable.

[0133] The atmospheric conditions in the first heating step (S8) are preferably a reducing atmosphere.

[0134] (9) Second heating step (S9) In the second heating step (S9), after the first heating step (S8), a dielectric layer 11 is formed from the dielectric layer precursor sheet 71, an internal electrode layer 12 is formed from the internal electrode layer pattern 72, an external electrode 20 is formed from the external electrode precursor, and the internal electrode layer 12 contains a first phase 17 containing nickel and copper and a common material 18, and a first segregation portion 50 in which copper is segregated at the interface between the first phase 17 and the common material 18 is formed, and the laminate in which the external electrode precursor is formed is heated so that the copper concentration in the first segregation portion 50 is higher than the copper concentration in the first phase 17.

[0135] The heating temperature in the second heating step (S9) is not particularly limited, but is preferably 1100°C or higher and 1300°C or lower. The heating time in the second heating step (S9) is also not particularly limited, but is preferably maintained for 10 minutes to 2 hours. Among these, it is particularly preferred that in the second heating step (S9), the laminate that has been subjected to the first heating step (S8) be maintained at a temperature of 1100°C or higher and 1300°C or lower for 10 minutes to 2 hours.

[0136] The laminate may be gradually heated from a heating temperature of 1000°C or less in the first heating step until it reaches a maximum temperature specified as 1100°C or more and 1300°C or less. In this case, the average heating rate from 1000°C or less to 1100°C is not particularly limited, but is preferably 50°C / min or more, more preferably 100°C / min or more. The average heating rate is also preferably 500°C / min or less, more preferably 400°C / min or less.

[0137] The oxygen partial pressure in the second heating step (S9) is not particularly limited, but is preferably 10 -12 atm over 10 -7 atm or less is preferable, and 10 -12 atm over 10 -8 atm or less is preferable, and 10 -12 atm over 10 -9 Atm or less is more preferable.

[0138] The atmospheric conditions in the second heating step (S9) are preferably a reducing atmosphere.

[0139] (9) Reoxidation treatment step (S10) In the reoxidation treatment step (S10), heat treatment is performed in a mixed gas of water vapor in a reducing atmosphere at 600°C to 1000°C, or in air at 500°C to 700°C. This allows oxygen to be returned to the partially reduced main phase of the dielectric layer 11 sintered in a reducing atmosphere. Note that the reoxidation treatment step (S10) is performed in such a way as not to oxidize the internal electrode layers 12.

[0140] (11) Plating process (S11) In the plating step (S11), the exposed portions of the first external electrode 20a and the second external electrode 20b are plated using a metal such as copper (Cu), nickel (Ni), or tin (Sn).

[0141] Through the above steps, the multilayer ceramic capacitor 100 can be manufactured.

[0142] The above steps are merely an example, and the method for manufacturing the multilayer ceramic capacitor of this embodiment is not limited to the above-described embodiment.

[0143] [Other embodiments] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims.

[0144] For example, although the above embodiment is applied to a multilayer ceramic capacitor having two terminal electrodes, it may also be applied to a multilayer ceramic capacitor having three or more terminals.

[0145] Although the above embodiment describes a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component, the present disclosure is applicable to multilayer ceramic electronic components in general, such as chip varistors, chip thermistors, and multilayer inductors.

[0146] [Circuit Module] The circuit module of this embodiment includes the multilayer ceramic electronic component of this embodiment. A specific example of the circuit module is one in which the multilayer ceramic capacitor 100 is mounted on an electronic circuit board.

[0147] In addition to the multilayer ceramic capacitor 100, various other electronic components can also be mounted on the circuit module.

[0148] [Electronic equipment] The electronic device of this embodiment includes the circuit module of this embodiment. Specific examples of the electronic device include smartphones, tablets, game consoles, automotive electrical components, and servers, but may also include various other electronic devices. [Example]

[0149] The present disclosure will be specifically explained below with reference to examples and comparative examples, but the present disclosure is not limited to these examples in any way.

[0150] [Example 1] The multilayer ceramic capacitor 100 was manufactured according to the flowchart shown in FIG.

[0151] <Raw material powder preparation step (S1) and slurry preparation step (S2)> Barium titanate powder was wet mixed with polyvinyl butyral (PVB) resin as an organic binder, ethanol, toluene, dioctyl phthalate (DOP) as a plasticizer, and silicon dioxide (SiO2) as a sintering aid to prepare a slurry.

[0152] <Coating process (S3)> The obtained slurry was applied onto a polyethylene terephthalate (PET) film using a die coater to prepare a dielectric layer precursor sheet.

[0153] <Internal electrode layer pattern formation process (S4)> A first metal paste was prepared by adding copper oxide dispersed in terpineol to a mixture of nickel powder as the main component, barium titanate powder as a co-material, and polyvinyl butyral resin as an organic binder, so that the copper content was 1.1 at% when the nickel content was 100 at%. The first metal paste was printed by screen printing on a dielectric layer precursor sheet, and an internal electrode layer pattern was formed that alternately led to a pair of external electrodes, thereby forming a laminate unit. This laminate unit has a dielectric layer precursor sheet and an internal electrode layer pattern formed on the surface of the dielectric layer precursor sheet.

[0154] <Laminate formation step (S5)> While peeling off the PET film from the dielectric layer precursor sheet, 400 laminated units were stacked to form a laminate. Five cover layers were then stacked on the top and bottom surfaces of the laminate of laminated units, followed by thermocompression bonding to form a laminate. The cover layers had the same composition as the dielectric layer precursor sheet.

[0155] <Singulation process (S6)> The laminate was cut into individual pieces of 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height by dicing, to obtain chip-shaped laminates (hereinafter sometimes referred to as "ceramic laminate precursors").

[0156] <External electrode formation process (S7)> A second metal paste containing nickel powder and a co-material was applied to the two opposing end faces, the first side face 10a and the second side face 10b, of the ceramic laminate precursor to form an external electrode precursor. The external electrode precursor was heated at 150°C in a nitrogen atmosphere for 10 minutes to dry the solvent in the external electrode precursor.

[0157] <First heating step (S8)> The ceramic laminate precursor was heated at an oxygen partial pressure of 10 -7 The mixture was sintered at 950°C for 5 minutes in a reducing atmosphere of 1 atm.

[0158] <Second heating step (S9)> After the first heating step (S8), the oxygen partial pressure is 10 -9 The mixture was sintered at 1300°C for 15 minutes in a reducing atmosphere of 1 atm.

[0159] <Reoxidation treatment step (S10)> After the second heating step (S9), a reoxidation treatment was further carried out at 1000° C. in a nitrogen gas atmosphere.

[0160] As a result of the above, a multilayer ceramic capacitor 100 was produced, having a chip shape of 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, having a first external electrode 20a and a second external electrode 20b, having an average thickness of the dielectric layers 11 of 0.4 μm, an average thickness of the internal electrode layers 12 of 0.6 μm, and having 400 layers.

[0161] [Examples 2 to 4 and Comparative Examples 1 and 2] Multilayer ceramic capacitors of Examples 2 to 4 and Comparative Examples 1 and 2 were produced in the same manner as in Example 1, except that in the internal electrode layer pattern forming process of Example 1, the amount of copper oxide added in the first metal paste was changed so that the amount of copper added was as shown in Table 1 below when the amount of nickel added was 100 at%.

[0162] Comparative Example 3 The multilayer ceramic capacitor of Comparative Example 3 was produced in the same manner as in Example 1, except that the first heating step (S8) of Example 1 was not performed and the second heating step (S9) was performed after the external electrode forming step (S7).

[0163] Comparative Example 4 A multilayer ceramic capacitor of Comparative Example 4 was produced in the same manner as in Example 1, except that in the internal electrode layer pattern forming step (S4) of Example 1, the first metal paste was changed to a comparative metal paste prepared as follows.

[0164] The comparative metal paste was prepared by adding gold dispersed in terpineol to a mixture of nickel powder as the main component, barium titanate powder as a co-material, and polyvinyl butyral resin as an organic binder, so that the amount of gold added was 1.0 at% when the amount of nickel added was 100 at%.

[0165] [evaluation] -Preparation of measurement samples- The multilayer ceramic capacitors 100 of Examples 1 to 4 and Comparative Examples 1 to 4 were each polished along the Y axis up to the center along the Y axis, and measurement samples 1 were produced in which the XZ plane on which the dielectric layers 11 and internal electrode layers 12 were laminated was exposed.

[0166] Next, a 0.5 μm×2 μm area was cut out from an arbitrary area selected from the capacitance section 14 using a Focused Ion Beam (FIB) device (manufactured by Thermo Fisher Scientific) to prepare a measurement sample 2.

[0167] <Confirmation of the Presence or Absence of the First Segregation Portion 50> An elemental analysis was performed by measuring the interface between the first phase 17 in the internal electrode layer 12 and the common material 18 in the XZ plane of the measurement sample 2 using STEM in the direction from the first phase 17 side in the internal electrode layer 12 to the common material 18 side, as shown by the arrow in Figure 6B, to confirm whether Cu was concentrated at the interface. If concentration was observed, the first segregation portion was judged to be "present", and if concentration was not observed, the first segregation portion was judged to be "absent".

[0168] The interface between the first phase 17 in the internal electrode layer 12 and the common material 18 in the XZ plane of the measurement sample 2 was thinly sliced ​​to a thickness of about 100 nm, and elemental analysis was performed using STEM by measuring from the first phase 17 side in the internal electrode layer 12 to the common material 18 side as shown by the arrow in Figure 6B, and the presence or absence of Cu segregation was evaluated using the obtained profile data from the first phase 17 side in the copper internal electrode layer 12 to the common material 18 side. As an example of the result of elemental analysis, the analysis result of Example 1 is shown in Figure 10.

[0169] If the end position where measurement on the first phase 17 side in the internal electrode layer 12 begins is defined as position A, and the distance from position A to an arbitrary position x is defined as measurement distance d(x) nm, then the measurement distance at position A is expressed as d(A) nm = 0 nm. The measurement distance from position A to position B where the Cu concentration has decreased to baseline B is expressed as d(B) nm. Next, if the end position where measurement ends in Figure 10 is defined as position C, then the measurement distance is expressed as d(C) nm. The average value of the Cu concentration of the common material 18 in the internal electrode layer 12 was defined as the Cu concentration of baseline B. Specifically, the average value of the Cu concentration in the range from position B to position C in Figure 10, i.e., from measurement distance d(B) nm to measurement distance d(C) nm, was defined as the Cu concentration of baseline B. In this way, the average value of the Cu concentration of the first phase 17, which is not the common material 18 in the internal electrode layer 12, was calculated. Next, assuming that a position 3 nm toward position A from position B is position (B-3), the peak concentration c(A) of Cu was measured in the range from position (B-3) to position B, i.e., the range from d(B-3) nm to d(B) nm. When the Cu concentration of baseline B was 100 at%, the peak concentration c(A) of Cu was measured, and the peak concentration of Cu in the first segregation portion 50 was determined. When the Cu concentration of baseline B was 100 at%, if the peak concentration c(A) was 120% or more, it was determined that the first segregation portion 50, in which copper, a metal added to the internal electrode layer 12, was segregated at the interface between the first phase 17 and the common material 18, was "present." The results are shown in Table 1.

[0170] In Comparative Example 4, gold was added instead of copper, and therefore there was no first segregation portion containing copper. However, when Au, which is a comparative metal, was analyzed at the same time as the analysis of Cu, no segregation portion where Au was segregated was observed at the interface between the first phase 17 and the common material 18.

[0171] <Confirmation of the Presence or Absence of the Second Segregation Portion 40> An elemental analysis was performed by measuring the interface between the dielectric layer 11 and the internal electrode layer 12 in the XZ plane of the measurement sample 2 using STEM in a direction from the first phase 17 side in the internal electrode layer 12 toward the dielectric layer 11 side, as shown by the arrow in FIG. 7B, to check whether Cu was concentrated at the interface. If a concentration was observed, the second segregation portion was judged to be "present," and if a concentration was not observed, the second segregation portion was judged to be "absent."

[0172] The interface between the first phase 17 in the internal electrode layer 12 and the dielectric layer 11 in the XZ plane of the measurement sample 2 was thinly sliced ​​to a thickness of about 100 nm, and STEM elemental analysis was performed by measuring from the first phase 17 side in the internal electrode layer 12 to the dielectric layer 11 side as shown by the arrow in Figure 7B using STEM, and the presence or absence of Cu segregation was evaluated using the obtained profile data from the first phase 17 side in the internal electrode layer 12 to the dielectric layer 11 side.

[0173] The position of the end where measurement on the first phase 17 side in the internal electrode layer 12 begins is defined as position D, and the distance from position D to an arbitrary position x is defined as measurement distance d(x) nm. The measurement distance at position D is expressed as d(D) nm = 0 nm. The measurement distance from position D to position E where the Cu concentration has decreased to baseline E is expressed as d(E) nm. The average Cu concentration in the dielectric layer 11 was defined as the Cu concentration at baseline E. Specifically, the average Cu concentration in the range from position E to position F, i.e., from measurement distance d(E) nm to measurement distance d(F) nm, was defined as the Cu concentration at baseline E. This resulted in the calculation of the average Cu concentration in the dielectric layer 11. Next, a position 3 nm toward position D from position E was defined as position (E-3). The peak Cu concentration c(B) was measured in the range from position (E-3) to position E, i.e., the range from d(E-3) nm to d(E) nm. When the Cu concentration of the baseline E is taken as 100%, if the peak concentration c(B) of the Cu concentration is 120% or more, it was determined that a second segregation portion 40, in which copper, a metal added to the internal electrode layer 12, segregated at the interface between the dielectric layer 11 and the internal electrode layer 12, was present. The results are shown in Table 2.

[0174] In Comparative Example 4, gold, which is a comparative metal, was added instead of copper, and therefore there was no second segregation portion containing copper. However, when Au, which is a comparative metal, was analyzed at the same time as Cu was analyzed, a segregation portion containing gold was observed at the interface between the dielectric layer 11 and the internal electrode layer 12, and this is listed in Table 2.

[0175] <Area ratio of common material 18 in internal electrode layer 12> The internal electrode layers 12 in the XZ plane of measurement sample 2 in Example 1 and Comparative Examples 1 and 4 were observed at a magnification of 80,000 times using BF-STEM (BRIGHT Field Scanning Transmission Electron Microscopy). FIG. 11A is a traced BF-STEM image in the XZ plane of measurement sample 2 in Comparative Example 1. FIG. 11B is a traced BF-STEM image in the XZ plane of measurement sample 2 in Example 1. FIG. 11C is a traced BF-STEM image in the XZ plane of measurement sample 2 in Comparative Example 4. Compared to FIG. 11A (Comparative Example 1) and FIG. 11B (Example 1), the presence of large grains of co-existing material can clearly be confirmed in FIG. 11C (Comparative Example 4).

[0176] 12A is a diagram showing the frequency of the total area of ​​the common material 18 in three layers obtained from a BF-STEM image of the internal electrode layer 12 in the XZ plane of the measurement sample 2 of Comparative Example 1. FIG. 12B is a diagram showing the frequency of the total area of ​​the common material 18 in three layers obtained from a BF-STEM image of the internal electrode layer 12 in the XZ plane of the measurement sample 2 of Example 1. FIG. 12C is a diagram showing the frequency of the total area of ​​the common material 18 in three layers obtained from a BF-STEM image of the internal electrode layer 12 in the XZ plane of the measurement sample 2 of Comparative Example 4. In BF-STEM, the total area of ​​the common material 18 was difficult to distinguish, but it was confirmed that FIG. 12B (Example 1) had the most fine particles of the common material 18, followed by FIG. 12A (Comparative Example 1) and FIG. 12C (Example 4) had large particles of a single digit size that protruded outward.

[0177] The total area of ​​the three internal electrode layers 12 and the total area of ​​the common material 18 were calculated from the BF-STEM images of the internal electrode layers 12 in the XZ plane, which were cross sections in the first axis direction of the measurement samples 2 of Example 1 and Comparative Examples 1 and 4, and the common material area ratio in the internal electrode layers 12 was calculated based on the following formula. The results are shown in Fig. 13. Common material area ratio (%) = total area of ​​common material 18 / total area of ​​internal electrode layer 12 × 100

[0178] It was confirmed that the amount of the common material 18 remaining in the internal electrode layer 12, which is mainly composed of Ni, was the least in Example 1, in which Cu was added, followed by Comparative Example 1, in which no copper was added, and the most in Comparative Example 4, in which Au was added. From the results of Figures 11A to 13, it was confirmed that adding Cu together with the common material 18 to the internal electrode layer 12 makes it easier to expel the common material 18 from the internal electrode layer 12. Not just any metal can be added to the internal electrode layer 12; some metals, such as Au, can make it more difficult to expel the common material 18 from the internal electrode layer 12 by adding them. The detailed mechanism as to why Cu makes it easier to expel the common material 18 and why Au makes it difficult to expel the common material 18 is unknown, but Au is added alone, but Cu is added in the form of an oxide such as CuO, so it is thought that this makes it more likely to flow due to the detachment of oxygen atoms (O) during firing.

[0179] <Diffusion of Metal into Dielectric Layer 11> The dielectric layers 11 of the multilayer ceramic capacitors 100 of Example 1 and Comparative Example 4 were scanned using a laser-induced coupled plasma mass spectrometer (LA-ICP-MS) under the following conditions to perform elemental analysis of Cu or Au. The laser irradiation diameter was 3 μm, the scanning mode was spot irradiation, and the frequency was 10 Hz. The laser irradiation pattern was continuous point analysis. The atomic percentages (at%) of Cu or Au when Ti was 100 at% were calculated using a semi-quantitative analysis method using a glass standard material. FIG. 14A shows the atomic percentages (at%) of Cu when Ti was 100 at% obtained using the semi-quantitative analysis method using the glass standard material of Example 1. FIG. 14B shows the atomic percentages (at%) of Au when Ti was 100 at% obtained using the semi-quantitative analysis method using the glass standard material of Comparative Example 4.

[0180] 14A and 14B, when Cu was added to the internal electrode layer 12, a larger amount of Cu was diffused into the dielectric layer 11 compared to when Au was added to the internal electrode layer 12. From this, it was considered that the result of FIG. 14B is that when Au was added to the internal electrode layer 12, the amount of Au diffused was small, so the amount of common material 18 remaining in the internal electrode layer 12 was large, whereas when Cu was added to the internal electrode layer 12, the amount of Cu diffused was large, so the amount of common material 18 remaining in the internal electrode layer 12 was small.

[0181] <Connectivity> The XZ plane of the measurement sample 1 was observed using an SEM. A multilayer ceramic capacitor 100 of Comparative Example 1, in which the internal electrode layers 12 were made of Ni alone without Cu or Au added, was used as a control. The connection state between the internal electrode layers 12 and the external electrodes 20 was confirmed from the XZ plane of the measurement sample 1 at a total of 60 locations, 20 locations arbitrarily selected from the upper end, center, and lower end in the Z-axis direction. The "connection state" here refers to the state in which the internal electrode layers 12 and the external electrodes 20 are connected on the SEM image of the XZ plane of the measurement sample 1. Specifically, the connection was determined to be good in two cases: when the internal electrode layers 12 and the external electrodes 20 are observed without a boundary on the SEM image at each observation location; or when the internal electrode layers 12 and the external electrodes 20 are in contact on the SEM image, and the boundary is observed, but 80% or more of the internal electrode layers 12 are in contact in the thickness direction. The following two cases were determined to have poor connectivity: when the internal electrode layers 12 and the external electrodes 20 are in contact with each other on the SEM image and their boundary is observed, but less than 80% of the internal electrode layers 12 are in contact in the thickness direction; or when the internal electrode layers 12 and the external electrodes 20 are not in contact with each other on the SEM image and gaps are observed between the internal electrode layers 12 and the external electrodes 20. The connectivity of the measurement samples was evaluated based on the following evaluation criteria by calculating the ratio of the number of good connection points out of 60 points in Examples 1 to 4 and Comparative Examples 2 to 4 to the number of good connection points out of 60 points in the control (Comparative Example 1). Note that Comparative Example 1, which was used as the control in the connectivity evaluation, was rated C. The results are shown in Table 3. -Evaluation criteria- A: Compared to the control (Comparative Example 1), an improvement of 10% or more in the connection state was confirmed. B: Improvement in connection state compared to the control (Comparative Example 1) is 2% or more but less than 10% C: Compared to the control (Comparative Example 1), the improvement in connection state is less than 2% or is equal to or less than Comparative Example 1.

[0182] <Reliability> A HALT test was conducted at 6 V and 125°C to evaluate reliability. The average value of the HALT life was calculated for 100 samples of each of the multilayer ceramic capacitors 100 of Examples 1 to 4 and Comparative Examples 1 to 4. The multilayer ceramic capacitor 100 of Comparative Example 1, which had only Ni without adding Cu or Au to the internal electrode layers 12, was used as a control and evaluated based on the following evaluation criteria. Note that Comparative Example 1, which was used as a control in the reliability evaluation, was given a grade of C. The results are shown in Table 3. -Evaluation criteria- A: The average lifespan is more than twice as long as that of the control (Comparative Example 1). B: The average lifespan is 1.5 times or more compared to the control (Comparative Example 1). C: The average lifespan is equal to or less than 1.5 times that of the control (Comparative Example 1).

[0183] <Overall rating> Based on the evaluation results of connectivity and reliability, an overall evaluation was made based on the following evaluation criteria. An overall evaluation of A or B indicates practical use, with A being particularly good. Note that Comparative Example 1, which was used as a control in the evaluation of connectivity and reliability, was given a D. The results are shown in Table 3. -Evaluation criteria- A: Connectivity is A and reliability is A B: Either connectivity or reliability is A, and the other is B. C: Either connectivity or reliability is A or B, and the other is C. D: Both connectivity and reliability are C

[0184] [Table 1]

[0185] [Table 2]

[0186] [Table 3]

[0187] According to Examples 1 to 4, it was confirmed that the copper content (copper concentration relative to nickel) in the first phase 17 of the internal electrode layer 12 is preferably 1 at% or more and 11 at% or less, and more preferably 1 at% or more and 6 at% or less, from the viewpoint of connectivity.

[0188] According to Examples 1 to 4, it was confirmed that the copper content (copper concentration relative to nickel) in the first phase 17 of the internal electrode layer 12 is preferably 1 at% or more, and more preferably 3 at% or more, from the viewpoint of reliability.

[0189] According to Examples 1 to 4, it was confirmed that the copper content (copper concentration relative to nickel) in the first phase 17 of the internal electrode layer 12 is preferably 1 at% or more and 11 at% or less overall. From the overall viewpoint of the connectivity and reliability between the internal electrode layer 12 and the external electrode 20, it was confirmed that the copper content is particularly preferably 3 at% or more and 6.0 at% or less.

[0190] It was confirmed that when the copper content (copper concentration relative to nickel) in the first phase 17 is too low, as in Comparative Example 2, the first segregation portion 50 cannot be formed. Even when the copper content (copper concentration relative to nickel) in the first phase 17 is higher than in Example 1, as in Comparative Example 3, it was confirmed that when the first heating step is not performed, Cu cannot be segregated at the interface between the first phase 17 and the common material 18, and the first segregation portion 50 is not formed. In both Comparative Examples 2 and 3, since the first segregation portion 50 was not formed, the common material 18 was not discharged due to the flow of copper inside the internal electrode layer 12 during firing, and the amount of copper moving toward the external electrode 20 was insufficient, so the connectivity between the internal electrode layer 12 and the external electrode 20 was not improved, and furthermore, the common material 18 remained in the internal electrode layer 12, which is thought to have prevented the reliability from being improved.

[0191] From the above results, the multilayer ceramic capacitor 100 of the present disclosure can suppress over-sintering of the internal electrode layers 12, improve the connectivity between the internal electrode layers 12 and the external electrodes 20, and improve reliability since the amount of common material 18 remaining in the internal electrode layers 12 is small after sintering.

[0192] Aspects of the present disclosure include, for example, the following. <1> a plurality of dielectric layers stacked along a first axis; a plurality of internal electrode layers each disposed between adjacent dielectric layers along the first axis; and an element field having a pair of external electrodes provided on the surface of the element body and electrically connected to the internal electrode layers; and The dielectric layer is a compound of the general formula ABO 3-α Contains a compound having a perovskite structure represented by (0≦α≦1), the internal electrode layer contains a first phase containing nickel and copper and a common material, and has a first segregation portion in which copper is segregated at an interface between the first phase and the common material, the copper concentration in the first segregation portion is higher than the copper concentration in the first phase; The external electrodes are multilayer ceramic electronic components containing nickel. <2> The copper concentration in the first segregation portion relative to the copper concentration in the first phase is 120% or more. <1> 1. The multilayer ceramic electronic component according to claim 1. <3> The peak concentration of copper in the first segregation portion is 1.20 at% or more. <1> or the above <2> 1. The multilayer ceramic electronic component according to claim 1. <4> In a cross section of the element body in the direction of the first axis, the cross-sectional area of ​​the common material relative to the cross-sectional area of ​​the internal electrode layers is 1.5% or less. <1> From the above <3> 1. The multilayer ceramic electronic component according to claim 1, wherein the thickness of the multilayer ceramic electronic component is 100 nm. <5> a second segregation portion in which copper is segregated at the interface between the dielectric layer and the internal electrode layer; <1> From the above <4> 1. The multilayer ceramic electronic component according to claim 1, wherein the thickness of the multilayer ceramic electronic component is 100 nm. <6> The external electrodes contain copper. <1> From the above <5> 1. The multilayer ceramic electronic component according to claim 1, wherein the thickness of the multilayer ceramic electronic component is 100 nm. <7> The external electrodes contain a common material. <1> From the above <6> 1. The multilayer ceramic electronic component according to claim 1, wherein the thickness of the multilayer ceramic electronic component is 100 nm. <8> General formula ABO 3-α an internal electrode layer pattern forming step of forming an internal electrode layer pattern on a dielectric layer precursor sheet containing a raw material powder of a ceramic containing a compound having a perovskite structure represented by (0≦α≦1) using a first metal paste containing nickel, copper oxide, and a co-material; a laminate forming step of forming a laminate by laminating a plurality of the dielectric layer precursor sheets, on which the internal electrode layer patterns have been formed, along a first axis so that the internal electrode layer patterns are alternately exposed on two opposing end faces; an external electrode precursor forming step of forming an external electrode precursor on the surface of the laminate using a second metal paste containing nickel; a first heating step of heating the laminate on which the external electrode precursors are formed at a temperature of 800°C or higher and 1000°C or lower; a second heating step of heating the laminate having the external electrode precursor formed thereon, such that after the first heating step, a dielectric layer is formed from the dielectric layer precursor sheet, an internal electrode layer is formed from the internal electrode layer pattern, an external electrode is formed from the external electrode precursor, the internal electrode layer contains a first phase containing nickel and copper and a common material, a first segregation portion where copper is segregated at an interface between the first phase and the common material, and a copper concentration in the first segregation portion is higher than a copper concentration in the first phase; The present invention relates to a method for manufacturing a multilayer ceramic electronic component, comprising the steps of: <9> The first metal paste contains the copper oxide so that the concentration of copper relative to the concentration of nickel is 1 at % or more and 11 at % or less. <8> 1. A method for producing the multilayer ceramic electronic component according to claim 1. <10> The aforementioned <1> From the above <7> A circuit module is provided with the multilayer ceramic electronic component according to any one of the above items. <11> The aforementioned <10> An electronic device having the circuit module described above.

[0193] As described above, the present disclosure has been described based on specific embodiments and examples, but these embodiments and examples are presented merely as examples, and the present disclosure is not limited to the above embodiments and examples. The above embodiments can be implemented in various other forms, and various combinations, omissions, substitutions, additions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents set forth in the claims. [Explanation of symbols]

[0194] 100 Multilayer ceramic capacitors 10 Base 10a First side 10b Second side 10c 3rd side 10d 4th side 11 Dielectric layer 12 Internal electrode layer 12a 1st internal electrode layer 12b Second internal electrode layer 13 Cover Layer 14 Capacity part 15a First End Margin 15b Second End Margin 16 Side Margin 17 First Phase 18 Common materials 20 External electrode 20a 1st external electrode 20b 2nd external electrode 40 Second segregation area 50 First segregation section C area D area S1 Raw material powder preparation process S2 Slurry preparation process S3 Coating process S4 Internal electrode layer pattern formation process S5 Laminate formation process S6 singulation process S7 External electrode precursor formation process S8 First heating process S9 Second heating process S10 Reoxidation treatment process S11 Plating process 71 Dielectric layer precursor sheet 72 Internal electrode layer pattern 72a First internal electrode layer pattern 72b Second internal electrode layer pattern 73 Dielectric Pattern d(A) End where measurement begins d(B) Measurement distance at which Cu concentration decreased to baseline B d(C) End point where measurement ends c(A) Peak concentration of Cu d(D) End where measurement starts d(E) Measurement distance at which Cu concentration decreased to baseline E d(F) End point of measurement c(B) Peak concentration of Cu c(B) Peak concentration of Cu

Claims

1. a plurality of dielectric layers stacked along a first axis; a plurality of internal electrode layers each disposed between adjacent dielectric layers along the first axis; and an element field having a pair of external electrodes provided on the surface of the element body and electrically connected to the internal electrode layers; and The dielectric layer is formed of a material having the general formula ABO ３－α (0≦α≦1) the internal electrode layer includes a first phase containing nickel and copper and a common material, and has a first segregation portion in which copper is segregated at an interface between the first phase and the common material, the copper concentration in the first segregation portion is higher than the copper concentration in the first phase; The external electrodes contain nickel.

2. 2. The multilayer ceramic electronic component according to claim 1, wherein the copper concentration in said first segregation portion is 120% or more of the copper concentration in said first phase.

3. 2. The multilayer ceramic electronic component according to claim 1, wherein the peak copper concentration in the first segregation portion is 1.20 at % or more.

4. 2. The multilayer ceramic electronic component according to claim 1, wherein in a cross section of said element body in the direction of said first axis, a cross-sectional area of ​​said common material relative to a cross-sectional area of ​​said internal electrode layers is 1.5% or less.

5. 2. The multilayer ceramic electronic component according to claim 1, further comprising a second segregated portion in which copper is segregated at the interface between the dielectric layer and the internal electrode layer.

6. 2. The multilayer ceramic electronic component according to claim 1, wherein the external electrodes contain copper.

7. The multilayer ceramic electronic component according to claim 1 , wherein the external electrodes contain a common material.

8. General formula ABO ３－α an internal electrode layer pattern forming step of forming an internal electrode layer pattern on a dielectric layer precursor sheet containing a raw material powder of a ceramic containing a compound having a perovskite structure represented by (0≦α≦1) using a first metal paste containing nickel, copper oxide, and a co-material; a laminate forming step of forming a laminate by laminating a plurality of the dielectric layer precursor sheets, on which the internal electrode layer patterns are formed, along a first axis so that the internal electrode layer patterns are alternately exposed on two opposing end surfaces; an external electrode precursor forming step of forming an external electrode precursor on the surface of the laminate using a second metal paste containing nickel; a first heating step of heating the laminate on which the external electrode precursors have been formed at a temperature of 800°C or higher and 1000°C or lower; a second heating step of heating the laminate having the external electrode precursor formed thereon such that, after the first heating step, a dielectric layer is formed from the dielectric layer precursor sheet, an internal electrode layer is formed from the internal electrode layer pattern, an external electrode is formed from the external electrode precursor, and the internal electrode layer contains a first phase containing nickel and copper and a common material, and a first segregation portion in which copper is segregated at an interface between the first phase and the common material is formed, and a copper concentration in the first segregation portion is higher than a copper concentration in the first phase; A method for manufacturing a multilayer ceramic electronic component, comprising:

9. 9. The method for producing a multilayer ceramic electronic component according to claim 8, wherein the first metal paste contains the copper oxide such that a concentration of copper relative to a concentration of nickel is 1 at % or more and 11 at % or less.

10. A circuit module comprising the multilayer ceramic electronic component according to claim 1 .

11. An electronic device comprising the circuit module according to claim 10.

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