Pulse width measuring circuit and method for measuring pulse width

Abstract

To provide a pulse width measuring circuit with which a measurement time is shortened.SOLUTION: A first programmable delay circuit 130 and a second programmable delay circuit 140 respectively delay a first pulse S1 and a second pulse S2 corresponding to an input pulse SIN and generate a first delay pulse Sd1 and a second delay pulse Sd2. A latch circuit 150 latches the first delay pulse Sd1 in response to an edge of the second delay pulse Sd2. A controller 160 continuously sweeps a delay amount τ2 of the second programmable delay circuit 140 in first processing, and detects a first delay mount τP when the output Q of the latch circuit 150 changes. In second processing, the delay amount τ2 of the second programmable delay circuit 140 is changed by a binary search and a second delay amount τn is detected when the output Q of the latch circuit 150 changes. The difference between the first delay amount τP and the second delay amount τn is made a pulse width Tp of the input pulse SIN.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to pulse width measurement techniques. [Background technology]

[0002] In semiconductor integrated circuits, a time-to-digital converter (TDC) circuit is used to measure time. Proposed TDC circuit configurations include flash TDC and successive approximation register (SAR) TDC. [Prior art documents] [Non-patent literature]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-211539

[0004] [overview] The present disclosure has been made in light of such a situation, and one exemplary purpose of an embodiment thereof is to provide a pulse width measurement circuit that reduces measurement time.

[0005] One aspect of the present disclosure relates to a pulse width measurement circuit that measures the pulse width of an input pulse. The pulse width measurement circuit includes a first programmable delay circuit that delays a first pulse corresponding to the input pulse to generate the first delayed pulse, a second programmable delay circuit that delays a second pulse corresponding to the input pulse to generate the second delayed pulse, a latch circuit that latches the first delayed pulse in response to an edge of the second delayed pulse, and a controller that controls the delay of the second programmable delay circuit. The controller is capable of performing a first process that continuously sweeps the delay of the second programmable delay circuit to detect the first delay amount when the output of the latch circuit changes, and a second process that changes the delay of the second programmable delay circuit by binary search to detect the second delay amount when the output of the latch circuit changes. The difference between the first delay amount and the second delay amount is defined as the pulse width of the input pulse.

[0006] Another aspect of the present disclosure relates to a method for measuring the pulse width of an input pulse. The method includes a step of: a first programmable delay circuit delaying a first pulse corresponding to the input pulse to generate a first delayed pulse; a step of a second programmable delay circuit delaying a second pulse corresponding to the input pulse to generate a second delayed pulse; a step of a latch circuit latching the first delayed pulse in response to an edge of the second delayed pulse; and a control step of controlling the delay of the second programmable delay circuit. The control step includes a first step of continuously sweeping the delay of the second programmable delay circuit to detect the first delay amount when the output of the latch circuit changes; and a second step of changing the delay of the second programmable delay circuit by binary search to detect the second delay amount when the output of the latch circuit changes. The difference between the first delay amount and the second delay amount is defined as the pulse width of the input pulse.

[0007] Any combination of the above elements, or mutual substitution of elements or expressions between methods, devices, systems, etc., are also valid aspects of the present invention or the present disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a circuit diagram of a pulse width measurement circuit according to an embodiment. [Figure 2] FIG. 2 is a diagram illustrating a first process of pulse width measurement by the pulse width measurement circuit. [Figure 3] FIG. 3 is a diagram illustrating a second process of pulse width measurement by the pulse width measurement circuit.

[0009] [Detailed explanation] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0010] A pulse width measurement circuit according to one embodiment includes a first programmable delay circuit that delays a first pulse corresponding to an input pulse to generate a first delayed pulse, a second programmable delay circuit that delays a second pulse corresponding to the input pulse to generate a second delayed pulse, a latch circuit that latches the first delayed pulse in response to an edge of the second delayed pulse, and a controller that controls the delay of the second programmable delay circuit. The controller is capable of performing a first process that continuously sweeps the delay of the second programmable delay circuit to detect the first delay amount when the output of the latch circuit changes, and a second process that changes the delay of the second programmable delay circuit by binary search to detect the second delay amount when the output of the latch circuit changes. The pulse width measurement circuit determines the difference between the first delay amount and the second delay amount as the pulse width of the input pulse.

[0011] One possible method for measuring the pulse width is to search for the position of the positive edge (rising edge) and the position of the negative edge (falling edge) of the first pulse by sweeping the delay amount of the second programmable delay circuit. This method has the problem that the longer the pulse width, the longer the pulse width measurement time. In contrast, the configuration according to one embodiment allows the pulse width to be measured in a short time.

[0012] In one embodiment, in the second process, when the delay amount to be set in the second programmable delay circuit is smaller than the first delay amount, the controller may skip measurement by assuming that the output of the latch circuit is high, thereby shortening the measurement time for the pulse width.

[0013] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0014] In this specification, "a state in which component A is connected to component B" includes a case in which component A and component B are directly physically connected, and a case in which component A and component B are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the function or effect achieved by their combination.

[0015] Similarly, "a state in which component C is provided between component A and component B" includes not only cases in which components A and C, or components B and C, are directly connected, but also cases in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the functions or effects achieved by their combination.

[0016] In addition, the vertical and horizontal axes of the waveform diagrams and time charts shown in this specification have been appropriately enlarged or reduced to facilitate understanding, and each waveform shown has also been simplified to facilitate understanding.

[0017] (Embodiment) 1 is a circuit diagram of a pulse width measurement circuit 100 according to an embodiment. The pulse width measurement circuit 100 measures an input pulse S INThe pulse width measurement circuit 100 includes a first pulse generator 110, a second pulse generator 120, a first programmable delay circuit 130, a second programmable delay circuit 140, a latch circuit 150, and a controller 160.

[0018] The first pulse generator 110 generates an input pulse S IN Upon receiving the input pulse S IN The second pulse generator 120 generates a first pulse S1 according to the input pulse S IN Upon receiving the input pulse S IN The first pulse generator 110 and the second pulse generator 120 generate a second pulse S2 according to the input pulse S IN A comparator may be included that compares the first pulse S1 and the second pulse S2 with a threshold voltage. In this embodiment, the first pulse S1 and the second pulse S2 are replicas of pulses having the same waveform and phase.

[0019] The first programmable delay circuit 130 delays the first pulse S1 to generate a first delay pulse Sd1. The second programmable delay circuit 140 delays the second pulse S2 to generate a second delay pulse Sd2. The delay amounts τ1 and τ2 of the first programmable delay circuit 130 and the second programmable delay circuit 140 can be controlled as an integer multiple of the unit delay τ. Here, the delay amount τ1 of the first programmable delay circuit 130 is assumed to be fixed.

[0020] The first programmable delay circuit 130 includes an input buffer 131, a plurality of delay elements 132, a plurality of multiplexers 134, an output buffer 135, and a decoder 136. The delay amounts of the plurality of delay elements 132 are binary-weighted. The multiplexer 134 receives the output signal of the corresponding delay element 132 and the input signal before delay. The decoder 136 controls the states of the plurality of multiplexers 134 in response to a control signal CTRL1.

[0021] The second programmable delay circuit 140 is configured similarly to the first programmable delay circuit 130, and includes an input buffer 141, a plurality of delay elements 142, a plurality of multiplexers 144, an output buffer 145, and a decoder 146. The decoder 146 controls the states of the plurality of multiplexers 144 in response to a control signal CTRL2.

[0022] The configurations of the first programmable delay circuit 130 and the second programmable delay circuit 140 are not limited to that shown in FIG.

[0023] The latch circuit 150 latches the first delay pulse Sd1, which is the output of the first programmable delay circuit 130, in response to a positive edge of the second delay pulse Sd2, which is the output of the second programmable delay circuit 140.

[0024] The controller 160 controls the delay amounts τ1 and τ2 of the first programmable delay circuit 130 and the second programmable delay circuit 140 to delay the input pulse S IN Measure the pulse width Tp.

[0025] The controller 160 fixes the delay amount τ1 of the first programmable delay circuit 130, continuously sweeps the delay amount τ2 of the second programmable delay circuit 140, and detects the delay amount (called the first delay amount τp) when the output Q of the latch circuit 150 changes. This is called the first process. The first delay amount τp is calculated by dividing the delay amount τ1 by the input pulse S IN The delay amount of the first programmable delay circuit 130 should preferably be set small.

[0026] Next, the controller 160 changes the delay amount τ2 of the second programmable delay circuit 140 by binary search to detect the delay amount (second delay amount τn) when the output Q of the latch circuit 150 changes. In other words, a successive approximation process is performed to determine the delay amount bit by bit from the most significant bit to the least significant bit. This is called the second process. At this time, for delay amounts smaller than the first delay amount τp, the process is performed assuming that the output Q of the latch circuit 150 is high. The second delay amount τn is determined by the time the input pulse S IN indicates the position of the negative edge of

[0027] The controller 160 calculates the difference between the second delay amount τn and the first delay amount τp as a function of the input pulse S IN The pulse width is Tp.

[0028] The above is the configuration of the pulse width measurement circuit 100. Next, the operation will be described.

[0029] 2 is a diagram illustrating the first process performed by the pulse width measurement circuit 100. For ease of understanding, it is assumed here that the control signal CTRL2 has five bits, and that the delay amount τ1 of the first programmable delay circuit 130 is 9×τ.

[0030] In the first process, the delay amount τ2 increases by one unit delay τ from 0×τ. Then, in the range of τ2=0 to 9×τ, the output Q of the latch circuit 150 is low (L), and when τ2=10×τ, the output Q of the latch circuit 150 becomes high (H). Therefore, the first delay amount τp, which indicates the position of the positive edge, is τ×9.

[0031] FIG. 3 is a diagram illustrating the second process performed by the pulse width measurement circuit 100. In FIG.

[0032] In the second process, the delay amount τ2 is changed by a binary search. Initially, the control signal CTRL2 is set to

[10000] in binary, and the delay amount τ2 is 16×τ. At this time, the output Q of the latch circuit 150 becomes low (L).

[0033] The next control signal CTRL2 becomes

[1000] , and the delay τ2 becomes 8 × τ. This delay τ2 is smaller than the first delay τp determined in the first process. Therefore, although the output Q of the latch circuit 150 should be low, it is considered to be high, and the control signal CTRL2 =

[1000] is not actually set in the second programmable delay circuit 140, and one measurement is skipped.

[0034] As a result of the output Q of the latch circuit 150 being regarded as high,

[1100] is set in the second programmable delay circuit 140 as the next control signal CTRL2, and the delay amount τ2 becomes 12×τ. At this time, the output Q of the latch circuit 150 becomes high.

[0035] As a result of the output Q of the latch circuit 150 becoming high,

[1110] is set in the second programmable delay circuit 140 as the next control signal CTRL2, and the delay amount τ2 becomes 14×τ. At this time, the output Q of the latch circuit 150 becomes high.

[0036] As a result of the output Q of the latch circuit 150 becoming high,

[1111] is set in the second programmable delay circuit 140 as the next control signal CTRL2, and the delay amount τ2 becomes 15×τ. At this time, the output Q of the latch circuit 150 becomes high.

[0037] As a result of this binary search, the second delay amount τn indicating the position of the negative edge is 16×τ.

[0038] The pulse width Tp of the input pulse SIN is τn-τp=16×τ-9×τ=7×τ.

[0039] The above is the operation of the pulse width measurement circuit 100. The pulse width measurement circuit 100 will become clearer when compared with the comparative technology.

[0040] The pulse width measurement circuit according to comparative technique 1 has the same configuration as the pulse width measurement circuit 100 of FIG. 1, but differs in the way the controller 160 controls the delay amount. In comparative technique 1, the controller 160 fixes the delay amount τ1 of the first programmable delay circuit 130. This is the same as in the embodiment. Meanwhile, the controller 160 sweeps the delay amount τ2 of the second programmable delay circuit 140. This detects the positions of the positive and negative edges of the first pulse S1, and the difference between these is taken as the pulse width Tp. With this method, as the pulse width Tp becomes wider, the number of latches increases, lengthening the measurement time.

[0041] In this embodiment, the detection of positive edges is the same as in the first comparative technique, but the detection of negative edges can be shortened compared to the first comparative technique because a binary search is used.

[0042] The pulse width measurement circuit according to Comparative Technique 2 differs from Comparative Technique 1 in the control of the delay amount of the second programmable delay circuit 140. In Comparative Technique 2, the controller 160 fixes the delay amount τ1 of the first programmable delay circuit 130. This is the same as in the embodiment.

[0043] The controller 160 detects the positive edge of the delay amount τ2 of the second programmable delay circuit 140 by binary search. However, because the first delay pulse Sd1 has two low sections and one high section sandwiched between them, performing a binary search on it as is would not be able to detect the correct edge position. Therefore, in comparison technique 2, a single-edge signal (step waveform) having only a positive edge must be generated and latched with the second delay pulse Sd2. As described above, comparison technique 2 has the problem of requiring additional hardware because it is necessary to generate a single-edge signal. In contrast, in the embodiment, no additional hardware is required. This is a major advantage.

[0044] Furthermore, when the number of latches required for detecting a positive edge is compared between Comparative Technique 2 and the embodiment, there is no difference in the number of latches if the fixed first delay amount τ1 is made small.

[0045] In this way, the pulse width measurement circuit 100 according to the embodiment makes it possible to measure the pulse width Tp in a short time.

[0046] Finally, a modified example will be described.

[0047] In the embodiment, when the delay amount τ2 to be set in the second programmable delay circuit 140 is smaller than the first delay amount τp in the second process, measurement is skipped, but the present disclosure is not limited to this. In a modified example, even in this case, the output Q of the latch circuit 150 may actually be measured, and the output Q measured as low may be regarded as high, and the process may proceed to the next step.

[0048] The pulse width measurement circuit 100 of FIG. 1 generates a first pulse S1 and a second pulse S2 by a first pulse generator 110 and a second pulse generator 120. IN If the output impedance of the circuit that generates the pulses is sufficiently low, in other words, if the driving capability is sufficiently high, the first pulse generator 110 and the second pulse generator 120 may be omitted.

[0049] (Addendum) The present specification discloses the following techniques.

[0050] (Item 1) A pulse width measurement circuit for measuring the pulse width of an input pulse, a first programmable delay circuit that delays a first pulse corresponding to the input pulse to generate a first delayed pulse; a second programmable delay circuit that delays a second pulse corresponding to the input pulse to generate a second delayed pulse; a latch circuit that latches the first delay pulse in response to an edge of the second delay pulse; a controller for controlling the delay amount of the second programmable delay circuit; Equipped with The controller a first process for continuously sweeping the delay amount of the second programmable delay circuit and detecting a first delay amount when the output of the latch circuit changes; a second process of detecting a second delay amount when the output of the latch circuit changes by changing the delay amount of the second programmable delay circuit by binary search; and a difference between the first delay amount and the second delay amount is set as the pulse width of the input pulse.

[0051] (Item 2) 2. The pulse width measurement circuit according to claim 1, wherein, in the second process, when the delay amount to be set in the second programmable delay circuit is smaller than the first delay amount, the controller considers the output of the latch circuit to be high and skips measurement.

[0052] (Item 3) A method for measuring the pulse width of an input pulse, comprising: a first programmable delay circuit delaying a first pulse corresponding to the input pulse to generate a first delayed pulse; a second programmable delay circuit delaying a second pulse in response to the input pulse to generate a second delayed pulse; a latch circuit latching the first delayed pulse in response to an edge of the second delayed pulse; a control step of controlling the delay amount of the second programmable delay circuit; Equipped with The control step a first step of continuously sweeping the delay amount of the second programmable delay circuit and detecting a first delay amount when the output of the latch circuit changes; a second step of detecting a second delay amount when the output of the latch circuit changes by changing the delay amount of the second programmable delay circuit by binary search; Including, A measurement method in which the difference between the first delay amount and the second delay amount is set as the pulse width of the input pulse.

[0053] (Item 4) 4. The measurement method according to item 3, wherein, in the second step, when the delay amount to be set in the second programmable delay circuit is smaller than the first delay amount, the output of the latch circuit is considered to be high, and measurement is skipped. [Explanation of symbols]

[0054] 100 Pulse width measurement circuit 110 First pulse generator 120 Second Pulse Generator 130 First programmable delay circuit 140 Second programmable delay circuit 150 Latch Circuit 160 Controller S IN Input pulse S1 First pulse S2 Second pulse Sd1 First delay pulse Sd2 Second delay pulse

Claims

1. A pulse width measurement circuit for measuring the pulse width of an input pulse, a first programmable delay circuit that delays a first pulse corresponding to the input pulse to generate a first delayed pulse; a second programmable delay circuit that delays a second pulse corresponding to the input pulse to generate a second delayed pulse; a latch circuit that latches the first delay pulse in response to an edge of the second delay pulse; a controller for controlling the delay amount of the second programmable delay circuit; Equipped with The controller a first process for continuously sweeping the delay amount of the second programmable delay circuit and detecting a first delay amount when the output of the latch circuit changes; a second process of detecting a second delay amount when the output of the latch circuit changes by changing the delay amount of the second programmable delay circuit by binary search; and a difference between the first delay amount and the second delay amount is set as the pulse width of the input pulse.

2. 2. The pulse width measurement circuit according to claim 1, wherein, in the second process, when the delay amount to be set in the second programmable delay circuit is smaller than the first delay amount, the controller considers the output of the latch circuit to be high and skips measurement.

3. A method for measuring the pulse width of an input pulse, comprising: a first programmable delay circuit delaying a first pulse in response to the input pulse to generate a first delayed pulse; a second programmable delay circuit delaying a second pulse in response to the input pulse to generate a second delayed pulse; a latch circuit latching the first delayed pulse in response to an edge of the second delayed pulse; a control step of controlling the delay amount of the second programmable delay circuit; Equipped with The control step a first step of continuously sweeping the delay amount of the second programmable delay circuit and detecting a first delay amount when the output of the latch circuit changes; a second step of detecting a second delay amount when the output of the latch circuit changes by changing the delay amount of the second programmable delay circuit by binary search; Including, A measurement method in which the difference between the first delay amount and the second delay amount is set as the pulse width of the input pulse.

4. 4. The measuring method according to claim 3, wherein, in the second step, when the delay amount to be set in the second programmable delay circuit is smaller than the first delay amount, the output of the latch circuit is considered to be high, and measurement is skipped.

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