Semiconductor circuit and method for testing semiconductor circuit

Abstract

To provide a semiconductor circuit capable of producing multiple products with a single semiconductor circuit, control of pad connection states during testing in the semiconductor circuit being simplified, and to provide a test method for the semiconductor circuit.SOLUTION: The semiconductor circuit includes: a plurality of pads for connection to external package terminals; and a test circuit for outputting a test signal. Different types of products can be produced from the same semiconductor circuit by connecting one pad among a group of pads composed of predetermined pads to a package terminal, and the test circuit is configured to be capable of performing simultaneous driving in which a plurality of pads included in the pad group are simultaneously driven with the same output value.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor circuits and methods for testing semiconductor circuits. [Background technology]

[0002] There are known semiconductor circuits that can be connected to any macro via one pad from outside the semiconductor circuit by controlling the connection state between pads and multiple macros within the semiconductor circuit (see, for example, Patent Documents 1 to 4). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-003812 [Patent Document 2] Japanese Patent Application Publication No. 07-225258 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-077816 [Patent Document 4] Japanese Patent Application Laid-Open No. 2002-243806 Summary of the Invention [Problem to be solved by the invention]

[0004] Typically, only macros that are used in a product are formed within a semiconductor circuit. However, by forming multiple macros with different functions within the semiconductor circuit, such as macros that are used in one product but not in another, or macros that are not used in one product but are used in another, and selectively connecting package terminals of a semiconductor device that includes the semiconductor circuit to pads that are connected to some of the multiple macros, it becomes possible to create multiple types of products using a single semiconductor circuit.

[0005] In this way, in a semiconductor circuit that can be used to create multiple products, the control of pad connections during testing becomes more complex depending on the number of macros formed in the semiconductor circuit.

[0006] In consideration of the above circumstances, the present disclosure aims to provide a semiconductor circuit that can be used to create multiple products using a single semiconductor circuit, and a test method for this semiconductor circuit, in which pad connection control during testing is simplified. [Means for solving the problem]

[0007] The semiconductor circuit of the present disclosure comprises a plurality of pads for connecting to external package terminals and a test circuit for outputting test signals, and by connecting one pad from a group of a predetermined number of pads to a package terminal, it is possible to create different types of products, and the test circuit is configured to be able to simultaneously drive the multiple pads included in the pad group with the same output value.

[0008] The disclosed method for testing a semiconductor circuit is a method for testing a semiconductor circuit, in which the simultaneous driving is performed by the test circuit in a test mode, and the output test signal is simultaneously detected outside the semiconductor circuit via multiple pads. [Effects of the Invention]

[0009] According to the semiconductor circuit of the present disclosure, in a semiconductor circuit that can be used to create a plurality of different products using a single semiconductor circuit, it is possible to simplify the connection control of pads during testing.

[0010] According to the semiconductor circuit testing method of the present disclosure, it is possible to check the operation of a semiconductor circuit with simplified pad connection control. [Brief explanation of the drawings]

[0011] [Figure 1]1 is a diagram illustrating a schematic configuration of a semiconductor device according to an embodiment of the present disclosure. [Figure 2] FIG. 10 is a diagram for explaining an aspect in which operation is checked using only the second chip before the first chip and the second chip are connected. [Figure 3] These are diagrams for explaining the joining of a first chip and a second chip using solder bumps, where Figure 3(A) is a diagram showing the state before the first chip and the second chip are joined, and Figure 3(B) is a diagram showing the state after the first chip and the second chip are joined. DETAILED DESCRIPTION OF THE INVENTION

[0012] Next, an embodiment of the present disclosure will be described with reference to the drawings. Fig. 1 is a diagram showing a schematic configuration of a semiconductor device 1 according to an embodiment of the present disclosure.

[0013] 1, the semiconductor device 1 of this embodiment is formed by bonding a substrate 10 and a chip 20. The chip 20 is an example of a semiconductor circuit in the technology of the present disclosure.

[0014] The substrate 10 includes a package terminal block 11 consisting of a plurality of package terminals 11a to 11n, and a package terminal block 12 consisting of a plurality of package terminals 12a to 12n.

[0015] For example, chip 20 includes macro 31, which is used in common when manufacturing multiple products, and macros 41 and 51, which are used selectively. In other words, macros 31 and 41 are used when manufacturing one product, and macros 31 and 51 are used when manufacturing another product. Note that a "macro" is a circuit block that realizes a specific function.

[0016] A macro 31 that is commonly used when separately manufacturing a plurality of products is connected to a plurality of pads 32a to 32n. A macro 41 that is selectively used when separately manufacturing a plurality of products is connected to a plurality of pads 42a to 42n. A macro 51 that is selectively used when separately manufacturing a plurality of products is connected to a plurality of pads 52a to 52n.

[0017] Since chip 20 is configured as described above, different types of products can be produced using the same chip 20 by connecting one pad from a group of a predetermined number of pads to a package terminal.

[0018] Specifically, by connecting any one of the pads in each of the pad groups consisting of pads 42a and 52a to pads 42n and 52n to package terminals 12a to 12n, different types of products can be manufactured.

[0019] 1, in this embodiment, the plurality of package terminals 11a-11n are connected by bonding wires 71a-71n to pads 32a-32n connected to the macro 31. The plurality of package terminals 12a-12n are connected by bonding wires 72a-72n to pads 52a-52n connected to the macro 51.

[0020] A macro 31, which is commonly used when creating multiple products, is connected to multiple pads 32a to 32n. Each of the pads 32a to 32n is connected to input drivers 33a to 33n and output drivers 34a to 34n. Each of the input drivers 33a to 33n is connected to input sub-test circuits 35a to 35n. Each of the output drivers 34a to 34n is connected to output sub-test circuits 36a to 36n. The input sub-test circuits 35a to 35n and output sub-test circuits 36a to 36n are connected to a main test circuit 65.

[0021] The main test circuit 65 is a higher-level test circuit that centrally controls sub-test circuits such as the input sub-test circuits 35a to 35n and the output sub-test circuits 36a to 36n. Each of the input sub-test circuits 35a to 35n is a lower-level test circuit that only performs peripheral control around the input drivers 33a to 33n. Each of the output sub-test circuits 36a to 36n is a lower-level test circuit that only performs peripheral control around the output drivers 34a to 34n.

[0022] The main test circuit 65 receives input test signals via input sub-test circuits such as the input sub-test circuits 35a to 35n. The input test signals are, for example, setting signals for changing the operating state of the chip 20.

[0023] The main test circuit 65 also transmits output test signals via output sub-test circuits such as the output sub-test circuits 36a to 36n. The output test signals are, for example, signals for checking the connections between the package terminals and the pads, or signals indicating the results of predetermined test processing in the main test circuit 65.

[0024] When an "H" signal is input to the input enable signal lines IE35a to IE35n, the input drivers 33a to 33n output the input test signals input from the pads 32a to 32n to the input test signal lines DI35a to DI35n, respectively.

[0025] When an "H" signal is input to the output enable signal lines OE36a to OE36n, the output drivers 34a to 34n output the output test signals input from the output test signal lines DO36a to DO36n to the pads 32a to 32n, respectively.

[0026] In this embodiment, only one macro 31 is connected to each of the pads 32a-32n. If multiple macros are connected to the pads 32a-32n, the parasitic capacitance of the unused macros will be added to the pads 32a-32n, making it difficult to increase the maximum transfer speed of each of the pads 32a-32n during normal operation of the used macros. In contrast, in this embodiment, because only one macro 31 is connected to each of the pads 32a-32n, the maximum transfer speed of each of the pads 32a-32n during normal operation can be set to 100 Mbps or more.

[0027] A macro 41, which is selectively used when creating multiple products, is connected to multiple pads 42a-42n. Each of the pads 42a-42n is connected to an input driver 43a-43n and an output driver 44a-44n. Each of the input drivers 43a-43n is connected to an input sub-test circuit 45a-45n. Each of the output drivers 44a-44n is connected to an output common sub-test circuit 60a-60n. The input sub-test circuits 45a-45n and the output common sub-test circuits 60a-60n are connected to a main test circuit 65.

[0028] When an "H" signal is input to the input enable signal lines IE45a to IE45n, the input drivers 43a to 43n output the input test signals input from the pads 42a to 42n to the input test signal lines DI45a to DI45n, respectively.

[0029] When an "H" signal is input to the common output enable signal lines OE60a to OE60n, the output drivers 44a to 44n output the output test signals input from the common output test signal lines DO60a to DO60n to the pads 42a to 42n.

[0030] Since only one macro 41 is connected to each of the pads 42a to 42n, as described above, the maximum transfer rate of each of the pads 52a to 52n can be set to 100 Mbps or more during normal operation.

[0031] A macro 51, which is selectively used when creating multiple products, is connected to multiple pads 52a-52n. Each of the pads 52a-52n is connected to an input driver 53a-53n and an output driver 54a-54n. Each of the input drivers 53a-53n is connected to an input sub-test circuit 55a-55n. Each of the output drivers 54a-54n is connected to an output common sub-test circuit 60a-60n. The input sub-test circuits 55a-55n and the output common sub-test circuits 60a-60n are connected to a main test circuit 65.

[0032] When an "H" signal is input to the input enable signal lines IE55a to IE55n, the input drivers 53a to 53n output the input test signals input from the pads 52a to 52n to the input test signal lines DI55a to DI55n, respectively.

[0033] When an "H" signal is input to the common output enable signal lines OE60a to OE60n, the output drivers 54a to 54n output the output test signals input from the common output test signal lines DO60a to DO60n to the pads 52a to 52n.

[0034] Since only one macro 51 is connected to each of the pads 52a to 52n, as described above, the maximum transfer rate of each of the pads 52a to 52n can be set to 100 Mbps or more during normal operation.

[0035] As described above, the output drivers 44a to 44n and the output drivers 54a to 54n are commonly connected to the output common sub-test circuits 60a to 60n via the common output enable signal lines OE60a to OE60n and the common output test signal lines DO60a to DO60n.

[0036] Therefore, the output drivers 44a to 44n and the output drivers 54a to 54n each receive the same signal from the common output enable signal lines OE60a to OE60n, and output the same output test signal input from the common output test signal lines DO60a to DO60n.

[0037] In this way, by commonly connecting the output common sub-test circuits 60a to 60n to the output drivers 44a to 44n and the output drivers 54a to 54n, the configuration of the semiconductor device 1 can be simplified compared to the case where different output sub-test circuits are individually connected to the output drivers 44a to 44n and the output drivers 54a to 54n.

[0038] Furthermore, by making the above connections, the main test circuit 65 outputs test signals of the same output value to the pads 42a to 42n connected to the output drivers 44a to 44n and the pads 52a to 52n connected to the output drivers 54a to 54n, thereby driving them all at once.

[0039] Therefore, in the test mode, the connection control of the pads 42a to 42n and the pads 52a to 52n by the main test circuit 65 can be simplified compared to when test signals are output individually to the pads 42a to 42n and the pads 52a to 52n.

[0040] Next, the operation of the semiconductor device 1 of this embodiment in the test mode will be described.

[0041] First, the operation in the test mode using the pads 32a to 32n connected to the macro 31 that is used in common when separately manufacturing a plurality of products will be described.

[0042] Input drivers 33a to 33n and output drivers 34a to 34n are connected to the pads 32a to 32n, respectively.

[0043] When inputting test signals to the pads 32a to 32n, the main test circuit 65 inputs an "H" signal to the input enable signal lines IE35a to IE35n, enabling the input drivers 33a to 33n to output the test signals input from the pads 32a to 32n to the input test signal lines DI35a to DI35n.

[0044] In this state, a test signal is input from outside the semiconductor device 1 via the package terminals 11a to 11n, and the input test signal is received by the main test circuit 65.

[0045] When inputting the test signal to the pads 32a to 32n, the signal may be input to all pads simultaneously, or may be input to each pad or multiple pads in sequence, or may be input to only some of the pads.

[0046] Furthermore, when outputting test signals from the pads 32a to 32n, the main test circuit 65 inputs an "H" signal to the output enable signal lines OE36a to OE36n, enabling the output drivers 34a to 34n to output the test signals input from the output test signal lines DO36a to DO36n to the pads 32a to 32n.

[0047] In this state, a test signal is output from the main test circuit 65 and the output test signal is detected outside the semiconductor device 1.

[0048] When the test signal is output from the pads 32a to 32n, the signal may be output to all pads simultaneously, or may be output sequentially to each pad or to multiple pads, or may be output to only some of the pads.

[0049] Next, a description will be given of the operation in a test mode using pads 52a to 52n connected to a macro 51 that is selectively used when producing a plurality of products.

[0050] Input drivers 53a to 53n and output drivers 54a to 54n are connected to the pads 52a to 52n, respectively.

[0051] When inputting test signals to the pads 52a to 52n, the main test circuit 65 inputs an "H" signal to the input enable signal lines IE55a to IE55n, enabling the input drivers 53a to 53n to output the test signals input from the pads 52a to 52n to the input test signal lines DI55a to DI55n.

[0052] In this state, a test signal is input from outside the semiconductor device 1 via the package terminals 12a to 12n, and the input test signal is received by the main test circuit 65.

[0053] When inputting a test signal to pads 52a to 52n, the signal may be input to all pads simultaneously, or may be input sequentially to each pad or to multiple pads, or may be input to only some of the pads.

[0054] Furthermore, when outputting test signals from the pads 52a to 52n, the main test circuit 65 inputs an "H" signal to the common output enable signal lines OE60a to OE60n, enabling the output drivers 54a to 54n to output the test signals input from the common output test signal lines DO60a to DO60n to the pads 52a to 52n.

[0055] In this state, a test signal is output from the main test circuit 65 and the output test signal is detected outside the semiconductor device 1.

[0056] When the test signal is output from the pads 52a to 52n, the signal may be output to all pads simultaneously, or may be output sequentially to each pad or to multiple pads, or may be output to only some of the pads.

[0057] In this embodiment, the chip 20 may be tested as a standalone device before connecting the substrate 10 to the chip 20, as shown in Fig. 2. In Fig. 2, the macro 31 and its peripheral circuits are omitted.

[0058] When inputting test signals to the pads 42a to 42n, the main test circuit 65 inputs an "H" signal to the input enable signal lines IE45a to IE45n, enabling the input drivers 43a to 43n to output the test signals input from the pads 42a to 42n to the input test signal lines DI45a to DI45n.

[0059] In this state, the probes 80a to 80n are brought into contact with the pads 42a to 42n, and test signals are input via the probes 80a to 80n. The input test signals are then received by the main test circuit 65.

[0060] When inputting the test signal to the pads 42a to 42n, the signal may be input to all pads simultaneously, or may be input sequentially to each pad or to multiple pads, or may be input to only some of the pads.

[0061] Furthermore, when inputting test signals to the pads 52a to 52n, the main test circuit 65 inputs an "H" signal to the input enable signal lines IE55a to IE55n, enabling the input drivers 53a to 53n to output the test signals input from the pads 52a to 52n to the input test signal lines DI55a to DI55n.

[0062] In this state, the probes 81a to 81n are brought into contact with the pads 52a to 52n, and test signals are input via the probes 81a to 81n. The input test signals are then received by the main test circuit 65.

[0063] When inputting a test signal to pads 52a to 52n, the signal may be input to all pads simultaneously, or may be input sequentially to each pad or to multiple pads, or may be input to only some of the pads.

[0064] As explained above, the output drivers 44a to 44n and the output drivers 54a to 54n are each commonly connected to the output common sub-test circuits 60a to 60n, so that test signals of the same output value are output from the pads 42a to 42n and the pads 52a to 52n, and are driven simultaneously.

[0065] Therefore, when test signals are output from the pads 42a to 42n and the pads 52a to 52n, they must be detected simultaneously from the pads 42a to 42n and the pads 52a to 52n.

[0066] When outputting test signals from pads 42a to 42n and pads 52a to 52n, the main test circuit 65 inputs an "H" signal to the common output enable signal lines OE60a to OE60n, enabling the output drivers 44a to 44n and output drivers 54a to 54n to output the test signals input from the common output test signal lines DO60a to DO60n to pads 42a to 42n and pads 52a to 52n.

[0067] In this state, the probes 80a to 80n are brought into contact with the pads 42a to 42n, and the probes 81a to 81n are brought into contact with the pads 52a to 52n, and the test signals output from the pads 42a to 42n and pads 52a to 52n are received by the probes 80a to 80n and probes 81a to 81n.

[0068] When outputting test signals from pads 42a to 42n and pads 52a to 52n, the signals may be output simultaneously to all pads, or may be output sequentially for each pair or for each set of pads 42a and 52a to pads 42n and 52n, or may be output for only some of the sets.

[0069] [Variations] Although the semiconductor device 1 according to one embodiment of the present disclosure has been described above, the present disclosure is not limited to the above embodiment and can be modified as appropriate.

[0070] For example, the connection between the package terminal block 11 of the substrate 10 and the pads 32a to 32n connected to the macro 31 of the chip 20 is not limited to the connection by the bonding wires 71a to 71n, but may be the connection by solder bumps.

[0071] Similarly, the connection between the package terminal block 12 of the substrate 10 and the pads 42a to 42n connected to the macro 41 of the chip 20 or the pads 52a to 52n connected to the macro 51 is not limited to the connection by the bonding wires 72a to 72n, but may also be the connection by the solder bumps.

[0072] Here, a configuration in which connections are made using solder bumps will be described with reference to Fig. 3. As an example, the connection between package terminal block 12 of substrate 10 and pads 52a-52n connected to macro 51 of chip 20 will be described, but connections to other pads are similar. Note that Fig. 3 only shows package terminals 12a-12n and pads 52a-52n connected by solder bumps 73a-73n, and omits other components.

[0073] As shown in FIG. 3(A), solder bumps 73a to 73n are formed on package terminals 12a to 12n of package terminal block 12 of substrate 10 and on one of pads 52a to 52n connected to macro 51 of chip 20 (package terminals 12a to 12n in FIG. 3).

[0074] In this state, the substrate 10 and the chip 20 are stacked so that the package terminals 12a to 12n and the pads 52a to 52n face each other, and as shown in FIG. 3(B), the solder bumps 73a to 73n are melted by reflow, thereby electrically connecting the package terminals 12a to 12n and the pads 52a to 52n.

[0075] The package terminals 12a to 12n also have connection portions formed on the back side (upper side in FIG. 3(B)) of the substrate 10 so that they can be connected to the outside when the substrate 10 and the chip 20 are stacked together.

[0076] Furthermore, a test system is formed by the package terminal block 12, macros 41 and 51 selectively connected to the package terminal block 12, and output common sub-test circuits 60a to 60n commonly connected to the macros 41 and 51, but the semiconductor device 1 may have multiple such test systems.

[0077] Furthermore, the number of macros selectively connected to one package terminal block is not limited to two as in the above embodiment, but may be three, four or more.

[0078] In addition to the above, appropriate changes may be made to the above-described and illustrated contents, such as deleting unnecessary parts, adding new elements, or substituting elements, within the scope of the gist of the technology of the present disclosure.

[0079] [Note] The following additional notes are provided regarding aspects included in the present disclosure.

[0080] (Appendix 1) a plurality of pads for connecting to external package terminals; a test circuit that outputs a test signal; By connecting one pad from a group of predetermined pads to a package terminal, it is possible to create different types of products. The test circuit is configured to be able to simultaneously drive a plurality of pads included in the pad group with the same output value. Semiconductor circuit.

[0081] (Appendix 2) Equipped with multiple pad groups, By connecting one pad in each pad group to a different package terminal, it is possible to create different types of products. 10. The semiconductor circuit of claim 1.

[0082] (Appendix 3) The test circuit performs the simultaneous driving in a test mode. 3. The semiconductor circuit according to claim 1 or 2.

[0083] (Appendix 4) The package terminals are connected to the pads via bonding wires or solder bumps. 4. The semiconductor circuit according to claim 1.

[0084] (Appendix 5) During normal operation, the maximum transfer speed of one pad is 100Mbps or more. 5. The semiconductor circuit according to claim 1.

[0085] (Appendix 6) A test method for a semiconductor circuit according to any one of Supplementary Notes 1 to 5, comprising: In a test mode, the simultaneous driving is performed by the test circuit; The output test signals are simultaneously detected outside the semiconductor circuit via a plurality of pads. Testing methods for semiconductor circuits. [Explanation of symbols]

[0086] 1. Semiconductor device 10 Substrate 11, 12 Package terminal block 11a~11n, 12a~12n package terminals 20 chips 31 Macro 32a~32n pads 33a~33n input drivers 34a~34n output drivers 35a~35n Input sub-test circuit 36a~36n Output sub-test circuit 41 Macro 42a~42n pads 43a~43n input drivers 44a~44n output drivers 45a~45n Input sub-test circuit 51 Macro 52a~52n pads 53a~53n input drivers 54a~54n output drivers 55a~55n Input sub-test circuit 60a~60n Output common sub-test circuit 65 Main Test Circuit 71a~71n, 72a~72n Bonding wire 73a~73n Solder bumps 80a~80n, 81a~81n probes

Claims

1. a plurality of pads for connecting to external package terminals; a test circuit that outputs a test signal; By connecting one pad from a group of predetermined pads to a package terminal, it is possible to create different types of products. The test circuit is configured to be able to simultaneously drive a plurality of pads included in the pad group with the same output value. Semiconductor circuit.

2. Equipped with multiple pad groups, By connecting one pad from each pad group to a different package terminal, it is possible to create different types of products. The semiconductor circuit according to claim 1 .

3. The test circuit performs the simultaneous driving in a test mode. The semiconductor circuit according to claim 1 .

4. The package terminals are connected to the pads via bonding wires or solder bumps. The semiconductor circuit according to claim 1 .

5. During normal operation, the maximum transfer speed of one pad is 100Mbps or more. The semiconductor circuit according to claim 1 .

6. 6. A method for testing a semiconductor circuit according to claim 1, comprising: In a test mode, the simultaneous driving is performed by the test circuit; The output test signals are simultaneously detected outside the semiconductor circuit via a plurality of pads. Testing methods for semiconductor circuits.

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