Wiring board and method of manufacturing the same

Abstract

To provide a wiring board including an insulating layer and a conductor that adheres satisfactorily to the insulating layer and has comparatively little transmission loss.SOLUTION: A wiring board 1 according to an embodiment includes: an insulating layer 110 having a first surface 110A and a second surface 110B opposite to the first surface 110A; a through-hole 110vh penetrating the insulating layer 110 from the first surface 110A to the second surface 110B; a through-conductor 13 filling the through-hole 110vh; and a conductor portion 130 formed on the first surface 110A integrally with the 13. The first surface 110A has a first region 110AR1 including the periphery of the through-hole 110vh and a second region 110AR2 other than the first region 110AR1, the surface roughness of the first region 110AR1 is greater than the surface roughness of the second region 110AR2, and the conductor portion 130 comes in contact with the entire first region 110AR1 and a part of the second region 110AR2.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a wiring board and a method for manufacturing a wiring board. [Background technology]

[0002] Patent Document 1 discloses a wiring board and a method for manufacturing the wiring board. An opening is formed in an insulating layer that constitutes the wiring board. The inner wall surface of the opening and the surface of the insulating layer near the opening are roughened to form a roughened portion. A via composed of a seed layer and an electrolytic plating layer is formed in the opening. A wiring layer is formed integrally with the via on the surface of the insulating layer around the via. The seed layer that constitutes the via and the wiring layer is formed in approximately the same region as the roughened portion. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-108637 Summary of the Invention [Problem to be solved by the invention]

[0004] In the wiring board of Patent Document 1, the vias and the wiring layer formed integrally with the vias are all in contact with the roughened portion, and it is thought that there may be cases in which the transmission loss of signals transmitted through the vias and the wiring layer is relatively large. [Means for solving the problem]

[0005] The wiring board of the present invention comprises an insulating layer having a first surface and a second surface opposite to the first surface, a through hole penetrating the insulating layer from the first surface to the second surface, a through conductor filling the through hole, and a conductor portion formed integrally with the through conductor on the first surface, wherein the first surface has a first region including the periphery of the through hole and a second region other than the first region, the surface roughness of the first region being greater than the surface roughness of the second region, and the conductor portion being in contact with the entire first region and a portion of the second region.

[0006] A method for manufacturing a wiring board of the present invention includes: preparing an insulating layer having a first surface and a second surface opposite to the first surface, the insulating layer having a protective film on the first surface; irradiating a laser beam from outside the protective film toward the insulating layer to form a through hole that penetrates the protective film and the insulating layer in a thickness direction; removing the protective film from the insulating layer; and forming a through conductor in the through hole. Forming the through hole includes roughening a predetermined area from the periphery of the through hole on the first surface by irradiating it with ultraviolet laser light, and forming the through conductor includes forming a conductor portion on the first surface that is larger than the roughened area in a plan view.

[0007] According to the embodiment of the present invention, a wiring board can be provided that has a conductor portion that has relatively good adhesion between the insulating layer and the conductor portion and that has relatively little transmission loss in the transmission of high frequency signals. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing an example of a wiring substrate according to an embodiment of the present invention. [Figure 2] FIG. 2 is a partially enlarged view of the wiring board shown in FIG. [Figure 3A] 2A to 2C are diagrams showing an example of a method for manufacturing the wiring board shown in FIG. 1; [Figure 3B] 2A to 2C are diagrams showing an example of a method for manufacturing the wiring board shown in FIG. 1; [Figure 3C]2A to 2C are diagrams showing an example of a method for manufacturing the wiring board shown in FIG. 1; [Figure 3D] 2A to 2C are diagrams showing an example of a method for manufacturing the wiring board shown in FIG. 1; [Figure 3E] 2A to 2C are diagrams showing an example of a method for manufacturing the wiring board shown in FIG. 1; [Figure 3F] 2A to 2C are diagrams showing an example of a method for manufacturing the wiring board shown in FIG. 1; [Figure 3G] 2A to 2C are diagrams showing an example of a method for manufacturing the wiring board shown in FIG. 1; [Figure 3H] 2A to 2C are diagrams showing an example of a method for manufacturing the wiring board shown in FIG. 1; [Figure 3I] 2A to 2C are diagrams showing an example of a method for manufacturing the wiring board shown in FIG. 1; [Figure 3J] 2A to 2C are diagrams showing an example of a method for manufacturing the wiring board shown in FIG. 1; [Figure 3K] 2A to 2C are diagrams showing an example of a method for manufacturing the wiring board shown in FIG. 1; [Figure 3L] 2A to 2C are diagrams showing an example of a method for manufacturing the wiring board shown in FIG. 1; [Figure 3M] 2A to 2C are diagrams showing an example of a method for manufacturing the wiring board shown in FIG. 1; DETAILED DESCRIPTION OF THE INVENTION

[0009] Next, a wiring board according to one embodiment of the present invention will be described with reference to the drawings. The drawings are not intended to show the exact proportions of the components, but are instead drawn to facilitate understanding of the features of the present invention. FIG. 1 shows a cross section of a wiring board 1, which is an example of a wiring board according to this embodiment. The illustrated wiring board 1 has a laminate 100 having one surface 100A and another surface 100B opposite to the one surface 100A. A first buildup section 11 is formed on the one surface 100A. A second buildup section 12 is formed on the other surface 100B. In the following description, the laminate 100 is also referred to as a core substrate 100. The core substrate 100 has an insulating layer (core insulating layer) 10 and conductor layers (core conductor layers) 111 and 121.

[0010] In the following description of the wiring board, the side farther from the core insulating layer 10 will be referred to as the "top," "upper side," "outside," or "outside," and the side closer to the core insulating layer 10 will be referred to as the "bottom," "lower side," "inside," or "inside." Furthermore, in each insulating layer and conductor layer, the surface facing away from the core insulating layer 10 will be referred to as the "top surface," and the surface facing the core insulating layer 10 will be referred to as the "bottom surface." Therefore, for example, in the description of each element constituting the core substrate 100, the first buildup section 11, and the second buildup section 12, the side farther from the core insulating layer 10 will be referred to as the "top side," "upper," "upper layer side," "outside," or simply "top" or "outside," and the side closer to the core insulating layer 10 will be referred to as the "bottom side," "lower," "lower layer side," "inside," or simply "bottom" or "inside."

[0011] The core conductor layer 111 and the core conductor layer 121 that constitute the core substrate 100 are connected by a through conductor 113 that penetrates the core insulating layer 10 in the thickness direction. The through conductor 113 is composed of a conductor that covers the inner wall of a through hole 10th that penetrates the core insulating layer 10 in the thickness direction. In the example shown in the figure, the through conductor 113 that covers the inner wall of the through hole 10th is formed so as to have a hollow portion on the inside. The hollow portion on the inside of the through conductor 113 is filled with a filler 113f.

[0012] The first buildup section 11 is composed of insulating layers 110 and conductor layers 112 that are alternately stacked on one surface 100A of the core substrate 100. The second buildup section 12 is composed of insulating layers 120 and conductor layers 122 that are alternately stacked on the other surface 100B of the core substrate 100. The insulating layers 110 that constitute the first buildup section 11 and the insulating layers 120 that constitute the second buildup section 12 each include through conductors (via conductors) 13, 23 that connect conductor layers that are formed in contact with two surfaces that are opposite in the thickness direction.

[0013] As will be described in detail later with reference to Fig. 2, the through conductor 13 is formed integrally with the conductor that constitutes the conductor layer 112 above the through conductor 13, and the portion of this conductor layer 112 that is formed integrally with the through conductor 13 is shown as a conductor portion 130. The through conductor 23 is formed integrally with the conductor that constitutes the conductor layer 122 above the through conductor 23, and the portion of this conductor layer 122 that is formed integrally with the through conductor 23 is shown as a conductor portion 230. The conductor portions 130, 230 may have the form of, for example, a land portion.

[0014] A solder resist layer SR1 is formed on the first buildup section 11. A solder resist layer SR2 is formed on the second buildup section 12. An opening SR1o is formed in the solder resist layer SR1, and a conductor pad 112p of the outermost conductor layer 112 in the first buildup section 11 is exposed through the opening SR1o. An opening SR2o is formed in the solder resist layer SR2, and a conductor pad 122p of the outermost conductor layer 122 in the second buildup section 12 is exposed through the opening SR2o.

[0015] The conductor pad 112p may be, for example, a connection pad used for mounting an external electronic component (not shown), etc. On the other hand, the conductor pad 122p may be, for example, a connection pad used for connecting to an external motherboard (not shown), etc. A surface protection film (not shown) made of Au, Ni / Au, Ni / Pd / Au, solder, heat-resistant preflux, etc. may be formed on the exposed surfaces of the conductor pads 112p, 122p.

[0016] The core insulating layer 10, the insulating layer 110 constituting the first buildup section 11, and the insulating layer 120 constituting the second buildup section 12 are each formed using an insulating resin such as epoxy resin, bismaleimide triazine resin (BT resin), or phenolic resin. Each of the insulating layers 10, 110, and 120 may contain a reinforcing material (core material) such as glass fiber and / or an inorganic filler such as silica or alumina. In the illustrated example, the insulating layer 10 contains a core material, while the other insulating layers 110 and 120 do not contain a core material.

[0017] The solder resist layers SR1 and SR2 are formed using, for example, a photosensitive epoxy resin or a polyimide resin. The filler 113f that fills the hollow portion of the through conductor 113 may be, for example, an insulating resin such as epoxy, acrylic, or phenol. The filler 113f may also be a solidified conductive paste or conductive ink containing conductive particles such as silver particles.

[0018] The conductor layers 111, 121, 112, 122 and the through conductors 13, 23, 113 may be formed using any metal, such as copper or nickel. For example, the conductor layers 111, 121 may be formed using a metal foil, such as copper foil, and / or a metal film formed by plating, sputtering, or the like. The conductor layers 112, 122 may be formed using a metal film formed by plating, sputtering, or the like. The conductor layers 111, 121, 112, 122 and the through conductors 13, 23, 113 are shown in FIG. 1 as a simplified single-layer structure for ease of viewing, but may have a multilayer structure of two or more layers. The conductor layers 111, 121 may have a five-layer structure including a metal foil, a metal film layer (e.g., an electroless copper-plated film), and an electrolytic plated film layer (e.g., an electrolytic copper-plated film). The conductor layers 112, 122 and the through conductors 13, 23, 113 may have, for example, a two-layer structure including a metal film layer (for example, an electroless copper plating film) and an electrolytic plating film layer.

[0019] Each of the conductor layers 111, 121, 112, and 122 included in the wiring board 1 is patterned to have a predetermined conductor pattern. In the core substrate 100 included in the wiring board 1 of the illustrated example, the conductor layers 111 and 121 are formed in a pattern having lands formed integrally with the through-hole conductors 113. The conductor layer 112 is formed in a pattern including a conductor portion 130 formed integrally with the through conductors 13 formed in the insulating layer 110. The conductor layer 122 is formed in a pattern including a conductor portion 230 formed integrally with the through conductors 23 formed in the insulating layer 120. The wiring board of the embodiment includes at least the insulating layer 110, the through conductors 13 formed in the insulating layer 110, and the conductor portion 130 formed integrally with the through conductors 13.

[0020] Next, with reference to FIG. 2, which is an enlarged view of an area II enclosed by a dashed line in FIG. 1, the insulating layer 110, the through conductor 13, and the conductor portion 130, which are at least included in the wiring board of the embodiment, will be described in detail.

[0021] The insulating layer 110 included in the wiring board of the embodiment has a first surface 110A and a second surface 110B opposite to the first surface 110A. In the illustration, the first surface 110A contacts a conductor portion 130 constituting a conductor layer formed on the first surface 110A, and the second surface 110B contacts a conductor layer 111 formed below the insulating layer 110. The insulating layer 110 has a through hole 110vh formed therein, penetrating the insulating layer 110 in the thickness direction from the first surface 110A to the second surface 110B. A through conductor 13 is formed by a conductor filling the through hole 110vh. A conductor formed integrally with the through conductor 13 constitutes the conductor portion 130 on the first surface 110A.

[0022] 1, the through conductor 13 and the conductor portion 130 are shown as a single layer for ease of viewing, but in FIG. 2, they are shown as a two-layer structure consisting of a metal film layer 112a, for example, an electroless copper plating film, and a plating film layer 112b, for example, an electrolytic copper plating film layer. In the illustrated example, the through conductor 13 is a so-called filled via that fills the through hole 110vh, and is composed of a metal film layer 112a and a plating film layer 112b that cover the bottom and inner wall surface (side surface) of the through hole 110vh. The conductor portion 130, which is formed integrally with the through conductor 13 on the first surface 100A, is composed of a metal film layer 112a that contacts the first surface 110A and a plating film layer 112b on the metal film layer 112a.

[0023] In the illustrated example, the through hole 110vh (the through conductor 13) has a tapered shape that narrows from the first surface 110A toward the opposite second surface 110B, but the shape of the through hole 110vh is not limited to this. The through hole 110vh may be formed in a cylindrical shape that has a substantially constant diameter in the thickness direction of the insulating layer 110 and is substantially perpendicular to the conductor layer 112. Although the term "reduced diameter" is used for convenience, the opening shape of the through hole 110vh in a planar view is not necessarily limited to a circular shape. The "diameter" refers to the linear distance between the two most distant points on the outer edge of an object when viewed from above. The "reduced diameter" simply means that the linear distance between the two most distant points on the outer edge of the through hole 110vh in a horizontal cross section becomes smaller. The "planar view" refers to the view of the object from a line of sight parallel to the thickness direction of the wiring board 1 (i.e., the thickness direction of the insulating layer 110).

[0024] The through-hole 110vh may be formed so that the diameter of the opening of the through-hole 110vh on the first surface 110A is, for example, 7 μm or more and 18 μm or less. The conductor portion 130, which may be formed as a land, may have any shape in plan view, such as a circle or a rectangle. The conductor portion 130 may be formed so that the diameter is 14 μm or more and 25 μm or less.

[0025] The first surface 110A of the insulating layer 110 included in the wiring board of the embodiment has at least two regions with different surface roughnesses: a first region 110AR1 and a second region 110AR2. Specifically, as shown in the figure, the first region 110AR1 is a region that includes the periphery of the opening of the through-hole 110vh on the first surface 110A and extends over a predetermined range from the periphery of the opening, and has a different surface roughness from that of the second region 110AR2. The second region 110AR2 is a region that extends around the first region 110AR1 on the first surface 110A. The surface roughness of the first region 110AR1 is greater than the surface roughness of the second region 110AR2.

[0026] Specifically, the first region 110AR1 extends over an area in which the extension from the periphery of the through hole 110vh in plan view is 1.5 μm or more and 8 μm or less. The extension from the periphery of the through hole 110vh refers to the shortest linear distance from any point on the periphery of the through hole 110vh to the outer edge of the first region 110AR1 (the boundary with the second region 110AR2). The surface roughness of the first region 110AR1 may be, for example, 0.35 μm or more and 0.8 μm or less in arithmetic mean roughness Ra. The second region 110AR2 is, for example, a region covering the entire area of ​​the first surface 110A other than the first region 110AR1. The surface roughness of the second region 110AR2 may be, for example, 0.05 μm or more and 0.5 μm or less in arithmetic mean roughness Ra.

[0027] The conductor portion 130, which is formed on the first surface 100A integrally with the through conductor 13, is formed on the first region 110AR1 and the second region 110AR2. Specifically, the metal film layer 112a constituting the conductor portion 130 contacts the entire first region 110AR1 and a portion of the second region 110AR2. The conductor portion 130, which is formed integrally with the through conductor 13, contacts the insulating layer 110 in the first region 110AR1, which has a relatively large surface roughness, thereby enabling the conductor portion 130 and the through conductor 13 to adhere relatively firmly to the insulating layer 110. In addition, the conductor portion 130 contacts the insulating layer 110 also in the second region 110AR2, which has a relatively small surface roughness, which may improve the quality of signal transmission via the conductor portion 130. Specifically, in general, a conductor having a surface with a large surface roughness may have reduced transmission characteristics during high-frequency signal transmission due to an increase in effective impedance caused by the skin effect. In contrast, in the wiring board of the embodiment, the conductor 130 is in contact with the second region 110AR2 on the first surface 110A, which has a relatively small surface roughness, and the surface of the conductor 130 that is in contact with the second region 110AR2 has a relatively small surface roughness. Therefore, it is thought that the deterioration of the transmission characteristics of high-frequency signals in the conductor 130 can be suppressed.

[0028] In order to prevent degradation of the transmission characteristics of high-frequency signals, it is preferable that the inner wall surface of the through hole 110vh has a relatively small surface roughness. The surface roughness of the inner wall surface of the through hole 110vh is preferably smaller than the surface roughness of the first region 110AR1. The surface roughness of the inner wall surface of the through hole 110vh may be, for example, 0.15 μm or more and 0.6 μm or less in arithmetic mean roughness Ra. Note that the surface roughness of the second region 110AR2 may sometimes be smaller than the surface roughness of the inner wall surface of the through hole 110vh.

[0029] Next, an example of a method for manufacturing a wiring board according to an embodiment will be described with reference to Figures 3A to 3M, taking as an example the case where wiring board 1 shown in Figure 1 is manufactured. Of Figures 3A to 3M, Figures 3A to 3C and 3L to 3M illustrate the range corresponding to Figure 1, with each conductor layer shown as a single layer. Figures 3D to 3K illustrate the range corresponding to Figure 2, with each of the multiple layers (metal film layers and plating film layers) that make up the conductor layer shown.

[0030] First, as shown in FIG. 3A, a core insulating layer 10 is prepared. A through hole 10th is formed in the core insulating layer 10 at a position where a through conductor 113 (see FIG. 1) is to be formed. A metal foil (not shown) made of any metal having suitable conductivity may be provided on both surfaces of the core insulating layer perpendicular to the thickness direction. That is, a double-sided copper-clad laminate may be used as the core insulating layer 10. The through hole 10th may be formed, for example, by drilling the core insulating layer 10 or by laser processing using a carbon dioxide laser or other laser beam. In the example of FIG. 3A, the through hole 10th has a substantially constant width in the thickness direction of the core insulating layer 10 and a columnar shape.

[0031] 3B, a through conductor 113 that covers the inner wall of the through hole 10th and core conductor layers 111 and 121 that cover both sides of the core insulating layer 10 are integrally formed. In forming the through conductor 113 and the core conductor layers 111 and 121, a metal film layer is first formed on the inner wall surface of the through hole 10th and on the metal foil (not shown) on the surface of the core insulating layer 10 by, for example, electroless plating or sputtering. Next, an electrolytic plating film layer is formed on the metal film layer by electrolytic plating using the metal film layer as a power supply layer, and a through conductor 113 having a two-layer structure (single layer in the figure) of the metal film layer and the electrolytic plating film layer is formed on the inner wall surface of the through hole 10th. Next, the hollow portion inside the through conductor 113 is filled with a filler 113f, which is, for example, a resin such as epoxy, acrylic, or phenol.

[0032] Furthermore, on the upper side of the core insulating layer 10, a metal film layer and an electrolytic plated film layer are sequentially formed on the electrolytic plated film layer and the filler material 113f, resulting in the formation of conductor layers 111, 121 having a five-layer structure (single layer in the figure). The conductor layers 111, 121 are patterned, for example, by etching using an etching mask with openings in appropriate positions. The conductor layers 111, 121 can be formed in this manner using a subtractive method. This completes the formation of the core substrate 100 having one surface 100A and the other surface 100B.

[0033] Next, as shown in FIG. 3C , an insulating layer 110 is laminated on one surface 100A of the core substrate 100, and through holes 110vh are formed therein. Furthermore, a conductor layer 112 is formed on the insulating layer 110. The through conductors 13 are formed simultaneously with the formation of the conductor layer 112. The conductor layer 112 is formed to have, as its pattern, conductor portions 130 that are integral with the through conductors 13. An insulating layer 120 is laminated on the other surface 100B of the core substrate 100, and through holes 120vh are formed therein. Furthermore, a conductor layer 122 is formed on the insulating layer 120. The through conductors 23 are formed simultaneously with the formation of the conductor layer 122. The conductor layer 122 is formed to have, as its pattern, conductor portions 230 that are integral with the through conductors 23.

[0034] The method for manufacturing a wiring board according to the embodiment includes at least the formation of an insulating layer 110, the formation of through holes 110vh, and the formation of through conductors 13 and conductor portions 130 integral with the through conductors 13, which have been described with reference to Fig. 3C. The steps described with reference to Fig. 3C will be described in detail with reference to Figs. 3D to 3K, which correspond to the range shown in Fig. 2, regarding the formation of the insulating layer 110, the formation of through holes 110vh, and the formation of through conductors 13 and conductor portions 130 integral with the through conductors 13.

[0035] 3D, in forming the insulating layer 110, a film-like insulating resin (e.g., epoxy resin) is thermocompression bonded onto one surface 100A of the core substrate 100. The insulating layer 110 includes a protective film PF, which is, for example, a polyethylene terephthalate (PET) film, etc., covering the upper surface of the insulating layer 110.

[0036] Next, as shown in FIG. 3E, a through hole 110vh is formed in a position where the through conductor 13 (see FIG. 2) is to be formed, penetrating the protective film PF and the insulating layer 110 in the thickness direction. The through hole 110vh is formed by irradiating ultraviolet laser light from outside the protective film PF. The ultraviolet laser light used has a wavelength of 100 nm or more and 500 nm or less. The through hole 110vh can be formed so that the diameter of the opening on the first surface 110A is, for example, 7 μm or more and 18 μm or less.

[0037] As shown in the figure, the through-hole 110vh is drilled with ultraviolet laser light, resulting in a roughened inner wall surface of the through-hole 110vh formed in the insulating layer 110. At the same time, a predetermined region from the periphery of the through-hole 110vh on the first surface 110A, including the periphery, is also roughened by the ultraviolet laser light. It is believed that the protective film PF stores heat from the ultraviolet laser light, and that heat modifies and roughens the predetermined region from the periphery of the through-hole 110vh on the first surface 110A. In other words, it is believed that by irradiating ultraviolet laser light from above the protective film PF while the protective film PF is disposed on the first surface 110A, it is possible to roughen the surface around the through-hole 110vh that is in contact with the protective film PF. The predetermined region from the periphery of the through-hole 110vh on the first surface 110A can be roughened to a roughness greater than the roughness of the inner wall surface of the through-hole 110vh. The region of the first surface 110A including the periphery of the through hole 110vh that is roughened by drilling the through hole 110vh with the ultraviolet laser light corresponds to the range of the first region 110AR1 described with reference to Fig. 2. That is, for example, drilling the through hole 110vh with the ultraviolet laser light can roughen an area of ​​the first surface 110A that extends from the periphery of the through hole 110vh by 1.5 µm or more and 8 µm or less. The region that is roughened simultaneously with drilling the through hole 110vh can have a surface roughness of, for example, 0.35 µm or more and 0.8 µm or less in arithmetic mean roughness Ra.

[0038] After the through-holes 110vh are formed, a desmear process may be performed to remove process-induced defects generated in the through-holes 110vh. The desmear process may preferably be a dry desmear process using plasma gas. The desmear process may be performed while protecting the first surface 110A of the insulating layer 110, with the first surface 110A of the insulating layer 110 covered with the protective film PF.

[0039] 3F, the protective film PF is removed from the first surface 110A of the insulating layer 110. The entire first surface 110A of the insulating layer 110 and the inner surfaces (bottom surfaces and inner wall surfaces) of the through holes 110vh are exposed.

[0040] 3G, the inner wall surfaces of the through holes 110vh in the insulating layer 110 and the entire first surface 110A can be roughened by any method, such as a wet process using a solvent or a dry process in which roughening is performed in a gas phase. This roughening can result in the surface roughness of the inner wall surfaces of the through holes 110vh being, for example, 0.15 μm or more and 0.6 μm or less in arithmetic mean roughness Ra. The region of the first surface 110A including the periphery of the through holes 110vh, which was roughened in the process of forming the through holes 110vh described with reference to FIG. 3E, is roughened as a first region 110AR1 to, for example, 0.35 μm or more and 0.8 μm or less in arithmetic mean roughness Ra. The area of ​​the first surface 110A other than the first region 110AR1 is roughened as the second region 110AR2, for example, to an arithmetic mean roughness Ra of 0.05 μm or more and 0.5 μm or less. The surface roughness of the inner wall surface of the through hole 110vh, the first region 110AR1, and the second region 110AR2 can be adjusted by adjusting the ultraviolet laser light irradiation conditions during drilling of the through hole 110vh, the desmearing conditions, and the roughening conditions. In the state shown in FIG. 3G, the surface roughness of the first region 110AR1 is greater than that of the second region 110AR2. The surface roughness of the inner wall surface of the through hole 110vh may be smaller than that of the first region 110AR1. The surface roughness of the second region 110AR2 may be smaller than that of the inner wall surface of the through hole 110vh.

[0041] 3H, a metal film layer 112a, for example, an electroless copper plating film layer, is formed by electroless plating on the inner surfaces (bottom surfaces and inner wall surfaces) of the through holes 110vh and over the entire first surface 110A of the insulating layer 110. In the first region 110AR1 having a relatively large surface roughness, the insulating layer 110 and the metal film layer 112a can adhere relatively firmly to each other due to the anchor effect.

[0042] Next, as shown in FIG. 3I, a plating resist 112r for electrolytic plating is formed on the metal film layer 112a. The plating resist 112r is formed by forming a resin layer containing, for example, a photosensitive polyhydroxyether resin, epoxy resin, phenolic resin, or polyimide resin, followed by exposure and development using a mask with an appropriate opening pattern. The plating resist 112r is formed to have an opening 112ro corresponding to the conductor pattern to be formed on the conductor layer 112 (see FIG. 1) that contacts the first surface 110A of the insulating layer 110. As shown in the figure, the opening 112ro is formed so as to expose the entire through-hole 110vh, the entire first region 110AR1, and part of the second region 110AR2.

[0043] 3J, the inside of the through hole 110vh and the inside of the opening 112ro of the plating resist 112r are filled with a plating film layer 112b by electrolytic plating using the metal film layer 112a as a seed layer, thereby forming the through conductor 13 and the conductor portion 130 directly above the through conductor 13 integrally.

[0044] Next, the plating resist 112r is removed. The metal film layer 112a exposed by the removal of the plating resist 112r is removed by etching, exposing the first surface 110A of the insulating layer 110 (specifically, a portion of the second region 110AR2) as shown in FIG. 3K. The conductor portion 130 integrally formed with the through conductor 13 is formed, for example, as a land, so as to contact the entire first region 110AR1 and a portion of the second region 110AR2. As shown in FIG. 3C, the formation of the insulating layer 110, via conductor 13, and conductor layer 112 closest to the first surface 100A of the core substrate 100 is completed. The insulating layer 120, via conductor 23, and conductor layer 122 closest to the second surface 100B of the core substrate 100, which were described with reference to FIG. 3C, can be formed simultaneously with the insulating layer 110 and the conductor layer 112 by processes similar to those described with reference to FIGS. 3D to 3K. The state shown in FIG. 3C is completed.

[0045] Next, as shown in FIG. 3L, the same steps as those for forming the insulating layer 110, the conductor layer 112, and the through conductor 13 described above are repeated on the upper side of one surface 100A of the core substrate 100. The same steps as those for forming the insulating layer 120, the conductor layer 122, and the through conductor 23 described above are repeated on the other surface 100B of the core substrate 100. The formation of the first buildup section 11 and the second buildup section 12 is completed. The outermost conductor layer 112 of the first buildup section 11 can be formed in a pattern including conductor pads 112p. The outermost conductor layer 122 of the second buildup section 12 can be formed in a pattern including conductor pads 122p.

[0046] Next, as shown in FIG. 3M, a solder resist layer SR1 is formed on the first buildup section 11, and a solder resist layer SR2 is formed on the second buildup section 12. The solder resist layers SR1 and SR2 are formed, for example, by forming a resin layer containing a photosensitive epoxy resin or polyimide resin, and then exposing and developing it using a mask with an appropriate opening pattern. The solder resist layers SR1 and SR2 are formed to have openings SR1o and SR2o that expose the conductor pads 112p and 122p. A surface protection film (not shown) made of Au, Ni / Au, Ni / Pd / Au, solder, heat-resistant preflux, or the like may be formed on the exposed surfaces of the conductor pads 112p and 122p by electroless plating, solder leveling, spray coating, or the like. Through these steps, the wiring board 1 is completed.

[0047] The wiring board of the embodiment is not limited to the structure illustrated in each drawing, and the structure, shape, and material illustrated in this specification. The described wiring board 1 includes a core substrate 100, a first buildup portion 11, and a second buildup portion 12, but the wiring board of the embodiment may have a configuration that does not include the core substrate 100 and the second buildup portion 12 as long as it includes at least an insulating layer 110, a through conductor 13, and a conductor portion 130.

[0048] The method for manufacturing a wiring board according to the embodiment is not limited to the method described with reference to FIGS. 3A to 3M. In the method for manufacturing a wiring board according to the embodiment, the through-hole 110vh is formed by irradiating the insulating layer 110 with ultraviolet laser light while the insulating layer 110 is provided with a protective film PF, thereby roughening the area including the periphery of the through-hole and forming a conductor portion larger than the roughened area. For example, the through-hole conductor 13 and the conductor portion 130 may be formed only by electroless plating. Any process may be added in addition to the above-described processes, and any part of the processes described above may be omitted. [Explanation of symbols]

[0049] 1. Wiring board 10 Insulation layer (core insulation layer) 11 First build-up section 12 Second build-up section 13, 23 Through conductor (via conductor) 100 Laminate (core substrate) 110, 120 Insulation layer 111, 121 Conductor layer (core conductor layer) 112, 122 Conductor layer 113 Through conductor 130, 230 Conductor part 110AR1 1st area 110AR2 2nd area 10th, 110vh through hole SR1, SR2 solder resist layers

Claims

1. an insulating layer having a first surface and a second surface opposite the first surface; a through hole penetrating the insulating layer from the first surface to the second surface; a through conductor filling the through hole; a conductor portion formed integrally with the through conductor on the first surface; A wiring board having the first surface has a first region including a periphery of the through hole and a second region other than the first region, The surface roughness of the first region is greater than the surface roughness of the second region; The conductor portion is in contact with the entire first region and a part of the second region.

2. 2. The wiring board according to claim 1, wherein the first region is formed in a region where the expansion from the periphery of the through hole is 1.5 μm or more and 8.0 μm or less.

3. 2. The wiring board according to claim 1, wherein the surface roughness of the inner wall surface of the through hole is smaller than the surface roughness of the first region.

4. 2. The wiring board according to claim 1, wherein the surface roughness of the second region is smaller than the surface roughness of the inner wall surface of the through hole.

5. 2. The wiring board according to claim 1, wherein the arithmetic mean roughness of the first region is 0.35 [mu]m or more and 0.8 [mu]m or less.

6. 2. The wiring board according to claim 1, wherein the arithmetic mean roughness of the second region is not less than 0.05 [mu]m and not more than 0.5 [mu]m.

7. 2. The wiring board according to claim 1, wherein the arithmetic mean roughness of the inner wall surface of the through hole is 0.15 [mu]m or more and 0.6 [mu]m or less.

8. 2. The wiring board according to claim 1, wherein the diameter of the through hole on the first surface is not less than 7 [mu]m and not more than 18 [mu]m.

9. 2. A wiring board according to claim 1, wherein the conductor portion formed integrally with the through conductor is formed as a land, and the linear distance between the two furthest points on the outer edge of the conductor portion in a planar view is 14 μm or more and 25 μm or less.

10. providing an insulating layer having a first surface and a second surface opposite to the first surface, the insulating layer having a protective film on the first surface; irradiating a laser beam from outside the protective film toward the insulating layer to form a through hole that penetrates the protective film and the insulating layer in a thickness direction; removing the protective film from the insulating layer; forming a through conductor in the through hole; A method for manufacturing a wiring substrate, comprising: forming the through hole includes roughening a region of the first surface from a periphery of the through hole to a predetermined range by irradiating the first surface with ultraviolet laser light; Forming the through conductor includes forming a conductor portion on the first surface that is larger than the roughened region in a plan view.

11. 11. A method for manufacturing a wiring board according to claim 10, wherein the roughening includes roughening only the area of ​​the first surface that extends from the periphery of the through hole by 1.5 μm or more and 8.0 μm or less to an arithmetic mean roughness of 0.35 μm or more and 0.8 μm or less.

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