Semiconductor integrated circuit device

Abstract

To provide a semiconductor integrated circuit device that suppresses the effects of moisture intrusion from outside.SOLUTION: A semiconductor integrated circuit device has an analog circuit including an analog element 120, a digital circuit including a digital element 110, and aluminum wiring (13, 23), the analog element and aluminum wiring are electrically connected via a high-melting-point metal nitride (11, 24), and the digital element and aluminum wiring are electrically connected via high-melting-point metals (12, 26).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor integrated circuit device. [Background technology]

[0002] 2. Description of the Related Art Semiconductor integrated circuit devices that output signals to electrical equipment based on analog signals applied from the outside, or that perform analog-to-digital conversion for digital processing of analog signals, comprise analog circuits and digital circuits.

[0003] Analog circuits use analog elements such as constant voltage circuits, constant current circuits, and resistors that have structures that provide low variation, high stability of element characteristics, and high reliability. On the other hand, digital circuits require digital elements that have a structure with low parasitic resistance that allows high-speed operation. Digital elements do not often require strict variations in element characteristics as long as there is a clear difference between the on and off states.

[0004] One of the high stability requirements for analog elements is minimal long-term fluctuation in characteristics due to external stresses such as temperature, humidity, bias, etc. In particular, the mechanism by which element characteristics deteriorate due to bias stress has been studied, and various configurations for bias relaxation have been proposed.

[0005] On the other hand, the effects of humidity and moisture intrusion often act in combination with the bias, and the degradation mechanism is complex, so structures have been proposed that prevent moisture from invading at all.

[0006] Patent Document 1 discloses a technique for providing a guard ring around a passivation opening provided for laser irradiation on a fuse element in order to suppress fluctuations in characteristics due to moisture penetration. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-160801 Summary of the Invention [Problem to be solved by the invention]

[0008] Patent Document 1 discloses that by further providing a guard ring made of a metal wiring material surrounding a predetermined fuse opening, the path of moisture intrusion from the sidewall of the laminated interlayer insulating film from the fuse opening, which can cause deterioration of long-term reliability, is reliably blocked, thereby preventing deterioration of IC characteristics due to NBTI and wiring corrosion.

[0009] However, although there has been disclosure of suppressing the characteristic fluctuation of a semiconductor element due to moisture penetration starting from a passivation opening for a fuse, there is room for improvement in suppressing the characteristic fluctuation of a semiconductor element due to moisture penetration into the deep layers of the semiconductor element. [Means for solving the problem]

[0010] In order to solve the above problems, the present invention provides: A semiconductor integrated circuit device having an analog circuit including analog elements, a digital circuit including digital elements, and aluminum wiring, the digital circuit is formed in a first element forming region, and the analog circuit is formed in a second element forming region; the analog element and the aluminum wiring are electrically connected via a refractory metal nitride; The semiconductor integrated circuit device is characterized in that the digital elements and the aluminum wiring are electrically connected via a high melting point metal. [Effects of the Invention]

[0011] A semiconductor integrated circuit device is provided that suppresses the influence of fluctuations in the characteristics of semiconductor elements due to the intrusion of moisture from the outside. Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a cross-sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention. [Figure 2] 2 is an enlarged cross-sectional view of part A (part of the wiring portion of the digital element) of FIG. 1 in the semiconductor integrated circuit device according to the embodiment of the present invention. [Figure 3] 2 is an enlarged cross-sectional view of part B (part of the wiring portion of the analog element) of FIG. 1 in the semiconductor integrated circuit device according to the embodiment of the present invention. [Figure 4] FIG. 10 is a diagram illustrating a route of moisture penetration. [Figure 5] 1 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention; [Figure 6] 1 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention; [Figure 7] 1 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention; [Figure 8] 1 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention; [Figure 9] FIG. 2 is a diagram schematically illustrating a cross-sectional structure of a fuse opening. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The drawings used in the following description may be partially omitted to make the features of the present invention easier to understand, and may differ from the actual product. Note that the same components in each drawing are designated by the same reference numerals, and detailed descriptions of overlapping parts will be omitted.

[0014] Fig. 1 is a cross-sectional view showing a semiconductor integrated circuit device 100 according to an embodiment of the present invention. Fig. 4 is a diagram illustrating the path of moisture penetration.

[0015] Before describing the embodiments of the present invention, the mechanism by which moisture penetrates into a semiconductor element will be described with reference to FIG. 4 in order to facilitate understanding of the embodiments.

[0016] In FIG. 4, the lower layer aluminum Al (13) is in contact with tungsten W (27) constituting the via via through titanium Ti (12, 26) and is connected to the upper layer aluminum Al (23).

[0017] When aluminum Al (23, 13) and titanium Ti (26, 12) come into contact, an alloy layer (Al3Ti) of aluminum Al and titanium Ti is formed (not shown) by the heat treatment in the subsequent annealing process. The inventors have found that moisture can penetrate into the semiconductor element through this alloy layer (Al3Ti) (horizontal arrow in Figure 4), and further penetrate into the underlying titanium Ti (26, 12) and aluminum Al 13 through tungsten W (27) that constitutes the via (downward arrow in Figure 4), which can cause fluctuations in the characteristics of the semiconductor element.

[0018] Based on this knowledge, the present invention was devised to suppress the influence of moisture penetration into the deep layers of a semiconductor element on fluctuations in the characteristics of the semiconductor element. [Example]

[0019] A semiconductor integrated circuit device according to a first embodiment of the present invention will be described with reference to FIGS.

[0020] As shown in FIG. 1, the semiconductor integrated circuit device of the first embodiment of the present invention is a semiconductor integrated circuit device 100 that is composed of a first element formation region 500 for forming digital elements 110 and a second element formation region 600 for forming analog elements 120.

[0021] In the first element formation region 500 where the digital element 110 is formed, the wiring layer is limited to the following: titanium nitride TiN layer (21), titanium Ti layer (22), aluminum Al layer (23), titanium nitride TiN layer (24), and titanium Ti layer (25) are formed from top to bottom, and the tops of the tungsten W (27) and titanium Ti layer (26) that make up the via are connected to the upper aluminum Al layer (23), and the titanium Ti layer (26) at the bottom of the via is connected to the lower aluminum Al layer (13) through the lower titanium Ti layer (12).

[0022] In the second element formation region 600 where the analog element 120 is formed, the wiring layer is limited to the titanium nitride TiN layer (21), aluminum Al layer (23), titanium nitride TiN layer (24), and titanium Ti layer (25) formed from top to bottom. The tungsten W (27), titanium nitride TiN layer (24), and Ti layer (26) that make up the via are connected such that the tungsten W (27) and titanium nitride TiN layer (24) at the top of the via are connected to the upper aluminum Al layer (23), and the titanium nitride TiN layer (24) and titanium Ti layer (26) at the bottom of the via are connected to the aluminum Al layer (13) via the lower TiN layer (11).

[0023] The second element formation region 600 in which the analog element 120 is formed is connected to the aluminum Al layer (13) via the titanium nitride TiN layer (11), thereby suppressing the formation of an alloy layer (Al3Ti) of aluminum Al and titanium Ti, preventing moisture penetration, and suppressing fluctuations in the characteristics of the semiconductor element.

[0024] That is, in the second element forming region 600, by electrically connecting aluminum wiring via a high melting point metal nitride such as titanium nitride TiN layers (11, 14, 24), it is possible to prevent moisture from entering and suppress fluctuations in the characteristics of the semiconductor elements. [Example]

[0025] Next, a second embodiment of the present invention will be described.

[0026] 5 is a plan view of a second embodiment of the present invention. A second element formation region 600 is arranged on the inner periphery of an IC chip 200, and a first element formation region 500 is arranged further inside the second element formation region 600.

[0027] The second element formation region 600 is connected to the aluminum Al layer (13) via the titanium nitride TiN layer (11), which suppresses the formation of an alloy layer (Al3Ti) of aluminum Al and titanium Ti, thereby suppressing the effects of moisture penetration from outside the IC chip 200 on fluctuations in the characteristics of the semiconductor element.

[0028] Next, a modification of the second embodiment of the present invention will be described.

[0029] 6 is a plan view of a modified example of the second embodiment of the present invention. Compared with the configuration of the second embodiment shown in FIG. 5, the positional relationship between the first element formation region 500 and the second element formation region 600 has been reversed. That is, the first element formation region 500 is arranged on the inner periphery of the IC chip 200, and the second element formation region 600 is arranged further inward of the first element formation region 500.

[0030] The second element formation region 600 is connected to the aluminum Al layer (13) via the titanium nitride TiN layer (11), which suppresses the formation of an alloy layer (Al3Ti) of aluminum Al and titanium Ti, thereby suppressing the effects of moisture penetration from outside the IC chip 200 on fluctuations in the characteristics of the semiconductor element.

[0031] Next, a second modification of the second embodiment of the present invention will be described.

[0032] 7 is a plan view of Modification 2 of the second embodiment of the present invention. Compared to the configuration of the second embodiment shown in FIG. 5, a difference is that a second element formation region 600 is further disposed inside the first element formation region 500.

[0033] That is, the second element formation region 600 is arranged on the inner periphery of the IC chip 200, the first element formation region 500 is arranged inside the second element formation region 600, and the second element formation region 600 is further arranged inside the first element formation region 500. A plurality of second element formation regions 600 may be arranged.

[0034] The second element formation region 600 is connected to the aluminum Al layer (13) via the titanium nitride TiN layer (11), which suppresses the formation of an alloy layer (Al3Ti) of aluminum Al and titanium Ti, thereby suppressing the effects of moisture penetration from outside the IC chip 200 on fluctuations in the characteristics of the semiconductor element.

[0035] Next, a third modification of the second embodiment of the present invention will be described.

[0036] 8 is a plan view of Modification 3 of the second embodiment of the present invention. Compared to the configuration of FIG. 5 of the second embodiment, the difference is that the first element formation region 500 is not arranged inside or outside the second element formation region 600, but rather has a horizontal or vertical arrangement. In other words, the first element formation region 500 and the second element formation region 600 are arranged inside the IC chip 200 in a horizontal or vertical arrangement.

[0037] The second element formation region 600 is connected to the aluminum Al layer (13) via the titanium nitride TiN layer (11), which suppresses the formation of an alloy layer (Al3Ti) of aluminum Al and titanium Ti, thereby suppressing the effects of moisture penetration from outside the IC chip 200 on fluctuations in the characteristics of the semiconductor element. [Example]

[0038] Next, a third embodiment of the present invention will be described.

[0039] FIG. 9 is a cross-sectional view of an embodiment for explaining a fuse opening applied to the third embodiment of the present invention.

[0040] 9 is a schematic diagram showing the cross-sectional structure of the fuse portion, and is a cross-sectional view of the fuse element in the longitudinal direction, which is parallel to the current flowing through the fuse element 130. A first insulating film layer 150 is disposed on a semiconductor substrate such as a silicon substrate, and a fuse element 130 made of polycrystalline silicon is disposed thereon. A second insulating film layer 160 is formed to cover this fuse element 130. A final protective film 170 is formed on the second insulating film layer 160. The final protective film 170 has an opening region, and an opening is formed above the region where the fuse element 130 is formed, where a fuse opening 140 is disposed.

[0041] The semiconductor integrated circuit device of the third embodiment of the present invention is composed of a semiconductor integrated circuit device 100, a first element formation region 500 for forming a digital element 110, and a second element formation region 600 for forming an analog element 120, and further a fuse opening 140 is arranged in the second element formation region 600.

[0042] The second element formation region 600 is connected to the aluminum Al layer (13) via the titanium nitride TiN layer (11), which suppresses the formation of an alloy layer (Al3Ti) of aluminum Al and titanium Ti, thereby suppressing the effects of moisture penetration through the fuse opening on fluctuations in the characteristics of the semiconductor element.

[0043] Furthermore, it goes without saying that the present invention is not limited to the above-described embodiment, and various modifications are possible within the scope of the present invention.

[0044] Furthermore, similar effects can be obtained by adopting the embodiments of the present invention not only to analog elements but also to elements that require high precision, high stability, and high reliability, elements in which variations should be reduced, and semiconductor integrated circuit devices. [Explanation of symbols]

[0045] 11, 14, 21, 24 TiN layers 12, 15, 16, 22, 25, 26 Ti layers 17, 27 W layer 13, 23 Aluminum wiring layer 110 Digital Elements 120 Analog Elements 130 Fuse element 140 Fuse opening 150 First insulating film layer 160 Second insulating film layer 170 Final protective film 200 IC chips 500 First element formation region 600 Second element formation region A Part of the wiring of a digital element B Part of the wiring of the analog element

Claims

1. A semiconductor integrated circuit device having an analog circuit including analog elements, a digital circuit including digital elements, and aluminum wiring, the digital circuit is formed in a first element forming region, and the analog circuit is formed in a second element forming region; the analog element and the aluminum wiring are electrically connected via a refractory metal nitride; The semiconductor integrated circuit device is characterized in that the digital elements and the aluminum wiring are electrically connected via a high-melting-point metal.

2. 2. The semiconductor integrated circuit device according to claim 1, wherein a high melting point metal nitride film is formed on said aluminum wiring on said analog circuit.

3. 3. The semiconductor integrated circuit device according to claim 2, wherein a high melting point metal film and a high melting point metal nitride film are formed in this order on the aluminum wiring on the digital circuit.

4. a fuse element formed on a first insulating film layer, a second insulating film layer formed so as to cover the fuse element, a final protective film formed on the second insulating film layer, and a fuse opening formed by opening the final protective film and the second insulating film layer above the fuse element; 3. The semiconductor integrated circuit device according to claim 1, wherein the fuse opening is formed in the second element forming region.

5. 3. The semiconductor integrated circuit device according to claim 1, wherein the second element forming region is arranged on the periphery of the chip.

6. 4. The semiconductor integrated circuit device according to claim 3, wherein the second element forming region is arranged on the periphery of the chip.

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