Circuit board, circuit board manufacturing method, and electronic component package

Abstract

To provide a thin circuit board in which a stopper layer for forming a cavity and a pad structure exposed in the cavity can be formed in the same layer, a manufacturing method thereof, and an electronic component package.SOLUTION: A circuit board includes: an insulating layer including a first insulating layer portion and a second insulating layer portion stacked on the first insulating layer portion, and having a cavity penetrating a portion of the second insulating layer portion and the first insulating layer portion; a circuit layer at least partially embedded in the second insulating layer portion; and a metal pattern layer arranged along the edge of the cavity within the second insulating layer portion. The insulating layer has a first surface that forms the bottom surface of the cavity and a second surface that forms the side surface of the cavity. The metal pattern layer is exposed from the insulating layer at the second surface and includes a plurality of metal layers containing different metals.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a circuit board, a method for manufacturing a circuit board, and an electronic component package, and more particularly to a thinned circuit board, a method for manufacturing a circuit board, and an electronic component package. [Background technology]

[0002] In order to reduce the thickness of the circuit board, a cavity is formed in the circuit board, and various electronic components are arranged in the cavity. In this case, the circuit board is required to have pads whose surfaces are exposed through the cavities and on which electronic components are mounted.

[0003] However, in a circuit board including such a cavity, structural problems such as poor pad appearance quality may occur, and it is difficult to simultaneously realize a stopper for cavity processing and a mounting pad on the same layer. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above-mentioned problems with conventional circuit boards, and an object of the present invention is to provide a thin circuit board, a manufacturing method thereof, and an electronic component package, which are capable of forming a stopper layer for forming a cavity and a pad structure exposed in the cavity in the same layer. [Means for solving the problem]

[0005] The circuit board according to the present invention, which has been made to achieve the above-mentioned object, comprises an insulating layer including a first insulating layer portion and a second insulating layer portion stacked on the first insulating layer portion, the insulating layer having a cavity penetrating a portion of the second insulating layer portion and the first insulating layer portion, a circuit layer at least partially embedded in the second insulating layer portion, and a metal pattern layer arranged along the edge of the cavity within the second insulating layer portion, wherein the insulating layer has a first surface that forms the bottom surface of the cavity and a second surface that forms the side surface of the cavity, and the metal pattern layer is exposed from the insulating layer at the second surface and includes a plurality of metal layers containing different metals.

[0006] The plurality of metal layers preferably have different etching selectivities with respect to the same material. The metal pattern layer is preferably disposed in a corner region of the cavity so as to connect the first surface and the second surface. The metal pattern layer preferably includes a first metal layer containing copper, and a second metal layer disposed on the first metal layer and containing nickel. It is preferable that the circuit layer includes a first conductive layer disposed on the first insulating layer portion and a second conductive layer stacked on the first conductive layer, and one surface of the second conductive layer is disposed on substantially the same plane as one surface of the second metal layer. The circuit layer preferably includes a first conductive layer containing the same material as the first metal layer. The semiconductor device may further include a first pad exposed from the second insulating layer portion on the first surface.

[0007] The first pad is preferably partially embedded in the insulating layer. It is preferable that, based on the first insulating layer portion, the surface of the first pad exposed from the second insulating layer portion is located farther away in the stacking direction than the surface of the circuit layer facing the first insulating layer portion. It is preferable that the thickness of the first pad in the stacking direction is smaller than the thickness of the circuit layer. The circuit layer preferably includes a first conductive layer containing copper and a second conductive layer disposed on the first conductive layer. The first conductive layer preferably includes an electroless plating layer. The metal pattern layer is preferably disposed recessed inward from the second surface. It is preferable that the semiconductor device further includes a first pad exposed from the insulating layer on one side where the cavity is disposed.

[0008] In order to achieve the above object, a method for manufacturing a circuit board according to the present invention includes the steps of: forming a first stopper layer containing a first metal on a first insulating layer portion; forming a second stopper layer on the first stopper layer containing a second metal different from the first metal; forming a first pad on the second stopper layer; forming a second insulating layer portion by stacking the second stopper layer on the first insulating layer portion so that the first pad is embedded; removing the first insulating layer portion on the first stopper layer by an area smaller than an area of ​​the first stopper layer to form a first cavity forming portion; removing a portion of the first stopper layer exposed in the first cavity forming portion to form a second cavity forming portion; and removing a portion of the second stopper layer exposed in the second cavity forming portion to form a cavity.

[0009] Preferably, forming the second stopper layer includes forming the second stopper layer including the second metal having an etching selectivity different from that of the first metal with respect to the same material. Preferably, forming the second cavity forming portion includes removing the exposed portion of the first stopper layer and forming a remaining first metal layer along the edge of the first cavity forming portion. Preferably, the step of forming the cavity includes the step of removing the exposed portion of the second stopper layer and forming a remaining second metal layer along the edge of the second cavity forming portion. Preferably, the step of forming the first stopper layer includes forming the first stopper layer containing copper, and the step of forming the second stopper layer includes forming the second stopper layer containing nickel. It is preferable that the method further includes a step of forming a circuit layer on the first insulating layer portion, and the step of forming the circuit layer includes a step of forming a first conductive layer on the first insulating layer portion, and a step of forming a second conductive layer on the first conductive layer so as to have one side at substantially the same level as one side of the second stopper layer. Preferably, forming the first conductive layer includes forming the first conductive layer containing the same material as the first stopper layer.

[0010] Preferably, the method further includes forming a circuit layer on the first insulating layer portion, and forming the first pad includes forming the first pad so that a surface of the first pad exposed from the second insulating layer portion has a higher level than a surface of the circuit layer facing the first insulating layer portion. It is preferable that the method further includes a step of forming a circuit layer on the first insulating layer portion, and the step of forming the first pad includes a step of forming the first pad so that it has a thickness in the stacking direction that is smaller than the thickness of the circuit layer. Preferably, the method further comprises the step of forming a surface treatment layer on the first pad. It is preferable that the method further includes a step of forming a circuit layer on the first insulating layer portion, and the step of forming the circuit layer includes a step of forming a first conductive layer containing copper, and a step of forming a second conductive layer on the first conductive layer. Preferably, the step of forming the first conductive layer includes the step of forming an electroless plating layer. Preferably, the method further includes the step of etching the first stopper layer to form a first metal layer so as to extend inward from a side surface of the second insulating layer portion. Preferably, the method further includes the step of etching the second stopper layer to form a second metal layer so as to extend inward from a side surface of the second insulating layer portion. Preferably, the method further includes the steps of forming an insulating layer including the first insulating layer portion and the second insulating layer portion, the insulating layer having the cavity formed on one surface thereof, and forming a second pad on the one surface of the insulating layer so as to be exposed from the insulating layer.

[0011] The electronic component package according to the present invention, which has been made to achieve the above-mentioned object, comprises a circuit board having a cavity and including a pad portion exposed from an insulating layer within the cavity, and an electronic component mounted in the cavity so as to be connected to the pad portion, wherein the circuit board comprises an insulating layer having the cavity, a circuit layer at least partially embedded in the insulating layer, and a metal pattern layer arranged within the insulating layer along the edge of the cavity, wherein the insulating layer has a first surface that forms the bottom surface of the cavity and a second surface that forms the side surface of the cavity, and the metal pattern layer is exposed from the insulating layer at the second surface and includes a plurality of metal layers containing different metals.

[0012] The metal pattern layer preferably includes a first metal layer containing copper, and a second metal layer disposed on the first metal layer and containing nickel. [Effects of the Invention]

[0013] According to the circuit board, the method for manufacturing the circuit board, and the electronic component package of the present invention, a cavity structure and a pad structure exposed in the cavity can be more easily formed by using a plurality of metal layers containing different metals as etching stop layers, and a circuit board having a thin thickness can be provided, thereby making it possible to reduce the thickness of electronic products in which the circuit board is mounted. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a cross-sectional view schematically illustrating a structure of a circuit board according to an embodiment of the present invention. [Figure 2] 2 is an enlarged cross-sectional view of a portion A of the circuit board shown in FIG. 1. FIG. [Figure 3]2 is an enlarged cross-sectional view of a portion B of the circuit board shown in FIG. 1. FIG. [Figure 4] 5A to 5C are cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 5] 5A to 5C are cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 6] 5A to 5C are cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 7] 5A to 5C are cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 8] 5A to 5C are cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 9] 5A to 5C are cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 10] 5A to 5C are cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 11] 5A to 5C are cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 12] 5A to 5C are cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 13] 5A to 5C are cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 14] 5A to 5C are cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 15] 5A to 5C are cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 16] 5A to 5C are cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 17] 1 is a cross-sectional view showing a schematic configuration of an electronic component package according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0015] Next, specific examples of embodiments for carrying out the circuit board, the method for manufacturing the circuit board, and the electronic component package according to the present invention will be described with reference to the drawings.

[0016] In the drawings, parts unnecessary for the explanation are omitted in order to clearly explain the present invention, and the same reference numerals are used throughout the specification to refer to the same or similar components. In addition, in the accompanying drawings, some components are exaggerated, omitted, or illustrated schematically, and the size of each component does not entirely reflect the actual size. The attached drawings are merely for the purpose of facilitating understanding of the embodiments disclosed in this specification, and it should be understood that the attached drawings do not limit the technical ideas disclosed in this specification, and include all modifications, equivalents, and alternatives included in the idea and technical scope of the present invention.

[0017] Terms including ordinal numbers, such as first, second, etc., are used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another. Furthermore, when a layer, film, region, plate, or other part is said to be "on" or "on top of" another part, this includes not only the case where it is "directly on" the other part, but also the case where there is another part in between. Conversely, when a part is said to be "directly on" another part, it means that there are no other parts in between. Furthermore, being "on" or "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" or "above" in the direction opposite to gravity. Throughout the specification, the use of terms such as "comprises" or "having" is intended to specify the presence of any features, numerals, steps, operations, components, parts, or combinations thereof stated in the specification, and should be understood as not precluding the presence or possible addition of one or more other features, numerals, steps, operations, components, parts, or combinations thereof. Therefore, when a part is said to "comprise" certain elements, this means that it may further include other elements, but does not exclude other elements, unless specifically stated to the contrary.

[0018] Also, throughout the specification, "on a plane" means when the subject part is viewed from above, and "on a cross section" means when the subject part is cut vertically and viewed from the side. Furthermore, throughout the specification, when the term "connected" is used, it does not only mean that two or more components are directly connected, but also that two or more components are indirectly connected through other components, that two or more components are not only physically connected but also electrically connected, or that components are referred to by different names depending on their position or function but are integrated. Throughout the specification, the term "substantially the same" refers not only to things that are exactly the same numerically, but also to things that are designed to the same size or level but that would be considered the same by a person of ordinary skill in the art even if there are slight differences within the tolerance range due to tolerances in the manufacturing process or the characteristics of the materials.

[0019] A circuit board 10A according to an embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a cross-sectional view schematically showing the structure of a circuit board according to an embodiment of the present invention. Referring to FIG. 1, a circuit board 10A according to an embodiment of the present invention includes an insulating layer 110 including a first insulating layer portion 111 and a second insulating layer portion 112, a first circuit layer 121, and a metal pattern layer 200.

[0020] The second insulating layer portion 112 is laminated on the first insulating layer portion 111 . The insulating layer 110 has a cavity 110 a that penetrates a part of the second insulating layer portion 112 and the first insulating layer portion 111 . The first circuit layer 121 is at least partially embedded in the second insulating layer portion 112 . The metal pattern layer 200 is disposed within the second insulating layer portion 112 along the edge of the cavity 110a. The insulating layer 110 has a first surface S1 that forms the bottom surface of the cavity 110a and a second surface S2 that forms the side surface of the cavity 110a. The metal pattern layer 200 is exposed from the insulating layer 110 at the second surface S2 and includes a plurality of metal layers each containing a different metal. The insulating layer 110 has a structure in which multiple layers are stacked. As an example, the insulating layer 110 includes a first insulating layer portion 111, a second insulating layer portion 112, and a third insulating layer portion 113.

[0021] The second insulating layer portion 112 is laminated on one surface of the first insulating layer portion 111 . The third insulating layer portion 113 is disposed on the other surface of the first insulating layer portion 111 . The third insulating layer portion 113 is disposed so as to face the second insulating layer portion 112 . The insulating layer 110 includes an insulating material. The insulating material may be a photosensitive material and / or a non-photosensitive material, including a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material containing such a resin together with an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, and / or glass fabric).

[0022] As an example, insulating materials such as SR (Solder Resist), ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), RCC (Resin Coated Copper), and CCL (Copper Clad Laminate) can be used, but the insulating materials are not limited to these and may include other polymeric materials. On the other hand, the material of the insulating layer 110 may be any of these resins containing an inorganic filler such as silica and a reinforcing material such as glass fiber. For example, prepreg can be used, but is not limited to this. Furthermore, although the insulating layer 110 is depicted as three layers in FIG. 1, it is not limited thereto, and the insulating layer 110 may include one or more insulating layer portions.

[0023] The circuit board 10A according to one embodiment includes multiple circuit layers. As an example, the circuit board 10A according to one embodiment includes first to fourth circuit layers (121, 122, 123, 124). The first to fourth circuit layers (121, 122, 123, 124) are embedded in the insulating layer 110 or disposed on the insulating layer 110, respectively. The first circuit layer 121 is disposed on one surface of the first insulating layer portion 111 . The first circuit layer 121 is at least partially embedded in the second insulating layer portion 112 . The second circuit layer 122 is disposed on the second insulating layer portion 112 . The second circuit layer 122 is disposed on one side of the insulating layer 110 . The third circuit layer 123 is disposed on one surface of the third insulating layer portion 113 . The third circuit layer 123 is at least partially embedded in the first insulating layer portion 111 . The fourth circuit layer 124 is disposed on the other surface of the third insulating layer portion 113 . At least a portion of the fourth circuit layer 124 is exposed on the other surface of the insulating layer 110 . The fourth circuit layer 124 is at least partially embedded in the third insulating layer portion 113 .

[0024] A portion of the first circuit layer 121 may function as a pad for connection to another substrate or component. The first circuit layer 121 includes a first pad 121 a exposed to the outside of the insulating layer 110 on the other surface of the second insulating layer portion 112 . The first pad 121a is partially embedded in the second insulating layer portion 112, but this is not limited to this, and the first pad 121a can also be arranged on one surface of the first insulating layer portion 111 and protrude from that surface. A portion of the second circuit layer 122 may function as a pad for connection to another substrate or component. The second circuit layer 122 includes a second pad 122 a exposed to the outside of the insulating layer 110 on one surface of the second insulating layer portion 112 . The second pad 122 a is disposed on one surface of the insulating layer 110 . The second pad 122a may be arranged on one surface of the second insulating layer portion 112 and protrude from that surface, but is not limited to this, and the second pad 122a may also be partially embedded in the insulating layer portion 112. A portion of the fourth circuit layer 124 may function as a pad for connection to another substrate or component. The fourth circuit layer 124 includes a third pad 124 a exposed to the outside of the insulating layer 110 on the other surface of the third insulating layer portion 113 . The third pad 124a may be partially embedded in the third insulating layer portion 113, but is not limited to this, and the third pad 124a may also be arranged on the other side of the third insulating layer portion 113 and protrude from the other side.

[0025] The first pad 121a may include an electroplated layer. The first pad 121a may consist of a single layer. The second pad 122a may include an electroless plating layer and an electrolytic plating layer. The second pad 122a may include multiple layers. The third pad 124a may include an electroplated layer. The third pad 124a may consist of a single layer. Although FIG. 1 shows first to fourth circuit layers (121, 122, 123, 124), this is not limited to this, and a greater number of circuit layers than those shown may be arranged, or a smaller number of circuit layers may be arranged.

[0026] Each of the first to fourth circuit layers (121, 122, 123, 124) transmits a signal inside the circuit board 10A. The first to fourth circuit layers (121, 122, 123, 124) are each made of a metal material. The metallic material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the first to fourth circuit layers (121, 122, 123, 124) performs various functions according to its design, such as a ground pattern, a power pattern, and a signal pattern. Each of these patterns may have a line, plane, or pad form.

[0027] In the case of a circuit layer located on the outermost layer of a plurality of circuit layers, it can function as a pad for connection to another substrate or component. Each of the first to fourth circuit layers (121, 122, 123, 124) can be formed by a wiring formation process, such as AP (Additive Process), SAP (Semi AP), MSAP (Modified SAP), or TT (Tenting). Each of the first to third circuit layers (121, 122, 123) includes a seed layer that is an electroless plating layer and an electrolytic plating layer formed based on such a seed layer. The fourth circuit layer 124 may include an electroplated layer.

[0028] The first circuit layer 121 includes a first conductive layer 1211 disposed on one surface of the first insulating layer portion 111 , and a second conductive layer 1212 laminated on the first conductive layer 1211 . The first conductive layer 1211 includes an electroless plating layer, and the second conductive layer 1212 includes an electrolytic plating layer, but is not limited thereto. The second circuit layer 122 includes a third conductive layer 1221 disposed on the second insulating layer portion 112 and a fourth conductive layer 1222 laminated on the third conductive layer 1221 . The third conductive layer 1221 includes an electroless plating layer, and the fourth conductive layer 1222 includes an electrolytic plating layer, but is not limited thereto. The third circuit layer 123 includes a fifth conductive layer 1231 disposed on the third insulating layer portion 113, and a sixth conductive layer 1232 laminated on the fifth conductive layer. The fifth conductive layer 1231 includes an electroless plating layer, and the sixth conductive layer 1232 includes an electrolytic plating layer, but is not limited thereto. The electroless plating layer may be, but is not limited to, a chemical copper plating layer, and may be, for example, a sputtering layer.

[0029] The circuit board 10A according to one embodiment includes a first via electrode 131 that penetrates the second insulating layer portion 112 and electrically connects the first circuit layer 121 and the second circuit layer 122, a second via electrode 132 that penetrates the first insulating layer portion 111 and electrically connects the first circuit layer 121 and the third circuit layer 123, and a third via electrode 133 that penetrates the third insulating layer portion 113 and electrically connects the third circuit layer 123 and the fourth circuit layer 124. In FIG. 1, the first to third via electrodes (131, 132, 133) are shown as singular, but this is not limiting, and the first to third via electrodes (131, 132, 133) may each be provided as plural. The first to third via electrodes (131, 132, 133) are each made of a metal material. The metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof.

[0030] Each of the first to third via electrodes (131, 132, 133) may include a signal via, a ground via, a power via, etc., depending on the design. Each of the first to third via electrodes (131, 132, 133) may be a via hole filled with a metal material, or a via hole with a metal material formed along the wall surface thereof. Each of the plurality of via electrodes may be formed by a plating process. As an example, each of the first to third via electrodes (131, 132, 133) has a tapered shape in which the width of one side is smaller than the width of the other side. Meanwhile, although FIG. 1 shows the circuit board 10A according to an embodiment of the present invention as including first to third via electrodes (131, 132, 133), depending on the configuration of the insulating layer 110 and the design of the circuit layer, the via layer in which the via electrodes are arranged may be composed of a single layer or may be composed of more layers.

[0031] The circuit board 10A according to the embodiment includes a first protective layer 141 and a second protective layer 142. The first protective layer 141 and the second protective layer 142 each protect the internal components from external physical and chemical damage. The first protective layer 141 is disposed on one surface of the insulating layer 110 . The first protective layer 141 may cover one surface of the insulating layer 110 and have an opening to expose at least a portion of the second circuit layer 122. The first protective layer 141 has at least one opening. The first protective layer 141 includes a photosensitive resin material. The first protective layer 141 may be a solder resist layer. The second protective layer 142 is disposed on the other side of the insulating layer 110 . The second protective layer 142 may cover the other surface of the insulating layer 110 and have an opening to expose at least a portion of the fourth circuit layer 124. The second protective layer 142 has at least one opening. The second protective layer 142 includes a photosensitive resin material. The second protective layer 142 may be a solder resist layer.

[0032] The circuit board 10A according to one embodiment includes first to third surface treatment layers (151, 152, 153) that cover a part of the circuit layer exposed to the outside of the insulating layer 110. The first surface processing layer 151 is disposed on the first pad 121a. The second surface treatment layer 152 is disposed on the second pad 122a. The third surface processing layer 153 is disposed on the third pad 124a. The first to third surface treatment layers (151, 152, 153) may contain any one of nickel (Ni), palladium (Pd), and gold (Au), and may be realized as a plurality of these metal layers. However, the surface treatment layer is not limited thereto and may contain an organic substance. The first to third surface treatment layers (151, 152, 153) improve the bonding strength and signal transmission strength of the first to third pads (121a, 122a, 124a) and the configuration mounted on the first to third pads (121a, 122a, 124a).

[0033] The insulating layer 110 has a cavity 110 a that penetrates a part of the second insulating layer portion 112 and the first insulating layer portion 111 . The circuit board 10A according to one embodiment includes a metal pattern layer 200 disposed within the second insulating layer portion 112 around the cavity 110a. The insulating layer 110 has a first surface S1 that forms the bottom surface of the cavity 110a and a second surface S2 that forms the side surface of the cavity 110a. The first pads 121a are exposed from the second insulating layer portion 112 on the first surface S1. The metal pattern layer 200 is exposed from the insulating layer 110 on the second surface S2. The metal pattern layer 200 may include multiple metal layers. The metal layers may each contain a different metal.

[0034] The metal pattern layer 200 of the circuit board 10A according to the embodiment of the present invention will be described in more detail below with reference to FIGS. 2 is an enlarged cross-sectional view of a portion A of the circuit board shown in FIG. 1, and FIG. 3 is an enlarged cross-sectional view of a portion B of the circuit board shown in FIG. 1 to 3, the metal pattern layer 200 is disposed to connect the first surface S1 and the second surface S2.

[0035] The metal pattern layer 200 is disposed in the corner regions of the cavity 110a. The metal pattern layer 200 is disposed to surround the cavity 110a. The metal pattern layer 200 is disposed so as to surround the first surface S1. The metal pattern layer 200 includes a first metal layer 210 and a second metal layer 220 . The first metal layer 210 is disposed on one surface of the first insulating layer portion 111 . The second metal layer 220 is disposed on one surface of the first metal layer 210 . One surface of the second metal layer 220 may be in contact with the first surface S1.

[0036] The first metal layer 210 and the second metal layer 220 each contain different metals. The first metal layer 210 and the second metal layer 220 have different etching selectivities with respect to the same material. As an example, the first metal layer 210 includes copper (Cu) and the second metal layer 220 includes nickel (Ni), but is not limited thereto, and any metal that allows the first metal layer 210 and the second metal layer 220 to have different etching selectivities with respect to the same material is possible. Etching selectivity refers to the ratio of the etching rate of material X to the etching rate of material Y. Here, material X is a material that requires etching, and material Y is a material that does not require etching (such as a mask layer).

[0037] For example, the first metal layer 210 and the first conductive layer 1211 are formed through the same process. The first metal layer 210 includes the same material as the first conductive layer 1211 . The first metal layer 210 and the first conductive layer 1211 include the same material, which includes copper (Cu). In addition, the first metal layer 210 includes the same material as the third conductive layer 1221 and the fifth conductive layer 1231 . The first metal layer 210, the third conductive layer 1221, and the fifth conductive layer 1231 include the same material, which includes copper (Cu). Therefore, the second metal layer 220 comprises a different material than the first conductive layer 1211 . The second metal layer 220 includes a different material from the third conductive layer 1221 and the fifth conductive layer 1231 .

[0038] Referring to FIG. 2, the metal pattern layer 200 is disposed inside the second surface S2 in a direction perpendicular to the stacking direction. The metal pattern layer 200 is disposed recessed inward from the second surface S2. The edge of the metal pattern layer 200 includes a portion extending inward from the second surface S2. One surface of the metal pattern layer 200 exposed toward the cavity 110a includes an inclined surface that is inclined with respect to a reference line parallel to the stacking direction. The inclined surface of the metal pattern layer 200 may be a curved surface. For example, the metal pattern layer 200 has a curved inclined surface formed by a wet etching process. The edge of the first metal layer 210 may be shaped to extend inward from the second surface S2. The surface of the first metal layer 210 exposed toward the cavity 110a includes an inclined surface that is inclined with respect to a reference line parallel to the stacking direction. The inclined surface of the first metal layer 210 may be a curved surface. The edge of the second metal layer 220 may be shaped to extend inward from the second surface S2. The surface of the second metal layer 220 exposed toward the cavity 110a includes an inclined surface that is inclined with respect to a reference line parallel to the stacking direction. The inclined surface of the second metal layer 220 may be a curved surface.

[0039] Referring to FIG. 3, the lower surface S1212 of the second conductive layer 1212 is disposed at substantially the same level as the lower surface S220 of the second metal layer 220. The second conductive layer 1212 is disposed substantially coplanar with the second metal layer 220 . The lower surface S1212 of the second conductive layer 1212 is disposed at substantially the same distance from the lower surface S220 of the second metal layer 220 and the upper surface of the first insulating layer portion 111. The distance d1 from the upper surface of the first insulating layer portion 111 to the lower surface S1212 of the second conductive layer 1212 may be substantially the same as the distance d2 from the upper surface of the first insulating layer portion 111 to the lower surface S220 of the second metal layer 220. The lower surface S121a of the first pad 121a is disposed at a greater distance from the upper surface of the first insulating layer portion 111 in the stacking direction than the lower surface S121 of the first circuit layer 121.

[0040] In terms of distance in the stacking direction based on the first insulating layer portion 111, the surface of the first pad 121a exposed from the second insulating layer portion 112 is positioned farther away than the surface of the first circuit layer 121 facing the first insulating layer portion 111. The lower surface S121a of the first pad 121a is disposed at a greater distance from the upper surface of the first insulating layer portion 111 in the stacking direction than the lower surface S220 of the second metal layer 220. A distance d3 from the upper surface of the first insulating layer portion 111 to the lower surface S121a of the first pad 121a is greater than a distance d2 from the upper surface of the first insulating layer portion 111 to the lower surface S220 of the second metal layer 220. In terms of distance in the stacking direction based on the first insulating layer portion 111, the surface of the first pad 121a exposed from the second insulating layer portion 112 is positioned farther away than the surface of the second metal layer 220 facing the first insulating layer portion 111.

[0041] Referring to FIG. 3, the thickness t1 of the first pad 121a in the stacking direction is smaller than the thickness t2 of the first circuit layer 121. In terms of thickness in the stacking direction, the thickness t1 of the first pad 121a is smaller than the thickness t3 of the second conductive layer 1212. In terms of thickness in the stacking direction, the thickness t4 of the metal pattern layer 200 is smaller than the thickness t2 of the first circuit layer 121. In terms of thickness in the stacking direction, the thickness t5 of the first metal layer 210 may be substantially the same as the thickness t6 of the first conductive layer 1211. According to one embodiment of the circuit board, a plurality of metal layers containing different metals can be used as etching stop layers to more easily form a cavity structure and a pad structure exposed in the cavity, thereby providing a circuit board with a thin thickness and enabling the electronic product package to which the circuit board is attached to be made thinner.

[0042] A method for manufacturing a circuit board 10A according to an embodiment of the present invention will be described below with reference to FIGS. 4 to 16 are cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment of the present invention.

[0043] Referring to FIG. 4, a carrier board, which is a basic material for manufacturing a circuit board 10A according to an embodiment of the present invention, is prepared. The carrier board includes a carrier insulating layer 510 and a carrier conductive layer 520 disposed on one side of the carrier insulating layer 510 . The carrier conductive layer 520 may be disposed on one side of the carrier insulating layer 510, or alternatively, may be disposed on both sides. When the carrier conductive layers 520 are all disposed on both sides of the carrier insulating layer 510, the following process involves carrying out the circuit board manufacturing process on both sides of the carrier board respectively before the carrier board is removed. The carrier conductive layer 520 is formed by electroless plating on the surface of the carrier insulating layer 510 .

[0044] Referring again to FIG. 4, the fourth circuit layer 124 is formed on the carrier conductive layer 520 . The fourth circuit layer 124 is formed through a plating process. For example, the fourth circuit layer 124 is formed by forming a photoresist on the carrier conductive layer 520, patterning the photoresist through an exposure and development process, filling the patterned area with plating, and then peeling off the photoresist. However, the present invention is not limited to this, and any method that can form a pattern on a circuit board can be used without any restrictions.

[0045] Referring to FIG. 5, the third insulating layer portion 113 is formed so that the carrier conductive layer 520 and the fourth circuit layer 124 are embedded therein. The third insulating layer portion 113 is formed using a material such as Prepreg (PPG), ABF (Ajinomoto build-up film), or RCC (Resin Coated Copper foil). Referring to FIG. 5, a third via hole 1331 is formed through the third insulating layer portion 113 . The third via hole 1331 is formed by laser or mechanical drilling. Furthermore, on one surface of the third insulating layer portion 113, a fifth conductive layer formation layer P1231 is formed. The fifth conductive layer-forming layer P1231 is formed on one surface of the third insulating layer portion 113 by electroless plating. In Figure 5, the fifth conductive layer forming layer P1231, which is an electroless plating layer, is shown as being located only on one surface of the third insulating layer portion 113, but an electroless plating layer may also be disposed on the inner surface of the third via hole 133.

[0046] Referring to FIG. 6, a sixth conductive layer 1232 is formed on a fifth conductive layer forming layer P1231. The sixth conductive layer 1232 is formed through a plating process. In addition, the third via hole 1331 is filled with a conductive material to form the third via electrode 133 . As an example, the sixth conductive layer 1232 and the third via electrode 133 are formed by forming a photoresist on the fifth conductive layer formation layer P1231, patterning the photoresist through an exposure and development process, plating to fill the patterned area, and then peeling off the photoresist. However, the present invention is not limited to this, and any method that can form a pattern on a circuit board can be used without any restrictions.

[0047] Referring to FIG. 7, the fifth conductive layer 1231 is formed by removing a portion of the fifth conductive layer-forming layer P1231. As a result, the third circuit layer 123 including the fifth conductive layer 1231 and the sixth conductive layer 1232 can be formed. As an example, the fifth conductive layer 1231 is removed through flash etching. Then, the first insulating layer portion 111 is formed so that the fifth conductive layer 1231 and the sixth conductive layer 1232 are buried. The first insulating layer portion 111 is formed using a material such as Prepreg (PPG), ABF (Ajinomoto build-up film), or RCC (Resin Coated Copper foil).

[0048] Referring again to FIG. 7, a second via hole 1321 is formed through the first conductive layer-forming layer P1211 and the first insulating layer portion 111. The second via hole 1321 is formed by laser or mechanical drilling. Then, on one surface of the first insulating layer portion 111, a first conductive layer formation layer P1211 is formed. The first conductive layer-forming layer P1211 is formed on one surface of the first insulating layer portion 111 by electroless plating. In Figure 7, the first conductive layer forming layer P1211, which is an electroless plating layer, is shown as being located only on one surface of the first insulating layer portion 111, but an electroless plating layer may also be disposed on the inner surface of the second via hole 1321.

[0049] Referring to FIG. 8, a mask layer 530 is formed on one surface of the first conductive layer-forming layer P1211. Specifically, a mask layer 530 is formed in the area excluding the region where the second stopper layer 2200 is to be formed. The mask layer 530 is formed to include a dry film. Then, the second stopper layer 2200 is formed on the first insulating layer portion 111. The second stopper layer 2200 is formed to contain a second metal. In one example, the second metal includes nickel (Ni). The second stopper layer 2200 is formed on the first conductive layer formation layer P1211. The first conductive layer-forming layer P1211 includes a first metal that is different from the second metal. In one example, the first metal includes copper (Cu).

[0050] Referring to FIG. 9, the second via hole 1321 is filled with a conductive material to form the second via electrode 132. 9, the mask layer 530 is removed, and the second conductive layer 1212 is formed on a part of the first conductive layer-forming layer P1211 and the second stopper layer 2200. The second conductive layer 1212 is formed through a plating process. The second conductive layer 1212 is formed so that the lower surface S1212 of the second conductive layer 1212 is substantially flush with the lower surface of the second stopper layer 2200. The lower surface S1212 of the second conductive layer 1212 and the lower surface of the second stopper layer 2200 may be disposed at substantially the same distance from the upper surface of the first insulating layer portion 111.

[0051] For example, the second conductive layer 1212 is formed by forming a photoresist on the first conductive layer formation layer P1211, patterning the photoresist through an exposure and development process, filling the patterned area with plating, and then peeling off the photoresist. However, the present invention is not limited to this, and any method that can form a pattern on a circuit board can be used without any restrictions. Here, the second conductive layer 1212 is formed so as to include the first pad 121a. The first pad 121 a is formed on the second stopper layer 2200 . The second conductive layer 1212 is formed to include the first pad 121a and a pattern portion disposed around the first pad 121a. The first pad 121 a is formed to include a part of the second conductive layer 1212 .

[0052] Referring to FIG. 10, a portion of the first conductive layer-forming layer P1211 is removed to form the first conductive layer 1211 and the first stopper layer 2100. The first conductive layer 1211 is formed using the same material as the first stopper layer 2100 . As a result, the first circuit layer 121 including the first conductive layer 1211 and the second conductive layer 1212 can be formed on the first insulating layer portion 111 . The first pad 121 a is formed such that the lower surface S 121 a of the first pad 121 a is positioned at a higher level than the lower surface S 121 of the first circuit layer 121 . The first pad 121a is formed such that the lower surface S121a of the first pad 121a is located farther from the upper surface of the first insulating layer portion 111 than the lower surface S121 of the first circuit layer 121.

[0053] As an example, the first conductive layer 1211 is removed through flash etching. The first stopper layer 2100 is formed to contain a first metal. The first metal is a material that has a different etch selectivity to the same material than the second metal. The first metal includes copper (Cu). The first stopper layer 2100 is formed on the first insulating layer portion 111. The first stopper layer 2100 has a shape corresponding to the second stopper layer 2200 . The first stopper layer 2100 can overlap the second stopper layer in the stacking direction.

[0054] Referring to FIG. 11, the second insulating layer portion 112 is formed so that the first circuit layer 121, the first stopper layer 2100, and the second stopper layer 2200 are embedded. The second insulating layer portion 112 is formed by laminating it on the first insulating layer portion 111 so that the first pads 121a are embedded therein. The second insulating layer portion 112 can be formed using a material such as prepreg (PPG), ABF (Ajinomoto build-up film), or RCC (Resin Coated Copper foil). As a result, the insulating layer 110 including the first insulating layer portion 111, the second insulating layer portion 112, and the third insulating layer portion 113 can be formed. Although the insulating layer is shown in the embodiment as including three layers, it is not limited thereto.

[0055] Referring again to FIG. 11, a first via hole 1311 is formed through the third conductive layer forming layer P1221 and the second insulating layer portion 112. The first via hole 1311 is formed by laser, mechanical drilling, or the like. Then, on one surface of the second insulating layer portion 112, a third conductive layer formation layer P1221 is formed. The third conductive layer-forming layer P1221 is formed on one surface of the second insulating layer portion 112 by electroless plating. In Figure 11, the third conductive layer forming layer P1221, which is an electroless plating layer, is shown as being placed only on one surface of the second insulating layer portion 112, but an electroless plating layer may also be placed on the inner surface of the first via hole 1311.

[0056] Referring to FIGS. 11 and 12, a fourth conductive layer 1222 is formed on a third conductive layer-forming layer P1221. The fourth conductive layer 1222 is formed through a plating process. In addition, the first via hole 1311 is filled with a conductive material to form the first via electrode 131 . As an example, the fourth conductive layer 1222 and the first via electrode 131 are formed by forming a photoresist on the third conductive layer formation layer P1221, patterning the photoresist through an exposure and development process, plating to fill the patterned area, and then peeling off the photoresist. However, the present invention is not limited to this, and any method that can form a pattern on a circuit board can be used without any restrictions. Then, referring to FIG. 12, a third conductive layer 1221 is formed by removing a portion of the third conductive layer-forming layer P1221. As a result, the second circuit layer 122 including the third conductive layer 1221 and the fourth conductive layer 1222 can be formed. As an example, the third conductive layer 1221 can be removed through flash etching.

[0057] Here, the second circuit layer 122 is formed to include the second pads 122a. The second pad 122 a is formed on one surface of the insulating layer 110 so as to be exposed from the insulating layer 110 . The second circuit layer 122 is formed to include second pads 122a and a pattern portion disposed around the second pads 122a. The second pad 122 a is formed to include a part of the third conductive layer 1221 and a part of the fourth conductive layer 1222 . The second pad 122a is formed by laminating an electroless plated layer and an electrolytic plated layer. Additionally, the carrier insulating layer 510 and the carrier conductive layer 520 are removed. For example, the carrier conductive layer 520 is removed through a quick etch. As a result, the third pad 124a, which is a part of the fourth circuit layer 124 exposed on the other surface of the insulating layer 110, can be formed. In other words, the fourth circuit layer 124 is formed to include the third pad 124a. In FIG. 12, the fourth circuit layer 124 is shown as being exposed on the other side of the insulating layer 110, but this is not limited thereto, and the fourth circuit layer 124 may be formed to include a third pad 124a and a pattern portion arranged around the third pad 124a. The third pad 124a is formed to include an electrolytic plating layer.

[0058] Referring to FIG. 13, a first protective layer 141 is formed on the second insulating layer portion 112 so as to expose a portion of the second circuit layer 122 . The second protective layer 142 is formed on the third insulating layer portion 113 so as to expose a portion of the fourth circuit layer 124 . The first protective layer 141 and the second protective layer 142 may be formed through an exposure and development process. The first protective layer 141 has an opening that exposes a portion of the second circuit layer 122 . The second protective layer 142 has an opening that exposes a portion of the fourth circuit layer 124 . The first protective layer 141 and the second protective layer 142 may be solder resist layers.

[0059] Referring to FIG. 14, a portion of the insulating layer 110 is removed from the other surface of the insulating layer 110 to the first stopper layer 2100 to form a first cavity forming portion 110a1. As an example, the insulating layer 110 is partially removed using a CO2 laser. By processing up to first stopper layer 2100 during laser processing, the portion of insulating layer 110 located above first stopper layer 2100 can be prevented from being damaged. For this reason, the area of ​​the first cavity forming portion 110a1 in the direction perpendicular to the stacking direction is smaller than the area of ​​the first stopper layer 2100. In other words, the width of the first cavity forming portion in the direction perpendicular to the stacking direction is smaller than the width of the first stopper layer 2100.

[0060] Referring to FIG. 15, the portion of the first stopper layer 2100 exposed in the first cavity forming portion 110a1 is etched and removed to form the first metal layer 210 and the second cavity forming portion 110a2. Forming the second cavity forming portion 110a2 includes removing the exposed portion of the first stopper layer 2100 and forming the remaining first metal layer 210 along the edge of the first cavity forming portion 110a1. The first metal layer 210 is formed to surround the cavity. The etching process may be, but is not limited to, dry etching or wet etching. As an example, an etching resist is formed on the remaining area of ​​the first stopper layer 2100 excluding the area to be etched, and the part of the first stopper layer 2100 to be etched is removed by etching. The etch resist may include a dry film.

[0061] Referring to FIG. 16, the portion of the second stopper layer 2200 exposed in the second cavity forming portion 110a2 is removed to form the second metal layer 220 and the cavity 110a. As a result, the metal pattern layer 200 including the first metal layer 210 and the second metal layer 220 can be formed. Forming the cavity 110a includes removing the exposed portion of the second stopper layer 2200 and forming the remaining second metal layer 220 along the edge of the second cavity forming portion 110a2. The second metal layer 220 is formed to surround the cavity 110a. The second metal layer 220 is formed at a position corresponding to the first metal layer 210 . The second metal layer 220 is formed so as to overlap the first metal layer 210 in the stacking direction.

[0062] The first pad 121 a is formed such that a lower surface S 121 a of the first pad 121 a is positioned at a higher level than a lower surface S 220 of the second metal layer 220 . The first pad 121 a is formed such that the bottom surface S 121 a of the first pad 121 a is located farther from the top surface of the first insulating layer portion 111 than the bottom surface S 220 of the second metal layer 220 . The etching process may be, but is not limited to, dry etching or wet etching. As an example, an etching resist is formed on the remaining area of ​​the first stopper layer 2100 excluding the area to be etched, and the part of the first stopper layer 2100 to be etched is removed by etching. The etch resist may include a dry film.

[0063] As an example, the first stopper layer 2100 is etched using a first etching solution, and the second stopper layer 2200 is etched using a second etching solution that is different from the first etching solution. The first stopper layer 2100 and the second stopper layer 2200 include metal materials that can be selectively removed by different etchants. As described above, for example, the first stopper layer 2100 includes a first metal, and the second stopper layer 2200 includes a second metal having an etching selectivity different from that of the first metal. Therefore, the first stopper layer 2100 and the second stopper layer 2200 can be sequentially removed using metals having different etching selectivities, and the first pad 121a can be exposed from the insulating layer 110 without damage.

[0064] Referring again to FIG. 1 together with FIG. 16, first to third surface treatment layers (151, 152, 153) are formed to cover portions of the circuit layer exposed to the outside of the insulating layer 110, thereby forming the circuit board 10A according to an embodiment of the present invention as shown in FIG. 1. A first surface processing layer 151 is formed on the first pad 121a. A second surface treatment layer 152 is formed on the second pad 122a. A third surface processing layer 153 is formed on the third pad 124a. For example, the first to third surface treatment layers (151, 152, 153) may be formed by ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold), ENIG (Electroless Nickel Immersion Gold), or the like. The first pad 121a is formed to have a thickness in the stacking direction that is smaller than the thickness of the first circuit layer 121. The first pad 121a is formed to have a thickness in the stacking direction that is smaller than the thickness of the second conductive layer 1212. The metal pattern layer 200 is formed to have a thickness in the stacking direction that is smaller than the thickness of the first circuit layer 121 . The first metal layer 210 is formed to have substantially the same thickness in the stacking direction as the thickness of the first conductive layer 1211 .

[0065] 1 and 2 together with FIG. 16, the first metal layer 210 is formed by etching the first stopper layer 2100 so as to extend inward from the side surface of the second insulating layer portion 112. For example, the first metal layer 210 has a curved inclined surface formed by a wet etching process. The first metal layer 210 is formed so that one surface exposed toward the cavity 110a includes an inclined surface inclined with respect to a reference line parallel to the stacking direction. The first metal layer 210 is formed to have a curved inclined surface. Furthermore, the second metal layer 220 is formed by etching the second stopper layer 2200 so as to extend inward from the side surface of the second insulating layer portion 112 . For example, the second metal layer 220 has a curved inclined surface formed by a wet etching process. The second metal layer 220 is formed so that one surface exposed toward the cavity 110a includes an inclined surface inclined with respect to a reference line parallel to the stacking direction. The second metal layer 220 is formed to have a curved inclined surface.

[0066] According to the method for manufacturing a circuit board according to an embodiment of the present invention, by using a plurality of metal layers each containing different metals as an etching stop layer, the efficiency of the process can be improved and the pads can be more easily exposed in the cavity, thereby making it possible to form a thinner circuit board.

[0067] An electronic component package according to an embodiment of the present invention will now be described with reference to FIG. FIG. 17 is a cross-sectional view showing a schematic configuration of an electronic component package according to an embodiment of the present invention. Referring to FIG. 17, an electronic component package 20 according to an embodiment of the present invention includes a first circuit board 10. The first circuit board 10 includes the circuit board 10A according to the embodiment of the present invention described above. In the following, the description of the first circuit board 10 is the same as the description of the circuit board 10A according to the embodiment of the present invention.

[0068] The electronic component package 20 according to the embodiment of the present invention includes a first circuit board 10, a second circuit board 21, an electronic component 22, an encapsulant 23, a conductive member 24, and an electrode 25. The second circuit board 21 is connected to the first circuit board 10. The first circuit board 10 has a cavity 110a and includes a first pad 121a exposed from the insulating layer 110 within the cavity 110a. The electronic component 22 is mounted on one surface of the first circuit board 10 so as to be connected to the pad portion of the first circuit board 10 . An electronic component 22 may be housed inside the cavity 110a. The sealing material 23 is disposed between the first and second circuit boards (10, 21). The sealing material 23 covers at least a portion of the electronic component 22 . The conductive member 24 electrically connects the first and second circuit boards (10, 21). The electrodes 25 electrically connect the first circuit board 10 and the electronic component 22 .

[0069] The second circuit board 21 is a circuit board on which electronic components 22 are mounted, and includes an insulating layer, a wiring layer, a via layer, and a solder resist layer. As an example, the electronic component 22 may be an integrated circuit (IC) die in which hundreds to millions of elements are integrated into a single chip. For example, the electronic component 22 may be a processor chip such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, specifically an application processor (AP), but is not limited thereto. It may also be memory such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory, or logic such as an analog-to-digital converter or an application-specific IC (ASIC). If necessary, the electronic component 22 may be a chip-type passive component, for example, a chip-type capacitor such as a multi-layer ceramic capacitor (MLCC), or a chip-type inductor such as a power inductor (PI). The electronic component 22 may be covered by the encapsulant 23 and may be in physical contact with the encapsulant 23 on at least one side.

[0070] The sealing material 23 covers one surface of the first circuit board 10 and at least a portion of the outer surface of the electronic component 22 . The encapsulant 23 also fills at least a portion of the cavity 110 a , thereby covering at least a portion of the top surface of the electronic component 22 . For example, the encapsulant 23 is in physical contact with at least a portion of each of the top, bottom, and side surfaces of the electronic component 22 . The sealing material 23 has fluidity before hardening, and therefore can flow along the outer surface of the electronic component 22 and fill the inside of the cavity 110a. The sealing material 23 is made of an insulating material, and the insulating material may be a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. Furthermore, these resins may contain inorganic fillers such as silica. For example, the material of the sealing material 23 may be ABF (Ajinomoto Build-up Film). The ABF may be provided in a resin coated copper (RCC) form, but is not limited thereto. If necessary, a photosensitive material such as PIE (Photo Imageable Dielectric) can also be used. The sealing material 23 may be a known EMC (Epoxy Molding Compound), but is not limited to this.

[0071] The conductive member 24 is disposed in at least a portion of the opening in the first circuit board 10 . The conductive member 24 physically and / or electrically connects the first circuit board 10 to the outside. For example, the conductive member 24 electrically connects the exposed circuit pattern layer of the second circuit board 21 and the third pad 124 a of the first circuit board 10 . The conductive members 24 may be formed from tin (Sn) or an alloy containing tin (Sn), such as, but not limited to, solder. For example, the conductive member 24 may be a ball, a land, a pin, a metal post in the shape of a pillar, or a pillar formed by combining a plurality of balls. The electrode 25 is disposed in the cavity 110 a of the first circuit board 10 . The electrodes 25 physically and / or electrically connect the first circuit board 10 to the electronic component 22 . For example, the electrode 25 electrically connects the pad portion of the electronic component 22 to the first pad 121 a of the first circuit board 10 .

[0072] According to the electronic component package of the embodiment of the present invention, the pad portion is arranged inside the cavity of the first circuit board in which the electronic component is housed, thereby making it possible to provide a thin package while ensuring mounting space for the electronic component.

[0073] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0074] 10A, 10B circuit board 20 Electronic Component Package 22 Electronic Components 110 Insulating layer 111, 112, 113 (1st to 3rd) insulating layer parts 110a cavity 121, 122, 123, 124 (1st to 4th) circuit layer 121a 1st pad 122a 2nd pad 124a 3rd Pad 131, 132, 133 (1st to 3rd) via electrodes 141, 142 (1st, 2nd) protective layer 151, 152, 153 (1st to 3rd) surface treatment layers 200 metal pattern layers 210 first metal layer, 220 2nd metal layer 1211 First conductive layer 1212 Second conductive layer 1221 Third conductive layer 1222 4th conductive layer 1231 5th conductive layer 1232 6th conductive layer 2100 First stopper layer 2200 Second stopper layer

Claims

1. an insulating layer including a first insulating layer portion and a second insulating layer portion stacked on the first insulating layer portion, the insulating layer having a cavity penetrating a part of the second insulating layer portion and the first insulating layer portion; a circuit layer at least partially embedded in the second insulating layer portion; a metal pattern layer disposed within the second insulating layer portion along the edge of the cavity; the insulating layer has a first surface that forms a bottom surface of the cavity and a second surface that forms a side surface of the cavity, The metal pattern layer is exposed from the insulating layer on the second surface and includes a plurality of metal layers containing different metals.

2. The circuit board according to claim 1 , wherein the plurality of metal layers have different etching selectivities with respect to the same material.

3. The circuit board according to claim 1 , wherein the metal pattern layer is disposed in a corner region of the cavity so as to connect the first surface and the second surface.

4. 2. The circuit board according to claim 1, wherein the metal pattern layer includes a first metal layer containing copper and a second metal layer disposed on the first metal layer and containing nickel.

5. the circuit layer includes a first conductive layer disposed on the first insulating layer portion and a second conductive layer stacked on the first conductive layer; The circuit board according to claim 4 , wherein one surface of the second conductive layer is disposed on substantially the same plane as one surface of the second metal layer.

6. The circuit board according to claim 4 , wherein the circuit layer includes a first conductive layer containing the same material as the first metal layer.

7. The circuit board of claim 1 , further comprising a first pad exposed from the second insulating layer on the first surface.

8. The circuit board according to claim 7 , wherein the first pad is partially embedded in the insulating layer.

9. 8. The circuit board according to claim 7, wherein, in terms of distance in the stacking direction relative to the first insulating layer portion, the surface of the first pad exposed from the second insulating layer portion is located farther away than the surface of the circuit layer facing the first insulating layer portion.

10. 2. The circuit board according to claim 1, wherein the thickness of the first pad in the stacking direction is smaller than the thickness of the circuit layer.

11. 2. The circuit board according to claim 1, wherein the circuit layer includes a first conductive layer containing copper and a second conductive layer disposed on the first conductive layer.

12. The circuit board according to claim 11 , wherein the first conductive layer comprises an electroless plating layer.

13. The circuit board according to claim 1 , wherein the metal pattern layer is recessed inward from the second surface.

14. The circuit board according to claim 1 , further comprising a first pad exposed from the insulating layer on one surface where the cavity is disposed.

15. forming a first stopper layer including a first metal on the first insulating layer portion; forming a second stopper layer on the first stopper layer, the second stopper layer including a second metal different from the first metal; forming a first pad on the second stopper layer; forming a second insulating layer portion on the first insulating layer portion so that the first pad is embedded therein; removing the first insulating layer portion on the first stopper layer by an area smaller than an area of ​​the first stopper layer to form a first cavity forming portion; removing a portion of the first stopper layer exposed in the first cavity forming portion to form a second cavity forming portion; removing a portion of the second stopper layer exposed in the second cavity forming portion to form a cavity.

16. 16. The method of claim 15, wherein forming the second stopper layer comprises forming the second stopper layer including the second metal having a different etching selectivity than the first metal with respect to the same material.

17. The step of forming the second cavity forming portion includes:

16. The method of claim 15, further comprising removing the exposed portion of the first stopper layer and forming a remaining first metal layer along an edge of the first cavity forming portion.

18. 18. The method of claim 17, wherein forming the cavity comprises removing the exposed portion of the second stopper layer and forming a remaining second metal layer along an edge of the second cavity forming portion.

19. forming the first stopper layer includes forming the first stopper layer containing copper; 20. The method of claim 18, wherein forming the second stopper layer comprises forming the second stopper layer containing nickel.

20. The method further includes forming a circuit layer on the first insulating layer portion, The step of forming the circuit layer includes: forming a first conductive layer on the first insulating layer portion; 16. The method of claim 15, further comprising: forming a second conductive layer on the first conductive layer so that the second conductive layer has one surface at substantially the same level as one surface of the second stopper layer.

21. The step of forming the first conductive layer includes:

21. The method of claim 20, further comprising forming the first conductive layer containing the same material as the first stopper layer.

22. The method further includes forming a circuit layer on the first insulating layer portion, 16. The method of claim 15, wherein forming the first pad comprises forming the first pad such that a surface of the first pad exposed from the second insulating layer portion is at a higher level than a surface of the circuit layer facing the first insulating layer portion.

23. The method further includes forming a circuit layer on the first insulating layer portion, 16. The method of claim 15, wherein forming the first pad comprises forming the first pad to have a thickness in the stacking direction that is smaller than a thickness of the circuit layer.

24. The method of claim 15, further comprising forming a surface treatment layer on the first pad.

25. The method further includes forming a circuit layer on the first insulating layer portion, The step of forming the circuit layer includes: forming a first conductive layer comprising copper; 16. The method of claim 15, further comprising: forming a second conductive layer on the first conductive layer.

26. 26. The method of claim 25, wherein forming the first conductive layer comprises forming an electroless plating layer.

27. 16. The method of claim 15, further comprising the step of etching the first stopper layer to form a first metal layer inward from a side surface of the second insulating layer portion.

28. 28. The method of claim 27, further comprising the step of etching the second stopper layer to form a second metal layer so as to extend inward from a side surface of the second insulating layer portion.

29. forming an insulating layer including the first insulating layer portion and the second insulating layer portion, the insulating layer having the cavity formed on one surface; The method of claim 15, further comprising forming a second pad on the one surface of the insulating layer so as to be exposed from the insulating layer.

30. a circuit board having a cavity and including a pad portion exposed from an insulating layer within the cavity; an electronic component mounted in the cavity so as to be connected to the pad portion, The circuit board includes: an insulating layer having the cavity; a circuit layer at least partially embedded in the insulating layer; a metal pattern layer disposed within the insulating layer along an edge of the cavity; the insulating layer has a first surface that forms a bottom surface of the cavity and a second surface that forms a side surface of the cavity; The electronic component package, wherein the metal pattern layer is exposed from the insulating layer at the second surface and includes a plurality of metal layers containing different metals.

31. 31. The electronic component package of claim 30, wherein the metal pattern layer includes a first metal layer including copper and a second metal layer including nickel disposed on the first metal layer.

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