Method for transferring pattern onto epitaxial layer of light emitting element

Abstract

To provide a method for transferring a suitable pattern onto an epitaxial layer of a light emitting element.SOLUTION: A light emitting element has a light extraction or guiding structure, the light extraction or the guiding structure is integrated within their epitaxial layers, the light extraction and the guiding structure are fabricated using a lateral epitaxial growth technique that transfers the pattern from the growth-restricting mask and / or host substrate to the epitaxial layer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit under 35 USC Section 119(e) of the following co-pending and commonly assigned applications:

[0002] U.S. Provisional Application No. 63 / 106,444 (Attorney Docket No. G&C30794.0786USP1 (UC 2021-565-1)), filed October 28, 2020, by Srinivas Gandrothula and Takeshi Kamikawa, and entitled "METHOD OF TRANSFERRING A PATTERN TO AN EPITAXIAL LAYER OF A LIGHT EMITTING DEVICE," is incorporated herein by reference.

[0003] This application is related to the following co-pending and commonly assigned applications:

[0004] U.S. Utility Patent Application No. 16 / 608,071 (Attorney Docket No. 30794.0653USWO(UC2017-621-2)), filed October 24, 2019, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, entitled "METHOD OF REMOVING A SUBSTRATE," which application was filed May 7, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, entitled "METHOD OF REMOVING A SUBSTRATE," under 35 U.S.C. Section 365(c). This application claims the benefit of commonly assigned, copending PCT International Patent Application No. PCT / US18 / 31393 (Attorney Docket No. 30794.0653WOU1 (UC2017-621-2)), entitled "METHOD OF REMOVING A SUBSTRATE," which in turn claims the benefit of commonly assigned, copending U.S. Provisional Patent Application No. 62 / 502,205 (Attorney Docket No. 30794.0653USP1 (UC2017-621-1)), filed May 5, 2017, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, entitled "METHOD OF REMOVING A SUBSTRATE," under 35 U.S.C. § 119(e).

[0005] U.S. Utility Patent Application No. 16 / 642,298 (Attorney Docket No. 30794.0659USWO(UC2018-086-2)) filed on February 26, 2020, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled "METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE," which was filed on September 17, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled "METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE" under 35 U.S.C. Section 365(c) (U.S.C. 365(c)). This application claims the benefit of co-pending and commonly assigned PCT International Patent Application No. PCT / US18 / 51375 (Attorney Docket No. 30794.0659WOU1 (UC2018-086-2)), entitled "METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE," filed September 15, 2017, under 35 U.S.C. Section 119(e) by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled "METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE." This application claims the benefit of co-pending and commonly assigned U.S. Provisional Patent Application No. 62 / 559,378 (Attorney Docket No. 30794.0659USP1 (UC2018-086-1)), entitled "METHOD OF USE IN A HIGH-FREQUENCY PHOTOMETRY TECHNIQUE."

[0006] U.S. Utility Patent Application No. 16 / 978,493 (Attorney Docket No. 30794.0680USWO(UC2018-427-2)) filed September 4, 2020, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled "METHOD OF FABRICATING NON-POLAR AND SEMI-POLAR DEVICES USING EPITAXIAL LATERAL OVERGROWTH," which application was filed April 1, 2019, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled "METHOD OF FABRICATING NON-POLAR AND SEMI-POLAR DEVICES USING EPITAXIAL LATERAL OVERGROWTH" under 35 U.S.C. Section 365(c) (35 U.S.C. § 365(c)). This application claims the benefit of co-pending and commonly assigned PCT International Patent Application No. PCT / US19 / 25187 (Attorney Docket No. 30794.0680WOU1 (UC2018-427-2)), entitled "METHOD OF FABRICATING NON-POLAR AND SEMI-POLAR DEVICES USING EPITAXIAL LATERAL MICROFIBER OVERGROWTH," filed March 30, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li under 35 U.S.C. Section 119(e) and entitled "METHOD OF FABRICATING NON-POLAR AND SEMI-POLAR DEVICES USING EPITAXIAL LATERAL MICROFIBER OVERGROWTH." This application claims the benefit of co-pending and commonly assigned U.S. Provisional Patent Application No. 62 / 650,487 (Attorney Docket No. G&C30794.0680USP1 (UC2018-427-1)), entitled "METHOD OF USE IN A HIGH-FREQUENCY PHASE OVERGROWTH."

[0007] U.S. Utility Patent Application No. 17 / 049,156 (Attorney Docket No. 30794.0682USWO(UC 2018-614-2)), filed October 20, 2020, by Srinivas Gandrothula and Takeshi Kamikawa, entitled "METHOD OF REMOVING SEMICONDUCTING LAYERS FROM A SEMICONDUCTING SUBSTRATE," which application is hereby incorporated by reference in its entirety under 35 U.S.C. § 365(c) by Srinivas Gandrothula and Takeshi Kamikawa, filed May 30, 2019 ... This application claims the benefit of co-pending and commonly assigned PCT International Patent Application No. PCT / US19 / 34868 (Attorney Docket No. G&C30794.0682WOU1 (UC 2018-614-2)) entitled "METHOD OF REMOVING SEMICONDUCTION LAYERS FROM A SEMICONDUCTION SUBSTRATE," filed May 30, 2018, by Srinivas Gandrothula and Takeshi Kamikawa under 35 U.S.C. Section 119(e) and entitled "METHOD OF REMOVING SEMICONDUCTION LAYERS FROM A SEMICONDUCTION SUBSTRATE." This application claims the benefit of co-pending and commonly assigned U.S. Provisional Application No. 62 / 677,833 (Attorney Docket No. G&C30794.0682USP1 (UC2018-614-1)), entitled "A Method and Apparatus for Producing a Novel Substrate."

[0008] The entirety of that application is incorporated herein by reference.

[0009] FIELD OF THE INVENTION The present invention relates to a method for transferring a pattern into an epitaxial layer of a light emitting device. [Background technology]

[0010] For III-nitride semiconductor devices such as light-emitting diodes (LEDs) and laser diodes (LDs), both the extraction and the corresponding output power have been significantly improved by surface roughening methods such as patterned sapphire substrates (PSS) and photoelectrochemical (PEC) etching techniques. For III-nitride LEDs, the light extraction efficiency has become the most important limiting factor for LED efficiency, as the internal quantum efficiency (IQE) of nitride-based LEDs has been significantly improved (above 80%) due to the availability of low-dislocation GaN substrates and advances in metalorganic chemical vapor deposition (MOCVD) techniques.

[0011] The effectiveness of these surface roughening methods generally depends on the crystallographic orientation and polarity of the surface to be patterned, which to date has only been established for the nitrogen face of c-polar 0001 GaN and is not yet available for arbitrary GaN crystallographic orientations and polarities, including most semipolar and nonpolar a- and m-plane surfaces.

[0012] Reactive ion etching (RIE) is another method used to pattern conical features and improve light extraction regardless of crystal orientation, although a limitation lies in the lack of control over the direction of emitted light.

[0013] Improving the directionality of light emission has been widely investigated to control the propagation of electromagnetic modes within optoelectronic devices, either through the use of microcavities or photonic crystals (PhCs). Periodic modulation of the refraction acts as an optical lattice, coupling guided modes from the semiconductor device to the air, thus increasing the extraction efficiency and directionality of the LED. The application of gratings for light diffraction within optoelectronic devices requires that the grating period be approximately half the wavelength of the light generated by the device. For GaN-based optoelectronic devices, the grating period needs to be approximately several hundred nanometers.

[0014] A major drawback of PhC LEDs is their delicate fabrication requirements. Thus, there is a need in the art for improved methods of fabricating light directing or extraction features. Summary of the Invention [Means for solving the problem]

[0015] To overcome the limitations in the prior art described above, as well as other limitations that will become apparent upon perusal and understanding of this specification, the present invention discloses a method for epitaxially fabricating light guiding or extraction features on a growth-limiting mask of a host substrate, which can be a homogeneous or heterogeneous substrate, including a substrate with a template deposited thereon. The light guiding or extraction features are fabricated on wings of a III-nitride epitaxial lateral overgrowth (ELO) layer, thereby resulting in devices with superior crystalline quality in terms of reduced dislocation density and stacking faults.

[0016] Specifically, the present invention implements the following steps: an island-shaped III-nitride semiconductor layer is grown on a substrate using a growth-limiting mask and an ELO method, where the growth-limiting mask plays an important role in obtaining the desired light extraction or light guiding function; before growth, the growth-limiting mask is patterned with either a roughened surface or a PhC surface; and the light-emitting aperture is at least partially confined to the wings of the III-nitride ELO layer so that a good crystal quality layer can be guaranteed.

[0017] Devices are then fabricated on the wings of the III-nitride ELO layer, and the devices are extracted from the host substrate. Note that the isolated devices remain on the host substrate with only minimal connections, such as epitaxial or non-epitaxial bridges, until the entire device is finished. Once removed from the substrate, the devices are transferred to another carrier or substrate by an elastomeric stamp, a vacuum chuck, adhesive tape, or simply by bonding or attaching the device to a separate carrier or substrate.

[0018] The III-nitride semiconductor layers are dimensioned so that one or more of the III-nitride semiconductor island layers form rods (known as element rods). This allows nearly identical elements to be fabricated adjacent to each other in a self-assembled array, and therefore scaling up by integration can be more easily achieved. Alternatively, the III-nitride ELO layers can be first fabricated to coalesce so that they can later be separated into element rods or individual elements.

[0019] All elements can be addressed separately or together with other elements by designing an appropriate fabrication process. For example, one can fabricate a common cathode or anode for such a bar of elements for monolithic integration, or address individual elements for full-color display applications. As a result, high yields can be obtained.

[0020] Important aspects of the present invention include the following: Light extraction and / or directionality is controlled. Light extraction or guiding features are introduced onto the wings of the III-nitride ELO layer prior to growth of the active layer of the device. · Light extraction or guiding features are placed on the backside of the III-nitride ELO layer. · Roughening or periodic patterning is achieved without the plasma damage of chemical etchants or dry etching processes. A roughened or periodic pattern is created on the epitaxial layer. · Roughening or periodic patterning is present in the vicinity of the active area. The light-emitting area of ​​the device is fabricated on the wings of the III-nitride ELO layer, thereby providing better crystal quality within the light-emitting area, which improves performance. The present invention can be utilized to increase yield by fabricating smaller footprint devices confined to the wings of III-nitride ELO layers. The present invention can utilize foreign substrates such as Si, SiC, sapphire, template substrates, ELO-assisted semiconductor substrates, etc. to expand manufacturability for industrial needs. The present invention is independent of the crystal orientation of the host substrate. The substrate can be recycled for the next batch of devices.

[0021] Some possible designs using the method are illustrated in the detailed description of the invention below. The present invention, when combined with the cross-referenced inventions relating to removing semiconductor devices from semiconductor substrates described above, has many advantages over conventional manufacturable device elements. The present invention provides, for example, the following. (Item 1) 1. A method, comprising: forming a growth-limiting mask on a host substrate, wherein one or more patterns are formed on the growth-limiting mask and / or the host substrate; growing one or more epitaxial lateral overgrowth (ELO) layers and device layers on the host substrate using the growth limiting mask; Including, The method wherein the ELO layer and device layer contain copies of the pattern. (Item 2) Item 10. The method of item 1, wherein the pattern provides a light control structure at the interface between the ELO layer and the host substrate. (Item 3) Item 10. The method of claim 1, wherein the pattern comprises one or more random valley-peak patterns. (Item 4) Item 10. The method of item 1, wherein the pattern comprises one or more two-dimensional (2D) periodic grating arrays equal in size to the wavelength of light emitted from the active region. (Item 5) Item 6. The method of item 1, wherein the 2D periodic grating array comprises a photonic crystal. Item 10. The method of item 1, wherein the pattern comprises one or more curved surfaces. (Item 7) Item 7. The method of item 6, wherein at least one of the curved surfaces comprises a plano-concave mirror of a resonant cavity of a vertical-cavity surface-emitting laser (VCSEL). (Item 8) 8. The method of claim 7, wherein the resonant cavity is comprised of one or more layers that are epitaxially grown. (Item 9) Item 10. The method of item 1, wherein the pattern comprises one or more non-horizontal regions. (Item 10) Item 10. The method of item 1, wherein the host substrate has a trench. (Item 11) Item 10. The method of claim 1, wherein the host substrate is a semiconductor substrate. (Item 12) Item 12. The method of item 11, wherein the semiconductor substrate is independent of crystal orientation. (Item 13) Item 10. The method of claim 1, wherein the growth-limiting mask comprises one or more layers. (Item 14) A device fabricated by the method described in item 1. (Item 15) Item 15. The device according to item 14, wherein the device is a light emitting diode (LED). (Item 16) Item 15. The device of item 14, wherein the device is a vertical cavity surface emitting laser (VCSEL). [Brief explanation of the drawings]

[0022] Reference is now made to the drawings in which like reference numbers represent corresponding parts throughout.

[0023] [Figure 1A] 1A, 1B, and 1C are schematic diagrams of a substrate, a growth-limiting mask, and coalesced and non-coalesced epitaxial layers according to one embodiment of the present invention. [Figure 1B] 1A, 1B, and 1C are schematic diagrams of a substrate, a growth-limiting mask, and coalesced and non-coalesced epitaxial layers according to one embodiment of the present invention. [Figure 1C] 1A, 1B, and 1C are schematic diagrams of a substrate, a growth-limiting mask, and coalesced and non-coalesced epitaxial layers according to one embodiment of the present invention.

[0024] [Figure 2] FIG. 2 is a flow chart for a method of fabricating a light-emitting device.

[0025] [Figure 3A] 3A, 3B, and 3C are schematic diagrams of growth-limiting masks with different shapes of possible patterns. [Figure 3B] 3A, 3B, and 3C are schematic diagrams of growth-limiting masks with different shapes of possible patterns. [Figure 3C] 3A, 3B, and 3C are schematic diagrams of growth-limiting masks with different shapes of possible patterns.

[0026] [Figure 4A] 4A, 4B, and 4C illustrate experimental results for various patterns of host substrate and growth-limiting mask. [Figure 4B] 4A, 4B, and 4C illustrate experimental results for various patterns of host substrate and growth-limiting mask. [Figure 4C] 4A, 4B, and 4C illustrate experimental results for various patterns of host substrate and growth-limiting mask.

[0027] [Figure 5A] 5A, 5B, 5C, and 5D illustrate structures for realizing a plano-concave resonant cavity VCSEL. [Figure 5B] 5A, 5B, 5C, and 5D illustrate structures for realizing a plano-concave resonant cavity VCSEL. [Figure 5C] 5A, 5B, 5C, and 5D illustrate structures for realizing a plano-concave resonant cavity VCSEL. [Figure 5D]5A, 5B, 5C, and 5D illustrate structures for realizing a plano-concave resonant cavity VCSEL.

[0028] [Figure 6A] 6A, 6B, and 6C illustrate different types of curvature shapes obtained at the interface of epitaxial lateral overgrowth layers. [Figure 6B] 6A, 6B, and 6C illustrate different types of curvature shapes obtained at the interface of epitaxial lateral overgrowth layers. [Figure 6C] 6A, 6B, and 6C illustrate different types of curvature shapes obtained at the interface of epitaxial lateral overgrowth layers.

[0029] [Figure 7A] 7A and 7B illustrate a device fabricated using the present invention. [Figure 7B] 7A and 7B illustrate a device fabricated using the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0030] In the following description of the preferred embodiment, reference is made to specific embodiments in which the present invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

[0031] (overview) The present invention describes a method for fabricating semiconductor devices such as light-emitting devices (including LEDs and plano-concave VCSELs) by appropriately designing growth restriction masks. Because ELO is relied upon in this invention, it is easily applicable to foreign substrates (such as Si, SiC, sapphire, semiconductor layer templates, or host substrates containing ELO-engineered layer templates). The ELO-engineered layer templates enable the use of GaN on sapphire substrates, GaN on silicon substrates, etc. LEDs, PhC LEDs, and VCSELs can be fabricated on the ELO wings with good crystal quality, and then each device can be isolated from the host substrate, selectively removed, or transferred to a display back panel or product.

[0032] 1A illustrates the method using schematic diagrams 100a1 and 100a2. The method begins with providing a III-nitride based substrate 101, such as a bulk GaN substrate 101.

[0033] Schematic diagram 100a1 shows a growth-limiting mask 102 formed on or above a III-nitride based substrate 101. Specifically, the growth-limiting mask 102 is placed in direct contact with the substrate 101, or the growth-limiting mask 102 is placed indirectly, such as through an intermediate layer (made from a III-nitride based semiconductor layer or template deposited on the substrate 101) grown by MOCVD or the like.

[0034] The growth limiting mask 102 can be formed from an insulator film (e.g., a SiO2 film deposited on a base substrate 101 by plasma-enhanced chemical vapor deposition (CVD), sputtering, ion beam deposition (IBD), etc.), which is patterned by photolithography using a predetermined optical mask and then etched to include open areas 103 and no-growth regions 104 (which may or may not be patterned). The present invention can use SiO2, SiN, SiON, TiN, etc. as the growth limiting mask 102. A multi-layer growth limiting mask 102 made of the above materials is preferred.

[0035] An epitaxial III-nitride layer 105, such as a GaN-based layer 105, is grown on the GaN substrate 101 and the growth-limiting mask 102 using the ELO method. Growth of the III-nitride ELO layer 105 occurs first in the open areas 103 on the III-nitride-based substrate 101 and then laterally from the open areas 103 over the growth-limiting mask 102. The growth of the III-nitride ELO layer 105 can be stopped (or interrupted) before the III-nitride ELO layer 105 in adjacent open areas 103 can coalesce on top of the growth-limiting mask 102, and this interrupted growth results in no-growth regions 104 between adjacent III-nitride ELO layers 105. Alternatively, the growth of III-nitride ELO layer 105 may continue and coalesce with neighboring III-nitride ELO layers 105, thereby forming coalesced regions 106 of increased defects in the encountered areas, as shown in schematic diagram 100a2.

[0036] 1B, schematic diagram 100b1 illustrates that additional III-nitride device layers 107 may include active region 107a, p-type layer 107b, electron blocking layer (EBL) 107c, and cladding layer 107d, as well as other layers, deposited on or above III-nitride ELO layer 105.

[0037] III-nitride ELO layer 105 and III-nitride device layer 107 include one or more flat surface regions 108 and layer bending regions 109 adjacent to and at the edges of no-growth regions 104 when III-nitride ELO layer 105 is stopped before coalescence, as shown at 100a1 in FIG. 1A, or when III-nitride ELO layer 105 is continued to coalesce within coalesced regions 106, as shown at 100a2 in FIG. 1A. The width of flat surface region 108 is at least 3 μm, and most preferably 10 μm or greater.

[0038] The light-emitting active region 107a of the device 110 is preferably processed in the flat surface region 108 between the open area 103 and the edge portion 109 or merged region 106. By doing so, the rod of the device 110 will possess an array of pairs of, or nearly identical, light-emitting apertures along the length of the rod, on either side of the open area 103. Additionally, electrodes may be placed on the device layer 107 and on the back interface 111 between the III-nitride ELO layer 105 and the growth limiting mask 102.

[0039] There are many methods for removing the light emitting device 110 from the substrate 101. For example, the present invention can utilize an ELO method to remove the light emitting device 110. In the present invention, the bonding strength between the substrate 101 and the III-nitride ELO layer 105 is weakened by the growth limiting mask 102. In this case, the bonding area between the substrate 101 and the III-nitride ELO layer 105 is the open area 103, and the width of the open area 103 is narrower than that of the III-nitride ELO layer 105. As a result, the bonding area is reduced by the growth limiting mask 102, thereby making this method preferable for removing the epitaxial layers 105, 107.

[0040] In the schematic diagrams 100c1 and 100c2 in FIG. 1C, the open regions of III-nitride ELO layer 105 are labeled as regions 112, and the regions where wings of neighboring III-nitride ELO layers 105 may or may not meet are labeled as regions 113.

[0041] The present invention proposes several approaches to realizing light extraction or light steering tools for light emitting devices.

[0042] Typical fabrication steps for the present invention are described in further detail below:

[0043] Step 1: Form the desired shape on the growth limiting mask 102, which can be achieved by: The growth limiting mask 102 is placed on the host substrate 101, and the growth limiting mask 102 is patterned or shaped using nanoimprint lithography, or the pattern or shape can be transferred onto the growth limiting mask 102 using photolithography and wet etching, or photolithography and dry etching.

[0044] Step 2: The growth limiting mask 102 has a plurality of stripe-shaped open areas 103 exposing the substrate 101, and the substrate 101 is a group III nitride-based semiconductor, or the substrate 101 is a heterosubstrate (silicon, silicon nitride, sapphire, etc.), or a template is prepared to include the growth limiting mask 102.

[0045] Step 3: Multiple epitaxial layers 105, 107 are grown on or above the substrate 101 using the growth-limiting mask 102, with the growth extending in a direction parallel to the striped open areas 103 of the growth-limiting mask 102. The epitaxial layers 105, 107 take on the pattern or shape designed on the growth-limiting mask 102, thereby transferring the designed pattern or shape onto the interface 111 surface between the III-nitride ELO layer 105 and the growth-limiting mask 102.

[0046] Step 4: Light emitting devices 110, such as LEDs or VCSELs, are fabricated by conventional methods on the wing regions of the III-nitride ELO layer 105, primarily on the planar surface regions .

[0047] Step 5: Divide the device 110 and isolate the device 110 on the host substrate 101.

[0048] Step 6: Install the submount.

[0049] Step 7: A chemical etchant such as buffered hydrofluoric acid (BHF) or hydrofluoric acid (HF) is used to dissolve the growth limiting mask 102 and the protective layer.

[0050] Step 8: Separate the device 110 from the host substrate 101.

[0051] Step 9: Final processing of device 110 is performed (such as placing a distributed Bragg reflector (DBR) on the curved mirror for the VCSEL), and then device 110 is packaged.

[0052] (Process Step) FIG. 2 is a flow chart illustrating steps for implementation of element 110 according to one embodiment of the present invention.

[0053] Block 201 represents the step of providing a host substrate 101, which is a semiconductor substrate, and which is crystal orientation independent. In one example, the host substrate 101 has one or more trenches.

[0054] Block 202 represents the step of forming a growth limiting mask 102 on the host substrate 101, the growth limiting mask consisting of one or more layers.

[0055] Blocks 203, 204, and 205 represent steps of forming one or more patterns on the growth-limiting mask 102 and / or the host substrate 101, where the patterns provide light control structures at the interface between the III-nitride ELO layer 105 and the host substrate 101. Specifically, block 203 comprises one or more random patterns, such as one or more random valley-ridge patterns (e.g., one or more non-horizontal regions), block 204 represents a 2D periodic grating array with a size equal to the wavelength of light emitted from the active region 107a, i.e., the PhC, and block 205 represents one or more concave patterns or curved surfaces (e.g., a plano-concave mirror of a resonant cavity of a vertical-cavity surface-emitting laser (VCSEL)), where the resonant cavity is composed of one or more epitaxially grown layers.

[0056] Block 206 represents the step of opening stripes of open areas 103 on the growth-limiting mask 102 for ELO growth.

[0057] Blocks 207 and 208 represent the step of growing a III-nitride ELO layer 105 on the growth limiting mask 102; the III-nitride ELO layer 105 may be uncoalesced in block 207 or may be coalesced in block 208, after which the III-nitride device layer 107 may be grown on the III-nitride ELO layer 105.

[0058] Block 209 represents the step of singulating the devices 110 onto the host substrate 101 .

[0059] Block 210 represents the step of removing device 110 from host substrate 101, and block 211 represents the step of reusing host substrate 101.

[0060] Block 212 represents the step of performing any necessary post-processing of the device 110, for example, for the VCSEL device 110.

[0061] These steps are described in further detail below.

[0062] (Forming a growth restriction mask) In one embodiment, a III-nitride based layer 105 is grown by ELO on a III-nitride substrate 101, such as an m-plane GaN substrate 101, patterned with a growth-limiting mask 102 made of SiO, where the III-nitride ELO layer 105 may or may not coalesce on top of the SiO.

[0063] The growth-limiting mask 102 consists of striped open areas 103, and the SiO2 stripes of the growth-limiting mask 102 between the open areas 103 have a width of 1 μm to 20 μm and a spacing of 10 μm to 100 μm. If a non-polar substrate is used, the open areas 103 may be <0001> The open area 103 is oriented along the axis. If a semipolar (20-21) or (20-2-1) plane is used, the open area 103 is oriented parallel to the [-10-14] or [10-14] axis, respectively. Other planes may be used as well, with the open area 103 oriented in other directions.

[0064] When using the III-nitride substrate 101, the present invention can obtain high-quality III-nitride semiconductor layers 105, 107. As a result, the present invention can easily obtain devices with reduced defect (such as dislocations and stacking faults) density.

[0065] Furthermore, these techniques can be used with heterosubstrates such as sapphire, SiC, LiAlO 2 , Si, Ga 2 O 3 , etc., as long as they allow growth of the III-nitride ELO layer 105 through the growth-limiting mask 102.

[0066] (Pattern on growth restriction mask) Before proceeding to open the stripes on the growth-limiting mask 102, pre-processing is performed on the growth-limiting mask 102. The present invention proposes three different possible types of patterns for the elements 110. However, several alternative designs can also be implemented in the same manner as described below. The random peak-valley pattern on the growth-limiting mask 102 will be transferred to the interface 111 with the ELO layer 105 during MOCVD growth. The element 110 fabrication, including p-pads and n-pads, is performed on the surface of the III-nitride ELO layer 105, and the elements 110 are singulated on the host substrate 101, and the elements 110 are removed using a carrier wafer. The result is a random peak-valley pattern remaining at the interface 111 of the III-nitride ELO layer 105. This also applies to any other patterns, such as PhC for LEDs or VCSELs. In the case of a PhC for an LED, the pattern must have dimensions on the order of the wavelength of the light emitted by the element 110, and in the case of a PhC for a VCSEL, a concave surface with a radius of curvature is designed such that the beam waist must pass through the plano-concave mirror cavity with little loss.

[0067] (Growth-limiting masks are used to grow epitaxial layers on the substrate) III-nitride semiconductor device layer 107 is grown by conventional methods on III-nitride ELO layer 105 in planar region 108. In one embodiment, MOCVD is used for epitaxial growth of III-nitride semiconductor islands, including III-nitride ELO layer 105 and III-nitride semiconductor device layer 107. III-nitride semiconductor islands 105, 107 are separated from each other because MOCVD growth is stopped before III-nitride ELO layer 105 coalesces. In one embodiment, III-nitride semiconductor islands 105, 107 are made to coalesce, after which etching is performed to remove unwanted regions.

[0068] Trimethylgallium (TMGa), trimethylindium (TMIn), and triethylaluminum (TMAl) are used as III-element sources. Ammonia (NH3) is used as the starting gas to supply nitrogen. Hydrogen (H2) and nitrogen (N2) are used as carrier gases for the III-element sources. It is important to include hydrogen in the carrier gas to obtain a smooth surface epilayer.

[0069] Salt and bis(cyclopentadienyl)magnesium (CpMg) are used as n-type and p-type dopants. Pressure settings are typically 50-760 Torr. III-nitride semiconductor layers are generally grown at temperatures ranging from 700-1,250°C.

[0070] For example, the growth parameters include: TMG is 12 sccm, NH3 is 8 slm, carrier gas is 3 slm, SiH4 is 1.0 sccm, and the V / III ratio is about 7,700.

[0071] (ELO of Limited Area Epitaxy (LAE) Group III Nitride Layers) In the prior art, several pyramidal hillocks have been observed on the surface of m-plane III-nitride films following growth. See, for example, U.S. Patent Application Publication No. 2017 / 0092810. Furthermore, wavy surfaces and depressions appear on the growth surface, which worsen the surface roughness. This is a very serious problem. For example, according to some papers, a smooth surface can be obtained by controlling the deviation angle (>1 degree) of the substrate's growth surface and by using N carrier gas conditions. However, these conditions are very limited for mass production due to high production costs. Furthermore, GaN substrates have large deviation angle variations relative to the origin due to their fabrication method. For example, if a substrate has a large deviation angle distribution, it will have different surface morphologies at these points on the wafer. In this case, the yield is reduced due to the large deviation angle distribution. Therefore, it is necessary for the technique to be independent of the deviation angle distribution.

[0072] The present invention, as described below, solves these problems. 1. The growth area is limited by the area of ​​the growth limiting mask 102 from the edge of the substrate 101. 2. The substrate 101 is a non-polar or semi-polar III-nitride substrate 101 with a tilt angle ranging from -16 degrees to +30 degrees from the m-plane towards the c-plane. Alternatively, a heterosubstrate 101 on which III-nitride based semiconductor layers are deposited can be used, with the layers having a tilt angle ranging from +16 degrees to -30 degrees from the m-plane towards the c-plane. 3. The island-shaped III nitride semiconductor layers 105 and 107 have long sides that are perpendicular to the a-axis of the III nitride semiconductor crystal. 4. During MOCVD growth, a hydrogen atmosphere can be used.

[0073] In the present invention, a hydrogen atmosphere can be used during non-polar and semi-polar growth, and using this condition is preferred because hydrogen can prevent excessive growth at the edges of the open areas 103 from occurring in the initial growth stages.

[0074] These results were obtained under the following growth conditions:

[0075] In one embodiment, the growth pressure ranges from 60 to 760 Torr, but preferably from 100 to 300 Torr to obtain a wide width for the island-shaped III-nitride semiconductor layers 105 and 107, the growth temperature ranges from 900 to 1,200°C, the V / III ratio ranges from 10 to 30,000, the TMG is 2 to 20 sccm, the NH3 ranges from 0.1 to 10 slm, and the carrier gas is hydrogen gas only or both hydrogen and nitrogen gases. To obtain a smooth surface, the growth conditions for each plane need to be optimized by conventional methods.

[0076] After growth for about 2-8 hours, the III-nitride ELO layer 105 has a thickness of about 1-50 μm and a bar width of about 50-150 μm.

[0077] (Making elements) The device 110 is fabricated in the planar surface region 108 by conventional methods, and various device 110 designs are possible. For example, for μLEDs, where only front-end processing is required to realize the device 110, p-pads and n-pads can be fabricated along either the length or width of the wings of the III-nitride ELO layer 105.

[0078] (Forming a structure for separating element units) The aim of this step is to isolate the device 110 from the host substrate 101 due to the III-nitride ELO layer 105 and the III-nitride device layer 107. At least two methods can be used to transfer the device 110 onto a carrier substrate.

[0079] In one method, III-nitride ELO layer 105 and device layer 107 are separated from host substrate 101 by etching regions 112, 113 to expose at least growth limit mask 102. Separation can also be performed by tools such as, but not limited to, scribing with a diamond-tipped or laser scriber, RIE (reactive ion etching) or ICP (inductively coupled plasma), and other methods can also be used to isolate device 110.

[0080] To keep the isolated III-nitride device layer 107 on the host substrate 101, the regions 112 directly connecting the III-nitride ELO layer 105 to the host substrate 101 were modified so that the connecting joints with the host substrate 101 still remained after exposing the growth limiting mask 102 in regions 113. Alternatively, one could choose to eliminate any connection to the host substrate 101 in the open areas 103 by etching all of the open areas 103.

[0081] Alternatively, the elements 110 are isolated by etching in the regions 113 to expose at least the growth limiting mask 102 (for ELO type 2). The method described in the publication by Srinivas Gandrothula et al., Appl. Phys. Express, vol. 13, p. 041003 (2020) can then be used to isolate the elements 110 from the host substrate 101. Alternatively, a support carrier such as a submount can also be used to transfer the isolated elements 110 onto the carrier before attaching the adhesive film.

[0082] (The ELO III-nitride device layers are removed from the substrate) After etching regions 112 and 113, whichever is best, the completed III-nitride device layer 107 can be transferred from its host substrate 101 using one of the following methods.

[0083] When the substrate 101 is left with weak connecting links or no links after etching the areas 112, 113: 1. Elastomeric stamp (PDMS stamp): The PDMS stamp is flexible enough to release the isolated III-nitride device layers 107 from the host substrate 101. The device layers 107 can be selectively released in order to transfer them onto a target back panel. 2. Vacuum chuck: A new method for removing the isolated III-nitride device layer 107 from the host substrate 101, which uses a vacuum-controlled chuck to remove the III-nitride device layer 107 when the III-nitride device layer 107 has weak connecting links with the host substrate 101.

[0084] When etching is not performed in region 112: 1. After isolating the device 110 with the region 112 intact, an adhesive film is placed over the device 110 and with the aid of low temperature and slight pressure, the device 110 is peeled off from the host substrate 101. 2. Alternatively, a support carrier may also be used, along with an adhesive film, followed by a similar procedure to peel off the element 110 so that the element 110 can be transferred onto a rigid carrier substrate.

[0085] (The element is mounted on the display panel) The separated / isolated elements 110 are picked up using the approaches described above, namely, (1) a PDMS stamp or (2) a vacuum chuck.

[0086] (Use a vacuum chuck to remove the element) The present invention provides a solution to the problem of mass-transferring devices 110 with smaller light-emitting apertures, also known as emissive inorganic pixels, when the targeted size is below 50 μm. These devices 110, known as μLEDs, are fabricated on the wings of a III-nitride ELO layer 105 and can be removed from the substrate 1010, as described above. In particular, these devices 110 preferably have larger wing areas and smaller open areas 112 of the III-nitride ELO layer 105; that is, the ratio between the wing area and the open area 112 should be greater than 1, more preferably 5-10, and in particular, the open area 112 should be approximately 1-5 μm. Therefore, the devices 110 can be more easily removed from the III-nitride substrate 101 and easily transferred to an external carrier or processed in further steps.

[0087] (Definition of terms) (III-nitride substrate) The III-nitride substrate 101 may comprise any type of III-nitride substrate, i.e., any GaN substrate 101 sliced ​​from a bulk GaN and AlN crystal substrate on the {0001}, {11-22}, {1-100}, {20-21}, {20-2-1}, {10-11}, {10-1-1} plane, etc., or other plane, so long as the III-nitride substrate allows growth of the III-nitride semiconductor layers 105, 107 through the growth-limiting mask 102.

[0088] (hetero substrate) Furthermore, the present invention can also use a heterosubstrate 101. For example, a GaN template or other III-nitride semiconductor layer can be grown on a heterosubstrate 101 such as sapphire, Si, GaAs, SiC, Ga2O3, etc., prior to the growth limiting mask 102. The GaN template or other III-nitride semiconductor layer is typically grown on the heterosubstrate 101 to a thickness of about 2-6 μm, and then the growth limiting mask 102 is placed on the GaN template or other III-nitride semiconductor layer.

[0089] (growth restriction mask) The growth limiting mask 102 comprises a dielectric layer such as SiO2, SiN, SiON, Al2O3, AlN, AlON, MgF, ZrO2, TiN, or a refractory or noble metal such as W, Mo, Ta, Nb, Rh, Ir, Ru, Os, Pt, etc. The growth limiting mask 102 can be a layered structure selected from the above materials. It can also be a multi-stacking layer structure selected from the above materials.

[0090] In one embodiment, the thickness of the growth limiting mask 102 is approximately 0.05-3 μm. The width of the mask 102 is preferably greater than 20 μm, and more preferably greater than 40 μm. The growth limiting mask 102 may be deposited by methods such as, but not limited to, sputtering, electron beam evaporation, plasma enhanced chemical vapor deposition (PECVD), ion beam deposition (IBD), and the like.

[0091] On an m-plane freestanding GaN substrate 101, a growth limiting mask 102 includes a plurality of open areas 103, which are periodically arranged at intervals extending in a second direction, in a first direction parallel to the 11-20 direction of the substrate 101 and in a second direction parallel to the 0001 direction of the substrate 101. The length of the open areas 103 is, for example, 200 to 35,000 μm, the width is, for example, 2 to 180 μm, and the spacing between the open areas 103 is, for example, 20 to 180 μm. The width of the open areas 103 is typically constant in the second direction, but can be varied in the second direction as needed.

[0092] On the c-plane freestanding GaN substrate 101, the open areas 103 are arranged in a first direction parallel to the 11-20 direction of the substrate 101 and in a second direction parallel to the 1-100 direction of the substrate 101.

[0093] On the semipolar (20-21) or (20-2-1) GaN substrate 101, the open areas 103 are oriented parallel to [-1014] and [10-14], respectively.

[0094] Alternatively, a heterosubstrate 101 can be used. When a c-plane GaN template is grown on a c-plane sapphire substrate 101, the open area 103 is transformed into a c-plane freestanding GaN substrate 101, and when an m-plane GaN template is grown on an m-plane sapphire substrate 101, the open area 103 is transformed into an m-plane freestanding GaN substrate 101. By doing this, the m-plane cleavage plane can be used to split the rod of device 110 using the c-plane GaN template, and the c-plane cleavage plane can be used to split the rod of device 110 using the m-plane GaN template, which is much preferred.

[0095] (Group III nitride semiconductor layer) The III-nitride ELO layer 105 and the III-nitride semiconductor device layer 107 may contain In, Al, and / or B, as well as other impurities such as Mg, Si, Zn, O, C, H, and the like.

[0096] The III-nitride semiconductor device layer 107 generally includes three or more layers, including at least one of an n-type layer, an undoped layer, and a p-type layer. Specifically, the III-nitride semiconductor device layer 107 includes a GaN layer, an AlGaN layer, an AlGaInN layer, an InGaN layer, etc. When the device 110 has multiple III-nitride semiconductor layers 105, 107, the distance between adjacent island-shaped III-nitride semiconductor layers 105, 107 is generally 30 μm or less, preferably 10 μm or less, but is not limited to these figures. In the semiconductor device 110, several electrodes are arranged at predetermined positions depending on the type of the semiconductor device 110.

[0097] (flat surface area) The flat surface regions 108 are layers between the bent regions 109. Furthermore, the flat surface regions 108 are within the area of ​​the growth limiting mask 102.

[0098] Fabrication of the semiconductor device 110 is primarily performed on the flat surface region 108. The width of the flat surface region 108 is preferably at least 5 μm, and more preferably 10 μm or greater. The flat surface region 108 has a highly uniform thickness for each of the semiconductor layers 105, 107.

[0099] (Layer bending area) If the layer bending region 109, including the active layer 107a, remains in the device 110, some of the light emitted from the active layer 107a will be reabsorbed. As a result, it is preferable to remove at least a portion of the active layer 107a in the layer bending region 109 by etching.

[0100] From another perspective, the epitaxial layer in the flat surface region 108, excluding the open area 103, has a lower defect density than the epitaxial layer in the open area 103. Therefore, it is more preferable that the opening structure be formed in the flat surface region 108, including on the wing regions of the III-nitride ELO layer 105.

[0101] (semiconductor element) The semiconductor element 110 may be, but is not limited to, a Schottky diode, a light emitting diode, a semiconductor laser, a photodiode, a transistor, etc. The present invention is particularly useful for micro LEDs and VCSELs. The present invention is particularly useful for semiconductor lasers, which require a smooth region for cavity formation.

[0102] Alternative Embodiments The following describes alternative embodiments of the present invention.

[0103] (First embodiment) The first embodiment is directed to a III-nitride based light emitting diode device 110 with an attached pattern for extracting and / or guiding light and a method for making the same.

[0104] 3A, the growth-limiting mask 102 is patterned to create valleys 300a2, peaks 300a3, or random valleys and peaks 300a4 on the growth-limiting mask 102, e.g., for better light extraction. Alternatively, the same structure can be created on the host substrate 101, and then the growth-limiting mask 102 is draped over the structure created on the host substrate 101. In either case, the growth-limiting mask 102 takes the shape of the structure, and the III-nitride layers 105, 107 subsequently take the inverse shape of the structure.

[0105] As shown in schematic diagrams 300b1, 300b2, and 300b3 in Figure 3B, growth-limiting mask 102 includes a plurality of striped open areas 103. III-nitride ELO layer 105 is grown from substrate 101, through open areas 103, and over the surface of growth-limiting mask 102, taking the shape of the pattern on the surface of growth-limiting mask 102. Device layer 107 is grown on III-nitride ELO layer 105, and devices are fabricated on wing regions of III-nitride ELO layer 105.

[0106] A cross-section of device 110 with a pattern formulated at interface 111 between growth-limiting mask 102 and III-nitride ELO layer 105 is shown in schematic diagram 300c1 in Figure 3C, where the depth of the pattern on growth-limiting mask 102 is represented as h2 and the height of growth-limiting mask 102 from surface S of host substrate 101 is represented as h1. Preferably, depth h2 is less than h1.

[0107] Preferably, the surface for initiating ELO growth and the upper surface of the growth limit mask 102 should be within 3 μm. Otherwise, if the application requires a deeper pattern such that h2 exceeds 3 μm, a trench pattern can be formed on the host substrate 101, following the approach described in the third embodiment, which keeps the surface of the host substrate 101 relative to the surface of the growth limit mask 102 below 3 μm.

[0108] For proof of concept, feasibility experiments were performed to transfer a random valley-ridge pattern onto the interface 111 of the III-nitride ELO layer 105. However, some other patterns are also possible, such as PhC or a curved concave mirror (described in the second embodiment).

[0109] A nonpolar GaN substrate 101 was used for this study. A random valley-peak pattern in the form of stripes was deposited on the host substrate 101, as shown in schematic diagram 400a1 and SEM image 400a2 in FIG. 4A. Atomic force microscope (AFM) image 400a3 in FIG. 4A shows the pattern on the stripes. A line scan of the pattern is also shown in 400a3, and the extent of the peaks and valleys is also provided.

[0110] In the next step, a combination of growth-limiting masks 102 consisting of 300 nm of SiO2 was placed on the patterned host substrate 101, and parallel stripes acting as open areas 103 were opened on the host substrate 101 along the c-axis, as shown in schematic diagram 400b1, SEM image 400b2, schematic diagram 400b3, and schematic diagram 400b4 in Figure 4B. Cross sections of the host substrate 101 and the random valley-peak pattern are shown diagrammatically in 400b3 and 400b4.

[0111] As shown in schematic diagrams 400c1, 400c2, 400c3, SEM image 400c4, and AFM image 400c5 in Figure 4C, III-nitride ELO layer 105 is grown using MOCVD and allowed to distribute over the random valley pattern, as shown in schematic diagram 400c1. Schematics 400c2 and 400c3 are cross-sectional views of III-nitride ELO layer 105 overlying growth-limiting mask 102, showing the pattern transferred onto interface 111 of III-nitride ELO layer 105. SEM image 400c4 shows experimental results of interface 111 of III-nitride ELO layer 105, where III-nitride ELO layer 105 has been transferred onto an adhesive film. An AFM scan was performed at the location where the random valley-peak pattern was expected to appear, and the results are shown in 400c5. The pattern on interface 111 of III-nitride ELO layer 105 largely replicates the pattern on growth-limiting mask 102, as seen at 400a3 and 400c5.

[0112] Note that for demonstration purposes, the random valley-peak pattern was limited to stripes; however, the same results can be observed when the pattern is extended to the entire element 110.

[0113] The same applies when the pattern design is a PhC, which is implemented on the back interface 111 of the III-nitride ELO layer 105, and the light emitted from the element 110 is controlled to a desired angle.

[0114] The device 110 with the patterned III-nitride ELO layer 105 is then transferred onto a desired carrier, which may be a display panel, using tools such as a PDMS elastomer stamp, a vacuum chuck, etc. The display panel can be used in several applications such as TVs, laptops, phones, AR / VR / MR headsets, HUDs, etc.

[0115] (Second embodiment) The second embodiment is directed to increasing the pattern size and realizing a simple fabrication method for curved-mirror VCSELs. Plano-concave mirror VCSELs are considered attractive for long-resonant cavity VCSELs from the perspective of cavity wavelength resonance control and thermal management. Researchers have proposed methods such as thinning the host substrate to the desired cavity length, forming a curved mirror on the backside of the substrate, and photochemical etching to achieve thin-cavity VCSELs. However, these approaches have serious disadvantages in terms of controllability and substrate orientation limitations. The method proposed here works regardless of substrate orientation or crystallinity, and furthermore, allows for the recycling of the host substrate.

[0116] As shown in the schematic diagrams 500a1 (top view) and 500a2 (side view) in Figure 5A, a growth-limiting mask 102 with a concave shape 501 is formed on the host substrate 101 by leaving open areas 103 on the host substrate 101.

[0117] As shown in schematic diagram 500b1 (side view) in FIG. 5B, device layer 107 including III-nitride ELO layer and active region 107a is formed on growth limiting mask 102, and concave features 501 are formed on host substrate 101 by leaving open areas 103 on host substrate 101.

[0118] As shown in schematic diagrams 500c1 and 500c2 in FIG. 5C , the cavity length L is defined by the III-nitride ELO layer 105. Because it is epitaxially controlled, precise control of the cavity length L can be achieved. The radius of curvature R of the curved shape 501 is designed so that the beam waist w of the stable resonator is formed by the DBR comprising the flat mirror 502 and the curved mirror 503 without generating diffraction or scattering losses. The beam waist w formed on the flat mirror 502 depends on the cavity length L and the radius of curvature R. Theoretically, by setting R equal to L, the beam waist w can be minimized, thereby reducing diffraction losses. In one example, when a cavity length L greater than 20 μm is desired, the active layer 107a can be placed 100 nm behind the flat mirror 502, the tunnel junction or transparent conductive layer 505, and the current blocking region 506, thereby providing good lateral confinement.

[0119] 5D , a VCSEL device 110, shown as a dashed rectangle, is formed on the wings of the III-nitride ELO layer 105. Fabrication of the entire VCSEL device 110, including the DBR flat mirror 502, p-pad, and n-pad 504, can be performed while the III-nitride ELO layer 105 is still attached to the host substrate 101. Once the VCSEL device 110 is separated from the host substrate 101, a second DBR curved mirror 503 is fabricated on the curved feature 501 at the bottom interface 111 of the III-nitride ELO layer 105, substantially free of the host substrate 101, to complete the VCSEL device 110.

[0120] (Third embodiment) A third embodiment is a type of preparation for achieving a pattern at the interface 111 of the III-nitride ELO layer 105, as shown in Figures 6A, 6B, and 6C.

[0121] (Type 1 pattern) As shown in schematic diagrams 600a1, 600a2, 600a3, and 600a4 in FIG. 6A , a type 1 pattern is formed on a growth-limiting mask 102. To achieve this, a III-nitride host substrate 101 is provided, as shown in schematic diagram 600a1. A growth-limiting mask 102 with a thickness h1 is overlaid on the III-nitride host substrate 101, as shown in schematic diagram 600a2, and a pattern 601 with desired parameters, e.g., a depth h2, is formed on the growth-limiting mask 102 using nanoimprint lithography or a similar pattern transfer technique, e.g., holographic lithography, optical lithography, etc., as shown in schematic diagram 600a3. Open areas 103 are opened so that the surface S of the host substrate 101 is visible, as shown in schematic diagram 600a4. Devices 110 are grown on or above the host substrate 101 and the growth-limiting mask 102. The III-nitride ELO layer 105 grown from the open areas 103 curves around its edges in the growth-limiting mask 102 to follow the designed pattern. Note that h1 must be larger than h2 to avoid substantial host substrate 101 material in the final device 110.

[0122] (Type 2 pattern) As shown in schematic diagrams 600b1, 600b2, 600b3, and 600b4 in FIG. 6B, an alternative embodiment can avoid the h1 > h2 condition by generating the desired type 2 pattern directly on the host substrate 101. Nanoimprint lithography or a similar method is used to transfer the pattern to the host substrate 101 using a combination of etching. To accomplish this, a III-nitride host substrate 101 is provided, as shown in schematic diagram 600b1, and the host substrate 101 is patterned, as shown in schematic diagram 600b2. A growth-limiting mask 102 is placed over the patterned host substrate 101, as shown in schematic diagram 600b3. The growth-limiting mask 102 takes the shape of the pattern on the host substrate 101, such as that described in the proof-of-concept study. Later, the open areas 103 on the host substrate 101 are used to perform ELO, as shown in schematic diagram 600b4. III-nitride ELO layer 105 takes the shape of the pattern on substrate 101 at interface 111, resulting in device 110 with interface 111 pattern.

[0123] (Type 3 pattern) Another alternative embodiment is shown in schematic diagrams 600c1, 600c2, 600c3, 600c4, 600c5 in FIG. 6C.

[0124] In some cases of Type 1, when h2 requires a deeper depth (>3 μm), the resulting h1 will also increase to satisfy the condition that h1 must exceed h2. As a result, the III-nitride ELO layer 105 arising from the open areas 103 of the host substrate 101 may find it difficult to rise beyond the designed pattern shape on the growth-limiting mask 102. In such a scenario, a raised surface S near the surface of the growth-limiting mask 102 would be preferable.

[0125] One such possibility is presented in Type 3. To achieve this, a III-nitride host substrate 101 is provided, as shown in schematic diagram 600c1. A trench of height h is formed on the host substrate 101 in the open region 112, as shown in schematic diagram 600c2. A growth-limiting mask 102 of thickness h1 is placed over the substrate 101, covering the trench and the host substrate 101 in the open region 103, as shown in schematic diagram 600c3. A desired pattern is formed on the growth-limiting mask 102, for example, with a depth h2, as shown in schematic diagram 600c4. The open area 103 is open over the trench in the host substrate 101, such that the surface S is just below the thickness d, as shown in schematic diagram 600c5, thus providing a lower-height wall for a subsequently grown III-nitride ELO layer 105.

[0126] (Fourth embodiment) In the fourth embodiment, AlGaN layers are used as the island-shaped III-nitride semiconductor layers 105, 107. The AlGaN layers can be grown as the ELO III-nitride layers 105 on various tilted substrates 101 and device layers 107. The AlGaN layers 105, 107 can have very smooth surfaces using the present invention. The AlGaN layers 105, 107 can be removed from various tilted substrates 101 as the island-shaped III-nitride semiconductor layers 105, 107 using the present invention.

[0127] In this case, an active laser emitting UV-light (UV-A or UV-B or UV-C) can be grown on the AlGaN ELO layer 105. After removal, the AlGaN ELO layer 105 with the active region 107a looks like a UV-device with a pseudo-AlGaN substrate. By doing so, a high-quality UV-LED device 110 can be obtained, which is useful for applications such as sterilization, lighting, etc.

[0128] (Fifth embodiment) In a fifth embodiment, III-nitride ELO layers 105 are grown on various tilt substrates 101. The tilt orientations range from 0 to +15 degrees and 0 to -28 degrees from the m-plane towards the c-plane. The present invention allows the rods of elements 110 to be removed from various tilt substrates 101. This is a great advantage to the present technique, as various tilt orientation semiconductor planar elements 110 can be realized without changing the fabrication process.

[0129] (Sixth embodiment) In a sixth embodiment, III-nitride ELO layers 105 are grown on a c-plane substrate 101 with two different miscut orientations. The III-nitride semiconductor layers 105, 107 are removed after processing the desired device 110 using the invention described herein.

[0130] (Seventh embodiment) In the seventh embodiment, a sapphire substrate 101 is used as the heterosubstrate 101. The resulting structure is almost the same as the first and second embodiments, except for the use of a sapphire substrate 101 and a buffer layer. In this embodiment, the buffer layer may also include an additional n-GaN layer or undoped GaN layer. The buffer layer is grown at a low temperature of about 500 to 700°C. The n-GaN layer or undoped GaN layer is grown at a higher temperature of about 900 to 1,200°C. The total thickness is about 1 to 3 μm. A growth-limiting mask 102 is then placed on the buffer layer and the n-GaN layer or undoped GaN layer.

[0131] On the other hand, there is no need to use a buffer layer. For example, the growth-limiting mask 102 can be directly disposed on the heterosubstrate 101. Then, the III-nitride ELO layer 105 and / or the III-nitride-based semiconductor device layer 107 can be grown.

[0132] (Eighth embodiment) The eighth embodiment describes devices fabricated using the first, second, or third embodiments described above. A random valley-ridge pattern LED device 110 is presented in the schematic diagram 700a1 in FIG. 7A . After patterning the growth-limiting mask 102 as a random valley-ridge pattern, a III-nitride ELO layer 105 is grown from the open areas 103 imprinted with the random valley-ridge pattern. LED devices 110 are then fabricated on the III-nitride ELO layer 105, including the active region 107a and p-GaN 107b and n-GaN layer 105. Contact pads 504 within these devices 110 can be formed on the flat surface 108 on the opposite side of the random valley-ridge pattern of the III-nitride ELO layer 105. Once removed from the substrate 101, the resulting device 110 is attached to a submount 701.

[0133] This approach of having light extraction / control structures near the active region 107a will certainly improve light extraction efficiency. Traditionally, such light extraction and / or control structures are fabricated either on the back surface of the substrate 101 or on the front surface of the device 110; the former relies on the conductivity of the substrate 101, while the latter imposes limitations on current injection and complicates fabrication. However, the method described in this invention allows the light control structures to be placed near the active region 107a while still allowing fabrication on the flat surface 108 of the light-emitting device 110. Alternatively, different shapes, such as PhCs, can also be used with this LED to provide the best light extraction. Schematics 300a2, 300a3, and 300a4 in FIG. 3A show different examples of shapes that can be used for better light extraction / control.

[0134] In a similar manner, a plano-concave mirror resonant cavity VCSEL device 110 can be fabricated by modifying the pattern on the growth-limiting mask 102 as a concave shape 501, as shown in schematic diagram 700a2 in FIG. 7B. The cavity length L is precisely controlled epitaxially, and the radius of curvature R of the structure is derived from the concave shape 501. Appropriate parameters for L and R are designed so that a beam waist w is formed on the flat mirror 502. In addition to the top and bottom DBR mirrors 502, 503, the resonant cavity includes an active region 107a, a tunnel junction or transparent conductive layer 505, a current blocking region 506, and a p-type layer 107b (not shown). Contact pads 504 are defined and singulation is performed, following which a transparent submount 701 is attached to the flat mirror 502. Finally, a bottom-side DBR curved mirror 503 is attached to the epitaxially formed curved feature 501 in the III-nitride ELO layer 105 at the back interface 111 .

[0135] (Conclusion) This concludes the description of the preferred embodiments of the invention. The foregoing description of one or more embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. It is intended that the scope of the invention be limited not by the detailed description provided herein, but rather by the claims appended hereto.

Claims

[Claim 1] The invention described in this specification.

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