Differential circuit

Abstract

To provide a differential circuit in which the input offset voltage and the temperature drift coefficient of the input offset voltage are both improved without deteriorating noise or frequency characteristics and without affecting the input voltage range.SOLUTION: A first current circuit 12 supplies current to a differential input pair 11. A first trimming circuit 13 includes trimming resistors R1 and R2. A second trimming circuit 14 includes trimming resistors R3 and R4. A second current circuit 15 supplies current to the trimming resistors R3 and R4. A current ITAIL supplied from the first current circuit 12 to the differential input pair 11 and currents IFD1 and IFD2 supplied from the second current circuit 15 to the trimming resistors R3 and R4 have different temperature dependencies.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a differential circuit. [Background technology]

[0002] From the viewpoint of high precision, differential circuits used as input stage circuits of operational amplifiers and comparators are required to have a small input offset voltage Vio and a small temperature drift coefficient TCVio of the input offset voltage.

[0003] Fig. 23 shows a conventional differential circuit 100 (Patent Document 1). As shown in the figure, the differential circuit 100 includes a current source CS1, transistors M1 and M2, and trimming resistors R1 and R2. Trimming the trimming resistors R1 and R2 can reduce the input offset voltage Vio.

[0004] 24 is a diagram showing how the input offset voltage Vio and its temperature drift coefficient TCVio change, with the horizontal axis representing the input offset voltage Vio and the vertical axis representing the temperature drift coefficient TCVio of the input offset voltage. In the diagram, the distribution of the input offset voltage Vio and the temperature drift coefficient TCVio before trimming is shown by a dashed circle, and the distribution of the input offset voltage Vio and the temperature drift coefficient TCVio after trimming is shown by a solid circle. As shown in the diagram, the differential circuit 100 shown in FIG. 23 described above has a problem in that, in some cases, reducing the input offset voltage Vio can worsen the temperature drift coefficient TCVio.

[0005] To solve this problem, a differential circuit 101 shown in Fig. 25 has been proposed (Patent Document 1). As shown in the figure, the differential circuit 101 includes current sources CS1 to CS4, transistors M1 to M5, trimming resistors R3 and R4, and a resistor R10. Trimming the trimming resistors R3 and R4 can reduce the input offset voltage Vio.

[0006] In Patent Document 1, the current I flowing through the transistors M4 and M5FD1 ,I FD2 is the current I of current source CS1 TAIL It is specified so that the temperature characteristic is more negative than that of V. By trimming the trimming resistors R3 and R4 under these conditions, it is possible to improve the input offset voltage Vio without worsening the temperature drift coefficient TCVio of the input offset voltage, as shown in Figure 26.

[0007] On the other hand, a differential circuit 102 shown in FIG. 27 has also been proposed (Non-Patent Document 1). As shown in the figure, the differential circuit 102 has a current source CS1, transistors M1 and M2, trimming resistors R1 and R2, and trimming resistors R31 and R32. Here, the trimming resistors R1, R2, R31, and R32 are trimming resistors for improving the input offset voltage Vio. The reason why the temperature drift coefficient TCVio of the input offset voltage does not change even when the trimming resistors R31 and R32 are trimmed is that the resistors R31 and R32 and the current I of the current source CS1 TAIL This is because the product of these is set to maintain a constant value regardless of temperature. As a result, the differential circuit 102 is said to be able to improve both the input offset voltage Vio and the temperature drift coefficient TCVio, as shown in FIG.

[0008] However, in the differential circuit 102, the input offset voltage Vio is determined by the trimming resistors R31 and R32 and the current I TAIL For example, when trimming resistors R31 and R32, the change in resistance is only a few ohms, and the current I TAIL is 100 μA, the input offset voltage Vio can only be improved to several hundred μV. In addition, because trimming resistors R31 and R32 are connected to the sources of transistors M1 and M2, there are issues such as increased noise, worsened frequency characteristics, and a narrower input voltage range. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Patent No. 5709682 [Non-patent literature]

[0010] [Non-Patent Document 1] CQ Publishing, Analog Devices, Inc. History of OP Amplifiers and Basic Circuit Technology Summary of the Invention [Problem to be solved by the invention]

[0011] The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a differential circuit in which both the input offset voltage and the temperature drift coefficient of the input offset voltage are improved without deteriorating noise or frequency characteristics or affecting the input voltage range. [Means for solving the problem]

[0012] In order to achieve the above-mentioned object, a differential circuit according to the present invention has the following features [1] to

[10] . [1] an input differential pair having a first differential transistor and a second differential transistor; a first current circuit connected between a first power supply terminal to which a first power supply voltage is supplied and the sources or emitters of the first differential transistor and the second differential transistor, and supplying a current to the input differential pair; a first adjustment circuit having a first adjustment resistor whose resistance value is adjustable and connected between the drain or collector of the first differential transistor and a second power supply terminal to which a second power supply voltage is supplied, and a second adjustment resistor whose resistance value is adjustable and connected between the drain or collector of the second differential transistor and the second power supply terminal; a second adjustment circuit including a third adjustment resistor having an adjustable resistance value connected between the connection point of the first differential transistor and the first adjustment resistor and the first power supply terminal, and a fourth adjustment resistor having an adjustable resistance value connected between the connection point of the second differential transistor and the second adjustment resistor and the first power supply terminal; a second current circuit that supplies current to the third adjustment resistor and the fourth adjustment resistor; The current supplied from the first current circuit and the current supplied from the second current circuit have different temperature dependencies. It must be a differential circuit. [2] In the differential circuit according to [1], the second current circuit includes a third transistor, a current section that supplies a current to the third transistor, and a fourth transistor and a fifth transistor that form a current mirror circuit together with the third transistor and mirror back the current flowing through the third transistor; the fourth transistor is connected between the third adjustment resistor and a connection point of the first differential transistor and the first adjustment resistor; the fifth transistor is connected between the fourth adjustment resistor and a connection point of the second differential transistor and the second adjustment resistor; It must be a differential circuit. [3] In the differential circuit according to [2], the second current circuit has a sixth transistor and a seventh transistor that form a current mirror circuit; the sixth transistor is connected between the fourth transistor and a connection point of the first differential transistor and the first adjustment resistor; the seventh transistor is connected between the fifth transistor and a connection point of the second differential transistor and the second adjustment resistor; It must be a differential circuit. [4] In the differential circuit according to [1], the first current circuit includes an eighth transistor, a first current source that supplies a current to the eighth transistor, a ninth transistor that forms a current mirror circuit together with the eighth transistor and returns the current flowing through the eighth transistor to supply the current to the input differential pair, a fifth resistor connected between the eighth transistor and the first power supply terminal, and a sixth resistor connected between the ninth transistor and the first power supply terminal; The fifth resistor and the sixth resistor are composed of resistors having different temperature dependencies. It must be a differential circuit. [5] In the differential circuit according to [2], the current unit includes a tenth transistor, a second current source that supplies a current to the tenth transistor, an eleventh transistor that forms a current mirror circuit together with the tenth transistor and returns the current flowing through the tenth transistor to supply the current to the third transistor, a seventh resistor connected between the tenth transistor and the second power supply terminal, and an eighth resistor connected between the eleventh transistor and the second power supply terminal; The seventh resistor and the eighth resistor are composed of resistors having different temperature dependencies. It must be a differential circuit. [6] In the differential circuit according to [1], the first adjustment resistor, the second adjustment resistor, the third adjustment resistor, and the fourth adjustment resistor each include a plurality of trimming resistors connected in series; a short-circuiting circuit for short-circuiting a part of the plurality of trimming resistors included in at least one of the first adjustment resistor, the second adjustment resistor, the third adjustment resistor, and the fourth adjustment resistor; It must be a differential circuit. [7] [6] The differential circuit according to [6], the short-circuiting circuit is composed of a test terminal provided between the plurality of trimming resistors; It must be a differential circuit. [8] [6] The differential circuit according to [6], the shorting circuit is composed of a transistor switch that shorts between the plurality of trimming resistors and the first power supply terminal or the second power supply terminal; It must be a differential circuit. [9] In the differential circuit according to [1], The transistor is composed of a field effect transistor. It must be a differential circuit.

[10] In the differential circuit according to [1], The transistor is composed of a bipolar transistor. It must be a differential circuit. [Effects of the Invention]

[0013] The differential circuit according to the present invention has the advantage that it is possible to improve both the input offset voltage and the temperature drift coefficient of the input offset voltage without deteriorating noise or frequency characteristics or affecting the input voltage range.

[0014] The present invention has been briefly described above. The details of the present invention will become clearer by reading the following detailed description of the invention (hereinafter referred to as "embodiments") with reference to the accompanying drawings. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a circuit diagram showing a differential circuit according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a graph showing the relationship between the amount of change ΔVio in the input offset voltage and the amount of change ΔTCVio in the temperature drift coefficient of the input offset voltage when trimming the trimming resistors R1 and R2 shown in FIG. [Figure 3] FIG. 3 is a graph showing the relationship between the amount of change ΔVio in the input offset voltage and the amount of change ΔTCVio in the temperature drift coefficient of the input offset voltage when trimming the trimming resistors R3 and R4 shown in FIG. [Figure 4] FIG. 4 is a graph showing the transition of the input offset voltage Vio and the temperature drift coefficient TCVio of the input offset voltage when trimming resistors R3 and R4 are trimmed after trimming resistors R1 and R2 shown in FIG. [Figure 5] FIG. 5 is a graph showing the transition of the input offset voltage Vio and the temperature drift coefficient TCVio of the input offset voltage when the trimming resistors R1 and R2 are trimmed after the trimming resistors R3 and R4 shown in FIG. [Figure 6] FIG. 6 is a distribution diagram showing the relationship between the input offset voltage Vio and the temperature drift coefficient TCVio of the input offset voltage before and after trimming in the differential circuit shown in FIG. [Figure 7] FIG. 7 is an explanatory diagram for explaining the relationship between the currents ITAIL, IFD1, IFD2 and the coefficients n1, n2. [Figure 8] FIG. 8 is a graph showing the results of measurements of the temperature dependency of the input offset voltage Vio before trimming in the differential circuit shown in FIG. [Figure 9] FIG. 9 is a graph showing the results of measurements of the temperature dependency of the input offset voltage Vio after trimming in the differential circuit shown in FIG. [Figure 10] FIG. 10 is a circuit diagram showing a differential circuit according to the second embodiment of the present invention. [Figure 11] FIG. 11 is a graph showing the temperature dependence of the resistors R5 and R6 and the current ITAIL in the differential circuit shown in FIG. [Figure 12] FIG. 12 is a graph showing the temperature dependence of the resistors R5 and R6 and the current ITAIL in the differential circuit shown in FIG. [Figure 13] FIG. 13 is a graph showing changes in n1 and n2 when the temperature dependency of the current ITAIL is changed under the condition that the current IFD has no temperature dependency. [Figure 14] FIG. 14 is a circuit diagram showing a differential circuit according to the third embodiment of the present invention. [Figure 15]FIG. 15 is a graph showing the temperature dependence of the resistors R7 and R8 and the currents IFD1 and IFD2 in the differential circuit shown in FIG. [Figure 16] FIG. 16 is a graph showing the temperature dependence of the resistors R7 and R8 and the currents IFD1 and IFD2 in the differential circuit shown in FIG. [Figure 17] FIG. 17 is a graph showing changes in n1 and n2 when the temperature dependency of the current IFD is changed under the condition that the current ITAIL has no temperature dependency. [Figure 18] FIG. 18 is a circuit diagram showing a differential circuit according to the fourth embodiment of the present invention. [Figure 19] FIG. 19 is a flowchart showing a procedure for trimming the differential circuit shown in FIG. [Figure 20] FIG. 20 is a circuit diagram showing a differential circuit according to the fifth embodiment of the present invention. [Figure 21] FIG. 21 is a circuit diagram showing a differential circuit according to the sixth embodiment of the present invention. [Figure 22] FIG. 22 is a circuit diagram showing a differential circuit according to the seventh embodiment of the present invention. [Figure 23] FIG. 23 is a circuit diagram showing an example of a conventional differential circuit. [Figure 24] FIG. 24 is a distribution diagram showing the relationship between the input offset voltage Vio and the temperature drift coefficient TCVio of the input offset voltage before and after trimming in the differential circuit of FIG. [Figure 25] FIG. 25 is a circuit diagram showing an example of a conventional differential circuit. [Figure 26] FIG. 26 is a distribution diagram showing the relationship between the input offset voltage Vio and the temperature drift coefficient TCVio of the input offset voltage before and after trimming in the differential circuit of FIG. [Figure 27] FIG. 27 is a circuit diagram showing an example of a conventional differential circuit. [Figure 28] FIG. 28 is a distribution diagram showing the relationship between the input offset voltage Vio and the temperature drift coefficient TCVio of the input offset voltage before and after trimming in the differential circuit of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0016] Specific embodiments of the present invention will be described below with reference to the accompanying drawings.

[0017] (First embodiment) First, the first embodiment will be described with reference to Fig. 1. The differential circuit 1 shown in Fig. 1 is a circuit that amplifies and outputs a differential voltage input to two input terminals T11 and T12. The differential circuit 1 includes an input differential pair 11, a first current circuit 12, a first trimming circuit 13 (=first adjustment circuit), a second trimming circuit 14 (=second adjustment circuit), and a second current circuit 15.

[0018] The input differential pair 11 has two transistors M1 (=first differential transistor) and M2 (=second differential transistor). The transistors M1 and M2 are configured as P-channel MOS field effect transistors. The sources of the transistors M1 and M2 are connected in common. The gates of the transistors M1 and M2 are connected to the two input terminals T11 and T12 mentioned above, respectively.

[0019] In this embodiment, the first current circuit 12 has a current source CS1. The current source CS1 is connected between a positive power supply terminal T21 (=first power supply terminal) to which a positive power supply voltage VDD is supplied and the sources of the transistors M1 and M2. A current I TAIL is shunted to the two transistors M1 and M2. The shunt ratio is a value that corresponds to the differential voltage input to the two input terminals T11 and T12.

[0020] The first trimming circuit 13 has a trimming resistor R1 (=first adjustment resistor) and a trimming resistor R2 (=second adjustment resistor). The trimming resistor R1 is connected between the drain of the transistor M1 and a negative power supply terminal T22 (=second power supply terminal) to which a negative power supply voltage VSS is supplied. The trimming resistor R2 is connected between the drain of the transistor M2 and the negative power supply terminal T22. By adjusting the resistance values ​​of the trimming resistors R1 and R2, the shunt ratio of the current flowing through the transistors M1 and M2 is adjusted, and the input offset voltage of the differential circuit 1 is adjusted.

[0021] The second trimming circuit 14 has a trimming resistor R3 (=third trimming resistor) and a trimming resistor R4 (=fourth trimming resistor). The trimming resistor R3 is connected between the connection point of the transistor M1 and the trimming resistor R1 and the positive power supply terminal T21. The trimming resistor R4 is connected between the connection point of the transistor M2 and the trimming resistor R2 and the positive power supply terminal T21. By adjusting the trimming resistors R3 and R4, the current supplied to the trimming resistors R1 and R2 from a current source CS2 (described later) is adjusted, and the input offset voltage of the differential circuit 1 is adjusted.

[0022] The second current circuit 15 is a circuit that supplies current to the trimming resistors R3 and R4 and includes a transistor M3 (=third transistor), a current section 151, a resistor R10, a transistor M4 (=fourth transistor), a transistor M5 (=fifth transistor), a transistor M6 (=sixth transistor), and a transistor M7 (=seventh transistor).

[0023] The transistors M3 to M5 are configured as P-channel MOS field effect transistors. The transistors M6 and M7 are configured as N-channel MOS field effect transistors. The current section 151 is configured as a current source CS2. The current source CS2 is connected between the drain of the transistor M3 and a negative power supply terminal T22 and supplies current to the transistor M3. The resistor R10 is connected between the positive power supply terminal T21 and the source of the transistor M3.

[0024] The gate and drain of transistor M3 are connected to the gates of transistors M4 and M5, and transistors M3 to M5 form a current mirror circuit. Transistors M4 and M5 mirror back the current flowing through transistor M3. Transistor M4 is connected between trimming resistor R3 and the connection point of transistor M1 and trimming resistor R1. The source of transistor M4 is connected to trimming resistor R3. Transistor M5 is connected between trimming resistor R4 and the connection point of transistor M2 and trimming resistor R2. The source of transistor M5 is connected to trimming resistor R4.

[0025] The gate and drain of transistor M6 are connected to the gate of transistor M7, and transistors M6 and M7 form a current mirror circuit. Transistor M7 mirrors the current flowing through transistor M6. Transistor M6 is connected between transistor M4 and the junction of transistor M1 and trimming resistor R1. The source of transistor M6 is connected to the junction of transistor M1 and trimming resistor R1, and the gate and drain are connected to the drain of transistor M4. Transistor M7 is connected between transistor M5 and the junction of transistor M2 and trimming resistor R2. The source of transistor M7 is connected to the junction of transistor M2 and trimming resistor R2, and the drain is connected to the drain of transistor M5.

[0026] The drain current I folded back by the above-mentioned transistors M4 and M5 FD1 ,I FD2The current ratio is a value that corresponds to the ratio of the resistance values ​​of the trimming resistors R3 and R4.

[0027] Next, the inventors calculated the relationship between the amount of change ΔVio(R12) in the input offset voltage when trimming resistors R1 and R2 are trimmed and the amount of change ΔTCVio(R12) in the temperature drift coefficient of the input offset voltage in the differential circuit 1 configured as described above. The results are shown in Figure 2. As shown in the figure, the relationship between ΔVio(R12) and ΔTCVio(R12) is expressed by the following equation (1). ΔTCVio(R12)=n1×ΔVio(R12) (1) n1: coefficient

[0028] That is, when ΔVio(R12) increases to the positive or negative side, ΔTCVio(R12) also increases to the positive or negative side, and it was found that ΔVio(R12) and ΔTCVio(R12) are correlated.

[0029] Furthermore, the inventors have calculated the relationship between the amount of change Vio (R34) in the input offset voltage when trimming resistors R3 and R4 are trimmed and the amount of change ΔTCVio (R34) in the temperature drift coefficient of the input offset voltage in the differential circuit 1 configured as described above. The results are shown in Figure 3. As shown in the figure, the relationship between ΔVio (R34) and ΔTCVio (R34) is expressed by the following equation (2). ΔTCVio(R34)=n2×ΔVio(R34) (2) n2: coefficient

[0030] That is, when ΔVio(R34) increases to the positive or negative side, ΔTCVio(R34) also increases to the positive or negative side, and it was found that ΔVio(R34) and ΔTCVio(R34) are correlated.

[0031] In this embodiment, with n2>n1 set, trimming resistors R1 and R2 are trimmed first, and then trimming resistors R3 and R4 are trimmed, thereby improving both the input offset voltage Vio and the temperature drift coefficient TCVio of the input offset voltage of the differential circuit 1.

[0032] This will be explained in more detail with reference to Figure 4. For example, let us consider a case where the input offset voltage Vio and temperature drift coefficient TCVio are positive before trimming, as shown in P1. First, trimming resistors R1 and R2 are trimmed so that the input offset voltage Vio moves negative, bringing the input offset voltage Vio closer to zero. At this time, the temperature drift coefficient TCVio also moves negative and approaches zero, but because coefficient n1 is set low, it cannot approach zero as much as the input offset voltage Vio. Therefore, trimming of trimming resistors R1 and R2 is stopped before the input offset voltage Vio reaches zero. Next, trimming resistors R3 and R4 are trimmed so that the input offset voltage Vio moves negative, bringing the input offset voltage Vio and temperature drift coefficient TCVio even closer to zero. Because coefficient n2 is set high, the temperature drift coefficient TCVio can approach zero as much as the input offset voltage Vio, improving both the input offset voltage Vio and the temperature drift coefficient TCVio.

[0033] If the input offset voltage Vio and the temperature drift coefficient TCVio are on the negative side as shown in P2 before trimming, the above explanation of P1 can be explained by replacing "positive side" with "negative side" and "negative side" with "positive side."

[0034] Next, we will explain the case where, before trimming, the input offset voltage Vio is negative and the temperature drift coefficient TCVio is positive, as shown in P3. First, trimming resistors R1 and R2 are trimmed to move the input offset voltage Vio toward the positive side, bringing the input offset voltage Vio closer to zero. At this time, the temperature drift coefficient TCVio also moves toward the positive side, making it larger than before trimming. Therefore, trimming resistors R1 and R2 are trimmed until the input offset voltage Vio becomes positive. Next, trimming resistors R3 and R4 are trimmed to move the input offset voltage Vio toward the negative side, bringing the input offset voltage Vio and temperature drift coefficient TCVio closer to zero. Because coefficient n2 is set high, the temperature drift coefficient TCVio can be brought closer to zero than the input offset voltage Vio, improving both the input offset voltage Vio and the temperature drift coefficient TCVio.

[0035] If, before trimming, the input offset voltage Vio is on the positive side and the temperature drift coefficient TCVio is on the negative side as shown in P4, then in the explanation of P3 above, "positive side" can be read as "negative side" and "negative side" as "positive side."

[0036] Furthermore, with n2>n1 set, trimming resistors R3 and R4 are trimmed first, and then trimming resistors R1 and R2 are trimmed, which can also improve both the input offset voltage Vio and the temperature drift coefficient TCVio of the input offset voltage of the differential circuit 1.

[0037] This will be explained in more detail with reference to Figure 5. For example, let us consider a case where the input offset voltage Vio and temperature drift coefficient TCVio are positive before trimming, as shown in P1. First, trimming resistors R3 and R4 are trimmed so that the temperature drift coefficient TCVio moves negative, bringing the temperature drift coefficient TCVio closer to zero. At this time, the input offset voltage Vio also moves negative and approaches zero, but because coefficient n2 is set high, it cannot approach zero as much as the temperature drift coefficient TCVio. Therefore, trimming of trimming resistors R3 and R4 is stopped before the temperature drift coefficient TCVio reaches zero. Next, trimming resistors R1 and R2 are trimmed so that the temperature drift coefficient TCVio moves negative, bringing the input offset voltage Vio and temperature drift coefficient TCVio even closer to zero. Because coefficient n1 is set low, the input offset voltage Vio can approach zero as much as the temperature drift coefficient TCVio, improving both the input offset voltage Vio and the temperature drift coefficient TCVio.

[0038] If the input offset voltage Vio and the temperature drift coefficient TCVio are on the negative side as shown in P2 before trimming, the above explanation of P1 can be explained by replacing "positive side" with "negative side" and "negative side" with "positive side."

[0039] Next, we will explain the case where, before trimming, the input offset voltage Vio is negative and the temperature drift coefficient TCVio is positive, as shown in P3. First, trimming resistors R3 and R4 are trimmed so that the temperature drift coefficient TCVio moves negative, bringing the temperature drift coefficient TCVio closer to zero. At this time, the input offset voltage Vio also moves negative, making it larger than before trimming. Therefore, trimming resistors R3 and R4 are trimmed until the temperature drift coefficient TCVio moves negative. Next, trimming resistors R1 and R2 are trimmed so that the input offset voltage Vio moves positive, bringing the input offset voltage Vio and temperature drift coefficient TCVio closer to zero. Because coefficient n1 is set low, the input offset voltage Vio can be brought closer to zero than the temperature drift coefficient TCVio, improving both the input offset voltage Vio and the temperature drift coefficient TCVio.

[0040] If, before trimming, the input offset voltage Vio is on the positive side and the temperature drift coefficient TCVio is on the negative side as shown in P4, then in the explanation of P3 above, "positive side" can be read as "negative side" and "negative side" as "positive side."

[0041] As explained above, it is important to make n1 and n2 different from each other, and when n1=n2, it is not possible to improve both the input offset voltage Vio and the temperature drift coefficient TCVio.

[0042] Figure 6 is a diagram showing how the input offset voltage Vio and its temperature drift coefficient TCVio change, with the horizontal axis representing the input offset voltage Vio and the vertical axis representing the temperature drift coefficient TCVio of the input offset voltage. In the diagram, the distribution of the input offset voltage Vio and its temperature drift coefficient TCVio before trimming is shown by a dashed circle, and the distribution of the input offset voltage Vio and its temperature drift coefficient TCVio after trimming is shown by a solid circle. As shown in the diagram, the differential circuit 1 shown in Figure 1 described above can improve both the input offset voltage Vio and the temperature drift coefficient TCVio.

[0043] Next, a method for determining the coefficient n1 will be described. First, the amount of change ΔVio(R12) in the input offset voltage when the resistors R1 and R2 are trimmed is determined by the following equation (3).

[0044]

number

[0045] gm(M1): Transconductance of transistor M1 ΔR12: The difference in resistance between resistors R1 and R2 after trimming resistors R1 and R2 R12: The average resistance value of resistors R1 and R2 after trimming resistors R1 and R2 I TAIL : Current flowing through current source CS1 I FD : Drain current I of transistors M3 and M4 FD1 ,I FD1 Average value of

[0046] By differentiating this ΔVio(R12) with respect to temperature, the amount of change ΔTCVio(R12) in the temperature drift coefficient of the input offset voltage when the resistors R1 and R2 are trimmed is calculated using the following equation (4).

[0047]

number

[0048] The coefficient n1 can be calculated by dividing equation (4) by equation (3) as follows:

[0049]

number

[0050] Next, a method for determining the coefficient n2 will be described. First, the amount of change ΔVio(R34) in the input offset voltage when the resistors R3 and R4 are trimmed is determined by the following equation (6).

[0051]

number

[0052] ΔR34: The difference in resistance between resistors R3 and R4 after trimming resistors R3 and R4 R34: Average resistance value of resistors R3 and R4 after trimming

[0053] By differentiating this ΔVio(R34) with respect to temperature, the amount of change ΔTCVio(R34) in the temperature drift coefficient of the input offset voltage when the resistors R3 and R4 are trimmed is calculated using the following equation (7).

[0054]

number

[0055] The coefficient n2 can be calculated by dividing equation (6) by equation (7) as follows:

[0056]

number

[0057] As mentioned above, in order to improve both the input offset voltage Vio and the temperature drift coefficient TCVio, n1 and n2 must be different. Next, we will explain an example of when n1 = n2. To start with, as shown in Figure 7, when the current I TAIL does not change with temperature, and the drain current I FD1 ,I FD2 The average value of I FD If n1 does not change with temperature, then n1 = n2.

[0058] This can be confirmed using the theoretical formula: Current I TAIL , drain current I FD1 ,I FD2When does not change with temperature and the trimming resistors R1 and R2 are trimmed, the coefficient n1 is given by the following equation (9).

[0059]

number

[0060] Furthermore, when the trimming resistors R3 and R4 are trimmed, the coefficient n2 is given by the following equation (10).

[0061]

number

[0062] The same result is obtained from equations (9) and (10). Looking at these equations in more detail, equations (9) and (10) can be summarized as the following equation (11).

[0063]

number

[0064] Here, the constants used in equation (11) are defined as follows: I TAIL : Current value flowing through current source CS1. No temperature dependency. W(M1): Gate length of transistor M1. No temperature dependency. L(M1): Gate width of transistor M1. No temperature dependency. k´: Mobility μ of transistor M1 and gate capacitance C per unit area OX Product of. Temperature dependent.

[0065] In equation (11), the temperature differential value of k' is entered. Since k' generally has a negative temperature characteristic, equation (11) indicates that n1 and n2 take positive values. And, equation (11) shows that n1 and n2 are only related to the magnitude of k' and the temperature characteristic of k'. That is, as explained in the conclusion above, the current I flowing through the current source CS1 TAILdoes not change with temperature, and the drain current I FD1 ,I FD2 The average value of I FD If the current I TAIL , drain current I FD1 ,I FD2 If varies with temperature, then n1 ≠ n2.

[0066] Next, the inventors calculate the current I TAIL , drain current I FD1 ,I FD2 When does not change with temperature (Fig. 7(A)), the current I TAIL is the negative temperature characteristic, the drain current I FD1 ,I FD2 When does not change with temperature (Fig. 7(B)), the current I TAIL , drain current I FD1 ,I FD2 In the case of negative temperature characteristics (Fig. 7(C)), the coefficients n1 and n2 were obtained by actual measurements. As explained in the theoretical formula above, in the case of Fig. 7(A), n1 and n2 were almost the same value, and the ratio n2 / n1 was almost 1. In the case of Fig. 7(B), there was a slight difference between n1 and n2, and the ratio n2 / n1 was slightly large at 1.554. In the case of Fig. 7(C), there was a large difference between n1 and n2, and the ratio n2 / n1 was large at 1.846. That is, the current I TAIL , drain current I FD1 ,I FD2 It was found that the ratio n1 / n2 can be increased by adjusting the temperature dependence of . A larger ratio n2 / n1 makes it easier to reduce both the input offset voltage Vio and the temperature drift coefficient TCVio.

[0067] Next, the inventors measured the input offset voltage of approximately 40 of the above-mentioned differential circuits 1 before trimming the trimming resistors R1 to R4. The results are shown in Figure 8. Furthermore, the inventors measured the input offset voltage of the above-mentioned differential circuits 1 after trimming the trimming resistors R1 to R4. The results are shown in Figure 9.

[0068] 8 and 9, the standard deviation of the input offset voltage Vio at 25°C was 306μV before trimming, but was reduced to 5μV after trimming. Also, the standard deviation of the temperature drift coefficient TCVio of the input offset voltage from -40°C to 125°C was 0.41μV / °C before trimming, but was reduced to 0.10μV after trimming.

[0069] (Second embodiment) Next, a differential circuit 1B of the second embodiment will be described with reference to Fig. 10. In Fig. 10, parts equivalent to those of the differential circuit 1 of Fig. 1 already described in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. The difference between the first and second embodiments is the configuration of the first current circuit 12B.

[0070] The first current circuit 12B has, in addition to the current source CS1, a transistor M8 (= eighth transistor), a transistor M9 (= ninth transistor), a resistor R5 (= fifth resistor), and a resistor R6 (= sixth resistor). The transistors M8 and M9 are configured by P-channel MOS field-effect transistors. In the second embodiment, the current source CS1 (= first current source) has no temperature dependency and is connected between the gate and drain of the transistor M8 and the negative power supply terminal T22. The gate and drain of the transistor M8 are connected.

[0071] The gate and drain of the transistor M8 are connected to the gate of the transistor M9, and the transistors M8 and M9 form a current mirror circuit. The transistor M9 mirrors the current flowing through the transistor M8, generating a current I TAIL The drain of transistor M9 is connected to the sources of transistors M1 and M2. Resistor R5 is connected between the source of transistor M8 and positive power supply terminal T21. Resistor R6 is connected between the source of transistor M9 and positive power supply terminal T21.

[0072] Here, resistors R5 and R6 are different types of resistors with different temperature dependencies. In this embodiment, for example, resistor R5 is made of a polysilicon resistor, and resistor R6 is made of a diffused resistor. As a result, as shown in FIG. 11(A), resistor R5 has a negative temperature dependency, and resistor R6 has a positive temperature dependency. In this case, as shown in FIG. 11(B), the current I supplied to transistors M1 and M2 TAIL can be adjusted to have a negative temperature dependence.

[0073] Conversely, if resistor R5 is a diffused resistor and resistor R6 is a polysilicon resistor, resistor R5 will have a positive temperature dependency and resistor R6 will have a negative temperature dependency, as shown in Figure 12(A). In this case, as shown in Figure 12(B), the current I supplied to transistors M1 and M2 will TAIL can be adjusted to have a positive temperature dependence.

[0074] Next, using the above equations (5) and (8), the current I TAIL The coefficients n1 and n2 were calculated when the temperature dependence was changed from negative to positive. The calculation results are shown in Figure 13. The following conditions were used for the calculation results: gm(M1) = 1000 μA / V However, the k' used in the function in gm(M1) is k' = 17.13 × 10 -6 , with a temperature dependency of -0.4% / ℃. Furthermore, the current I used in the function gm(M1) TAIL Also I TAIL = 160 μA, which is temperature dependent, and the current I FD teeth I FD = 80μA and is assumed to have no temperature dependency.

[0075] As shown in Figure 13, the coefficient n1 is TAIL As the temperature dependence of changes from negative temperature characteristics to positive temperature characteristics (positive temperature characteristics), a gradual decrease is observed. TAIL The temperature dependence of decreases as the temperature characteristic changes from negative to positive. TAIL A temperature change of 0% / ℃ means that the current I TAILThis means that the current I TAIL There is no temperature change in the FD When there is no temperature change, n1=n2. The calculation result in FIG. 13 also shows that n1=n2 when the horizontal axis is 0% / °C. In this embodiment, the current I TAIL In other words, in Figure 13, the current I TAIL Therefore, in this embodiment, different types of resistors R5 and R6 with different temperature dependencies are used to control the current I TAIL The temperature dependence of

[0076] Furthermore, noteworthy in Figure 13 is that there is a point where n2 becomes zero. TAIL When the temperature change of becomes about 0.4% / °C, n2 becomes zero. At this point, even if the input offset voltage Vio is changed by trimming the trimming resistors R3 and R4, the temperature drift coefficient TCVio will not change.

[0077] As described above, according to the second embodiment, resistors with different temperature dependencies are used as the resistors R5 and R6, and the current I TAIL It is characterized by adjusting the temperature dependence of the current I TAIL By adjusting the temperature dependency of n1, n2 can be adjusted so that they are not the same value. By making these values ​​different, it is possible to improve both the input offset voltage Vio and the temperature drift coefficient TCVio. In addition, the configuration is simple, and the current I TAIL The temperature dependence of the

[0078] (Third embodiment) Next, a differential circuit 1C of the third embodiment will be described with reference to Fig. 14. In Fig. 14, parts equivalent to those of the differential circuit 1 of Fig. 1 already described in the first embodiment are given the same reference numerals, and detailed description thereof will be omitted. The difference between the first and third embodiments is the configuration of a current section 151C of a second current circuit 15C.

[0079] In the third embodiment, the current section 151C has, in addition to a current source CS2 (=second current source), a transistor M10 (=tenth transistor), a transistor M11 (=eleventh transistor), a resistor R7 (=seventh resistor), and a resistor R8 (=eighth resistor). The transistors M10 and M11 are configured as N-channel MOS field-effect transistors. The gate and drain of the transistor M10 are connected. In the third embodiment, the current source CS2 has no temperature dependency, is connected between the gate and drain of the transistor M10 and the positive power supply terminal T21, and supplies current to the transistor M10.

[0080] The gate and drain of transistor M10 are connected to the gate of transistor M11, and transistors M10 and M11 form a current mirror circuit. The drain of transistor M11 is connected to the drain and gate of transistor M3. Transistor M11 reflects the current flowing through transistor M10 and supplies it to transistor M3. Resistor R7 is connected between the source of transistor M10 and negative power supply terminal T22. Resistor R8 is connected between the source of transistor M11 and negative power supply terminal T22.

[0081] Here, resistors R7 and R8 are different types of resistors with different temperature dependencies. In this embodiment, for example, resistor R7 is made of a polysilicon resistor, and resistor R8 is made of a diffused resistor. As a result, as shown in FIG. 15(A), resistor R7 has a negative temperature dependency, and resistor R8 has a positive temperature dependency. In this case, as shown in FIG. 15(B), the drain current I FD1 ,I FD2 can be adjusted to have a negative temperature dependence.

[0082] Conversely, if resistor R7 is configured as a diffused resistor and resistor R8 is configured as a polysilicon resistor, resistor R7 will have a positive temperature dependency and resistor R8 will have a negative temperature dependency, as shown in Figure 16(A). In this case, as shown in Figure 16(B), the drain current I FD1 ,I FD2can be adjusted to have a positive temperature dependence.

[0083] Next, using the above equations (5) and (8), the drain current I FD1 ,I FD2 The coefficients n1 and n2 were calculated when the temperature dependence was changed from negative to positive. The calculation results are shown in Figure 17. The following conditions were used for the calculation results. gm(M1) = 1000 μA / V However, the k' used in the function in gm(M1) is k' = 17.13 × 10 -6 , with a temperature dependency of -0.4% / ℃. Furthermore, the current I used in the function gm(M1) TAIL teeth I TAIL = 160 μA, there is no temperature dependency, and the current I FD teeth I FD = 80μA and is temperature dependent.

[0084] As shown in Figure 17, n1 is the drain current I FD1 ,I FD2 As the temperature dependence of changes from negative temperature characteristics to positive temperature characteristics, a large increase is observed. FD1 ,I FD2 As the temperature dependence of increases from negative temperature characteristics to positive temperature characteristics, the increase is smaller than n1. Here, the drain current I FD1 ,I FD2 When the temperature change is 0% / ℃, the drain current I FD1 ,I FD2 This means that the drain current I FD1 ,I FD2 There is no temperature change in the TAIL When there is no temperature change, n1=n2. The calculation results in FIG. 17 also show that n1=n2 when the horizontal axis is 0% / °C. In this embodiment, the drain current I FD1 ,I FD2 The purpose of this is to adjust the temperature dependence of the drain current I FD1 ,IFD2 Therefore, in this embodiment, different types of resistors R7 and R8 with different temperature dependencies are used to control the drain current I FD1 ,I FD2 The temperature dependence of

[0085] Furthermore, noteworthy in Figure 17 is that there are points where n1 is zero and n2 is zero. FD1 ,I FD2 When the temperature change of is about -0.2% / ℃, n1 becomes zero. At this point, even if the input offset voltage Vio is changed by trimming the trimming resistors R1 and R2, the temperature drift coefficient TCVio does not change. Also, the drain current I FD1 ,I FD2 When the temperature change of is about -0.3% / °C, n2 becomes zero. At this point, even if the input offset voltage Vio is changed by trimming the trimming resistors R3 and R4, the temperature drift coefficient TCVio will not change.

[0086] As described above, according to the third embodiment, resistors R7 and R8 with different temperature dependencies are used, and the drain current I FD1 ,I FD2 It is characterized by adjusting the temperature dependence of the drain current I FD1 ,I FD2 By adjusting the temperature dependency of n1, n2 can be adjusted so that they are not the same value. By making these values ​​different, it is possible to improve both the input offset voltage Vio and the temperature drift coefficient TCVio. In addition, the configuration is simple, the chip area is small, and the drain current I FD1 ,I FD2 The temperature dependence of the

[0087] (Fourth embodiment) Next, a differential circuit 1D of the fourth embodiment will be described with reference to Fig. 18. When resistors R5, R6, R7, and R8 having different temperature dependencies are used as in the second and third embodiments, the current ITAIL , drain current I FD1 ,I FD2 The magnitude and temperature characteristics of the resistors may differ from the design values. As a result, the input offset voltage Vio and temperature drift coefficient TCVio after trimming may not be improved below the expected values ​​at the time of design. The differential circuit 1D of the fourth embodiment solves this problem.

[0088] 18, parts equivalent to those in the differential circuit 1B shown in FIG. 10, which has already been described in the second embodiment, are designated by the same reference numerals, and detailed description thereof will be omitted. The main difference between the second embodiment and the fourth embodiment is the configurations of the first trimming circuit 13D and the second trimming circuit 14D.

[0089] The first trimming circuit 13D has trimming resistors R1A and R1B, trimming resistors R2A and R2B instead of the trimming resistors R1 and R2, and test terminals T31 and T32. The trimming resistors R1A and R1B are connected in series between the drain of the transistor M1 and the negative voltage terminal T22. The trimming resistors R2A and R2B are connected in series between the drain of the transistor M2 and the negative voltage terminal T22. The test terminal T31 is connected to the connection point of the trimming resistors R1A and R1B. The test terminal T32 is connected to the connection point of the trimming resistors R2A and R2B.

[0090] The second trimming circuit 14D has trimming resistors R3A and R3B, trimming resistors R4A and R4B instead of the trimming resistors R3 and R4, and test terminals T41 and T42. The trimming resistors R3A and R3B are connected in series between the source of the transistor M4 and the positive voltage terminal T21. The trimming resistors R4A and R4B are connected in series between the source of the transistor M5 and the positive voltage terminal T21. The test terminal T41 is connected to the connection point of the trimming resistors R3A and R3B. The test terminal T42 is connected to the connection point of the trimming resistors R4A and R4B.

[0091] In this embodiment, trimming resistors R1B, R2B, R3A, and R4A are shorted by applying an external potential to test terminals T31, T32, T41, and T42. When the test terminals T31 and T32 are supplied with the same voltage as the negative power supply voltage VSS, trimming resistors R1B and R2B can be shorted. When the test terminals T41 and T42 are supplied with the same voltage as the positive power supply voltage VDD, trimming resistors R3A and R4A can be shorted. This allows the resistance values ​​of the trimming resistors to be changed before trimming, enabling pre-verification of trimming. A detailed description of the pre-verification will be given with reference to FIG. 19.

[0092] First, the input offset voltage Vio is measured at 25°C before trimming the resistors R1A, R1B to R4A, R4B (S1). More specifically, the output of the differential circuit 1 when the input terminals T11 and T12 are open is measured as the input offset voltage Vio.

[0093] Next, voltages are applied to test terminals T31, T32, T41, and T42 at 25°C to determine the amounts of change in input offset voltage, ΔVio (R12) and ΔVio (R34) (S2). More specifically, when the same potential as the negative power supply voltage VSS is applied to test terminal T31, and when the same potential as the negative power supply voltage VSS is applied to test terminal T32, the input offset voltage Vio is measured for each. The amount of change in input offset voltage, ΔVio (R12), can be determined from this measured input offset voltage Vio and the input offset voltage Vio measured in S1. Furthermore, when the same potential as the positive power supply voltage VDD is applied to test terminal T41, and when the same potential as the positive power supply voltage VDD is applied to test terminal T42, the input offset voltage Vio is measured for each. The amount of change in input offset voltage, ΔVio (R34), can be determined from this measured input offset voltage Vio and the input offset voltage Vio measured in S1.

[0094] Next, the input offset voltage Vio before trimming the resistors R1A, R1B to R4A, R4B is measured at high and low temperatures, and the temperature drift coefficient TCVio of the input offset voltage Vio before trimming is calculated from the measurement results (S3).

[0095] Next, voltages are applied to test terminals T31, T32, T41, and T42 at high and low temperatures to determine the temperature drift coefficient changes ΔTCVio (R12) and ΔTCVio (R34) (S4). More specifically, the input offset voltage Vio is measured when the same potential as the negative power supply voltage VSS is applied to test terminal T31 at high and low temperatures, and when the same potential as the negative power supply voltage VSS is applied to test terminal T32 at high and low temperatures. The temperature drift coefficient change ΔTCVio (R12) can be calculated from this measured input offset voltage Vio and the temperature drift coefficient TCVio calculated in S3. The input offset voltage Vio is also measured when the same potential as the positive power supply voltage VDD is applied to test terminal T41 at high and low temperatures, and when the same potential as the positive power supply voltage VDD is applied to test terminal T42 at high and low temperatures. The amount of change in the temperature drift coefficient ΔTCVio (R34) can be calculated from the measured input offset voltage Vio and the temperature drift coefficient TCVio calculated in S3.

[0096] Next, coefficients n1 and n2 are calculated from the input offset voltage changes ΔVio(R12) and ΔVio(R34) calculated in S2 and the temperature drift coefficient changes ΔTCVio(R12) and ΔTCVio(R34) calculated in S4 (S5).

[0097] Next, the trimming resistors R1A, R1B to R4A, and R4B are trimmed based on the coefficients n1 and n2 (S6). After that, the input offset voltage Vio is measured at 25°C (S7) to confirm that the input offset voltage Vio has been reduced after trimming.

[0098] Furthermore, the input offset voltage Vio is measured at high and low temperatures, and the temperature drift coefficient TCVio is calculated from the measurement results (S8), and it is confirmed that the temperature drift coefficient TCVio has been reduced after trimming.

[0099] According to the above-described embodiment, accurate coefficients n1 and n2 can be determined before trimming, which makes it possible to further reduce both the input offset voltage Vio and the temperature drift coefficient TCVio.

[0100] (Fifth embodiment) Next, a differential circuit 1E of the fifth embodiment will be described with reference to FIG. 20. In the figure, parts equivalent to those of the differential circuit 1C shown in FIG. 14 already described in the third embodiment are given the same reference numerals, and detailed description thereof will be omitted. The differential circuit 1E of the fifth embodiment is characterized in that the differential circuit 1C of the third embodiment is provided with the test terminals T31, T32, T41, and T42 described in the fourth embodiment. The major difference between the third and fifth embodiments is the configuration of the first trimming circuit 13D and the second trimming circuit 14D.

[0101] The first trimming circuit 13D and the second trimming circuit 14D have already been described in the fourth embodiment, so detailed description thereof will be omitted.

[0102] In the fifth embodiment described above, similarly to the fourth embodiment, accurate coefficients n1 and n2 can be obtained before trimming using the test terminals T31, T32, T41, and T42, and both the input offset voltage Vio and the temperature drift coefficient TCVio can be further reduced.

[0103] (Sixth embodiment) Next, a differential circuit 1F of a sixth embodiment will be described with reference to FIG. 21. In the fourth embodiment described above, the test terminals T31, T32, T41, and T42 are set to the same potential as the negative power supply voltage VSS and the positive power supply voltage VDD. However, if there is contact resistance in the test terminals T31, T32, T41, and T42, there is a problem in that the test terminals T31, T32, T41, and T42 cannot be set to the same potential as the negative power supply voltage VSS and the positive power supply voltage VDD. In this case, the coefficients n1 and n2 cannot be calculated with high accuracy. The sixth embodiment solves this problem.

[0104] 21, the same reference numerals are used to designate the same parts as those in the differential circuit 1D shown in FIG. 18, which has already been described in the fourth embodiment, and detailed description thereof will be omitted. The major difference between the fourth embodiment and the sixth embodiment is the configurations of the first trimming circuit 13F and the second trimming circuit 14F.

[0105] The first trimming circuit 13F has trimming resistors R1A, R1B, R2A, and R2B, test terminals T31 and T32, and transistors MT1 and MT2 (=transistor switches). The transistors MT1 and MT2 are configured by N-channel MOS field-effect transistors. The drain of the transistor MT1 is connected to the connection point of the trimming resistors R1A and R1B, the source is connected to the negative power supply terminal T22, and the gate is connected to the test terminal T31.

[0106] The transistor MT2 has a drain connected to the connection point of the trimming resistors R2A and R2B, a source connected to the negative power supply terminal T22, and a gate connected to the test terminal T32.

[0107] The second trimming circuit 14F has trimming resistors R3A, R3B, R4A, and R4B, test terminals T41 and T42, and transistors MT3 and MT4 (=transistor switches). The transistors MT3 and MT4 are P-channel MOS field-effect transistors. The drain of the transistor MT3 is connected to the connection point of the trimming resistors R3A and R3B, the source is connected to the positive power supply terminal T21, and the gate is connected to the test terminal T41.

[0108] The transistor MT4 has a drain connected to the connection point of the trimming resistors R4A and R4B, a source connected to the positive power supply terminal T21, and a gate connected to the test terminal T42.

[0109] According to the sixth embodiment, by applying a voltage to the test terminals T31 and T32 and turning on the transistors MT1 and MT2, a negative power supply voltage VSS can be applied to the junction of the resistors R1A and R1B and the junction of the resistors R2A and R2B. Furthermore, by applying a voltage to the test terminals T41 and T42 and turning on the transistors MT3 and MT4, a positive power supply voltage VDD can be applied to the junction of the resistors R3A and R3B and the junction of the resistors R4A and R4B. The pre-trimming verification procedure is the same as in the fourth embodiment, and therefore a detailed description thereof will be omitted here.

[0110] (Seventh embodiment) Next, a differential circuit 1G of the seventh embodiment will be described with reference to FIG. 22. In the figure, parts equivalent to those of the differential circuit 1E shown in FIG. 20 already described in the fifth embodiment are given the same reference numerals, and detailed description thereof will be omitted. The differential circuit 1G of the seventh embodiment differs from the differential circuit 1E of the fifth embodiment in that it is provided with the transistors MT1 to MT4 described in the sixth embodiment. The major difference between the fifth and seventh embodiments is the configurations of the first trimming circuit 13F and the second trimming circuit 14F.

[0111] The first trimming circuit 13F and the second trimming circuit 14F have already been described in the sixth embodiment, and therefore detailed description thereof will be omitted.

[0112] In the seventh embodiment described above, similarly to the sixth embodiment, the test terminals T31, T32, T41, and T42 are used to control the on / off of the transistors MT1 to MT4, making it possible to obtain accurate coefficients n1 and n2 before trimming, and further reducing both the input offset voltage Vio and the temperature drift coefficient TCVio.

[0113] The present invention is not limited to the above-described embodiments, and can be appropriately modified, improved, etc. Furthermore, the material, shape, size, number, location, etc. of each component in the above-described embodiments are arbitrary and not limited as long as they can achieve the present invention.

[0114] In the above-described embodiment, the transistors M1 to M11 are configured as MOS field-effect transistors, but this is not limited thereto. The transistors M1 to M11 may be configured as J-FETs or bipolar transistors. When configured as bipolar transistors, the above description can be explained by replacing the "gate" with the "base," the "source" with the "emitter," and the "drain" with the "collector." [Explanation of symbols]

[0115] 1. 1B~1G differential circuit 11 Differential Input Pair 12, 12B First current circuit 13, 13D, 13F First trimming circuit (first adjustment circuit) 14, 14D, 14F Second trimming circuit (second adjustment circuit) 15,15C Second current circuit 151,151C current section CS1 Current Source (First Current Source) CS2 Current Source (Second Current Source) M1 transistor (first differential transistor) M2 transistor (second differential transistor) M3 transistor (third transistor) M4 transistor (fourth transistor) M5 transistor (fifth transistor) M6 transistor (sixth transistor) M7 transistor (seventh transistor) M8 transistor (8th transistor) M9 transistor (9th transistor) M10 Transistor (10th transistor) M11 transistor (11th transistor) MT1~MT4 Transistors (Transistor Switches) R1, R1A, R1B Trimming resistors (first adjustment resistors) R2, R2A, R2B Trimming resistors (second adjustment resistors) R3, R3A, R3B trimming resistors (third adjustment resistors) R4, R4A, R4B trimming resistors (fourth adjustment resistors) R5 Resistor (5th resistor) R6 Resistor (6th resistor) R7 Resistor (7th resistor) R8 Resistor (8th resistor) T21 Positive power supply terminal (first power supply terminal) T22 Negative power supply terminal (second power supply terminal) T31, T31, T41, T42 Test terminals (short circuit) VDD Positive power supply voltage (first power supply voltage) VSS Negative power supply voltage (second power supply voltage) T11, T12 input terminals

Claims

1. an input differential pair having a first differential transistor and a second differential transistor; a first current circuit connected between a first power supply terminal to which a first power supply voltage is supplied and the sources or emitters of the first differential transistor and the second differential transistor, and supplying a current to the input differential pair; a first adjustment circuit having a first adjustment resistor whose resistance value is adjustable and connected between the drain or collector of the first differential transistor and a second power supply terminal to which a second power supply voltage is supplied, and a second adjustment resistor whose resistance value is adjustable and connected between the drain or collector of the second differential transistor and the second power supply terminal; a second adjustment circuit including a third adjustment resistor having an adjustable resistance value connected between the connection point of the first differential transistor and the first adjustment resistor and the first power supply terminal, and a fourth adjustment resistor having an adjustable resistance value connected between the connection point of the second differential transistor and the second adjustment resistor and the first power supply terminal; a second current circuit that supplies current to the third adjustment resistor and the fourth adjustment resistor; The current supplied from the first current circuit and the current supplied from the second current circuit have different temperature dependencies. Differential circuit.

2. 2. The differential circuit according to claim 1, the second current circuit includes a third transistor, a current section that supplies a current to the third transistor, and a fourth transistor and a fifth transistor that form a current mirror circuit together with the third transistor and mirror back the current flowing through the third transistor; the fourth transistor is connected between the third adjustment resistor and a connection point of the first differential transistor and the first adjustment resistor; the fifth transistor is connected between the fourth adjustment resistor and a connection point of the second differential transistor and the second adjustment resistor; Differential circuit.

3. 3. The differential circuit according to claim 2, the second current circuit has a sixth transistor and a seventh transistor that form a current mirror circuit; the sixth transistor is connected between the fourth transistor and a connection point of the first differential transistor and the first adjustment resistor; the seventh transistor is connected between the fifth transistor and a connection point of the second differential transistor and the second adjustment resistor; Differential circuit.

4. 2. The differential circuit according to claim 1, the first current circuit includes an eighth transistor, a first current source that supplies a current to the eighth transistor, a ninth transistor that forms a current mirror circuit together with the eighth transistor and returns the current flowing through the eighth transistor to supply the current to the input differential pair, a fifth resistor connected between the eighth transistor and the first power supply terminal, and a sixth resistor connected between the ninth transistor and the first power supply terminal; the fifth resistor and the sixth resistor are composed of resistors having different temperature dependencies; Differential circuit.

5. 3. The differential circuit according to claim 2, the current unit includes a tenth transistor, a second current source that supplies a current to the tenth transistor, an eleventh transistor that forms a current mirror circuit together with the tenth transistor and returns the current flowing through the tenth transistor to supply the current to the third transistor, a seventh resistor connected between the tenth transistor and the second power supply terminal, and an eighth resistor connected between the eleventh transistor and the second power supply terminal; The seventh resistor and the eighth resistor are composed of resistors having different temperature dependencies. Differential circuit.

6. 2. The differential circuit according to claim 1, the first adjustment resistor, the second adjustment resistor, the third adjustment resistor, and the fourth adjustment resistor each include a plurality of trimming resistors connected in series; a short-circuiting circuit is provided for short-circuiting some of the plurality of trimming resistors included in at least one of the first adjustment resistor, the second adjustment resistor, the third adjustment resistor, and the fourth adjustment resistor; Differential circuit.

7. 7. The differential circuit according to claim 6, the short-circuiting circuit is composed of a test terminal provided between the plurality of trimming resistors; Differential circuit.

8. 7. The differential circuit according to claim 6, the shorting circuit is configured with a transistor switch that shorts between the plurality of trimming resistors and the first power supply terminal or the second power supply terminal; Differential circuit.

9. 2. The differential circuit according to claim 1, The transistor is composed of a field effect transistor. Differential circuit.

10. 2. The differential circuit according to claim 1, The transistor is composed of a bipolar transistor. Differential circuit.

Images