Integrated capacitor with extended head bump bond pillar

Abstract

To provide an integrated capacitor that achieves good performance without unnecessarily increasing a size.SOLUTION: A microelectronic device 100 includes a die 101, a first conductive pillar 113 mechanically coupled to the die, a second conductive pillar 114, a first conductive expansion head 119 electrically coupled to the first conductive pillar, and a second conductive expansion head 120 electrically coupled to the second conductive pillar. The first conductive pillar and the second conductive pillar are formed concurrently, resulting in having equal compositions of electrically conductive material. The first expansion head and the second expansion head are formed concurrently, resulting in having equal compositions of electrically conductive material. The first expansion head provides a bump pad and the second expanded head provides at least a portion of a first plate 122 of an integrated capacitor 110. The second plate 109 is disposed within the die, between the first plate and the die, or on a side opposite the die, of the first plate.SELECTED DRAWING: Figure 1G

Description

[Technical Field]

[0001] The present disclosure relates to the field of microelectronic devices, and more particularly to integrated capacitors in microelectronic devices. [Background technology]

[0002] Some microelectronic devices operate at high frequencies and use capacitors to regulate high-frequency currents. These capacitors should be tightly integrated with the microelectronic device to achieve better performance. However, the capacitors require significant area and can unnecessarily increase the size of the microelectronic device. Summary of the Invention

[0003] The present disclosure introduces a microelectronic device having a die with a connecting surface, a first conductive pillar, and a second conductive pillar. The pillars are mechanically coupled to the connecting surface. The microelectronic device includes a first conductive extension head electrically coupled to the first pillar and a second conductive extension head electrically coupled to the second pillar. The first pillar and the second pillar have an equal composition of conductive material, and the first extension head and the second extension head have an equal composition of conductive material. The first extension head provides a bump pad for the microelectronic device, and the second extension head provides at least a portion of a plate of an integrated capacitor for the microelectronic device. The microelectronic device is formed by simultaneously forming the first pillar and the second pillar and simultaneously forming the first extension head and the second extension head. [Brief explanation of the drawings]

[0004] [Figure 1A] 1A-1C are cross-sectional views of an exemplary microelectronic device having an integrated capacitor illustrating stages in an exemplary method of formation. [Figure 1B]1A-1C are cross-sectional views of an exemplary microelectronic device having an integrated capacitor illustrating stages in an exemplary method of formation. [Figure 1C] 1A-1C are cross-sectional views of an exemplary microelectronic device having an integrated capacitor illustrating stages in an exemplary method of formation. [Figure 1D] 1A-1C are cross-sectional views of an exemplary microelectronic device having an integrated capacitor illustrating stages in an exemplary method of formation. [Figure 1E] 1A-1C are cross-sectional views of an exemplary microelectronic device having an integrated capacitor illustrating stages in an exemplary method of formation. [Figure 1F] 1A-1C are cross-sectional views of an exemplary microelectronic device having an integrated capacitor illustrating stages in an exemplary method of formation. [Figure 1G] 1A-1C are cross-sectional views of an exemplary microelectronic device having an integrated capacitor illustrating stages in an exemplary method of formation.

[0005] [Figure 2A] 10A-10C are cross-sectional views of another exemplary microelectronic device having an integrated capacitor, illustrating stages in another exemplary method of formation. [Figure 2B] 10A-10C are cross-sectional views of another exemplary microelectronic device having an integrated capacitor, illustrating stages in another exemplary method of formation. [Figure 2C] 10A-10C are cross-sectional views of another exemplary microelectronic device having an integrated capacitor, illustrating stages in another exemplary method of formation. [Figure 2D] 10A-10C are cross-sectional views of another exemplary microelectronic device having an integrated capacitor, illustrating stages in another exemplary method of formation. [Figure 2E] 10A-10C are cross-sectional views of another exemplary microelectronic device having an integrated capacitor, illustrating stages in another exemplary method of formation. [Figure 2F] 10A-10C are cross-sectional views of another exemplary microelectronic device having an integrated capacitor, illustrating stages in another exemplary method of formation.

[0006] [Figure 3A]10A-10C are cross-sectional views of a further exemplary microelectronic device having an integrated capacitor, illustrating stages of a further exemplary method of formation. [Figure 3B] 10A-10C are cross-sectional views of a further exemplary microelectronic device having an integrated capacitor, illustrating stages of a further exemplary method of formation. [Figure 3C] 10A-10C are cross-sectional views of a further exemplary microelectronic device having an integrated capacitor, illustrating stages of a further exemplary method of formation. [Figure 3D] 10A-10C are cross-sectional views of a further exemplary microelectronic device having an integrated capacitor, illustrating stages of a further exemplary method of formation. [Figure 3E] 10A-10C are cross-sectional views of a further exemplary microelectronic device having an integrated capacitor, illustrating stages of a further exemplary method of formation. [Figure 3F] 10A-10C are cross-sectional views of a further exemplary microelectronic device having an integrated capacitor, illustrating stages of a further exemplary method of formation. [Figure 3G] 10A-10C are cross-sectional views of a further exemplary microelectronic device having an integrated capacitor, illustrating stages of a further exemplary method of formation. [Figure 3H] 10A-10C are cross-sectional views of a further exemplary microelectronic device having an integrated capacitor, illustrating stages of a further exemplary method of formation. [Figure 3I] 10A-10C are cross-sectional views of a further exemplary microelectronic device having an integrated capacitor, illustrating stages of a further exemplary method of formation. [Figure 3J] 10A-10C are cross-sectional views of a further exemplary microelectronic device having an integrated capacitor, illustrating stages of a further exemplary method of formation.

[0007] [Figure 4A] 10A-10C are cross-sectional views of another exemplary microelectronic device having an integrated capacitor, illustrating stages in another exemplary method of formation. [Figure 4B] 10A-10C are cross-sectional views of another exemplary microelectronic device having an integrated capacitor, illustrating stages in another exemplary method of formation. [Figure 4C] 10A-10C are cross-sectional views of another exemplary microelectronic device having an integrated capacitor, illustrating stages in another exemplary method of formation. [Figure 4D] 10A-10C are cross-sectional views of another exemplary microelectronic device having an integrated capacitor, illustrating stages in another exemplary method of formation. [Figure 4E] 10A-10C are cross-sectional views of another exemplary microelectronic device having an integrated capacitor, illustrating stages in another exemplary method of formation. [Figure 4F] 10A-10C are cross-sectional views of another exemplary microelectronic device having an integrated capacitor, illustrating stages in another exemplary method of formation. [Figure 4G] 10A-10C are cross-sectional views of another exemplary microelectronic device having an integrated capacitor, illustrating stages in another exemplary method of formation.

[0008] [Figure 5A] 10A-10C are cross-sectional views of a further exemplary microelectronic device having an integrated capacitor, illustrating stages of a further exemplary method of formation. [Figure 5B] 10A-10C are cross-sectional views of a further exemplary microelectronic device having an integrated capacitor, illustrating stages of a further exemplary method of formation. [Figure 5C] 10A-10C are cross-sectional views of a further exemplary microelectronic device having an integrated capacitor, illustrating stages of a further exemplary method of formation. DETAILED DESCRIPTION OF THE INVENTION

[0009] The present disclosure will be described with reference to the accompanying drawings. The drawings are not drawn to scale and are provided solely to illustrate the present disclosure. Several aspects of the present disclosure are described below with reference to example applications for purposes of illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the present disclosure. The present disclosure is not limited by the described order of acts or events, as some acts may occur in different orders and / or contemporaneously with other acts or events. Additionally, not all described acts or events are required to implement a methodology in accordance with the present disclosure.

[0010] The microelectronic device has a die, such as an integrated circuit, a discrete semiconductor device, a microelectromechanical system (MEMS) device, or a microfluidic device. The die has a connection surface. External electrical connections to components of the microelectronic device are made at the connection surface. The microelectronic device includes a first pillar and a second pillar, both of which are electrically conductive and mechanically coupled to the connection surface. The first pillar and the second pillar have the same composition of conductive material. The microelectronic device includes a first extended head electrically coupled to the first pillar and a second extended head electrically coupled to the second pillar. The first extended head and the second extended head are both electrically conductive and have the same composition of conductive material. The first extended head provides a bump pad, and the second extended head provides at least a portion of a first plate of an integrated capacitor of the microelectronic device. The second plate of the integrated capacitor can be located above or below the first plate. The microelectronic device is formed by simultaneously forming the first pillar and the second pillar and by simultaneously forming the first extended head and the second extended head.

[0011] It should be noted that terms such as top, above, below, underneath, etc. may be used in this disclosure and should not be construed as limiting the location or orientation of a structure or element, but should be used to provide a spatial relationship between structures or elements.

[0012] 1A-1G are cross-sectional views of an example microelectronic device having an integrated capacitor, shown at various stages of an example method of formation. Referring to FIG. 1A, microelectronic device 100 includes die 101. Die 101 may be implemented as, for example, an integrated circuit, a discrete semiconductor device, a MEMS device, or a microfluidics device. Die 101 in this example includes substrate 102, which may include a semiconductor material such as silicon, or a dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, glass, sapphire, ceramic, or a polymeric material such as polyimide, silicon, or polyethylene. Substrate 102 may be part of a wafer or workpiece that includes additional die, or may include only die 101. Die 101 has a connecting surface 103, and substrate 102 may extend to connecting surface 103 as shown in FIG. 1A.

[0013] The die 101 of this example includes a first terminal 104, a second terminal 105, and a third terminal 106 on a connecting surface 103. The first terminal 104, the second terminal 105, and the third terminal 106 are electrically conductive and may include, for example, aluminum, copper, nickel, palladium, platinum, gold, titanium, or tungsten. The first terminal 104, the second terminal 105, and the third terminal 106 may be implemented as, for example, bump bond pads or through-substrate vias. The first terminal 104, the second terminal 105, and the third terminal 106 may be electrically coupled to components within the die 101 by vias 107 or other interconnect elements. A passivation (PO) layer 108 may be disposed on the connecting surface 103, with openings exposing the first terminal 104, the second terminal 105, and the third terminal 106. The PO layer 108 may include, for example, silicon dioxide, silicon nitride, silicon oxynitride, or polyimide. The PO layer 108 may optionally be part of the die 101.

[0014] The die 101 in this example includes a second plate 109 of an integrated capacitor 110. The second plate 109 may have a similar composition of conductive material as the first terminal 104, the second terminal 105, and the third terminal 106. The second plate 109 may be covered by a PO layer 108 as shown in FIG. 1A. The second plate 109 may be electrically coupled to components within the die 101 by one or more of the vias 107.

[0015] A first interface layer 111 is formed on the connecting surface 103 and contacts the terminals 104, 105, and 106. The first interface layer 111 is electrically conductive. The first interface layer 111 may include an adhesion sublayer (not shown in FIG. 1A ) in contact with the PO layer 108 and the terminals 104, 105, and 106. The adhesion sublayer may include, for example, titanium or tungsten to provide adhesion of the first interface layer 111 to the PO layer 108 and the terminals 104, 105, and 106. The first interface layer 111 may include a barrier sublayer (not shown in FIG. 1A ) on the adhesion sublayer. The barrier sublayer may include, for example, nickel, cobalt, tantalum, tantalum nitride, titanium, or titanium nitride to reduce copper diffusion from the first pillar 113, the second pillar 114, and the third pillar 115 into the die 101. Diffusion of copper into the die 101 can degrade the performance of the microelectronic device 100. The first interface layer 111 can include a plating seed sublayer on a barrier sublayer, not shown in FIG. 1A. The plating seed sublayer can include copper, nickel, or gold to provide a low resistance layer suitable for electroplating. The first interface layer 111 can be formed by a series of sputtering, evaporation, cold spray, or other thin film deposition processes.

[0016] A pillar mask 112 is formed on the first interface layer 111. The pillar mask 112 exposes the first interface layer 111 in areas for the first pillar 113, the second pillar 114, and the third pillar 115. The area for the first pillar 113 is located above the first terminal 104, the area for the second pillar 114 is located above the second terminal 105, and the area for the third pillar 115 is located above the third terminal 106. The pillar mask 112 may include photoresist and may be formed using a photolithography process. Alternatively, the pillar mask 112 may be formed by an additive process such as a tape application process, material jetting, or material extrusion, or a subtractive process such as laser ablation. The pillar mask 112 may have a thickness of, for example, 1 micron to 100 microns.

[0017] First pillar 113, second pillar 114, and third pillar 115 are simultaneously formed on first interface layer 111 in areas exposed by pillar mask 112 by a first plating process using first plating solution 116. First plating solution 116 may contain copper ions, such that pillars 113, 114, and 115 contain copper. First plating solution 116 may contain other metal ions, such as nickel ions or gold ions, in addition to copper ions, such that pillars 113, 114, and 115 contain nickel or gold to provide desirable mechanical properties in pillars 113, 114, and 115. The first plating process may be implemented as an electroplating process in which a current flows from first plating solution 116 to first interface layer 111, providing a more consistent plating rate. Alternatively, the first plating process may be implemented as an electroless process, reducing the manufacturing complexity of microelectronic device 100. The pillars 113, 114, and 115 may have a height, by way of example, perpendicular to the connecting surface 103, of between 1 micron and 100 microns. The pillars 113, 114, and 115 are therefore mechanically coupled to the connecting surface 103 via the first interface layer 111. The microelectronic device 100 is separated from the first plating solution 116 after the pillars 113, 114, and 115 are formed. The pillar mask 112 is left in place for subsequent manufacturing steps.

[0018] 1B , a second interface layer 117 is formed on the pillar mask 112 and contacts the pillars 113, 114, and 115. The second interface layer 117 is conductive. The second interface layer 117 may include an adhesion sublayer in contact with the pillar mask 112 and the pillars 113, 114, and 115, and may include a plating seed sublayer in contact with the adhesion sublayer. The adhesion sublayer of the second interface layer 117 may have a composition similar to that disclosed for the adhesion sublayer of the first interface layer 111. The plating seed sublayer of the second interface layer 117 may have a composition similar to that disclosed for the plating seed sublayer of the first interface layer 111.

[0019] A head mask 118 is formed on the second interface layer 117. The head mask 118 exposes the second interface layer 117 in areas for a later-formed first extended head 119 and a later-formed second extended head 120, which are shown in FIG. 1C. Referring again to FIG. 1B, the area for the first extended head 119 exposes the second interface layer 117 above the first pillars 113 and extends beyond the first pillars 113 in at least one direction parallel to the connecting surface 103. The area for the second extended head 120 exposes the second interface layer 117 over the second pillar 114 and the third pillar 115, extends beyond the second pillar 114 in at least one direction parallel to the connecting surface 103, and extends beyond the third pillar 115 in at least one direction parallel to the connecting surface 103. The head mask 118 may include a photoresist and may be formed using a photolithography process. Alternatively, the head mask 118 may be formed by an additive process such as a tape application process, material jetting, or material extrusion, or a subtractive process such as laser ablation. The head mask 118 may have a different composition than the pillar mask 112 and may be formed by a process different from the process used to form the pillar mask 112.

[0020] 1C , the first expanded head 119 and the second expanded head 120 are simultaneously formed on the second interface layer 117 in the areas exposed by the head mask 118 by a second plating process using a second plating solution 121. The second plating solution 121 may contain copper ions, so that the first expanded head 119 and the second expanded head 120 contain copper. The second plating solution 121 may contain other metal ions, such as nickel ions or gold ions, in addition to copper ions, so that the first expanded head 119 and the second expanded head 120 contain nickel or gold to provide the desired mechanical properties in the first expanded head 119 and the second expanded head 120. The second plating process may be implemented as an electroplating process in which a current flows from the second plating solution 121 to the second interface layer 117, providing a more consistent plating rate. Alternatively, the second plating process may be implemented as an electroless process, reducing the manufacturing complexity of the microelectronic device 100. The first expanded head 119 and the second expanded head 120 can have a thickness perpendicular to the connecting surface 103, for example, between 1 micron and 25 microns. The first expanded head 119 is electrically coupled to the first pillar 113 via the second interface layer 117 and extends beyond the first pillar 113 in at least one direction parallel to the connecting surface 103. The second expanded head 120 is electrically coupled to the second pillar 114 via the second interface layer 117 and extends beyond the second pillar 114 in at least one direction parallel to the connecting surface 103. After the first expanded head 119 and the second expanded head 120 are formed, the microelectronic device 100 is separated from the second plating solution 121. The second expanded head 120 is positioned on the second plate 109.

[0021] 1D , an insulating layer 123 is formed on the second expanded head 120, covering a first portion of the second expanded head 120 and exposing a second portion of the second expanded head 120. The insulating layer 123 may be implemented as a solder mask and may include, for example, an epoxy, polyester, or resin, and may be formed by, for example, a dispensing, screen printing, or photolithography process.

[0022] Referring to FIG. 1E, the head mask 118 of FIG. 1D is removed. The head mask 118 may be removed by dissolving it in an organic solvent, leaving the insulating layer 123 in place. After the head mask 118 is removed, the second interface layer 117 of FIG. 1D is removed in the locations exposed by the first expanded head 119 and the second expanded head 120. The second interface layer 117 may be removed by one or more wet etching processes using a dilute acid solution. After the second interface layer 117 is removed in the locations exposed by the first expanded head 119 and the second expanded head 120, the pillar mask 112 of FIG. 1D is removed. The pillar mask 112 may be removed by dissolving it in an organic solvent, leaving the insulating layer 123 in place. The pillar mask 112 may be removed by a process similar to the process used to remove the head mask 118. After pillar mask 112 is removed, first interface layer 111 in FIG. 1D is removed where exposed by first pillar 113, second pillar 114, and third pillar 115. First interface layer 111 may be removed by one or more wet etching processes using a dilute acid solution, which may be similar to the wet etching process used to remove second interface layer 117.

[0023] Referring to FIG. 1F , a lead frame 124 of the microelectronic device 100 is provided. The lead frame 124 includes a first lead 125, a second lead 126, and a third lead 127. The leads 125, 126, and 127 may comprise copper, stainless steel, or Kovar and may be plated with nickel, palladium, or gold, for example. The first extended head 119 provides a bump pad for the microelectronic device 100. The bump pad may be implemented, for example, as a solder bump pad or an adhesive bump pad. The first lead 125 is electrically coupled to the first extended head 119 via a first solder connection 128, and the third lead 127 is electrically coupled to the second extended head 120 via a second solder connection 129 on a second portion of the second extended head 120 exposed by the insulating layer 123. In an alternative implementation of this example, the first lead 125 may be electrically coupled to the first extended head 119 via a first portion of a conductive adhesive, such as an epoxy with copper or silver particles. In such an alternative implementation, the third lead 127 may be electrically coupled to the second extended head 120 via a second portion of the conductive adhesive. The second lead 126 is electrically isolated from the second extended head 120 by an insulating layer 123. The integrated capacitor 110 may be used to capacitively couple a signal from the third lead 127 of the lead frame 124 to the second plate 109 of the integrated capacitor 110. The integrated capacitor 110 may be advantageously formed to have a desired capacitance without consuming area on the die 101.

[0024] 1G, a package insulating structure 130 is formed on the die 101, laterally surrounding the pillars 113, 114, and 115, the first extended head 119, and the second extended head 120, and in contact with the leads 125, 126, and 127. The term "laterally" refers to a direction parallel to the connecting surface 103, as is the case with other examples disclosed herein. The package insulating structure 130 is non-conductive and may include a dielectric material such as epoxy, silicone, or benzocyclobutene (BCB), and may include dielectric particles such as silicon dioxide particles to reduce the thermal expansion coefficient of the package insulating structure 130. The second extended head 120 and a second interface layer 117 in contact with the second extended head 120 provide the first plate 122 of the integrated capacitor 110. The package insulating structure 130 of the present example extends between the first plate 122 of the integrated capacitor 110 and the second plate 109 of the integrated capacitor 110, which may advantageously provide more capacitance for the integrated capacitor 110 than a capacitor without package dielectric material between the plates of the capacitor. Figure 1G shows the completed microelectronic device 100.

[0025] 2A-2F are cross-sectional views of another example microelectronic device having an integrated capacitor, illustrating another example method of formation at various stages. Referring to FIG. 2A, microelectronic device 200 includes die 201. Die 201 may be implemented, for example, as any of the examples disclosed with respect to die 101 of FIG. 1A. Die 201 in this example has substrate 202, which may be part of a wafer or workpiece including additional dies, or may include only die 201. Die 201 has connecting surface 203, and substrate 202 may extend to connecting surface 203 as shown in FIG. 2A.

[0026] In this example, die 201 includes first terminal 204, second terminal 205, and third terminal 206 on connection surface 203. First terminal 204, second terminal 205, and third terminal 206 are electrically conductive. Terminals 204, 205, and 206 may be implemented as bump bond pads or through-substrate vias, for example. Terminals 204, 205, and 206 may be electrically coupled to components within die 201 by vias 207.

[0027] The die 201 of this example includes a second plate 209 of an integrated capacitor 210. The second plate 209 is electrically conductive. The second plate 209 may extend to the connection surface 203 as shown in FIG. 2A. The second plate 209 may be electrically coupled to components on the die 201 by one or more of the vias 207.

[0028] A pillar mask 212 is formed on the connection surface 203. The pillar mask 212 exposes the first terminal 204 in an area for the later-formed first pillar 213, the second terminal 205 in an area for the later-formed second pillar 214, and the third terminal 206 in an area for the later-formed third pillar 215. The pillar mask 212 in this example may be formed of a photosensitive epoxy using a photolithography process. Alternatively, the pillar mask 212 in this example may include inorganic particles in a binder material formed by an additive process such as material jetting or material extrusion. The pillar mask 212 may have a thickness of, for example, 1 micron to 100 microns. The first pillar 213, the second pillar 214, and the third pillar 215 are shown in FIG. 2C.

[0029] Referring to FIG. 2B , an interface layer 231 is formed on the pillar mask 212, extends into the areas for the first pillar 213, the second pillar 214, and the third pillar 215, and contacts the first terminal 204, the second terminal 205, and the third terminal 206. The interface layer 231 is conductive. The interface layer 231 may include an adhesion sublayer, not shown in FIG. 2B , that contacts the terminals 204, 205, and 206. The interface layer 231 may include a barrier sublayer on the adhesion sublayer, not shown in FIG. 2B . The interface layer 231 may include a plating seed sublayer on the barrier sublayer, not shown in FIG. 2B . The interface layer 231 may be formed by a series of thin film deposition processes.

[0030] A head mask 218 is formed on the interface layer 231. The head mask 218 exposes the interface layer 231 in areas for a later-formed first extended head 219 and a later-formed second extended head 220. The area for the first extended head 219 exposes the interface layer 231 on the first pillar 213 and extends beyond the first pillar 213 in at least one direction parallel to the connection surface 203. The area for the second extended head 220 exposes the interface layer 231 on the second pillar 214 and the third pillar 215 and extends beyond the second pillar 214 in at least one direction parallel to the contact surface 203 and extends beyond the third pillar 215 in at least one direction parallel to the contact surface 203. The head mask 218 may include photoresist and may be formed using a photolithography process. Alternatively, the head mask 218 can be formed by an additive process such as a taping process, material jetting or material extrusion, or a subtractive process such as laser ablation. A first expanded head 219 and a second expanded head 220 are shown in Figure 2C.

[0031] 2C , first pillar 213, second pillar 214, and third pillar 215 are simultaneously formed on interface layer 231 in areas exposed by pillar mask 212 by a plating process using plating solution 232. The plating process continues to simultaneously form first extended heads 219 on first pillar 213 and second extended heads 220 on second pillar 214 and third pillar 215 in areas exposed by head mask 218. Second extended head 220 is located on second plate 209. Plating solution 232 may contain copper ions, nickel ions, or gold ions, so pillars 213, 214, and 215 and first extended head 219 and second extended head 220 may contain copper, nickel, or gold. The plating process may be implemented as an electroplating process or an electroless process. Pillars 213, 214, and 215 may have a height perpendicular to connecting surface 203 of, for example, 1 micron to 100 microns. First extended head 219 and second extended head 220 may have a thickness perpendicular to connecting surface 203 of, for example, 1 micron to 25 microns. Pillars 213, 214, and 215 are therefore mechanically coupled to connecting surface 203 via interface layer 231. First extended head 219 is electrically coupled directly to first pillar 213 and extends beyond first pillar 213 in at least one direction parallel to connecting surface 203. Second extended head 220 is electrically coupled directly to second pillar 214 and extends beyond second pillar 214 in at least one direction parallel to connecting surface 203. The microelectronic device 200 is separated from the plating solution 232 after the pillars 213, 214, and 215 and the first and second extended heads 219 and 220 are formed.

[0032] 2D, an insulating layer 223 is formed on the second expanded head 220. The insulating layer 223 may be implemented as a solder mask and may include, for example, epoxy, polyester, or resin, and may be formed by dispensing, screen printing, or a photolithography process. In this example, the insulating layer 223 covers the second expanded head 220 exposed by the head mask 218.

[0033] Referring to FIG. 2E, the head mask 218 of FIG. 2D is removed. The head mask 218 can be removed by dissolving it in an organic solvent, leaving the insulating layer 223 and pillar mask 212 in place. After the head mask 218 is removed, the second interface layer 231 of FIG. 2D is removed in the areas exposed by the first expanded head 219 and the second expanded head 220, leaving the insulating layer 223 and pillar mask 212 in place. The interface layer 231 can be removed by one or more wet etching processes using a dilute acid solution. The pillar mask 212 in this example provides permanent support for the pillars 213, 214, and 215, as well as the first expanded head 219 and the second expanded head 220.

[0034] 2F, the first extended head 219 provides the bump pads of the microelectronic device 200. The bump pads may be implemented as solder bump pads or adhesive bump pads, for example. Solder bumps 233 are formed on the first extended head 219. The solder bumps 233 may be formed by dispensing solder paste onto the first extended head 219 and then heating the solder paste in a reflow process to provide a low resistance interface between the solder bumps 233 and the first extended head 219.

[0035] The second extended head 220 and the interface layer 231 in contact with the second extended head 220 provide the first plate 222 of the integrated capacitor 210. The pillar mask 212 of this example extends between the first plate 222 of the integrated capacitor 210 and the second plate 209 of the integrated capacitor 210, which may advantageously provide more capacitance for the integrated capacitor 210 compared to a capacitor without a package dielectric material between the plates of the capacitor. Figure 2F shows the completed microelectronic device 200.

[0036] 3A-3J are cross-sectional views of a further example microelectronic device having an integrated capacitor, illustrating a further example method of formation at various stages. Referring to FIG. 3A, microelectronic device 300 includes die 301. Die 301 may be implemented, for example, as any of the examples disclosed with respect to die 101 of FIG. 1A. Die 301 in this example has substrate 302, which may be part of a wafer or workpiece including additional dies, or may include only die 301. Die 301 has connecting surface 303, and substrate 302 may extend to connecting surface 303 as shown in FIG. 3A.

[0037] In this example, die 301 includes first terminal 304 and second terminal 334 on connection surface 303. First terminal 304 and third terminal 334 are electrically conductive. Terminals 304 and 334 may be implemented as bump bond pads or through-substrate vias, for example. Terminals 304 and 334 may be electrically coupled to components within die 301 by vias 307.

[0038] A first interface layer 311 is formed on connection surface 303 and contacts terminals 304 and 334. First interface layer 311 may have a composition and sublayer structure similar to first interface layer 111 of FIG. 1A. A capacitor mask 335 is formed on first interface layer 311, exposing first interface layer 311 in the area for second plate 309 of integrated capacitor 310. Capacitor mask 335 may include a photoresist formed by a photolithography process, or may include a polymer formed by screen printing or an additive process.

[0039] Referring to FIG. 3B, the second plate 309 of the integrated capacitor 310 is formed on the first interface layer 311 in a location exposed by the capacitor mask 335. The second plate 309 is formed by a first plating process using a first plating solution 336. The first plating solution 336 may contain copper ions, nickel ions, or gold ions, so that the second plate 309 may contain copper, nickel, or gold. The first plating process may be implemented as an electroplating process or an electroless process. The second plate 309 may have a thickness of, for example, 1 micron to 100 microns. The microelectronic device 300 is separated from the plating solution 336 after the second plate 309 is formed.

[0040] 3C, the capacitor mask 335 of FIG. 3B is removed, leaving the first interface layer 311 and second plate 309 in place. The capacitor mask 335 can be removed, for example, by dissolving it in an organic solvent or organic acid. Other methods for removing the capacitor mask 335 are within the scope of this example.

[0041] Referring to FIG. 3D , a pillar mask 312 is formed on the first interface layer 311 and covers the second plate 309. The pillar mask 312 exposes the first interface layer 311 in areas for the first pillars 313, second pillars 314, and third pillars 315. The area for the first pillars 313 is located above the first terminal 304, the area for the second pillars 314 is located on one side of the second plate 309, and the area for the third pillars 315 is located on another side of the second plate 309. The pillar mask 312 may include photoresist and may be formed using a photolithography process. Alternatively, the pillar mask 312 may be formed by a tape application process, an additive process, or a subtractive process. The pillar mask 312 may have a thickness, for example, 1 micron to 50 microns greater than the thickness of the second plate 309.

[0042] Referring to FIG. 3E, first pillar 313, second pillar 314, and third pillar 315 are simultaneously formed on first interface layer 311 in the areas exposed by pillar mask 312 by a second plating process using second plating solution 316. Second plating solution 316 may contain copper ions, nickel ions, or gold ions, resulting in pillars 313, 314, and 315 containing copper, nickel, or gold. The second plating process may be implemented as an electroplating process or an electroless process. Pillars 313, 314, and 315 may have a height perpendicular to connecting surface 303 that is, for example, 1 micron to 50 microns greater than the thickness of second plate 309. Thus, pillars 313, 314, and 315 are mechanically coupled to connecting surface 303 via first interface layer 311. Microelectronic device 300 is separated from second plating solution 316 after pillars 313, 314, and 315 are formed, leaving pillar mask 312 in place for subsequent fabrication steps.

[0043] 3F , a second interface layer 317 is formed on the pillar mask 312 in contact with the pillars 313, 314, and 315. The second interface layer 317 is conductive. The second interface layer 317 may include an adhesion sublayer in contact with the pillar mask 312 and the pillars 313, 314, and 315, and may include a plating seed sublayer in contact with the adhesion sublayer. The adhesion sublayer of the second interface layer 317 may have a composition similar to the composition disclosed for the adhesion sublayer of the first interface layer 311. The plating seed sublayer of the second interface layer 317 may have a composition similar to the composition disclosed for the plating seed sublayer of the first interface layer 311.

[0044] A head mask 318 is formed on the second interface layer 317. The head mask 318 exposes the second interface layer 317 in areas for a later-formed first extended head 319 and a later-formed second extended head 320, which are shown in FIG. 3G. Referring again to FIG. 3F, the area for the first extended head 319 exposes the second interface layer 317 over the first pillar 313 and extends beyond the first pillar 313 in at least one direction parallel to the connection surface 303. The area for the second extended head 320 exposes the second interface layer 317 over the second pillar 314 and the third pillar 315 and extends beyond the second pillar 314 in at least one direction parallel to the contact surface 303 and extends beyond the third pillar 315 in at least one direction parallel to the contact surface 303. The head mask 318 may include photoresist and may be formed using a photolithography process. Alternatively, the head mask 318 may be formed by a taping process, an additive process, or a subtractive process. The head mask 318 may have a different composition than the pillar mask 312 or may be formed by a process different from the process used to form the pillar mask 312.

[0045] Referring to FIG. 3G , the first and second extended heads 319 and 320 are simultaneously formed on the second interface layer 317 in the areas exposed by the head mask 318 by a third plating process using a third plating solution 321. The third plating solution 321 may contain copper ions, nickel ions, or gold ions, so that the first and second extended heads 319 and 320 contain copper, nickel, or gold. The third plating process may be implemented as an electroplating process or an electroless process. The first and second extended heads 319 and 320 may have a thickness perpendicular to the connecting surface 303, for example, between 1 micron and 25 microns. The first extended head 319 is electrically coupled to the first pillar 313 via the second interface layer 317 and extends beyond the first pillar 313 in at least one direction parallel to the connecting surface 303. The second extended head 320 is electrically coupled to the second pillar 314 via the second interface layer 317 and extends beyond the second pillar 314 in at least one direction parallel to the connecting surface 303. The microelectronic device 300 is separated from the third plating solution 321 after the first extended head 319 and the second extended head 320 are formed. The second extended head 320 is located on the second plate 309.

[0046] Referring to FIG. 3H, the head mask 318 of FIG. 3G is removed. The head mask 318 may be removed by dissolving it in an organic solvent or organic acid, leaving the first extended head 319 and the second extended head 320 in place. After the head mask 318 is removed, the second interface layer 317 of FIG. 3G is removed in the locations exposed by the first extended head 319 and the second extended head 320. The second interface layer 317 may be removed by one or more wet etching processes using a dilute acid solution. After the second interface layer 317 is removed in the locations exposed by the first extended head 319 and the second extended head 320, the pillar mask 312 of FIG. 3G is removed. The pillar mask 312 may be removed by dissolving it in an organic solvent or organic acid, leaving the first pillar 313, the second pillar 314, the third pillar 315, the first extended head 319, and the second extended head 320 in place. The pillar mask 312 may be removed by a process similar to that used to remove the head mask 318. After the pillar mask 312 is removed, the pillars 313, 314, and 315, as well as the first interface layer 311 of FIG. 3G in the locations exposed by the second plate 309, are removed. The first interface layer 311 may be removed by one or more wet etching processes using a dilute acid solution, which may be similar to the wet etching process used to remove the second interface layer 317. As a result of removing the first interface layer 311, the second interface layer 317 can be removed below the first extended head 319 and the second extended head 320 in the locations exposed by the pillars 313, 314, and 315, as shown in FIG. 3H.

[0047] Referring to FIG. 3I, a package insulating structure 330 is formed on the die 301, laterally surrounding the pillars 313, 314, and 315 and contacting the first extended head 319 and the second extended head 320. The package insulating structure 330 is non-conductive. The second extended head 320 provides the first plate 322 of the integrated capacitor 310. The package insulating structure 330 of this example extends between the first plate 322 of the integrated capacitor 310 and the second plate 309 of the integrated capacitor 310 and may advantageously provide more capacitance for the integrated capacitor 310 compared to a capacitor without package dielectric material between the capacitor plates. The package insulating structure 330 may be formed, for example, by injection molding or reaction injection molding. The third pillar 315 may advantageously provide mechanical support for the second extended head 320 while the package insulating structure 330 is being formed.

[0048] Referring to FIG. 3J, the first extended head 319 provides bump pads for the microelectronic device 300. The bump pads may be implemented as solder bump pads or adhesive bump pads, for example. A first solder bump 333 is formed on the first extended head 319, and a second solder bump 337 is formed on the second extended head 320. The first solder bump 333 and the second solder bump 337 may be formed by dispensing solder paste on the first extended head 319 and the second extended head 320, and then heating the solder paste in a reflow process. FIG. 3J shows the completed microelectronic device 300. In this example, the first plate 322 of the integrated capacitor 310 may be electrically coupled to a printed circuit board or chip carrier (not shown in FIG. 3J) via the second solder bump 337. The first plate is electrically coupled to one or more components in the die 301 via the first interface layer 311 and the second terminal 334 .

[0049] 4A-4G are cross-sectional views of another example microelectronic device having an integrated capacitor, shown at various stages of another example method of formation. Referring to FIG. 4A, microelectronic device 400 includes die 401. Die 401 may be implemented as any of the examples disclosed with respect to die 101 of FIG. 1A, for example. Die 401 of this example may have a substrate 402, which may be part of a wafer or workpiece containing additional dies, or may include only die 401. Die 401 has a connection surface 403, and substrate 402 may extend to connection surface 403, as shown in FIG. 4A. Die 401 of this example includes first terminal 404, second terminal 405, and third terminal 434 at connection surface 403. Terminals 404, 405, and 434 are electrically conductive and may be implemented as bump bond pads or through-substrate vias, for example. Terminals 404 , 405 , and 434 may be electrically coupled to components on die 401 by vias 407 .

[0050] A first interface layer 411 is formed on connecting surface 403 and contacts terminals 404, 405, and 434. First interface layer 411 may have a composition and sublayer structure similar to first interface layer 111 of FIG. 1A.

[0051] A pillar mask 412 is formed on the first interface layer 411. The pillar mask 412 exposes the first interface layer 411 in areas for the first pillar 413, the second pillar 414, and the second plate 409 of the integrated capacitor 410. The area for the first pillar 413 is located above the first terminal 404, the area for the second pillar 414 is located above the second terminal 405, and the area for the second plate 409 is located above the third terminal 434. The pillar mask 412 may include photoresist and may be formed using a photolithography process, or may be formed by a tape application process, an additive process, or a subtractive process. The pillar mask 412 may have a thickness of, for example, 1 micron to 100 microns.

[0052] Referring to FIG. 4B , first pillars 413, second pillars 414, and second plate 409 are simultaneously formed on first interface layer 411 in the areas exposed by pillar mask 412 by a first plating process using first plating solution 416. First plating solution 416 may contain copper ions, nickel ions, or gold ions, resulting in pillars 413 and 414 and second plate 409 containing copper, nickel, or gold. The first plating process may be implemented as an electroplating process or an electroless process. Pillars 413 and 414 and second plate 409 may have heights perpendicular to connecting surface 403 of, for example, 1 micron to 100 microns. Thus, pillars 413 and 414 are mechanically coupled to connecting surface 403 via first interface layer 411. The microelectronic device 400 is separated from the first plating solution 416 after the pillars 413 and 414 and the second plate 409 are formed. The pillar mask 412 is left in place for subsequent fabrication steps.

[0053] Referring to FIG. 4C, a capacitor dielectric layer 438 is formed on the second plate 409. The capacitor dielectric layer 438 may include an organic polymer such as an epoxy or polyimide, a silicone polymer, or an inorganic material such as silicon dioxide particles in a binder material. The capacitor dielectric layer 438 may be formed by a photolithography process, a screen printing process, or an additive process. The capacitor dielectric layer 438 may have a thickness of, for example, 100 nanometers to 10 microns.

[0054] 4D , a second interface layer 417 is formed over the pillar mask 412, contacts the pillars 413 and 414, and extends over the capacitor dielectric layer 438. The second interface layer 417 is conductive. The second interface layer 417 may include an adhesion sublayer in contact with the pillar mask 412, the pillars 413 and 414, and the capacitor dielectric layer 438, and may include a plating seed sublayer in contact with the adhesion sublayer. The adhesion sublayer of the second interface layer 417 may have a composition similar to the composition disclosed for the adhesion sublayer of the first interface layer 411. The plating seed sublayer of the second interface layer 417 may have a composition similar to the composition disclosed for the plating seed sublayer of the first interface layer 411.

[0055] Referring to FIG. 4E, a head mask 418 is formed on the second interface layer 417. The head mask 418 exposes the second interface layer 417 in areas for a later-formed first extended head 419 and a later-formed second extended head 420, the first extended head 419 and the second extended head 420 being shown in FIG. 4F. Referring again to FIG. 4E, the area for the first extended head 419 exposes the second interface layer 417 on the first pillar 413 and extends beyond the first pillar 413 in at least one direction parallel to the connection surface 403. The area for the second extended head 420 exposes the second interface layer 417 on the second pillar 414 and the capacitor dielectric layer 438 and extends beyond the second pillar 414 in at least one direction parallel to the connection surface 403. The head mask 418 may include photoresist and may be formed using a photolithography process. Alternatively, the head mask 418 may be formed by a taping process, an additive process, or a subtractive process. The head mask 418 may have a different composition than the pillar mask 412 or may be formed by a different process than the process used to form the pillar mask 412.

[0056] Referring to FIG. 4F , the first and second extended heads 419 and 420 are simultaneously formed on the second interface layer 417 in the areas exposed by the head mask 418 by a second plating process using a second plating solution 421. The second plating solution 421 may contain copper ions, nickel ions, or gold ions, so that the first and second extended heads 419 and 420 contain copper, nickel, or gold. The second plating process may be implemented as an electroplating process or an electroless process. The first and second extended heads 419 and 420 may have a thickness perpendicular to the connecting surface 403, for example, between 1 micron and 25 microns. The first extended head 419 is electrically coupled to the first pillar 413 through the second interface layer 417 and extends beyond the first pillar 413 in at least one direction parallel to the connecting surface 403. The second extended head 420 is electrically coupled to the second pillar 414 via the second interface layer 417 and extends beyond the second pillar 414 in at least one direction parallel to the connecting surface 403. The microelectronic device 400 is separated from the second plating solution 421 after the first extended head 419 and the second extended head 420 are formed. The second extended head 420 is located on the second plate 409.

[0057] Referring to Figure 4G, the head mask 418 of Figure 4F is removed, leaving the first extended head 419 and the second extended head 420 in place. The second interface layer 417 of Figure 4F is removed where exposed by the first extended head 419 and the second extended head 420. The pillar mask 412 of Figure 4F is removed, leaving the first pillar 413, the second pillar 414, the second plate 409, the first extended head 419, and the second extended head 420 in place. The first interface layer 411 of Figure 4F is removed where exposed by the pillars 413 and 414 and the second plate 409. The head mask 418, the second interface layer 417, the pillar mask 412, and the first interface layer 411 can be removed by processes disclosed for removing the corresponding masks and interface layers of other examples herein.

[0058] An insulating layer 423 may optionally be formed on the second extended head 420. The insulating layer 423 may be implemented as a solder mask and may include, for example, epoxy, polyester, or resin, and may be formed by, for example, a dispensing, screen printing, or photolithography process. The insulating layer 423 may optionally be formed before removing the head mask 418. The first extended head 419 provides bump pads for the microelectronic device 400. The bump pads may be implemented as, for example, solder bump pads or adhesive bump pads. First solder bumps 433 are formed on the first extended head 419. The first solder bumps 433 may be formed by a process similar to the process disclosed with respect to the solder bumps 233 of FIG. 2F.

[0059] 4G shows the completed microelectronic device 400. The second extended head 420 and the second interface layer in contact with the second extended head 420 provide a first plate 422 of the integrated capacitor 410. The first plate is electrically coupled to one or more components on the die 401 via the first interface layer 411 and the second terminal 414. The capacitor dielectric layer 438 separates the first plate 422 and the second plate 409 and may advantageously provide a high capacitance value for the integrated capacitor 410 of this example.

[0060] 5A-5C are cross-sectional views of a further example microelectronic device having an integrated capacitor, illustrating a further example method of formation at various stages. Referring to FIG. 5A, microelectronic device 500 includes die 501. Die 501 may be implemented, for example, as any of the examples disclosed with respect to die 101 of FIG. 1A. Die 501 in this example includes substrate 502, which may be part of a wafer or workpiece including additional dies, or may include only die 501. Die 501 has connection surface 503, and substrate 502 may extend to connection surface 503 as shown in FIG. 5A. Die 501 in this example includes first terminal 504, second terminal 505, and third terminal 506 at connection surface 503. Terminals 504, 505, and 506 are electrically conductive and may be implemented, for example, as bump bond pads or through-substrate vias. Terminals 504 , 505 , and 506 may be electrically coupled to components on die 501 .

[0061] A first pillar 513, a second pillar 514, and a third pillar 515 are simultaneously formed on the first terminal 504, the second terminal 505, and the third terminal 506, respectively. Thus, the pillars 513, 514, and 515 are mechanically coupled to the connection surface 503. The pillars 513, 514, and 515 are electrically conductive. A first extended head 519 and a second extended head 520 are simultaneously formed on the pillars 513, 514, and 515. The first extended head 519 abuts the first pillar 513 and extends beyond the first pillar 513 in at least one direction parallel to the connection surface 503. The second extended head 520 abuts the second pillar 514 and the third pillar 515 and extends beyond the second pillar 514 in at least one direction parallel to the connecting surface 503 and extends beyond the third pillar 515 in at least one direction parallel to the connecting surface 503. The pillars 513, 514, and 515, the first extended head 519, and the second extended head 520 may be formed by any of the methods disclosed in the examples herein. Alternatively, the pillars 513, 514, and 515, the first extended head 519, and the second extended head 520 may be formed by an additive process such as three-dimensional (3D) metal printing. If pillars 513, 514, and 515 are formed by an additive process, pillars 513, 514, and 515 are formed in parallel, i.e., in the same operation, or simultaneously, because pillars 513, 514, and 515 are formed by the same additive process. The term "simultaneously" includes the case where some or all of first pillar 513 is formed before some or all of second pillar 514 is formed, as may occur when using an additive process with a limited number of print heads or material dispensing nozzles, similarly for first expanded head 519 and second expanded head 520. Other methods for simultaneously forming pillars 513, 514, and 515, and for simultaneously forming first expanded head 519 and second expanded head 520, are also within the scope of this example.

[0062] A capacitor dielectric layer 538 is formed on the second expanded head 520 on a surface of the second expanded head 520 opposite the connection surface 503. The capacitor dielectric layer 538 may have a composition disclosed for the capacitor dielectric layer 438 of FIG. 4C and may be formed by the disclosed methods.

[0063] Referring to FIG. 5B, a lead frame 524 for a microelectronic device 500 is provided. The lead frame 524 includes a first lead 525 and a second lead 526. The leads 525 and 526 may include any of the materials disclosed for the lead frame 124 of FIG. 1F. A first extended head 519 provides a bump pad for the microelectronic device 500. The bump pad may be implemented as a solder bump pad or an adhesive bump pad, for example. The first lead 525 is electrically coupled to the first extended head 519 via a solder connection 528. The second lead 526 is located on the second extended head 520 and is electrically insulated from the second extended head 520 by a capacitor dielectric layer 538.

[0064] 5C, a package insulating structure 530 is formed on die 501, laterally surrounding pillars 513, 514, and 515, first extended head 519, and second extended head 520, and contacting leads 525 and 526. Package insulating structure 530 is non-conductive and may include any of the materials disclosed for package insulating structure 130 of FIG. 1G.

[0065] A second extension head 520 provides a first plate 522 of the integrated capacitor 510. A second lead 526 provides a second plate 509 of the integrated capacitor 510, facing one side of the first plate 522 opposite the connection surface 503. A capacitor dielectric layer 538 separating the first plate 522 from the second plate 509 advantageously provides a high capacitance value for the integrated capacitor 510 of this example. The package insulating structure 530 of this example may optionally extend between the first plate 522 and the second plate 509, as shown in FIG. 5C . FIG. 5C shows the completed microelectronic device 500.

[0066] Various features of the examples disclosed herein may be combined in other manifestations of microelectronic devices. For example, the first pillar and second pillar of any microelectronic device may be simultaneously formed as disclosed according to the methods disclosed with respect to FIGS. 1A-1G, 2A-2F, 3A-3J, or 4A-4G. Similarly, the first extended head and second extended head of any microelectronic device may be simultaneously formed as disclosed according to the methods disclosed with respect to FIGS. 1A-1G, 2A-2F, 3A-3J, or 4A-4G. Any of the integrated capacitors may have a capacitor dielectric layer as shown in FIG. 4C or 5C. The second extended head of any microelectronic device may be electrically coupled to an external terminal as shown in FIG. 1G or 3J.

[0067] While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only, and not limitation. Many modifications to the disclosed embodiments may be made in accordance with the disclosure herein without departing from the spirit or scope of the present disclosure. Thus, the breadth and scope of the present invention should not be limited by any of the above-described embodiments. Rather, the scope of the present disclosure is defined according to the following claims and their equivalents.

Claims

1. 1. A microelectronic device comprising: a die having a connecting surface; a conductive first pillar mechanically coupled to the connection surface; a second pillar that is electrically conductive and mechanically coupled to the connection surface, the first pillar and the second pillar having an electrically conductive material of equal composition; a first extension head electrically coupled to the first pillar, the first extension head being electrically conductive and extending beyond the first pillar in a direction parallel to the connecting surface; a second extension head electrically coupled to the second pillar, the second extension head being electrically conductive and extending beyond the second pillar in a direction parallel to the connecting surface; the first and second expansion heads have conductive materials of equal composition; the first extension head providing a solder bump pad; a second extension head, the second extension head providing at least a portion of a first plate of an integrated capacitor of the microelectronic device; a second plate of the integrated capacitor; , a microelectronic device,

2. 10. The microelectronic device of claim 1, The microelectronic device wherein the second plate is located within the die below the first plate.

3. 10. The microelectronic device of claim 1, The second plate is located between the connecting surface and the first plate.

4. 4. The microelectronic device of claim 3, The microelectronic device, wherein the second plate and the first pillar have an electrically conductive material of equal composition.

5. 10. The microelectronic device of claim 1, The microelectronic device, wherein the second plate is positioned above the first plate and faces a side of the first plate opposite the connecting surface.

6. 10. The microelectronic device of claim 1, The microelectronic device further includes a lead frame, the leads of the lead frame providing the second plate.

7. 10. The microelectronic device of claim 1, 10. The microelectronic device of claim 1, further comprising a package insulation structure between the first plate and the second plate, the package insulation structure being non-conductive and laterally surrounding the first pillar and the second pillar.

8. 10. The microelectronic device of claim 1, The microelectronic device further comprising a lead frame, the first plate being electrically coupled to leads of the lead frame via a conductive material.

9. 10. The microelectronic device of claim 1, The microelectronic device further includes an insulating layer on a surface of the first plate opposite the connecting surface, the insulating layer being non-conductive.

10. 10. The microelectronic device of claim 1, the first pillar is electrically coupled to a second terminal of the die, the second terminal being located on the connecting surface, and the second terminal being electrically conductive.

11. 1. A method of forming a microelectronic device, comprising: providing a die having a connecting surface; simultaneously forming a first pillar and a second pillar on the connecting surface, wherein the first pillar and the second pillar are electrically conductive and the first pillar and the second pillar are mechanically coupled to the connecting surface; simultaneously forming a first extended head and a second extended head, the first extended head being electrically coupled to the first pillar and the second extended head being electrically coupled to the second pillar; the first expansion head and the second expansion head are electrically conductive; the first extension head extends beyond the first pillar in a direction parallel to the connecting surface of the die; the second extension head extends beyond the second pillar in a direction parallel to the connecting surface of the die; the first expansion head provides a bump pad; simultaneously forming the first and second extended heads, the second extended head providing at least a portion of a first plate of an integrated capacitor; A method comprising:

12. 12. The method of claim 11, The method wherein a second plate of the integrated capacitor is located within the die.

13. 12. The method of claim 11, The method further includes forming a second plate of the integrated capacitor on the connection surface before forming the second extended head.

14. 14. The method of claim 13, The method, wherein the second plate is formed simultaneously with the first pillar and the second pillar.

15. 12. The method of claim 11, forming a second plate of the integrated capacitor; forming a dielectric layer on the second plate before forming the second enlarged head; The method further comprises:

16. 12. The method of claim 11, The method further comprising electrically coupling the bump pad to a lead frame of the microelectronic device, the lead frame providing a second plate of the integrated capacitor.

17. 12. The method of claim 11, forming a second plate of the integrated capacitor; forming a non-conductive package insulating structure over the die; Further comprising: The method, wherein the package insulating structure laterally surrounds the first pillar and the second pillar and extends between the first plate and the second plate.

18. 12. The method of claim 11, The method further comprising forming an insulating layer on a surface of the first plate opposite the connecting surface, the insulating layer being non-conductive.

19. 12. The method of claim 11, The method, wherein the first pillar and the second pillar are formed by a plating process.

20. 12. The method of claim 11, The method, wherein the first enlarged head and the second enlarged head are formed by a plating process.

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