Real-time simulator and real-time simulation method

Abstract

To provide a real-time simulator and a real-time simulation method capable of improving simulation accuracy.SOLUTION: A real-time simulator 1 includes: an inverter simulator part 11; a gate signal ON ratio calculation model 111M that calculates a first ratio value RV1 with respect to a fixed time of a time when a gate signal Sguu becomes a signal level for turning on a transistor Qu; a gate signal ON ratio calculation model 112M that calculates a second ratio value RV2 with respect to the fixed time of the time when a gate signal Sglu becomes a signal level for turning on a transistor Ql; and a dead time ratio compensation model 113M that compensates a dead time ratio value DV with respect to a certain period of the time, which is the signal level for providing a dead time Td, to a first ratio value RV1 or a second ratio value RV2.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a real-time simulator and a real-time simulation method. [Background technology]

[0002] Patent Document 1 discloses the following technology: "When calculating the state of an object model that is defined by an equation in which the state of a pulse signal read in every cycle Ts is an input variable and that simulates the behavior of a predetermined object, the average amplitude value of the pulse signal for the period from the previous time the pulse signal was read to the current time it is read is calculated based on the time T1 from the previous time the pulse signal was read to the time the state of the pulse signal changed and the state of the pulse signal after the change, and this average amplitude value is used as the amplitude of the pulse signal at the current time it is read." [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-149035 Summary of the Invention [Problem to be solved by the invention]

[0004] In a circuit in which multiple semiconductor elements are connected in series to a power supply, a dead time is provided to keep all of the semiconductor elements in an off state so that they are not simultaneously turned on. However, in conventional techniques, the dead time is not taken into account in the average amplitude of the pulse signal. As a result, the conventional techniques have the problem of making it difficult to achieve sufficient simulation accuracy.

[0005] An object of the present invention is to provide a real-time simulator and a real-time simulation method that can improve the accuracy of simulation. [Means for solving the problem]

[0006] In order to achieve the above object, a real-time simulator according to one embodiment of the present invention includes: a power conversion device simulator unit that simulates the operation of a power conversion device that converts DC voltage to AC voltage; a first control signal on-proportion calculation model that calculates a first percentage value that is the percentage of a certain time during which a first control pulse signal that controls the on-off operation of a first transistor of two transistors connected in series and that is provided in the power conversion device, is at a signal level for turning the first transistor on; a second control signal on-proportion calculation model that calculates a second percentage value that is the percentage of the certain time during which a second control pulse signal that controls the on-off operation of a second transistor of the two transistors is at a signal level for turning the second transistor on; and a dead time percentage compensation model that compensates the first percentage value or the second percentage value for a dead time percentage value that is the percentage of the certain time during which the first control pulse signal and the second control pulse signal are at signal levels for providing a dead time during which both the first transistor and the second transistor are in an off state.

[0007] In addition, in order to achieve the above-mentioned object, a real-time simulation method according to one embodiment of the present invention is provided in a power conversion device that converts DC voltage to AC voltage, and calculates a first percentage value which is the percentage of a certain period of time during which a first control pulse signal which controls the on / off operation of a first transistor of two transistors connected in series, is at a signal level for turning the first transistor on; calculates a second percentage value which is the percentage of the certain period of time during which a second control pulse signal which controls the on / off operation of a second transistor of the two transistors is at a signal level for turning the second transistor on; and compensates the first percentage value or the second percentage value with a dead time percentage value which is the percentage of the certain period of time during which the first control pulse signal and the second control pulse signal are at signal levels for providing a dead time during which both the first transistor and the second transistor are in an off state. [Effects of the Invention]

[0008] According to each aspect of the present invention, it is possible to improve the accuracy of simulation. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram showing an example of a schematic configuration of a simulation system to which a real-time simulator according to an embodiment of the present invention is applied; [Figure 2] 1 is a circuit block diagram showing an example of a motor drive system to be simulated by a real-time simulator according to an embodiment of the present invention. FIG. [Figure 3] FIG. 1 is a timing chart (part 1) illustrating an example of gate signal waveforms and gate signal on rates, illustrating a conventional real-time simulator that simulates the operation of a three-phase inverter unit. [Figure 4] FIG. 10 is a timing chart (part 2) illustrating an example of a gate signal waveform and an on-rate of the gate signal, illustrating a conventional real-time simulator that simulates the operation of a three-phase inverter unit. [Figure 5] FIG. 10 is a timing chart illustrating an example of a gate signal waveform and an on-rate of the gate signal under a positive current condition, for explaining a conventional real-time simulator that simulates the operation of a three-phase inverter unit. [Figure 6] 10 is a timing chart illustrating an example of a gate signal waveform and a gate signal on rate under a negative current polarity condition, illustrating a conventional real-time simulator that simulates the operation of a three-phase inverter unit. FIG. [Figure 7] 10A and 10B are timing charts illustrating an example of a gate signal waveform and an on-rate of the gate signal under a positive current polarity condition, illustrating a real-time simulation method according to an embodiment of the present invention. [Figure 8]10 is a timing chart illustrating an example of a gate signal waveform and an on-rate of the gate signal under a negative current polarity condition, illustrating a real-time simulation method according to an embodiment of the present invention. FIG. [Figure 9] 1 is a block diagram showing an example of a schematic configuration of a real-time simulator according to an embodiment of the present invention; [Figure 10] FIG. 2 is a diagram showing an example of an output current waveform obtained by simulating the operation of a three-phase inverter using a real-time simulator according to an embodiment of the present invention. [Figure 11] FIG. 10 is a diagram showing the effective value of the output current obtained by simulating the operation of a three-phase inverter using a real-time simulator according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] The embodiments of the present invention are merely examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components to be described below. The technical idea of ​​the present invention can be modified in various ways within the technical scope defined by the claims.

[0011] A real-time simulator and a real-time simulation method according to an embodiment of the present invention will be described with reference to FIGS.

[0012] 1. Outline of the real-time simulator simulation system: A simulation system to which a real-time simulator and a real-time simulation method according to this embodiment are applied will be described with reference to Figures 1 and 2. Figure 1 is a diagram showing an example of the schematic configuration of a simulation system SS to which a real-time simulator 1 according to this embodiment is applied. Figure 2 is a circuit block diagram showing an example of a motor drive system MS to be simulated by the real-time simulator 1.

[0013] In this embodiment, a Hardware-In-the-Loop Simulation (HILS) is used as the simulation system SS. HILS is capable of simulating the actual machine by executing mathematical expressions that simulate the behavior of the motor and vehicle in real time.

[0014] As shown in FIG. 1, the simulation system SS in this embodiment includes a real-time simulator 1 in this embodiment, a control unit 2R that controls the real-time simulator 1, and a monitor 3R for observing the operation results of the real-time simulator 1.

[0015] The simulation system SS in this embodiment operates in cooperation with a control unit 2R, which is composed of, for example, an electronic control unit (ECU) and a real-time simulator 1. The real-time simulator 1 uses a program (plant model) to calculate the operating state of a virtual control target that serves as a substitute for the actual controlled device. The simulation system SS observes the calculation results of the real-time simulator 1 on a monitor 3R.

[0016] As will be described in detail later, the real-time simulator 1 simulates the operation of the three-phase inverter unit. To this end, gate signals for controlling the multiple transistors provided in the three-phase inverter unit are input from the control unit 2R to the real-time simulator 1. Furthermore, the real-time simulator 1 outputs, as the result of simulating the operation of the three-phase inverter unit, for example, three-phase AC output current as each detected value to the control unit 2R. The real-time simulator 1 also outputs the results of simulating the operation of the three-phase inverter unit, such as three-phase AC output current and three-phase AC output voltage, as internal signal values ​​to the monitor 3R. Furthermore, the real-time simulator 1 receives input from the monitor 3R of various setting values, such as the timing of reading data for calculations of the three-phase inverter unit and the timing of observing gate signals.

[0017] As shown in Figure 2, the motor drive system MS corresponding to the simulation system SS includes a power conversion system 1R whose operation is simulated by a real-time simulator 1 according to this embodiment (not shown in Figure 2, see Figure 1), a control unit 2R that controls the power conversion system 1R, and a monitor 3R that observes the operating state of the power conversion system 1R.

[0018] The power conversion system 1R includes a three-phase inverter unit 11R, a DC power supply 12R that supplies a DC voltage to the three-phase inverter unit 11R, and a capacitor 16R that is connected in parallel to the DC power supply 12R and stabilizes the voltage output from the DC power supply 12R. The power conversion system 1R also includes a voltage detection unit 17R that detects the DC voltage output from the DC power supply 12R to the three-phase inverter unit 11R, i.e., the DC voltage applied to the capacitor 16R. The power conversion system 1R also includes a motor 15R that is driven by the three-phase inverter unit 11R, and current detection units 13Ru, 13Rv, and 13Rw that detect the current flowing through the motor 15R.

[0019] The three-phase inverter unit 11R has semiconductor element units Suu and Slu, semiconductor element units Suv and Slv, and semiconductor element units Suw and Slw, which are connected in series between the positive and negative terminals of the DC power supply 12R. The semiconductor element units Suu and Slu, semiconductor element units Suv and Slv, and semiconductor element units Suw and Slw are connected in parallel with each other between the positive and negative terminals of the DC power supply 12R.

[0020] The semiconductor element units Suu and Slu, for example, form a U-phase arm and generate a U-phase AC voltage. The semiconductor element units Suv and Slv, for example, form a V-phase arm and generate a V-phase AC voltage. The semiconductor element units Suw and Slw, for example, form a W-phase arm and generate a W-phase AC voltage. The semiconductor element units Suu, Suv, and Suw form an upper arm of the three-phase inverter unit 11R. The semiconductor element units Slu, Slv, and Slw form a lower arm of the three-phase inverter unit 11R.

[0021] The semiconductor element units Suu, Suv, and Suw each have a transistor Qu and a freewheeling diode Du connected in anti-parallel. The semiconductor element units Slu, Slv, and Slw each have a transistor Ql and a freewheeling diode Dl connected in anti-parallel. The transistors Qu and Ql are, for example, power semiconductor elements. Examples of power semiconductor elements include power MOS transistors and insulated gate bipolar transistors (IGBTs).

[0022] For example, a motor 15R is connected to the connection portion between the semiconductor element units Suu and Slu, the connection portion between the semiconductor element units Suv and Slv, and the connection portion between the semiconductor element units Suw and Slw.

[0023] Current detection unit 13Ru detects a U-phase current flowing through the U-phase of motor 15R, current detection unit 13Rv detects a V-phase current flowing through the V-phase of motor 15R, and current detection unit 13Rw detects a W-phase current flowing through the W-phase of motor 15R. In other words, current detection unit 13Ru detects a U-phase output current output from the U-phase of three-phase inverter unit 11R, current detection unit 13Rv detects a V-phase output current output from the V-phase of three-phase inverter unit 11R, and current detection unit 13Rw detects a W-phase output current output from the W-phase of three-phase inverter unit 11R.

[0024] The control unit 2R receives a U-phase current detected by the current detection unit 13Ru, a V-phase current detected by the current detection unit 13Rv, a W-phase current detected by the current detection unit 13Rw, and a frequency command value F * The control unit 2R generates gate signals Sguu, Sglu, Sguv, Sglv, Sguw, and Sglw by the above. The control unit 2R outputs the generated gate signal Sguu to the gate of transistor Qu provided in the semiconductor element unit Suu, and outputs the generated gate signal Sglu to the gate of transistor Ql provided in the semiconductor element unit Slu. The control unit 2R outputs the generated gate signal Sguv to the gate of transistor Qu provided in the semiconductor element unit Suv, and outputs the generated gate signal Sglv to the gate of transistor Ql provided in the semiconductor element unit Slv. The control unit 2R outputs the generated gate signal Sguw to the gate of transistor Qu provided in the semiconductor element unit Suw, and outputs the generated gate signal Sglw to the gate of transistor Ql provided in the semiconductor element unit Slw.

[0025] The gate signals Sguu, Sglu, Sguv, Sglv, Sguw, and Sglw are pulse signals whose signal levels alternate between high and low at predetermined intervals and predetermined timings. The transistors Qu provided in the semiconductor element units Suu, Slu, Suv, Slv, Suw, and Slw are turned on and off at different timings by the gate signals Sguu, Sglu, Sguv, Sglv, Sguw, and Sglw. As a result, the three-phase inverter unit 11R converts the DC voltage input from the DC power supply 12R into a three-phase AC voltage and outputs the three-phase AC voltage to the motor 15R to drive the motor 15R.

[0026] 2. Real-time simulation method: The real-time simulation method according to this embodiment will be described with reference to Fig. 2 and Fig. 3 to Fig. 8. Fig. 3 is a diagram for explaining a conventional real-time simulator that simulates the operation of a three-phase inverter unit, and is a timing chart showing an example of a gate signal waveform and a gate signal on-rate. Fig. 3 shows the signal waveform of a gate signal without a dead time when the gate signal is input to the three-phase inverter unit, and the gate signal on-rate corresponding to the gate signal.

[0027] The motor drive system to be simulated by the conventional real-time simulator in Fig. 3 (hereinafter sometimes referred to as the "real-time simulator of Prior Art 1") has a configuration similar to that of the motor drive system MS shown in Fig. 2. For this reason, the three-phase inverter unit and control unit provided in the motor drive system to be simulated by the real-time simulator of Prior Art 1 will sometimes be referred to as the "three-phase inverter unit 11R" and the "control unit 2R."

[0028] "Sgu" in Fig. 3 indicates an upper arm gate signal, which collectively refers to gate signals Sguu, Sguv, and Sguw input to any of semiconductor element units Suu, Suv, and Suw constituting the upper arm of three-phase inverter unit 11R. "Sgl" in Fig. 3 indicates a lower arm gate signal input to any of semiconductor element units Slu, Slv, and Slw constituting the lower arm of three-phase inverter unit 11R. "ON" in Fig. 3 indicates a signal level for turning on transistors Qu provided in semiconductor element units Suu, Suv, and Suw, and "OFF" in Fig. 3 indicates a signal level for turning off transistors Qu provided in semiconductor element units Suu, Suv, and Suw.

[0029] "UNR" in Fig. 3 indicates the gate signal on rate of the upper arm gate signal Sgu. "LNR" in Fig. 3 indicates the gate signal on rate of the lower arm gate signal Sgl. "100%" in Fig. 3 indicates that the gate signal on rate is 100%, and "0%" in Fig. 3 indicates that the gate signal on rate is 0%.

[0030] Here, the gate signal on ratio of the upper arm gate signal Sgu is the ratio of the time during which the signal level is high enough to turn on the transistor Qu provided in the semiconductor element units Suu, Suv, and Suw relative to a certain period of time, and the gate signal on ratio of the lower arm gate signal Sgl is the ratio of the time during which the signal level is high enough to turn on the transistor Ql provided in the semiconductor element units Slu, Slv, and Slw relative to a certain period of time (details will be described later).

[0031] The "n+x steps" (x=0, 1, 2, 3, 4) shown in FIG. 3 indicate the timing at which data for simulating the operation of the three-phase inverter unit 11R is read in the inverter simulator unit. The data read in the inverter simulator unit is data used for the simulation calculation. Therefore, the timing at which the data is read is the timing at which the simulation calculation is executed. The inverter simulator unit is a simulator that simulates the three-phase inverter unit 11R, and executes calculations different from those executed by the simulator that simulates the operation of the three-phase inverter unit 11R in this embodiment. The time interval of n+k steps corresponds to the "fixed time" described above. In other words, the fixed time is the time interval at which data is read in the inverter simulator unit to simulate the operation of the power conversion device.

[0032] As shown in FIG. 3, in the real-time simulator of conventional technology 1, data reading is performed at n+0 steps at time t0, data reading is performed at n+1 steps at time t2, data reading is performed at n+2 steps at time t3, data reading is performed at n+3 steps at time t5, and data reading is performed at n+4 steps at time t6.

[0033] Assume that the time tx when the signal level of the upper arm gate signal Sgu changes from OFF to ON is time t1, which is between time t0 and time t2. When the real-time simulator of Prior Art 1 reads data at step n+0, it does not read data until step n+1. Therefore, the period from time tx when the signal level of the upper arm gate signal Sgu changes from OFF to ON to the immediately following time t2, n+1, is not reflected in the simulation by the real-time simulator. As a result, the gate signal ON ratio of the upper arm gate signal Sgu remains 0% even after time tx.

[0034] Also, at time tx, the signal level of the lower arm gate signal Sgl changes from ON to OFF. The change in the signal level of the lower arm gate signal Sgl, like the change in the signal level of the upper arm gate signal Sgu, is not reflected in the simulation by the real-time simulator. As a result, the gate signal ON ratio of the upper arm gate signal Sgu remains at 0% even after time tx. As a result, the gate signal ON ratio of the lower arm gate signal Sgl remains at 100% even after time tx.

[0035] As shown in FIG. 3 , step n+1 is the timing of the first data read after time tx. In step n+1, the signal level of upper arm gate signal Sgu is ON, and the signal level of lower arm gate signal Sgl is OFF. Therefore, a change in the signal levels of upper arm gate signal Sgu and lower arm gate signal Sgl at time tx is reflected by the calculation in step n+1. As a result, as indicated by arrow Y1, a change in the signal level of lower arm gate signal Sgl at time tx is reflected in step n+1, and at time t2, the gate signal ON ratio LNR of lower arm gate signal Sgl changes from 100% to 0%. Similarly, as indicated by arrow Y2, a change in the signal level of upper arm gate signal Sgu at time tx is reflected in step n+1, and at time t2, the gate signal ON ratio UNR of upper arm gate signal Sgu changes from 0% to 100%.

[0036] At time ty, the signal level of upper-arm gate signal Sgu changes from ON to OFF, and the signal level of lower-arm gate signal Sgl changes from OFF to ON. Time ty is assumed to be time t4 between time t0 and time t5. The real-time simulator of Prior Art 1 reads data at step n+2, but does not read data until step n+3. Therefore, as with time tx, the change in the signal levels of upper-arm gate signal Sgu and lower-arm gate signal Sgl at time ty is not reflected until step n+3. As a result, as indicated by arrow Y2, the change in the signal level of upper-arm gate signal Sgu at time ty is reflected in step n+3, and at time t5, the gate signal on ratio UNR of upper-arm gate signal Sgu changes from 100% to 0%. Similarly, as indicated by arrow Y3, the change in the signal level of lower arm gate signal Sgl is reflected in n+3 steps, and at time t5, the gate signal on ratio LNR of lower arm gate signal Sgl changes from 0% to 100%.

[0037] As described above, in the real-time simulator of Prior Art 1, if the timing at which the signal levels of the upper arm gate signal Sgu and the lower arm gate signal Sgl change differs from the timing at which data is read, a period occurs during which the signal levels of the gate signals are not reflected. As a result, the real-time simulator of Prior Art 1 suffers from reduced calculation accuracy in simulating the operation of three-phase inverter unit 11R (specifically, semiconductor element units Suu, Suv, Suw, Slu, Slv, and Slw).

[0038] 4 is a diagram illustrating a conventional real-time simulator that simulates the operation of a three-phase inverter unit, and is a timing chart showing an example of gate signal waveforms and gate signal on rates. The conventional real-time simulator in FIG. 4 (hereinafter sometimes referred to as "real-time simulator of prior art 2") is the simulator disclosed in Patent Document 1.

[0039] The motor drive system to be simulated by the real-time simulator of Prior Art 2 has a configuration similar to that of the motor drive system MS shown in Fig. 2. For this reason, the three-phase inverter unit and control unit provided in the motor drive system to be simulated by the real-time simulator of Prior Art 2 may be referred to as the "three-phase inverter unit 11R" and the "control unit 2R."

[0040] "Sgu", "Sgl", "ON", "OFF", "UNR", "LNR", "100%", and "0%" in Figure 4 indicate the same things as "Sgu", "Sgl", "ON", "OFF", "UNR", "LNR", "100%, "0%", and "n+x steps" (x=0,1,2,3,4) in Figure 3, and "Sgu", "Sgl", "ON", "OFF", "UNR", "LNR", "100%", and "0%" in Figure 3 indicate the same things as "Sgu", "Sgl", "ON", "OFF", "UNR", "LNR", "100%, "0%", and "n+x steps" (x=0,1,2,3,4) in Figure 3, so explanation will be omitted.

[0041] As shown in FIG. 4, in the real-time simulator of conventional technology 2, data reading is performed at n+0 steps at time t0, data reading is performed at n+1 steps at time t2, data reading is performed at n+2 steps at time t3, data reading is performed at n+3 steps at time t5, and data reading is performed at n+4 steps at time t6.

[0042] The time tx at which the signal level of the upper arm gate signal Sgu changes from OFF to ON is assumed to be time t1 between times t0 and t2. The real-time simulator of prior art 2 measures the signal levels of the upper arm gate signal Sgu and the lower arm gate signal Sgl at intervals smaller than the data read step interval. Based on the signal level measurements, the real-time simulator of prior art 2 calculates the proportion of time that the signal levels of the upper arm gate signal Sgu and the lower arm gate signal Sgl are ON relative to the step interval (i.e., the gate signal ON proportion). The real-time simulator of prior art 2 outputs a voltage at a voltage level that matches the gate signal ON proportion of the signal level of the upper arm gate signal Sgu between data read steps. As a result, the real-time simulator of prior art 2 makes the integral value of the voltage during the period when the signal level of the upper arm gate signal Sgu is ON equal to the integral value of the output voltage output between data read steps.

[0043] Similarly, the real-time simulator of prior art 2 calculates the proportion of time that the signal level of the lower arm gate signal Sgl is at the ON level relative to the step interval (i.e., the gate signal ON proportion) based on the measurement results of the signal level. The real-time simulator of prior art 2 outputs a voltage at a voltage level that matches the gate signal ON proportion of the signal level of the lower arm gate signal Sgl between data read steps. As a result, the real-time simulator of prior art 2 makes the integral value of the voltage during each period when the signal level of the lower arm gate signal Sgl is at the ON level equal to the integral value of the output voltage output between data read steps.

[0044] As a result, the real-time simulator of prior art 2 can improve the calculation accuracy of the simulation of the operation of the three-phase inverter section 11R (specifically, the semiconductor element sections Suu, Suv, Suw, Slu, Slv, and Slw) compared to the real-time simulator of prior art 1.

[0045] As shown in FIG. 4, the signal level of upper arm gate signal Sgu is ON from time tx to step n+1. Therefore, the real-time simulator of prior art 2 outputs a voltage between step n+1 and step n+2 that corresponds to the ratio of the period from time tx to step n+1, during which the signal level of upper arm gate signal Sgu is ON, to the period from step n+0 to step n+1. Suppose the ratio of the period from time tx to step n+1 to the period from step n+0 to step n+1 is, for example, 25%. Then, as indicated by arrow Y2 in FIG. 4, the voltage level of gate signal ON ratio UNR of upper arm gate signal Sgu during the period from step n+1 to step n+2 is 25% of the maximum voltage level.

[0046] Furthermore, the signal level of upper arm gate signal Sgu is maintained at the ON level during the period from time t2 of step n+1 to time t3 of step n+2. Therefore, as indicated by arrow Y3 in Figure 4, the voltage level of gate signal ON ratio UNR of upper arm gate signal Sgu during the period from step n+2 to step n+3 is 100% of the maximum voltage level.

[0047] Furthermore, suppose that the signal level of upper arm gate signal Sgu changes from ON level to OFF level at time ty, which corresponds to time t4 between time t3 of step n+2 and time t5 of step n+3. Suppose that the ratio of the period from step n+2 to time ty to the period from step n+2 to step n+3 is, for example, 50%. Then, as indicated by arrow Y4 in FIG. 4, the voltage level of gate signal ON ratio UNR of upper arm gate signal Sgu during the period from step n+3 to step n+4 becomes 50% of the maximum voltage level.

[0048] Furthermore, suppose that the signal level of lower arm gate signal Sgl changes from OFF level to ON level at time ty. Suppose that the ratio of the period from time ty to n+3 step to the period from n+2 step to n+3 step is, for example, 50%. Then, as indicated by arrow Y5 in FIG. 4 , the voltage level of gate signal ON ratio LNR of lower arm gate signal Sgl during the period from n+3 step to n+4 step becomes 50% of the maximum voltage level.

[0049] In this way, the real-time simulator of Prior Art 2 can reflect changes in the signal levels of the upper arm gate signal Sgu and the lower arm gate signal Sgl between data reading steps in its calculations. This allows the real-time simulator of Prior Art 2 to improve the calculation accuracy of the simulation of the operation of three-phase inverter unit 11R (specifically, semiconductor element units Suu, Suv, Suw, Slu, Slv, and Slw) compared to the real-time simulator of Prior Art 1.

[0050] The real-time simulator of Prior Art 2 can reflect changes in gate signals between data read steps in the simulation calculations. However, the real-time simulator of Prior Art 2 has a problem in that the calculation accuracy of the simulation of the operation of driving the transistors Qu and Ql is reduced by providing a dead time. Taking the semiconductor element units Suu and Slu as an example of the semiconductor element units Suu, Suv, and Suw that constitute the upper arm and the semiconductor element units Slu, Slv, and Slw that constitute the lower arm, the dead time is a period during which both the transistor Qu of the semiconductor element unit Suu and the transistor Ql of the semiconductor element unit Slu, which are connected in series, are in the off state.

[0051] 5 and 6 are diagrams illustrating the problem of reduced calculation accuracy in simulations using a real-time simulator according to Prior Art 2 that simulates the operation of a three-phase inverter unit. FIG. 5 is a timing chart of gate signal waveforms and gate signal on-ratios under the condition that the polarity of the output current flowing from the three-phase inverter unit 11R to the motor 15R is positive (positive current condition). FIG. 6 is a timing chart of gate signal waveforms and gate signal on-ratios under the condition that the polarity of the output current flowing from the three-phase inverter unit 11R to the motor 15R is negative (negative current condition). The current flowing from the three-phase inverter unit 11R toward the motor 15R is positive current, and the current flowing from the motor 15R toward the three-phase inverter unit 11R is negative current.

[0052] "ON", "OFF", "UNR", "LNR", "100%", "0%" and "n+x steps" (x=0,1,2,3,4) in "Sgu", "Sgl", "Sgu" and "Sgl" in Figures 5 and 6 indicate the same content as "Sgu", "Sgl", "ON", "OFF", "UNR", "LNR", "100%", "0%" and "n+x steps" (x=0,1,2,3,4) in Figure 3, so explanation will be omitted.

[0053] "Qu" in Figures 5 and 6 indicates a transistor provided in the semiconductor element units Suu, Suv, and Suw. "Du" in Figures 5 and 6 indicates a free wheel diode provided in the semiconductor element units Suu, Suv, and Suw. "Ql" in Figures 5 and 6 indicates a transistor provided in the semiconductor element units Slu, Slv, and Slw. "Dl" in Figures 5 and 6 indicates a free wheel diode provided in the semiconductor element units Slu, Slv, and Slw.

[0054] "ON" for "Qu" in Figures 5 and 6 indicates that the transistor Qu is in the on state, and "OFF" for "Qu" in Figures 5 and 6 indicates that the transistor Qu is in the off state. "ON" for "Ql" in Figures 5 and 6 indicates that the transistor Ql is in the on state, and "OFF" for "Ql" in Figures 5 and 6 indicates that the transistor Ql is in the off state.

[0055] "ON" for "Du" in Figures 5 and 6 indicates that the freewheel diode Du is in the on state (conducting state), and "OFF" for "Du" in Figures 5 and 6 indicates that the freewheel diode Du is in the off state (non-conducting state). "ON" for "Dl" in Figures 5 and 6 indicates that the freewheel diode Dl is in the on state (conducting state), and "OFF" for "Dl" in Figures 5 and 6 indicates that the freewheel diode Dl is in the off state (non-conducting state).

[0056] 5, the period between time t1, when upper-arm gate signal Sgu is in the OFF state and immediately after lower-arm gate signal Sgl changes from the ON state to the OFF state, and time t2, when upper-arm gate signal Sgu is immediately before changing from the OFF state to the ON state and lower-arm gate signal Sgl is in the OFF state, is a dead time Td during which both transistor Qu and transistor Ql are in the OFF state. Similarly, the period between time t5, when upper-arm gate signal Sgu is immediately after changing from the ON state to the OFF state and lower-arm gate signal Sgl is in the OFF state, and time t7, when upper-arm gate signal Sgu is in the OFF state and immediately before lower-arm gate signal Sgl changes from the OFF state to the ON state, is also a dead time Td during which both transistor Qu and transistor Ql are in the OFF state.

[0057] Under the positive current polarity condition, during the dead time Td, the transistors Qu and Ql and the freewheeling diode Du are in the off state, but the freewheeling diode Dl is in the on state. The semiconductor element units Slu, Slv, and Slw pass current toward the motor 15R when the transistor Ql is in the on state, and also pass current toward the motor 15R when the freewheeling diode Dl is in the on state. Therefore, the semiconductor element units Slu, Slv, and Slw act similarly on the motor 15R when the freewheeling diode Dl is in the on state and when the transistor Ql is in the on state.

[0058] As indicated by arrow Y2 in Fig. 5, even when dead time Td is provided under a positive current condition, the real-time simulator of Prior Art 2 can equalize the integral value of the voltage during the period from time tx when the signal level of upper-arm gate signal Sgu changes to step n+1 and the integral value of the voltage of gate signal on ratio UNR of upper-arm gate signal Sgu during step n+1 to step n+2. Similarly, as indicated by arrow Y5 in Fig. 5, even when dead time Td is provided under a positive current condition, the real-time simulator of Prior Art 2 can equalize the integral value of the voltage during the period from time ty when the signal level of lower-arm gate signal Sgl changes to step n+3 and the integral value of the voltage of gate signal on ratio LNR of lower-arm gate signal Sgl during step n+3 to step n+4.

[0059] However, the real-time simulator of Prior Art 2 cannot take into account, under positive current polarity conditions, the on state of the freewheeling diode Dl, which acts on the motor 15R in the same way as the on state of the transistor Ql, in the lower arm gate signal Sgl. Therefore, under positive current polarity conditions, the real-time simulator of Prior Art 2 may experience a decrease in the calculation accuracy of the simulation of the operation of the semiconductor element units Slu, Slv, and Slw.

[0060] 6, under the negative current polarity condition, during the dead time Td, the transistors Qu and Ql and the freewheeling diode Dl are in the off state, but the freewheeling diode Du is in the on state. When the transistor Qu is in the on state, current flows into the semiconductor element units Suu, Suv, and Suw from the motor 15R, and when the freewheeling diode Du is in the on state, current also flows from the motor 15R. Therefore, the on state of the freewheeling diode Du can have the same effect on the motor 15R as the on state of the transistor Qu.

[0061] As indicated by arrow Y2 in Fig. 6, even when dead time Td is provided under a negative current condition, the real-time simulator of Prior Art 2 can equalize the integral value of the voltage during the period from time tx when the signal level of upper-arm gate signal Sgu changes to step n+1 and the integral value of the voltage of gate signal on ratio UNR of upper-arm gate signal Sgu during step n+1 to step n+2. Similarly, as indicated by arrow Y5 in Fig. 6, even when dead time Td is provided under a negative current condition, the real-time simulator of Prior Art 2 can equalize the integral value of the voltage during the period from time ty when the signal level of lower-arm gate signal Sgl changes to step n+3 and the integral value of the voltage of gate signal on ratio LNR of lower-arm gate signal Sgl during step n+3 to step n+4.

[0062] However, in the real-time simulator of Prior Art 2, under negative current polarity conditions, the upper arm gate signal Sgu cannot take into account the on state of the freewheeling diode Du, which acts on the motor 15R in the same way as the on state of the transistor Qu. Therefore, under negative current polarity conditions, the real-time simulator of Prior Art 2 may experience a decrease in the calculation accuracy of the simulation of the operation of the three-phase inverter unit 11R (specifically, the semiconductor element units Suu, Suv, and Suw).

[0063] Therefore, the real-time simulation method according to this embodiment calculates the dead-time period ratio from the ratio of the period during which the upper-arm gate signal is in the ON state to the ratio of the period during which the lower-arm gate signal is in the ON state within the data read step period. The real-time simulation method according to this embodiment compensates for the calculated dead-time period ratio with either the ON rate of the upper-arm gate signal or the ON rate of the lower-arm gate signal based on the polarity of the output current. This allows the real-time simulation according to this embodiment to improve the calculation accuracy of the simulation of the operation of the three-phase inverter unit (specifically, the semiconductor device unit).

[0064] 7 and 8 are diagrams for explaining the real-time simulation method according to this embodiment. Fig. 7 is a timing chart showing an example of gate signal waveforms and gate signal on-ratios under a positive current polarity condition in the real-time simulation method according to this embodiment. Fig. 8 is a timing chart showing an example of gate signal waveforms and gate signal on-ratios under a negative current polarity condition in the real-time simulation method according to this embodiment. The current flowing from three-phase inverter unit 11R toward motor 15R is a positive current, and the current flowing from motor 15R toward three-phase inverter unit 11R is a negative current.

[0065] "Sgu," "Sgl," "ON," "OFF," "UNR," "LNR," "100%," "0%," "Qu," "Du," "Ql," "Dl," "Td," and "n+x steps" (x = 0, 1, 2, 3, 4) in FIGS. 7 and 8 represent the same information as "Sgu," "Sgl," "ON," "OFF," "100%," "0%," "Qu," "Du," "Ql," "Dl," "Td," and "n+x steps" (x = 0, 1, 2, 3, 4) in FIG. 5 , and therefore will not be described again. "UNR" in FIGS. 7 and 8 indicates the gate signal on ratio of the upper arm gate signal Sgu. "LNR" in FIGS. 7 and 8 indicates the gate signal on ratio of the lower arm gate signal Sgl. Although details will be described later, the gate signal on ratio UNR in this embodiment differs from the gate signal on ratio UNR in prior art 2 in that a first ratio value (details will be described later) equivalent to the gate signal on ratio UNR in prior art 2 is compensated for with a dead time ratio value (details will be described later) as needed. Similarly, the gate signal on ratio LNR in this embodiment differs from the gate signal on ratio LNR in prior art 2 in that a second ratio value (details will be described later) equivalent to the gate signal on ratio LNR in prior art 2 is compensated for with a dead time ratio value (details will be described later) as needed.

[0066] The real-time simulation method according to this embodiment calculates a first ratio value, which is the ratio of the time during which an upper arm gate signal (an example of a first control pulse signal) Sgu, which controls the on / off operation of a transistor Qu (an example of a first transistor) out of two transistors Qu and Ql connected in series in a three-phase inverter unit (an example of a power conversion device) 11R that converts DC voltage to AC voltage, reaches a signal level that turns on the transistor Qu, to a certain period of time.

[0067] Here, the certain time is the interval between data reads (an example of an interval between calculations) executed in an inverter simulator unit (details of which will be described later) to simulate the operation of the three-phase inverter unit 11R. In Figures 7 and 8, it is the time interval between temporally adjacent steps, and examples of the certain time include the period between step n+0 and step n+1, and the period between step n+1 and step n+2.

[0068] In the real-time simulation method according to this embodiment, if the first ratio value is "RV1", the on time of the upper arm gate signal is "UON", and the fixed time is "FT", the first ratio value is calculated by the following equation (1): RV1(%)=(UON / FT)×100 ···(1)

[0069] Focusing on the period from step n+0 to step n+1 shown in FIG. 7, the on-time UON of the upper arm gate signal is the period from time t2 to time t3, which corresponds to the period from time tx to step n+1. The fixed time FT is the period from time t0 to time t3, which corresponds to the period from step n+0 to step n+1. Therefore, from step n+0 to step n+1, the first ratio value RV1 is calculated by "((t3-t2) / (t3-t0))×100".

[0070] Next, the real-time simulation method according to this embodiment calculates a second ratio value, which is the ratio of the time during which the lower arm gate signal (an example of a second control pulse signal) Sgl, which controls the on / off operation of transistor Ql (an example of a second transistor) of two transistors Qu and Ql, reaches a signal level for turning on transistor Ql, to a certain period of time.

[0071] In the real-time simulation method according to this embodiment, if the second ratio value is "RV2", the on time of the lower arm gate signal is "LON", and the fixed time is "FT", the second ratio value is calculated by the following equation (2): RV2(%)=(LON / FT)×100 (2)

[0072] Focusing on the n+0 step to the n+1 step shown in FIG. 7 , the on-time LON of the lower arm gate signal is the period from time t0 to time t1, which corresponds to the period from the n+0 step to just before the start of the dead time Td. The fixed time FT is the period from time t0 to time t3, which corresponds to the period from the n+0 step to the n+1 step. Therefore, from the n+0 step to the n+1 step, the second ratio value RV2 is calculated by ((t1-t0) / (t3-t0))×100. The first ratio value RV1 and the second ratio value RV2 may be calculated, for example, from either the upper arm gate signal Sgu or the lower arm gate signal Sgl, which corresponds to the gate signal whose signal level becomes the ON level first during the fixed time FT. Therefore, from the n+0 step to the n+1 step, the second ratio value RV2 is calculated first, followed by the first ratio value RV1.

[0073] Next, the real-time simulation method according to this embodiment compensates for a dead time ratio value, which is the ratio of the time during which the upper arm gate signal Sgu and the lower arm gate signal Sgl are at a signal level for providing a dead time Td in which both the transistor Qu and the transistor Ql are in an off state, to a fixed time FT, with a first ratio value RV1 or a second ratio value RV2.

[0074] In the real-time simulation method according to this embodiment, when the dead time is "Td" and the dead time ratio is "DV", the dead time ratio is calculated by the following equation (3). DV(%) = (Td / FT) × 100 (3)

[0075] The sum of the on-time UON of the upper arm gate signal, the on-time LON of the lower arm gate signal, and the dead time Td is the constant time FT, and the constant time can be expressed by the following equation (4). FT = UON + LON + Td (4)

[0076] By substituting equations (1) to (3) into equation (4) and rearranging it, equation (4) can be expressed as the following equation (5). 100(%) = RV1 + RV2 + DV (5)

[0077] Therefore, the dead time ratio value DV can be calculated from the following equation (6) using the calculation results of the first ratio value RV1 and the second ratio value RV2. DV(%)=100(%)-(RV1+RV2) ···(6)

[0078] 7, under the positive current polarity condition, the freewheeling diode Dl provided in the semiconductor element units Slu, Slv, and Slw constituting the lower arm is turned on during the dead time Td. When the freewheeling diode Dl is turned on, a positive current flows from the three-phase inverter unit 11R to the motor 15R.

[0079] 7, the real-time simulation method according to this embodiment compensates for the dead-time percentage DV with the second percentage RV2 under the positive current condition in which a positive current flows. The second percentage RV2 from step n+1 to step n+2 is compensated for by the dead-time percentage DV based on the dead time Td between time t1 and time t2. As a result, the gate signal on-percentage LNR from step n+1 to step n+2 is equal to the level obtained by adding the second percentage RV2 based on the ON-level period of the lower arm gate signal Sgl from step n+0 to step n+1, in which the dead time Td is provided, to the dead-time percentage DV based on the dead time Td.

[0080] 7, the second ratio value RV2 from step n+3 to step n+4 is compensated for by the dead time ratio value DV based on the dead time Td between time t5 and time t6. As a result, the gate signal on ratio LNR from step n+3 to step n+4 is a voltage level obtained by adding the voltage of the second ratio value RV2 based on the ON level period of the lower arm gate signal Sgl from step n+2 to step n+3 in which the dead time Td is provided to the voltage of the dead time ratio value DV based on the dead time Td.

[0081] 8, under the negative current polarity condition, the freewheeling diode Du provided in the semiconductor element units Suu, Suv, and Suw constituting the upper arm is turned on during the dead time Td. When the freewheeling diode Du is turned on, a negative current flows from the motor 15R to the three-phase inverter unit 11R.

[0082] 8, the real-time simulation method according to this embodiment compensates for the dead-time percentage DV with the first percentage RV1 under a negative current condition in which a negative current flows. The first percentage RV1 from step n+1 to step n+2 is compensated for by the dead-time percentage DV based on the dead time Td between time t1 and time t2. As a result, the gate signal on-percentage UNR from step n+1 to step n+2 is a voltage level obtained by adding the voltage of the first percentage RV1 based on the ON-level period of the upper arm gate signal Sgu from step n+0 to step n+1, in which the dead time Td is provided, to the voltage of the dead-time percentage DV based on the dead time Td.

[0083] 8, the first ratio value RV1 from step n+3 to step n+4 is compensated for by the dead time ratio value DV based on the dead time Td between time t5 and time t6. As a result, the gate signal on ratio UNR from step n+3 to step n+4 becomes a voltage level obtained by adding the voltage of the first ratio value RV1 based on the ON level period of the upper arm gate signal Sgu from step n+2 to step n+3 in which the dead time Td is provided to the voltage of the dead time ratio value DV based on the dead time Td.

[0084] In this way, the real-time simulation method according to this embodiment compensates for the second ratio value RV2 with the dead-time ratio value DV under the current positive polarity condition, so that the on state of the freewheeling diode Dl, which acts on the motor 15R in the same manner as the on state of the transistor Ql, can be reflected in the gate signal on ratio LNR. As a result, the real-time simulation method according to this embodiment can improve the simulation accuracy of the operations of the semiconductor element units Slu, Slv, and Slw under the current positive polarity condition.

[0085] Similarly, the real-time simulation method according to this embodiment compensates for the first ratio value RV1 with the dead-time ratio value DV under the negative current polarity condition, so that the on state of the free wheel diode Du, which acts on the motor 15R in the same manner as the on state of the transistor Qu, can be reflected in the gate signal on ratio UNR. As a result, the real-time simulation method according to this embodiment can improve the simulation accuracy of the operation of the semiconductor element units Suu, Suv, and Suw under the negative current polarity condition.

[0086] 1-3. Real-time simulator configuration: The schematic configuration of the real-time simulator according to this embodiment will be described using FIGS. 9 to 11 with reference to FIGS. 2, 7, and 8. FIG. 9 is a block diagram showing an example of the schematic configuration of a simulation system SS to which a real-time simulator 1 according to this embodiment is applied. Unlike FIG. 1, FIG. 9 shows a specific configuration of the real-time simulator 1. The U-phase voltage calculation model 11Mu, V-phase voltage calculation model 11Mv, and W-phase voltage calculation model 11Mw provided in the real-time simulator 1 have the same configuration, so illustration and description of the specific configurations of the V-phase voltage calculation model and W-phase voltage calculation model will be omitted.

[0087] 9, the real-time simulator 1 includes an inverter simulator unit 11, an input voltage setting model 12M, a motor simulator unit 15, and current detection models 13Mu, 13Mv, and 13Mw. The inverter simulator unit (an example of a power conversion device simulator unit) 11 simulates the operation of a three-phase inverter unit (an example of a power conversion device) that converts DC voltage into AC voltage.

[0088] The input voltage setting model 12M is a model that simulates the operation of the DC power supply 12R (see FIG. 2), and outputs a DC voltage having the same voltage value as the DC voltage output by the DC power supply 12R to the inverter simulator unit 11 and the control unit 2R.

[0089] Although detailed description will be omitted, the motor simulator unit 15 simulates the operation of the motor 15R (see FIG. 2). The motor simulator unit 15 simulates the operation of the motor 15R using the U-phase AC output voltage Vmu, the V-phase AC output voltage Vmv, and the W-phase AC output voltage Vmw, which are input as simulation results from the inverter simulator unit 11, and the U-phase AC output current Imu, the V-phase AC output current Imv, and the W-phase AC output current Imw.

[0090] The current detection model 13Mu is a simulation model of the current detection unit 13Ru (see FIG. 2) that detects the U-phase AC output current Imu output from the three-phase inverter unit 11R. The current detection model 13Mu detects the U-phase AC output current Imu output from the inverter simulator unit 11 as a simulation result, and determines the polarity Pu of the detected U-phase AC output current Imu. The output of the current detection model 13Mu is connected to the input of the U-phase voltage calculation model 11Mu provided in the inverter simulator unit 11. The current detection model 13Mu outputs the determined polarity Pu to the U-phase voltage calculation model 11Mu.

[0091] The current detection model 13Mv is a simulation model of the current detection unit 13Rv (see FIG. 2) that detects the V-phase AC output current Imv output from the three-phase inverter unit 11R. The current detection model 13Mv detects the V-phase AC output current Imv output from the inverter simulator unit 11 as a simulation result, and determines the polarity Pv of the detected V-phase AC output current Imv. The output of the current detection model 13Mv is connected to the input of the V-phase voltage calculation model 11Mv provided in the inverter simulator unit 11. The current detection model 13Mv outputs the determined polarity Pv to the V-phase voltage calculation model 11Mv.

[0092] The current detection model 13Mw is a simulation model of the current detection unit 13Rw (see FIG. 2) that detects the W-phase AC output current Imw output from the three-phase inverter unit 11R. The current detection model 13Mw detects the W-phase AC output current Imw output from the inverter simulator unit 11 as a simulation result, and determines the polarity Pw of the detected W-phase AC output current Imw. The output of the current detection model 13Mw is connected to the input of the W-phase voltage calculation model 11Mw provided in the inverter simulator unit 11. The current detection model 13Mw outputs the determined polarity Pw to the W-phase voltage calculation model 11Mw.

[0093] The inverter simulator unit 11 has a U-phase voltage calculation model 11Mu, a V-phase voltage calculation model 11Mv, and a W-phase voltage calculation model 11Mw. The inputs of the U-phase voltage calculation model 11Mu, the V-phase voltage calculation model 11Mv, and the W-phase voltage calculation model 11Mw are connected to the output of the control unit 2R and the output of the input voltage setting model 12M, respectively. Thus, gate signals Sguu and Sglu are input to the U-phase voltage calculation model 11Mu, gate signals Sguv and Sglu are input to the V-phase voltage calculation model 11Mv, and gate signals Sguw and Sglw are input to the W-phase voltage calculation model 11Mw. Furthermore, DC voltages are input to the U-phase voltage calculation model 11Mu, the V-phase voltage calculation model 11Mv, and the W-phase voltage calculation model 11Mw from the input voltage setting model 12M. Furthermore, the polarity Pu is input to the U-phase voltage calculation model 11Mu from the current detection model 13Mu, the polarity Pv is input to the V-phase voltage calculation model 11Mv from the current detection model 13Mv, and the polarity Pw is input to the W-phase voltage calculation model 11Mw from the current detection model 13Mw.

[0094] The U-phase voltage calculation model 11Mu has gate signal on-proportion calculation models 111M and 112M, a dead time proportion compensation model 113M, a divider model 114M, a polarity reversal model 115M, multiplier models 116M and 117M, and an adder model 118M.

[0095] The gate signal on-proportion calculation model 111M (an example of a first control signal on-proportion calculation model) calculates a first ratio value RV1, which is the ratio of the time during which a gate signal Sguu (an example of a first control pulse signal) that controls the on / off operation of a transistor Qu (an example of a first transistor) among the transistors Qu and Ql of the semiconductor element units Suu and Slu connected in series in the three-phase inverter unit 11R (an example of a power conversion device) is at a signal level that turns the transistor Qu on. The gate signal on-proportion calculation model 111M calculates the first ratio value RV1 using the above-mentioned formula (1).

[0096] The gate signal on-proportion calculation model 112M (an example of a second control signal on-proportion calculation model) calculates a second proportion value RV2, which is the proportion of time to a certain period of time during which the gate signal Sglu (an example of a second control pulse signal) that controls the on / off operation of transistor Ql (an example of a second transistor) of transistors Qu and Ql of semiconductor element units Suu and Slu is at a signal level that turns transistor Ql on. The gate signal on-proportion calculation model 112M calculates the second proportion value RV2 using the above-mentioned equation (2).

[0097] As described above, the certain time in the gate signal on-ratio calculation models 111M and 112M is the interval between data reads (an example of an interval between calculations) executed in the inverter simulator unit 11 to simulate the operation of the three-phase inverter unit 11R. That is, it is the time interval between temporally adjacent data read steps, and examples of the certain time include the period between the n+0 step and the n+1 step and the period between the n+1 step and the n+2 step (see FIGS. 7 and 8).

[0098] The dead time proportion compensation model 113M compensates the first proportion RV1 or the second proportion RV2 with a dead time proportion DV, which is the proportion of the time during which the gate signals Sguu and Sglu are at a signal level for providing a dead time Td during which both the transistors Qu and Ql are in an off state, to a certain period of time. Here, the certain period of time is the same period as the certain period of time in the gate signal on proportion calculation models 111M and 112M.

[0099] As shown in FIG. 9, the dead time proportion compensation model 113M has an adder model 113Ma, a subtractor model 113Mb, a comparator model 113Mc, a selection unit model 113Md, a selection unit model 113Me, an adder model 113Mf, and an adder model 113Mg.

[0100] The input of the adder model 113Ma is connected to the outputs of the gate signal on ratio calculation models 111M and 112M. The output of the adder model 113Ma is connected to the negative input of the subtractor model 113Mb. The numerical value 100% is input to the positive input of the subtractor model 113Mb. The output of the subtractor model 113Mb is connected to the false value terminal F of the selection unit model 113Md and the true value terminal T of the selection unit model 113Me. The numerical value 0 is input to the true value terminal T of the selection unit model 113Md and the false value terminal F of the selection unit model 113Me.

[0101] The non-inverting input of the comparator model 113Mc is connected to the output of the current detection model 13Mu. The value 0 is input to the inverting input of the comparator model 113Mc. The output of the comparator model 113Mc is connected to the control terminals of the selection unit models 113Md and 113Me.

[0102] One input of the adder model 113Mf is connected to the output of the gate signal on-ratio calculation model 111M. The other input of the adder model 113Mf is connected to the output of the selection unit model 113Md. The output of the adder model 113Mf is connected to one input of the multiplier model 116M.

[0103] One input of the adder model 113Mg is connected to the output of the gate signal on ratio calculation model 112M. The other input of the adder model 113Mg is connected to the output of the selection unit model 113Me. The output of the adder model 113Mg is connected to one input of the multiplier model 117M.

[0104] In the dead time percentage compensation model 113M, the adder model 113Ma adds the first percentage value RV1 output from the gate signal on percentage calculation model 111M and the second percentage value RV2 input from the gate signal on percentage calculation model 112M, and outputs the addition result (RV1+RV2) in units of % to the subtractor model 113Mb. The subtractor model 113Mb subtracts the addition result (RV1+RV2) input from the adder model 113Ma from 100%. Therefore, the subtractor model 113Mb outputs the dead time percentage value DV to the selector models 113Md and 113Me to perform the calculation expressed by the above-mentioned equation (6).

[0105] In this way, the dead time percentage compensation model 113M calculates the dead time percentage value DV based on the first percentage value RV1 and the second percentage value RV2. The dead time percentage compensation model 113M also calculates the dead time percentage value DV using equation (6).

[0106] When the polarity Pu input from the current detection model 13Mu is a positive value indicating positive polarity, the comparator model 113Mc outputs an output signal of a high level to the selection unit models 113Md and 113Me. On the other hand, when the polarity Pu input from the current detection model 13Mu is a negative value indicating negative polarity, the comparator model 113Mc outputs an output signal of a low level to the selection unit models 113Md and 113Me.

[0107] When an output signal with a high signal level is input to the control terminal, the selection unit models 113Md and 113Me select the true value terminal T. On the other hand, when an output signal with a low signal level is input to the control terminal, the selection unit models 113Md and 113Me select the false value terminal F. A positive value of the polarity Pu, which indicates positive polarity, indicates that the U-phase AC output current Imu is positive. A negative value of the polarity Pu, which indicates negative polarity, indicates that the U-phase AC output current Imu is negative.

[0108] Therefore, when the U-phase AC output current Imu is positive, the selector models 113Md and 113Me select the true value terminal T, so that the selector model 113Md outputs an output signal with a voltage level of 0 to the other input of the adder model 113Mf, and the selector model 113Me outputs the dead time percentage value DV to the other input of the adder model 113Mg. On the other hand, when the U-phase AC output current Imu is negative, the selector models 113Md and 113Me select the false value terminal F, so that the selector model 113Md outputs the dead time percentage value DV to the other input of the adder model 113Mf, and the selector model 113Me outputs an output signal with a voltage level of 0 to the other input of the adder model 113Mg.

[0109] When the U-phase AC output current Imu is positive, the adder model 113Mf adds the output signal having a voltage level of 0 output from the selector model 113Md to the first ratio value RV1, and outputs a gate signal on ratio UNR based on the first ratio value RV1 to one input of the multiplier model 116M. On the other hand, when the U-phase AC output current Imu is positive, the adder model 113Mg adds the dead time ratio value DV output from the selector model 113Md to the second ratio value RV2, and outputs a gate signal on ratio LNR based on the second ratio value RV2 compensated by the dead time ratio value DV to one input of the multiplier model 116M.

[0110] When the U-phase AC output current Imu is negative, the adder model 113Mf adds the dead-time percentage value DV output from the selector model 113Md to the first percentage value RV1, and outputs a gate signal on-percentage UNR based on the first percentage value RV1 compensated by the dead-time percentage value DV to one input of the multiplier model 116M. On the other hand, when the U-phase AC output current Imu is negative, the adder model 113Mg adds the output signal with a voltage level of 0 output from the selector model 113Me to the second percentage value RV2, and outputs a gate signal on-percentage LNR based on the second percentage value RV2 to one input of the multiplier model 116M.

[0111] In this way, the dead time percentage compensation model 113M compensates for the second percentage value RV2 with the dead time percentage value DV when the polarity of the U-phase AC output current Imu is negative (negative current polarity condition) (see FIG. 7). On the other hand, the dead time percentage compensation model 113M compensates for the first percentage value RV1 with the dead time percentage value DV when the polarity of the U-phase AC output current Imu is positive (positive current polarity condition) (see FIG. 8).

[0112] 9, the input of a divider model 114M provided in the inverter simulator unit 11 is connected to the output of the input voltage setting model 12M, and the output of the divider model 114M is connected to the other input of the multiplier model 116M and the input of the polarity inversion model 115M. The divider model 114M divides the voltage value of the DC voltage set by the input voltage setting model 12M by 1 / 2, and outputs the DC voltage obtained by dividing the voltage value by 1 / 2 to the multiplier model 116M and the polarity inversion model 115M.

[0113] The output of the polarity reversal model 115M is connected to the input of the multiplier model 117M. The polarity reversal model 115M inverts the polarity of the DC voltage input from the divider model 114M and outputs a negative DC voltage to the other input of the multiplier model 117M.

[0114] The output of the multiplier model 116M is connected to one input of the adder model 118M. The multiplier model 116M multiplies the output voltage input from the divider model 114M by the gate signal on ratio UNR input from the adder model 113Mf, and calculates the voltage value of the AC output voltage output from the semiconductor element unit Suu that constitutes the upper arm.

[0115] The voltage value of the output voltage from the divider model 114M corresponds to the maximum value of the AC output voltage output by the semiconductor element unit Suu that constitutes the upper arm. The integral value of the voltage obtained by multiplying this maximum value by the gate signal on rate UNR is the integral value during one step period of data reading in the real-time simulator 1 (for example, the period between step n+0 and step n+1 shown in Figures 7 and 8), and is equivalent to the integral value of the AC output voltage of the semiconductor element unit Suu of the actual three-phase inverter unit 11R.

[0116] The output of the multiplier model 117M is connected to the other input of the adder model 118M. The multiplier model 117M multiplies the negative polarity output voltage input from the polarity inversion model 115M by the gate signal on rate LNR input from the adder model 113Mg, and calculates the voltage value of the AC output voltage output from the semiconductor device unit Slu that constitutes the lower arm.

[0117] The voltage value of the output voltage output from the polarity reversal model 115M corresponds to the minimum value of the AC output voltage output by the semiconductor device unit Slu that constitutes the lower arm. The integral value of the voltage obtained by multiplying this minimum value by the gate signal on rate LNR is the integral value during one step period of data reading in the real-time simulator 1, and is equivalent to the integral value of the AC output voltage of the semiconductor device unit Slu of the actual three-phase inverter unit 11R.

[0118] The adder model 118M adds the voltage input from the multiplier model 116M and the voltage input from the multiplier model 117M, and outputs a U-phase AC output voltage Vmu to the motor simulator unit 15.

[0119] The integral value of the U-phase AC output voltage Vmu output from the adder model 118M takes into consideration the on states of the freewheeling diodes Du, Dl provided in the semiconductor element units Suu, Slu during the dead time Td. For this reason, the integral value of the U-phase AC output voltage Vmu output from the adder model 118M is equivalent to the integral value of the AC output voltage of the semiconductor element unit Slu of the actual three-phase inverter unit 11R. This allows the real-time simulator 1 to improve the calculation accuracy of the simulation of the operation of the three-phase inverter unit 11R.

[0120] The effect of the real-time simulator 1 according to this embodiment will be described with reference to FIG. 2 and FIGS. 10 and 11. FIG. 10 shows an output current waveform obtained by simulating the operation of the three-phase inverter unit 11R using the real-time simulator 1 according to this embodiment. The horizontal axis of the graph shown in FIG. 10 represents time, and the vertical axis of the graph represents current. "Incp" in FIG. 10(a) represents the output current obtained by simulating the operation of the three-phase inverter unit 11R using the real-time simulator of Prior Art 2. "Icp" in FIG. 10(b) represents the output current obtained by simulating the operation of the three-phase inverter unit 11R using the real-time simulator 1. "Iref" in FIGS. 10(a) and 10(b) represents the output current obtained by simulating the operation of the three-phase inverter unit 11R using ordinary simulation software (e.g., PSIM).

[0121] FIG. 11 is a diagram showing the effective value of the output current obtained by simulating the operation of the three-phase inverter unit 11R using the real-time simulator 1 according to this embodiment. The horizontal axis of the graph shown in FIG. 11 represents time, and the vertical axis of the graph represents the effective current value. "IRncp" in FIG. 11 represents the effective value of the output current obtained by simulating the operation of the three-phase inverter unit 11R using the real-time simulator of Prior Art 2. "IRcp" in FIG. 11 represents the effective value of the output current obtained by simulating the operation of the three-phase inverter unit 11R using the real-time simulator 1. "IRref" in FIG. 11 represents the effective value of the output current obtained by simulating the operation of the three-phase inverter unit 11R using ordinary simulation software (e.g., PSIM).

[0122] Due to limitations in computing power, real-time simulations have calculation intervals that are coarser than regular simulations. Therefore, regular simulations have higher simulation accuracy than real-time simulations. Therefore, the output current in the simulation results of regular simulations is closer to the output current of the actual three-phase inverter unit 11R than the output current in the simulation results of a real-time simulator. Therefore, in this embodiment, the output current Iref and the effective value IRef of the output current obtained by regular simulations are used as references for the simulation results of real-time simulator 1 and prior art 2.

[0123] As shown in Figure 10(a), the real-time simulator of conventional technology 2 does not take into account the on state of the freewheeling diodes Du and Dl during the dead time Td, so the output current Incp obtained by the real-time simulator of conventional technology 2 is shifted in the direction of a smaller current value overall than the reference output current Iref.

[0124] As shown in Figure 10(b), in the real-time simulator 1 of this embodiment, the on state of the freewheeling diodes Du and Dl during the dead time Td is taken into account, so the output current Icp obtained by the real-time simulator 1 is more consistent with the reference output current Iref than the output current Incp obtained by the real-time simulator of conventional technology 2.

[0125] As described above, the output current Incp obtained by the real-time simulator of Conventional Technology 2 is generally smaller than the reference output current Iref (see FIG. 10(a)). On the other hand, the output current Icp obtained by the real-time simulator 1 of this embodiment is closer to the output current Iref than the output current Incp. In other words, the output current Incp obtained by the real-time simulator of Conventional Technology 2 is more asymmetrical on the positive and negative sides with respect to the zero current than the output current Icp and the reference output current Iref. For this reason, as shown in FIG. 11, the effective value IRcp of the output current obtained by the real-time simulator 1 of this embodiment is closer to the effective value IRref of the reference output current than the effective value IRncp of the output current obtained by the real-time simulator of Conventional Technology 2.

[0126] As described above, the real-time simulator 1 according to this embodiment has improved calculation accuracy in simulating the operation of the three-phase inverter unit 11R compared to the real-time simulator of the prior art 2.

[0127] As described above, the real-time simulator 1 according to this embodiment includes the inverter simulator unit 11 that simulates the operation of the three-phase inverter unit 11R that converts DC voltage into AC voltage, the gate signal on-proportion calculation model 111M that calculates the first proportion value RV1 that is the proportion of the time during which the gate signal Sguu that controls the on-off operation of the transistor Qu of the transistors Qu, Ql of the semiconductor element units Suu, Slu that are connected in series and that are provided in the three-phase inverter unit 11R, reaches a signal level that turns the transistor Qu on, to a certain period of time, and the inverter simulator unit 11 that calculates the first proportion value RV1 that is the proportion of the time during which the gate signal Sguu that controls the on-off operation of the transistor Qu of the semiconductor element units Suu, Slu that are connected in series, reaches a signal level that turns the transistor Qu on, to a certain period of time. The model 112M includes a gate signal on-proportion calculation model that calculates a second proportion value RV2, which is the proportion of a certain period of time during which the gate signal Sglu, which controls the on / off operation of the transistor Ql of the transistors Qu and Ql, is at a signal level for turning the transistor Ql on, and a dead time proportion compensation model 113M that compensates the first proportion value RV1 or the second proportion value RV2 for a dead time proportion value DV, which is the proportion of a certain period of time during which the gate signals Sguu and Sglu are at a signal level for providing a dead time Td during which both the transistor Qu and the transistor Ql are in an off state.

[0128] In addition, the real-time simulation method according to this embodiment is provided in a three-phase inverter unit 11R that converts DC voltage to AC voltage. The three-phase inverter unit 11R converts DC voltage to AC voltage and has two serially connected transistors Qu and Ql. The real-time simulation method calculates a first percentage value which is the percentage of a certain period of time during which an upper arm gate signal Sgu, which controls the on / off operation of transistor Qu, is at a signal level for turning transistor Qu on; calculates a second percentage value which is the percentage of a certain period of time during which a lower arm gate signal Sgl, which controls the on / off operation of transistor Ql, is at a signal level for turning transistor Ql on; and compensates the first percentage value RV1 or the second percentage value RV2 with a dead time percentage value which is the percentage of a certain period of time during which the upper arm gate signal Sgu and the lower arm gate signal Sgl are at signal levels for providing a dead time Td during which both transistor Qu and transistor Ql are in an off state.

[0129] According to the real-time simulator 1 and real-time simulation method having such a configuration, it is possible to improve the accuracy of the simulation.

[0130] The technical scope of the present invention is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to the object of the present invention. Furthermore, the technical scope of the present invention is not limited to the combination of inventive features defined by the claims, but can be defined by any desired combination of specific features from among all the respective disclosed features. [Explanation of symbols]

[0131] 1. Real-time simulator 1R Power Conversion System 2R control section 3R monitor 11 Inverter Simulator 11Mu U phase voltage calculation model 11Mv V-phase voltage calculation model 11Mw W-phase voltage calculation model 11R Three-phase inverter 12M Input voltage setting model 12R DC power supply 13Mu, 13Mv, 13Mw current detection model 13Ru, 13Rv, 13Rw Current detection section 15 Motor Simulator Section 15R motor 16R capacitor 17R Voltage detection section 111M Gate signal on rate calculation model 112M Gate signal on rate calculation model 113M Dead Time Percentage Compensation Model 113Ma, 113Mf, 113Mg, 118M adder model 113Mb subtractor model 113Mc Comparator Model 113Md,113Me selection model 114M Divider Model 115M polarity reversal model 116M,117M multiplier model Dl,Du Freewheeling diode DV Dead Time Percentage Value FT fixed time LNR gate signal on rate MS Motor Drive System Ql,Qu transistor RV1 First Ratio Value RV2 Second Ratio Value Sgl Lower arm gate signal Sglu, Sglv, Sglw, Sguu, Sguv, Sguw gate signals Sgu Upper arm gate signal Slu, Slv, Slw, Suu, Suv, Suw Semiconductor Devices SS Simulation System Td Dead time UNR Gate signal on rate

Claims

1. a power converter simulator unit that simulates the operation of a power converter that converts DC voltage into AC voltage; a first control signal on-proportion calculation model that calculates a first proportion value that is a proportion of a time during which a first control pulse signal that controls an on / off operation of a first transistor of two transistors that are provided in the power conversion device and connected in series is at a signal level for turning the first transistor on, to a certain time; and a second control signal on-proportion calculation model that calculates a second proportion value that is a proportion of a time during which a second control pulse signal that controls an on / off operation of a second transistor of the two transistors is at a signal level for turning the second transistor on, to the certain time; and a dead time proportion compensation model that compensates the first proportion value or the second proportion value for a dead time proportion, which is a proportion of a time to the certain time during which the first control pulse signal and the second control pulse signal are at a signal level for providing a dead time during which both the first transistor and the second transistor are in an off state; A real-time simulator with

2. The dead-time percentage compensation model calculates the dead-time percentage value based on the first percentage value and the second percentage value. The real-time simulator according to claim 1 .

3. The dead time percentage compensation model calculates the dead time percentage value using the following equation (1): The real-time simulator according to claim 2. Dead time percentage value=100%−(the first percentage value+the second percentage value) (1)

4. a current detection model that is a simulation model of a current detection unit that detects an AC output current output from the power conversion device; The dead time percentage compensation model is When the polarity of the AC output current is positive, the first ratio value is compensated by the dead time ratio value; When the polarity of the AC output current is negative, the second ratio value is compensated by the dead time ratio value. The real-time simulator according to claim 1 .

5. The certain time period is an interval between calculations performed in the power converter simulator unit to simulate the operation of the power converter. A real-time simulator according to any one of claims 1 to 4.

6. a first ratio value being the ratio of a time during which a first control pulse signal for controlling an on / off operation of a first transistor of two transistors connected in series in a power conversion device that converts a DC voltage into an AC voltage is at a signal level for turning the first transistor on, to a fixed time; calculating a second ratio value which is a ratio of a time during which a second control pulse signal for controlling an on / off operation of a second transistor of the two transistors is at a signal level for turning the second transistor on to the certain time; a dead time ratio value, which is a ratio of a time to the certain time when the first control pulse signal and the second control pulse signal are at a signal level for providing a dead time in which both the first transistor and the second transistor are in an off state, is compensated for in the first ratio value or the second ratio value. Real-time simulation method.

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