Printed wiring board and method for manufacturing printed wiring board

Abstract

To improve the quality of a printed wiring board.SOLUTION: A printed wiring board comprises: a core substrate having a low-density region in which through-holes are formed at a relatively low density, and a high-density region in which through-holes are formed at a higher density than in the low-density region; a through-hole conductor inside each through-hole; a thick conductor layer formed on a first surface and a second surface of the core substrate in the low-density region; a thin conductor layer formed on the first surface and the second surface of the core substrate in the high-density region and thinner than the thick conductor layer; and a prepreg insulating layer made of prepreg, the prepreg insulating layer covering the first surface and the second surface of the core substrate, being thin at portions in contact with the low-density region and thick at portions in contact with the high-density region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed technology relates to a printed wiring board and a method for manufacturing a printed wiring board. [Background technology]

[0002] Patent Document 1 describes a wiring board formed by alternately laminating build-up insulating layers and build-up wiring layers on the top and bottom surfaces of a core substrate having a large number of through holes. In this wiring board, a first group of through holes is arranged at a first density in a first region of the core substrate, and a second group of through holes is arranged at a second density lower than the first density in a second region spaced apart from the first region on the periphery of the core substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-192432 Summary of the Invention [Problem to be solved by the invention]

[0004] In a printed wiring board having a core substrate with regions of different through-hole density (low-density regions and high-density regions), the conductor layer formed on the core substrate may be thick in the low-density regions and thin in the high-density regions. In this case, when a resin layer is laminated on the core substrate, the resin layer conforms to the thickness of the conductor layer, making it difficult to flatten the outer surface of the printed wiring board. [Means for solving the problem]

[0005] The printed wiring board of the present disclosure comprises a core substrate having a low-density region where through holes are formed at a relatively low density and a high-density region where the through holes are formed at a higher density than the low-density region, through-hole conductors inside the through holes, thick conductor layers formed on the first and second surfaces of the core substrate in the low-density region, thin conductor layers formed on the first and second surfaces of the core substrate in the high-density region and thinner than the thick conductor layers, and prepreg insulating layers covering the first and second surfaces of the core substrate, respectively, and being thin at the contact portions with the low-density region and thick at the contact portions with the high-density region.

[0006] A method for manufacturing a printed wiring board according to the present disclosure includes preparing a core substrate including a low-density region in which through-holes with through-hole conductors therein are formed at a relatively low density, a high-density region in which the through-holes are formed at a higher density than the low-density region, thick conductor layers formed on first and second surfaces in the low-density region, and thin conductor layers formed on the first and second surfaces in the high-density region and thinner than the thick conductor layers, laminating prepreg sheet materials on the first and second surfaces, and pressing the core substrate and the sheet materials together in a thickness direction.

[0007] According to the embodiments of the present disclosure, it is possible to flatten the outer surface of a printed wiring board having a core substrate with regions where the density of through holes varies. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a printed wiring board according to a first embodiment of the present disclosure. [Figure 2] 3A to 3C are cross-sectional views illustrating an example of a printed wiring board manufacturing process according to the first embodiment of the present disclosure. [Figure 3] 3A to 3C are cross-sectional views illustrating an example of a printed wiring board manufacturing process according to the first embodiment of the present disclosure. [Figure 4]3A to 3C are cross-sectional views illustrating an example of a printed wiring board manufacturing process according to the first embodiment of the present disclosure. [Figure 5] 3A to 3C are cross-sectional views illustrating an example of a printed wiring board manufacturing process according to the first embodiment of the present disclosure. [Figure 6] 3A to 3C are cross-sectional views illustrating an example of a printed wiring board manufacturing process according to the first embodiment of the present disclosure. [Figure 7] 3A to 3C are cross-sectional views illustrating an example of a printed wiring board manufacturing process according to the first embodiment of the present disclosure. [Figure 8] 3A to 3C are cross-sectional views illustrating an example of a printed wiring board manufacturing process according to the first embodiment of the present disclosure. [Figure 9] 3A to 3C are cross-sectional views illustrating an example of a printed wiring board manufacturing process according to the first embodiment of the present disclosure. [Figure 10] 3A to 3C are cross-sectional views illustrating an example of a printed wiring board manufacturing process according to the first embodiment of the present disclosure. [Figure 11] 3A to 3C are cross-sectional views illustrating an example of a printed wiring board manufacturing process according to the first embodiment of the present disclosure. [Figure 12] 3A to 3C are cross-sectional views illustrating an example of a printed wiring board manufacturing process according to the first embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an example of an embodiment of the present disclosure will be described in detail with reference to the drawings.

[0010] Components indicated by the same reference numerals in each drawing are the same or similar components. Duplicate descriptions and reference numerals in the embodiments described below may be omitted. All drawings used in the following description are schematic. The dimensional relationships, ratios, etc. of each element shown in the drawings do not necessarily match those in reality. The dimensional relationships, ratios, etc. of each element do not necessarily match between multiple drawings.

[0011] [First embodiment] FIG. 1 is a cross-sectional view showing a printed wiring board 10 according to an embodiment.

[0012] Printed wiring board 10 has core substrate 11, prepreg insulating layer 31, resin insulating layer 21, and conductive pattern 22. Core substrate 11 has a first surface 11F on the front side and a second surface 11S on the back side, i.e., the side opposite first surface 11F.

[0013] The core substrate 11 has an insulating base material 13K. The insulating base material 13K is made of prepreg. Prepreg is an intermediate material made by impregnating glass fiber or carbon fiber with BT (bismaleimide triazine) resin, epoxy resin, or the like. Note that the insulating base material 13K does not have to be made of prepreg, and may simply be made of resin.

[0014] 1, the insulating base material 13K is a single layer, but a plurality of insulating base materials 13K may be arranged in layers.

[0015] Through holes 15 are formed in the core substrate 11. The through holes 15 penetrate the insulating base material 13K in the thickness direction. As also shown in FIG. 2, the core substrate 11 has a low-density region LD and a high-density region HD. The high-density region HD is a region where the density of through holes 15 is higher than that of the low-density region LD. This density is the number of through holes 15 per unit area when the core substrate 11 is viewed in the normal direction to the first surface 11F. The opening cross-sectional area per through hole 15 is approximately the same in the low-density region LD and the high-density region HD.

[0016] In the disclosed technology, when core substrate 11 is viewed in the normal direction to first surface 11F, high-density region HD is located in the central portion of core substrate 11, and low-density region LD is located in the area surrounding high-density region HD. This is because the central portion of core substrate 11 viewed in the normal direction to first surface 11F is densely populated with through-hole conductors for supplying power to elements mounted on the surface of printed wiring board 10, forming high-density region HD.

[0017] A through-hole conductor 16 is formed inside each of the through holes 15. A hole-filling resin 17 is filled inside the through-hole conductor 16. A portion of the through-hole conductor 16 is exposed on the first surface 11F side and the second surface 11S side of the core substrate 11. In the low-density region LD, the portions of the through-hole conductor 16 exposed on the first surface 11F side and the second surface 11S side are thick conductor layers 32A. In the high-density region HD, the portions of the through-hole conductor 16 exposed on the first surface 11F side and the second surface 11S side are thin conductor layers 32U.

[0018] The thick conductor layers 32A are continuous with the through-hole conductors 16 in the low-density region LD. The thick conductor layers 32A are connected by the through-hole conductors 16 from the first surface 11F side to the second surface 11S side of the core substrate 11.

[0019] The thin conductor layers 32U are continuous with the through-hole conductors 16 in the high density region HD. The thin conductor layers 32U are connected by the through-hole conductors 16 from the first surface 11F side to the second surface 11S side of the core substrate 11.

[0020] The thin conductor layer 32U is thinner as a conductor layer than the thick conductor layer 32A. In the disclosed technology, the difference (conductor thickness difference) between the thickness T2 of the thick conductor layer 32A and the thickness T3 of the thin conductor layer 32U is 5 μm or more.

[0021] In the example shown in FIG. 1, in the thick conductor layer 32A, the thickness of the conductor layer at a position close to the center of the core substrate 11 gradually decreases toward the thin conductor layer 32U.

[0022] The thickness T2 of the thick conductor layer 32A and the thickness T3 of the thin conductor layer 32U can be measured, for example, by taking cross sections of the printed wiring board 10 at the positions of the thick conductor layer 32A and the thin conductor layer 32U.

[0023] On the outer surface of the core substrate 11 in the thickness direction, a conductor pattern 12 is formed on the insulating base material 13K at a position different from the thick conductor layer 32A and the thin conductor layer 32U.

[0024] Prepreg insulating layers 31 are formed on the first surface 11F and the second surface 11S of the core substrate 11. The prepreg insulating layers 31 are made of prepreg. Prepreg is an intermediate material in which a core material of glass fiber or carbon fiber is impregnated with a resin such as BT (bismaleimide triazine) resin or epoxy resin. The material that constitutes the prepreg insulating layer 31 is filled between the conductive patterns 12. The material that constitutes the prepreg insulating layer 31 is also filled between the thin conductive layers 32U and between the thick conductive layers 32A.

[0025] The prepreg constituting the prepreg insulating layer 31 contains glass fiber or carbon fiber. For example, when a cross section of the core substrate 11 is taken, the glass fiber or carbon fiber is exposed in the prepreg insulating layer 31.

[0026] The thickness of prepreg insulating layer 31 is relatively thin in the contact portion with low density region LD and relatively thick in the contact portion with high density region HD. In prepreg insulating layer 31, the surface opposite core substrate 11 is prepreg outer surface 31G.

[0027] One or more resin insulating layers 21 are formed on the prepreg insulating layer 31. In the example shown in FIG. 1, there are two resin insulating layers 21. The resin insulating layer 21 may be one layer or three or more layers. On the first surface 11F side and the second surface 11S side of the core substrate 11, multiple insulating layers, i.e., one prepreg insulating layer 31 and one or more resin insulating layers 21, are formed. Of these multiple insulating layers, only the insulating layers formed on the first surface 11F and the second surface 11S of the core substrate 11 are prepreg insulating layers 31. A solder resist layer 26 is formed on the outermost resin insulating layer 21. The resin insulating layer 21 does not contain a core material and is a resin film containing a resin such as an epoxy resin or a phenolic resin and an inorganic material such as silica or alumina.

[0028] Conductive patterns 22 are formed on the resin insulating layer 21. The resin material that constitutes the resin insulating layer 21 is filled between the conductive patterns 22.

[0029] The resin insulating layer 21 covers the conductive pattern 22 of the resin insulating layer 21 and the prepreg insulating layer 31 or the resin insulating layer 21 in the portion where the conductive pattern 22 is not formed. The resin material constituting the resin insulating layer 21 is filled between the conductive patterns 22.

[0030] Via holes 23 are formed in the resin insulating layer 21, penetrating the resin insulating layer 21 in the thickness direction. The via holes 23 are filled with plating to form via conductors 24.

[0031] Openings 27 are formed in the solder resist layer 26, penetrating the solder resist layer 26 in the thickness direction. Bumps 28 are formed in the openings 27. The bumps 28 are connected to the conductor patterns 12, 22, the thick conductor layer 32A, and the thin conductor layer 32U through via conductors 24.

[0032] Next, a description will be given of a method for manufacturing the printed wiring board 10. The printed wiring board 10 is manufactured as follows.

[0033] (1) As shown in Fig. 2, a core substrate 11 is prepared. This core substrate 11 has an insulating base material 13K and metal foils (not shown) on both sides of the insulating base material 13K. In this embodiment, the insulating base material 13K is made of prepreg. Through holes 15 are formed in the insulating base material 13K. The through holes 15 are denser in the central portion of the core substrate 11 than in the surrounding portion, forming a high-density region HD and a low-density region LD.

[0034] A through-hole conductor 16 is formed on the inner wall of the through-hole 15. The inside of the through-hole conductor 16 is filled with a hole-filling resin 17. The insulating base material 13K is made of, for example, a cured prepreg made by impregnating glass fiber or carbon fiber with BT (bismaleimide triazine) resin, epoxy resin, or the like.

[0035] (2) Portions of the through-hole conductors 16 are exposed on the first surface 11F and the second surface 11S of the core substrate 11. The exposed portions of the through-hole conductors 16 are the thin conductor layer 32U or the thick conductor layer 32A. There is a difference in thickness between the thin conductor layer 32U (thickness T3) and the thick conductor layer 32A (thickness T2). Therefore, both the first surface 11F and the second surface 11S of the core substrate 11 are gently curved with the central portions of each surface, i.e., the portions corresponding to the high-density regions HD, concave. It can also be said that the central portion of the core substrate 11 is relatively thin compared to the peripheral portions.

[0036] (3) A conductive pattern 12 is further formed on the insulating base material 13K.

[0037] (4) As shown in Fig. 3, a prepreg insulating layer 31 is formed on the first surface 11F and the second surface 11S of the core substrate 11. Specifically, a prepreg sheet material 35 and a metal foil (not shown) are laminated on the first surface 11F and the second surface 11S of the core substrate 11. By pressing the core substrate 11 and the sheet material 35 in the thickness direction, the sheet material 35 is integrated with the core substrate 11, and the prepreg insulating layer 31 is formed.

[0038] In this embodiment, the resin that constitutes the prepreg of prepreg insulating layer 31 is thermosetting. Before core substrate 11 and prepreg insulating layer 31 are pressed together, the prepreg is in a semi-cured state. Because prepreg sheet material 35 is laminated by pressing, the outer surface after lamination is more likely to be flat than when resin insulating layer 21 is laminated.

[0039] The prepreg core substrate 11 and the prepreg sheet material 35 are laminated and pressed in the thickness direction. The prepreg outer surface 31G of the formed prepreg insulating layer 31 is flat. This "flat" means that the surface is relatively flat compared to when a resin insulating layer made of resin is formed in the same position as the prepreg insulating layer 31 instead of the prepreg insulating layer 31 made of prepreg.

[0040] The prepreg insulating layer 31 is relatively thin at the contact portion with the low-density region LD and relatively thick at the contact portion with the high-density region HD. The prepreg outer surface 31G is flatter than the outer surface of the insulating layer when the insulating layer is made of a resin other than prepreg.

[0041] (5) As shown in FIG. 4, via holes 23 are formed in the prepreg insulating layer 31 by laser processing.

[0042] (6) An electroless plating process is performed, and electroless plated film 33 is formed on prepreg insulating layer 31 and in via hole 23. In via hole 23, electroless plated film 33 contacts the portion of through-hole conductor 16 that is exposed from first surface 11F and second surface 11S, i.e., thick conductor layer 32A or thin conductor layer 32U.

[0043] Since prepreg outer surface 31G of prepreg insulating layer 31 is flat, it is easy to form electroless plated film 33 with an even thickness.

[0044] (7) As shown in FIG. 5, a plating resist 34 having a predetermined pattern is formed on the electroless plated film 33.

[0045] (8) An electrolytic plating process is carried out, and the via holes 23 are filled with electrolytic plating to form via conductors 24.

[0046] (9) As shown in Fig. 6, the plating resist 34 is peeled off and the electroless plated film 33 below the plating resist 34 is removed. Then, the remaining electroless plated film 33 forms the conductive pattern 22.

[0047] (10) As shown in Fig. 7, a resin insulating layer 21 is formed on the prepreg insulating layer 31 and on the conductor pattern 22. The resin material that constitutes the resin insulating layer 21 is filled between the conductor patterns 22. The resin insulating layer 21 covers the conductor patterns 22 and the prepreg insulating layer 31 in the portions where the conductor patterns 22 are not formed.

[0048] The resin insulating layer 21 is made of, for example, a resin film that does not contain a core material and contains an inorganic filler.

[0049] (11) As shown in FIG. 8, via holes 23 are formed in the resin insulating layer 21 by laser processing.

[0050] (12) An electroless plating process is carried out to form an electroless plated film 33 on the resin insulating layer 21 and in the via hole 23.

[0051] (13) As shown in FIG. 9, a plating resist 34 having a predetermined pattern is formed on the electroless plated film 33.

[0052] (14) An electrolytic plating process is carried out, and the via holes 23 are filled with electrolytic plating to form via conductors 24.

[0053] (15) As shown in Figure 10, the plating resist 34 is peeled off and the electroless plated film 33 below the plating resist 34 is removed. The remaining electroless plated film 33 then forms the conductive pattern 22.

[0054] (16) The same processes as those in the above-mentioned steps (10) to (15) are carried out. As shown in Fig. 11, a predetermined number of resin insulating layers 21 and conductive patterns 22 are formed on both the front and back surfaces.

[0055] (17) Solder resist layers 26 are formed on both the first surface 11F and the second surface 11S of core substrate 11. Via holes 23 are formed in solder resist layer 26. Electrolytic plating is performed inside via holes 23 in solder resist layer 26, and the via holes 23 are filled with the electrolytic plating to form bumps 28 (see FIG. 1). In this way, printed wiring board 10 shown in FIG. 1 is completed.

[0056] [Other embodiments] In the above embodiment, the core substrate 11 may be configured to include a plurality of layers of insulating base material 13K.

[0057] Furthermore, the printed wiring board of the technology of the present disclosure is not limited to the structures illustrated in the drawings and the structures, shapes, and materials illustrated in this specification. As described above, the printed wiring board of the embodiment may have any laminate structure. The printed wiring board of the embodiment may include any number of conductor layers and insulating layers.

[0058] The method for manufacturing a printed wiring board according to the technology of the present disclosure is not limited to the method described with reference to the drawings. Furthermore, each insulating layer may be formed using a resin in any form, not limited to a film-like resin. The method for manufacturing a printed wiring board according to the embodiment may include any additional process in addition to the above-described processes, or some of the above-described processes may be omitted. [Explanation of symbols]

[0059] 10 Printed wiring board 11 Core board 11F Front page 11S second side 12 Conductor pattern 13K insulating substrate 15 through holes 16 through-hole conductor 17 Hole-filling resin 21 Resin insulation layer 22 Conductor pattern 23 Beer Hall 24 via conductor 26 Solder resist layer 27 Opening 28 Bump 31 Prepreg insulating layer 31G Prepreg outer surface 32A thick conductor layer 32U thin conductor layer 33 Electroless plating film 34 Resist

Claims

1. a core substrate including a low-density region in which through-holes are formed at a relatively low density, and a high-density region in which the through-holes are formed at a higher density than the low-density region; a through-hole conductor inside the through-hole; a thick conductor layer formed on the first surface and the second surface of the core substrate in the low-density region; a thin conductor layer formed on the first surface and the second surface of the core substrate in the high-density region, the thin conductor layer being thinner than the thick conductor layer; a prepreg insulating layer covering each of the first surface and the second surface of the core substrate, the prepreg insulating layer being thin at a contact portion with the low-density region and thick at a contact portion with the high-density region; A printed wiring board having

2. 2. The printed wiring board according to claim 1, the high density region is located in a central portion of the core substrate; The low density region is located at a portion surrounding the high density region.

3. 2. The printed wiring board according to claim 1, the thick conductor layer is continuous with the through-hole conductors in the low-density region; The thin conductor layer is continuous from the through-hole conductors in the high density region.

4. 2. The printed wiring board according to claim 1, The difference between the thickness of the thick conductor layer and the thickness of the thin conductor layer is 5 μm or more.

5. 2. The printed wiring board according to claim 1, A plurality of resin insulating layers not including a core material are formed on the prepreg insulating layer.

6. 2. The printed wiring board according to claim 1, Of the multiple insulating layers formed on the first surface side and the second surface side of the core substrate, only the insulating layers formed on the first surface and the second surface of the core substrate are the prepreg insulating layers.

7. preparing a core substrate including a low-density region in which through holes with through-hole conductors therein are formed at a relatively low density, a high-density region in which the through holes are formed at a higher density than the low-density region, thick conductor layers formed on a first surface and a second surface in the low-density region, and thin conductor layers formed on the first surface and the second surface in the high-density region and thinner than the thick conductor layers; Laminating a prepreg sheet material on the first surface and the second surface; pressing the core substrate and the sheet material together in a thickness direction; A method for manufacturing a printed wiring board comprising:

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