Semiconductor device, multi-phase DC / DC converter and power supply device

Abstract

To improve uniformity of current supplied to a load in a multi-phase DC / DC converter and a power supply device including a semiconductor device.SOLUTION: In a semiconductor device (200), a control signal supply part (22) acquires setting information for setting a controller part (21) and adjusts a control signal (Scr) so that fluctuation of load current (Iout) obtained by synthesizing currents outputted from all output parts (300) is suppressed based on the setting information and adjustment current value information (Icp).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, and to a multiphase DC / DC converter and a power supply device that include the semiconductor device. [Background technology]

[0002] A multiphase DC / DC converter is configured to provide multiple channels of output stage circuits, each having a switching transistor, a coil, and a rectifying element, and to obtain a single stabilized output current by driving the switching transistors of the multiple output stage circuits with a phase difference (see Patent Document 1, etc.). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-165138

[0004] [overview] In the multi-phase DC / DC converters described above, there is an increasing demand for improving the uniformity of the current supplied to the load.

[0005] According to one aspect of the present disclosure, a semiconductor device includes a controller that outputs a PWM signal to each of a plurality of output units, a control signal supply unit that supplies a control signal to the controller unit for generating the PWM signal, and a processing unit that acquires current values ​​of currents output from the output units and supplies the current values ​​to the control signal supply unit as current value information. The control signal supply unit is configured to acquire setting information for setting the controller unit, and adjust the control signal based on the setting information and the current value information so as to suppress fluctuations in a load current obtained by combining the currents output from all of the output units. [Brief explanation of the drawings]

[0006] [Figure 1]FIG. 1 is an overall configuration diagram of a DC / DC converter according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a circuit diagram showing the configuration of the output section. [Figure 3] FIG. 3 is a diagram showing various signals in a state where the current output from the output section is being adjusted. [Figure 4] FIG. 4 is a flowchart showing a procedure for adjusting a control signal by the controller unit. [Figure 5] FIG. 5 is a circuit diagram showing the configuration of an output section of a modified example.

[0007] [Detailed explanation]

[0008] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings referred to, the same parts are designated by the same reference numerals, and duplicated descriptions of the same parts will be omitted as a general rule.

[0009] First, some terms used in describing the embodiments of the present disclosure will be explained. A line refers to a wiring through which an electrical signal is propagated or applied. A ground refers to a reference conductive part having a reference voltage of 0V (zero volts), or refers to the voltage of 0V itself. The reference conductive part is formed of a conductor such as metal. A voltage of 0V is sometimes referred to as a ground voltage. In the embodiments of the present disclosure, a voltage indicated without a particular reference represents a voltage seen from ground.

[0010] In this specification, a MOS (Metal Oxide Semiconductor) field effect transistor refers to a transistor whose gate structure is composed of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with a low resistance, an insulating layer, and a P-channel, N-channel, or intrinsic semiconductor layer. In other words, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of metal, oxide, and semiconductor.

[0011] <Multiphase DC / DC Converter 100> Fig. 1 is an overall configuration diagram of a multi-phase DC / DC converter 100 according to an embodiment of the present disclosure. Fig. 2 is a circuit diagram showing the configuration of an output unit 300. In the multi-phase DC / DC converter 100 shown in Fig. 1, a DC input voltage VDD is supplied to an input line 101. A load Z is connected to an output line 102 of the multi-phase DC / DC converter 100, and output currents IL output from the output units 300 of the respective channels are combined and supplied to the load Z.

[0012] The multiphase DC / DC converter 100 is configured with i-channel (i is an integer equal to or greater than 2) switching output stages. The number of channels i is arbitrary and may be determined depending on the load, for example, 2 channels, 3 channels, 4 channels, 6 channels, 8 channels, 12 channels, 16 channels, etc. Note that the multiphase DC / DC converter 100 of this embodiment will be described as having three channels. The multiphase DC / DC converter 100 has a control unit 200 and three output units 300. Note that in the following description, channel numbers will be indicated by subscripts as necessary. For example, the components constituting channel CH2 will be indicated as output unit 300_2, output current IL_2, etc.

[0013] The multi-phase DC / DC converter 100 is used as a power supply device that supplies a load current Iout to a load Z.

[0014] <Output unit 300> The output unit 300 is provided in the channels CH1, CH2, and CH3. An example of the output unit 300 will now be described with reference to the drawings. FIG. 2 is a diagram of an example of the output unit 300. As shown in FIG. 2, the output unit 300 has a driver MOS 31, an inductor 32, and a current detection unit 33. The output unit 300 includes a step-down output stage circuit that outputs a voltage lower than the input voltage VDD.

[0015] 2, the driver MOS 31 has a configuration in which a MOS transistor and a driver unit that drives the MOS transistor are integrated together. The driver MOS 31 has a high-side MOS transistor 311, a low-side MOS transistor 312, and a driver unit 313 connected in series.

[0016] In the driver MOS 31, the high-side MOS transistor 311 and the low-side MOS transistor 312 are both N-channel MOS transistors. That is, the high-side MOS transistor 311 and the low-side MOS transistor 312 are turned on when a high-level signal is input to their gates.

[0017] The high-side MOS transistor 311 and the low-side MOS transistor 312 are connected in series. That is, the source of the high-side MOS transistor 311 and the drain of the low-side MOS transistor 312 are connected at a connection point P1.

[0018] The drain of the high-side MOS transistor 311 is connected to an input terminal to which an input voltage VDD is supplied. The source of the low-side MOS transistor 312 is connected to a ground terminal for a ground voltage GND via a current detection resistor 331 (described later).

[0019] The driver unit 313 generates a high-side gate signal HG and a low-side gate signal LG so that the high-side MOS transistor 311 and the low-side MOS transistor 312 are controlled to be ON / OFF complementarily in accordance with a PWM (Pulse Width Modulation) signal Spwm received from the controller unit 21. Note that "complementarily" refers to a state in which the high-side MOS transistor 311 and the low-side MOS transistor 312 are alternately turned ON / OFF.

[0020] The high level of the high-side gate signal HG is a voltage level that turns on the high-side MOS transistor 311. Similarly, the high level of the low-side gate signal LG is a voltage level that turns on the low-side MOS transistor 312.

[0021] The high-side gate signal HG and the low-side gate signal LG output from the driver unit 313 do not necessarily have to be completely switched between high and low levels. For example, they may include a dead time during which both the high-side MOS transistor 311 and the low-side MOS transistor 312 are in the off state.

[0022] In this embodiment, both the high-side MOS transistor 311 and the low-side MOS transistor 312 are N-channel MOS transistors, but this is not limiting. The high-side MOS transistor may be a P-channel MOS transistor and the low-side MOS transistor may be an N-channel MOS transistor. In this case, the high-side MOS transistor is turned on when the high-side gate signal HG is at a low level.

[0023] A first end of an inductor 32 is connected to a connection point P1 between the high-side MOS transistor 311 and the low-side MOS transistor 312. Second ends of the inductors 32 of each channel are connected together at a connection point P2, and a first end of an output capacitor C1 is connected to the connection point. A second end of the output capacitor C1 is connected to a ground potential. The connection point P2, where the second ends of the inductors 32 of each channel are connected together, is connected to the output line 102. The output capacitor C1 smoothes the output currents IL_1, IL_2, and IL_3 from the output units 300 of each channel. The output currents IL_1, IL_2, and IL_3 from the output units 300 of each channel are combined at the connection point P2 and supplied to the load Z as a load current Iout.

[0024] The current detection unit 33 also supplies a current detection signal Ain, which includes information about the current value of the output current IL output from the output unit 300, to a signal switching unit 27 (described later) of the control unit 200. The current detection unit 33 includes a current detection resistor 331 and a signal generation unit 332. The signal generation unit 332 acquires a voltage drop across the current detection resistor 331. The signal generation unit 332 then estimates the output current IL based on the voltage drop and generates the current detection signal Ain. Note that the current detection unit 33 is not limited to this configuration, and for example, a configuration in which detection is based on a magnetic field generated around a wiring when a current flows through the wiring can be adopted. Note that the current detection unit 33 is not limited to this configuration, and a wide variety of methods can be adopted that can accurately acquire the current value of the output current IL.

[0025] <Control unit 200> The control unit 200 is a functional IC (Integrated Circuit) integrated on a single semiconductor substrate. The control unit 200 supplies a PWM signal Spwm for controlling the high-side MOS transistor 311 and the low-side MOS transistor 312 of each channel to the driver unit 313 of the driver MOS 31 of each output unit 300. The PWM signal Spwm is a signal that determines the value of a current output from the output unit 300. More specifically, the value of the output current IL output from the output unit 300 is determined according to a duty ratio, which is the ratio of the on state of the PWM signal Spwm.

[0026] As shown in FIG. 1, the control unit 200 includes a controller unit 21, a control signal supply unit 22, a processing unit 23, a phase information notification unit 24, a frequency information notification unit 25, a memory unit 26, a signal switching unit 27, and an AD converter unit 28.

[0027] <Controller section 21> The controller unit 21 has a PWM signal generation unit 211 corresponding to each channel. The PWM signal generation unit 211 generates a PWM signal Spwm based on the control signal Scr received from the control signal supply unit 22, and outputs the PWM signal Spwm to the output unit 300 of the corresponding channel. Note that the control signal Scr includes information on the on-duty value of the output current IL output from the output unit 300. Therefore, the PWM signal generation unit 211 generates a PWM signal Spwm with the same duty as the duty value included in the control signal Scr.

[0028] <Memory unit 26> The memory unit 26 is a memory unit that stores various types of information used for the control of the control unit 200. As the memory unit 26, for example, a memory device such as a RAM (Random Access Memory), a flash memory, etc., capable of writing and reading information can be adopted. The processing unit 23 stores a current value corresponding to the current value information Din output from the AD converter unit 28 described later in the memory unit 26. In the memory unit 26, each current value from the latest current value to the current value a predetermined number of times before is stored in association with each channel.

[0029] <Signal switching unit 27> The signal switching unit 27 receives the current detection signals Ain_1, Ain_2, Ain_3 from the output units 300_1, 30_2, 30_3 of each channel. Then, the signal switching unit 27 sends the received current detection signals Ain_1, Ain_2, Ain_3 to the AD converter unit 28 at the received timing.

[0030] Note that the current detection signal Ain from the output unit 300 of each channel is output from the output unit 300 according to the timing when the output current IL output from the output unit 300 is output. That is, the current detection signal Ain from each output unit 300 is input to the signal switching unit 27 at a timing corresponding to the phase shift of the output of the output current IL from the output unit 300.

[0031] <AD converter unit 28> The current detection signal Ain is an analog signal. The AD converter unit 28 converts the analog current detection signal Ain into digital current value information Din. The digital current value information Din converted by the AD converter unit 28 is sent to the processing unit 23.

[0032] <Processing section 23> The processing unit 23 associates the acquired current value information Din with the channel and the timing of acquisition and stores it in the storage unit 26. When the current value information Din is supplied from the AD converter unit 28, the processing unit 23 erases the oldest current value from among the current values ​​stored in the storage unit 26. When new current value information Din is acquired, the processing unit 23 acquires the channel of the output unit 300 that supplied the new current value information Din. The processing unit 23 then reads the current values ​​stored in the storage unit 26 and calculates the arithmetic mean of multiple current values ​​including the most recent current value. The arithmetic mean value is then output to the control signal supply unit 22 as adjustment current information Icp to be used for adjustment. The processing unit 23 may store the adjustment current information Icp in the storage unit 26. By using the adjustment current information Icp supplied from the processing unit 23, excessive adjustment due to the detection of an unexpectedly large or small current value can be prevented.

[0033] The processing unit 23 acquires the phase information Sph from the phase information notification unit 24 and the frequency information Shz from the frequency information notification unit 25. Then, the processing unit 23 operates to suppress adjustment of the control signal Scr by the current detection signal Ain detected before the output current IL is output from the output unit 300 based on the control signal Scr output by the control signal supply unit 22. The operation of the processing unit 23 will be described in detail later.

[0034] <Control signal supply unit 22> The control signal supplying unit 22 supplies a control signal Scr, which is a signal specifying the output current IL output by the output unit 300 of each channel, to the PWM signal generating unit 211 of each channel. The control signal supplying unit 22 generates the control signal Scr based on the current value information Din and the duty of the PWM signal Spwm as setting information.

[0035] <Phase information notification unit 24> The phase information notification unit 24 holds phase information Sph of the PWM signal Spwm output from the PWM signal generation unit 211 and supplied to the output unit 300 of each channel. The phase information Sph is an example of setting information. The phase information notification unit 24 supplies the phase information Sph of the PWM signal Spwm supplied to the output unit 300 of each channel to the control signal supply unit 22. As described above, the PWM signals Spwm supplied to the output unit 300 of each channel are shifted in phase by 120 degrees. The phase information notification unit 24 is configured to receive adjustment current information Icp from the processing unit 23. The phase information notification unit 24 supplies the control signal supply unit 22 with phase information Sph including information on the time (timing) at which the control signal Scr supplied to the PWM signal generation unit 211 of each channel is output.

[0036] <Frequency information notification unit 25> The frequency information notification unit 25 holds frequency information Shz of the PWM signal Spwm output from the PWM signal generation unit 211 and supplied to the output unit 300 of each channel. The frequency information Shz is an example of setting information. The frequency information notification unit 25 supplies the frequency information Shz to the control signal supply unit 22.

[0037] <Control signal supply unit 22> The control signal supplying unit 22 acquires adjustment current information Icp from the processing unit 23. The adjustment current information Icp is information indicating the current value of the output current IL output from the output unit 300 of each channel. The control signal supplying unit 22 generates a control signal Scr based on the adjustment current information Icp, the current target value Itg, the phase information Sph, and the frequency information Shz, and supplies the control signal Scr to the PWM signal generating unit 211.

[0038] In the multi-phase DC / DC converter 100, the output current IL output from the output unit 300 of each channel fluctuates within a certain range. The output capacitor C1 smooths this fluctuation in the output current IL to some extent, but smoothing can be difficult when the fluctuation is large. For example, if peaks or valleys of the output currents IL_1, IL_2, and IL_3 output from the output units 300 of each channel overlap, the peaks or valleys are amplified. As a result, the output capacitor C1 cannot sufficiently smooth the current, and the load current Iout may fluctuate. To suppress such fluctuations in the load current Iout due to fluctuations in the current output from the output unit 300, the multi-phase DC / DC converter 100 adjusts the output timing of the output current IL output from the output unit 300 of each channel so that it is staggered.

[0039] In the multi-phase DC / DC converter 100, the output timing of the output current IL is adjusted to be equally spaced. The output timing of the output current IL is expressed in terms of phase. That is, in the multi-phase DC / DC converter 100, since the number of channels i is 3, the phases of the output timing of the output currents IL_1, IL_2, and IL_3 output from the output units 300 of the respective channels are shifted by 120 degrees.

[0040] The control unit 200 and the multi-phase DC / DC converter 100 including the same have the configurations described above.

[0041] <Operation of multiphase DC / DC converter 100> The multi-phase DC / DC converter 100 is controlled so that the output current IL output from each of the output sections 300 of the channels is approximately the same. Here, the operation of adjusting the current for the output section 300 of one channel will be described with reference to the drawings.

[0042] 3 shows the load current Iout of the multi-phase DC / DC converter 100, the output current IL output from the output unit 300, the PWM signal Spwm, the output timing Sct of the control signal Scr, and the acquisition timing Sig of the current detection signal Ain. Note that the waveforms shown in FIG. 3 are simplified, exaggerated, or emphasized for ease of understanding.

[0043] As described above, the output currents IL_1, IL_2, IL_3 output from the output units 300_1, 300_2, 300_3 are generated to have the same frequency. The output currents IL_1, IL_2, IL_3 are generated based on the PWM signals Spwm_1, Spwm_2, Spwm_3 from the PWM signal generation units 211_1, 211_2, 211_3 of the controller unit 21. The rising edges of the PWM signals Spwm_1, Spwm_2, Spwm_3 are adjusted to be 120 degrees out of phase with each other.

[0044] The control signal supply unit 22 compares the adjustment current information Icp with the current target value Itg each time it outputs a control signal Scr to the output unit 300 of each channel, and adjusts the control signal Scr based on the comparison result. As shown in FIG. 3, the output timing of the control signal Scr is indicated by the pulse-like output timing Sct. The output timing Sct of each channel is shifted in phase by 120 degrees. Furthermore, the output timing Sct of the control signal Scr and the rising timing of the PWM signal Spwm are shifted.

[0045] The signal generating unit 332 of the current detecting unit 33 of the output unit 300 of each channel is configured to output the current detection signal Ain every time the acquisition timing Sig rises. For example, if the output timing Sct of the control signal Scr and the acquisition timing Sig of the current detection signal Ain have approximately the same frequency, the adjustment current information Icp acquired every time the current detection signal Ain is detected can be used to adjust the control signal Scr.

[0046] 3, if the frequency of the acquisition timing Sig of the current detection signal Ain is greater than the frequency of the output timing Sct of the control signal Scr, the current detection signal Ain may be acquired and the control signal Scr may be newly adjusted before the output current IL adjusted by the control signal Scr is output. In other words, if the control signal Scr is adjusted at the timing when the current detection signal Ain is detected, the adjustment may be excessive, making it impossible for the output current IL to be smoothed by the output capacitor C1, and causing the load current Iout to fluctuate.

[0047] In the multi-phase DC / DC converter 100, excessive adjustment of the control signal Scr is suppressed by not performing adjustment based on the detected current detection signal Ain before the output current IL based on the adjusted control signal Scr is output, thereby suppressing fluctuations in the load current Iout in the multi-phase DC / DC converter 100.

[0048] As shown in FIG. 3, in the multi-phase DC / DC converter 100, the detection timing of the current detection signal Ain is assumed to be more frequent than the output timing Sct of the control signal Scr.

[0049] 4, the processing unit 23 acquires current value information Din by converting the current detection signal Ain acquired in accordance with the acquisition timing Sig using the AD converter unit 28 (step S101). The current detection signals Ain from the output unit 300 of each channel are sequentially sent to the processing unit 23 in accordance with predetermined acquisition timings Sig_1, Sig_2, and Sig_3.

[0050] The processing unit 23 sends adjustment current information Icp to the control signal supplying unit 22 so that adjustment is performed once every time the output currents IL_1, IL_2, IL_3 are output from the output units 300_1, 300_2, 300_3 of the respective channels.

[0051] 4, the processing unit 23 acquires the phase information Sph from the phase information notification unit 24 and the frequency information Shz from the frequency information notification unit 25 (step S102). Then, the processing unit 23 identifies the channel of the output unit 300 from which the acquired current value information Din was sent (step S103).

[0052] Then, the processing unit 23 determines whether a predetermined time has elapsed since the output of the previous control signal Scr corresponding to the current value information Din, based on the phase information Sph and frequency information Shz corresponding to each channel (step S104). Here, the predetermined time is, for example, a time during which the control signal supplying unit 22 can change the control signal Scr at the timing of the rising edge of the next PWM signal.

[0053] If the processing unit 23 determines that the predetermined time has not elapsed (No in step S104), the processing unit 23 determines that adjusting the control signal Scr using the latest current value information Din would result in excessive adjustment, and does not use the latest current value information Din. Then, the processing returns to step S101 and continues.

[0054] If the processing unit 23 determines that the predetermined time has elapsed (Yes in step S104), the processing unit 23 stores the latest current value information Din in the storage unit 26 (step S105). At this time, the processing unit 23 deletes the oldest current value information Din stored in the storage unit 26. Then, the processing unit 23 reads out all of the current value information Din stored several times before in the storage unit 26, and calculates an arithmetic mean together with the latest current value information Din. Then, the processing unit 23 transmits the result of the arithmetic mean of the current value information Din to the control signal supply unit 22 as adjustment current information Icp (step S106).

[0055] The control signal supplying unit 22 determines whether or not adjustment of the output current IL output from the output unit 300 is necessary based on the adjustment current information Icp (step S107). The output current IL output from the output unit 300 has a target current value. The target current value is determined by the current value required by the load. The output current IL is smoothed by the output capacitor C1, so it is permissible for the output current IL to deviate slightly from the target current value. Since the current value information Din is information corresponding to the output current IL, the control signal supplying unit 22 has a current target value Itg to be compared with the current value information Din.

[0056] Therefore, in step S107, the control signal supply unit 22 determines whether adjustment is necessary based on, for example, whether the difference value of the current value information Din from the current target value Itg exceeds a threshold value. Note that this is not limited to this, and the necessity may be determined by determining whether the output current IL can be output so as to obtain a load current Iout with little fluctuation, in other words, a uniform load current Iout.

[0057] If the control signal supplying unit 22 determines that adjustment of the output current IL is not necessary (No in step S107), the control signal supplying unit 22 does not adjust the current control signal Scr, and outputs the control signal Scr to the output unit 300 (step S111). After step S111, the process returns to step S101 and continues. Also, if the control signal supplying unit 22 determines that adjustment of the output current IL is necessary (Yes in step S107), the control signal supplying unit 22 compares the current value information Din with the current target value Itg (step S108).

[0058] If the current value information Din is greater than the current target value Itg (Yes in step S108), the control signal supply unit 22 adjusts the control signal Scr to reduce the output current IL (step S109). The control signal supply unit 22 outputs the adjusted control signal Scr to the output unit 300 (step S111). After step S111, the process returns to step S101 and continues.

[0059] Furthermore, if the current value information Din is smaller than the current target value Itg (No in step S108), the control signal supply unit 22 adjusts the control signal Scr to reduce the output current IL (step S110). The control signal supply unit 22 outputs the adjusted control signal Scr to the output unit 300 (step S111). After step S111, the process returns to step S101 and continues.

[0060] If the current value information Din is greater than the current target value Itg, the control signal supplying unit 22 adjusts the control signal Scr to reduce the duty of the PWM signal Spwm. If the current value information Din is smaller than the current target value Itg, the control signal supplying unit 22 adjusts the control signal Scr to increase the duty of the PWM signal Spwm. The control signal supplying unit 22 adjusts the current value information Din to approach the current target value Itg, thereby suppressing fluctuations in the load current Iout.

[0061] The control signal supplying unit 22 acquires a current detection signal Ain corresponding to the output current IL output from the output unit 300 of each channel. The output current IL is adjusted using the current detection signal Ain corresponding to the actual output current IL, so that the load current Iout can be made uniform even if the temperature, power supply voltage, load current, frequency, or number of phases fluctuates.

[0062] <Modification> 5 is a circuit diagram showing the configuration of a modified output section 400. As shown in FIG. 5, the modified output section 400 has a driver MOS 41, an inductor 42, a current detection section 43, and a diode 44.

[0063] The driver MOS 41 has a configuration in which a MOS transistor and a driver section are integrated, similar to the driver MOS 31. The driver MOS 41 has a MOS transistor 411 and a driver section 412. Here, the MOS transistor 411 is an N-channel MOS transistor, but may be a P-channel MOS transistor.

[0064] In the output unit 400, an input voltage VDD is supplied to a first end of an inductor 42. A second end of the inductor 42 is connected to a drain of a MOS transistor 411 at a connection point P3. A source of the MOS transistor 411 is connected to a ground voltage GND via a current detection resistor 431 of a current detection unit 43.

[0065] A PWM signal Spwm is input to the driver unit 412. The driver unit 412 generates a gate signal SG based on the PWM signal Spwm and supplies the gate of the MOS transistor 411. The MOS transistor 411 is controlled to be turned on / off in accordance with the gate signal SG.

[0066] The anode of the diode 44 is connected to the connection point P3, and the cathodes of the diodes 44 of each channel are joined at the connection point P2, to which the output capacitor C1 is connected. The current detection unit 43 has the same configuration as the current detection unit 33 of the output unit 300. That is, the current detection resistor 431 and the signal generation unit 432 of the current detection unit 43 have the same configuration as the current detection resistor 331 and the signal generation unit 332 of the current detection unit 33.

[0067] As described above, the output unit 400 is a step-up output stage circuit. Therefore, the output unit 400 can be used when the rated voltage of the load Z is high.

[0068] <Other> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present disclosure is defined by the claims, not by the description of the above-described embodiments. Furthermore, it should be understood that all modifications within the meaning and scope of the claims are included.

[0069] <Additional Notes> The semiconductor device (200) described above includes a controller unit (21) configured to output a PWM signal (Spwm) to each of a plurality of output units (300, 400); a control signal supply unit (22) configured to supply a control signal (Scr) for generating a PWM signal (Spwm) to the controller unit (21); a processing unit (23) configured to acquire a current value of the current (IL) output from each output unit (300) and supply it to a control signal supply unit (22) as adjustment current value information (Icp); The control signal supply unit (22) is configured (first configuration) to acquire setting information for setting the controller unit (21), and adjust the control signal (Scr) based on the setting information and adjustment current value information (Icp) so as to suppress fluctuations in the load current (Iout) obtained by combining the currents output from all the output units (300).

[0070] In the semiconductor device (100) of the first configuration, the control signal supply unit (22) is configured (second configuration) to acquire, as setting information, phase information (Sph) of the PWM signal (Spwm) output to each output unit (300, 400), and generate a control signal (Scr) to adjust the PWM signal (Spwm).

[0071] In the semiconductor device (200) of the first or second configuration, the control signal supply unit (22) is configured to acquire frequency information (Shz) of the PWM signal (Spwm) output to each output unit (300, 400) as setting information, and generate a control signal (Scr) to adjust the PWM signal (Spwm) (third configuration).

[0072] The semiconductor device (200) having any one of the first to third configurations includes a storage unit (26) configured to store current value information (Din) acquired up to a predetermined number of times before the latest current value information (Din) in association with the output unit (300, 400), The processing unit (23) is configured (fourth configuration) to supply an average value calculated based on the current value (Din) stored in the memory unit (26) and the newly acquired current value information (Din) as adjustment current value information (Icp) to the control signal supply unit (22) when new current value information (Din) is acquired.

[0073] In the multiphase DC / DC converter (100) described above, a semiconductor device (200) having any one of the first to fourth configurations, a plurality of output sections (300, 400) each having a driver MOS (31, 41) in which MOS transistors (311, 312, 411) and driver sections (313, 412) that drive the MOS transistors (311, 312, 411) are integrated; The semiconductor device (200) outputs a PWM signal (Spwm) to each output section (300, 400), This is a configuration (fifth configuration) in which output currents (IL) from a plurality of output sections (300, 400) are combined.

[0074] The power supply device described above has a configuration (sixth configuration) that includes the multiphase DC / DC converter (100) of the fifth configuration and supplies a load current (Iout) obtained by combining output currents (IL) to a load (Z). [Explanation of symbols]

[0075] 100 Multiphase DC / DC Converter 101 Input Line 102 output lines 200 control section 21 Controller section 211 PWM signal generation section 22 Control signal supply unit 23 Processing section 24 Phase information notification unit 25 Frequency information notification unit 26 Memory section 27 Signal switching section 28 AD converter section 300 Output section 31 Driver MOS 311 High-side MOS transistor 312 Low-side MOS transistor 313 Driver section 32 Inductor 33 Current detection section 331 Current detection resistor 332 Signal Generation Unit 400 Output Section 411 MOS transistor 412 Driver section 41 Driver MOS 42 Inductor 43 Current detection section 431 Current detection resistor 432 Signal Generation Unit 44 Diode Ain Current detection signal Din current value information C1 Output capacitor CH1, CH2, CH3 channels HG High-side gate signal LG Low side gate signal SG Gate signal IL Output current Icp adjustment current information Iout Load current Itg Current target value Scr control signal Sct output timing Shz frequency information Sig acquisition timing Sph phase information Spwm PWM signal Z load

Claims

1. a controller configured to output a PWM signal to each of a plurality of outputs; a control signal supply unit configured to supply a control signal for generating the PWM signal to the controller unit; a processing unit configured to acquire current value information of the current output from each of the output units and supply the information to the control signal supply unit as adjustment current value information, The control signal supply unit acquires setting information for setting the controller unit, and adjusts the control signal based on the setting information and the adjustment current value information so as to suppress fluctuations in a load current that is a combination of currents output from all of the output units.

2. 2. The semiconductor device according to claim 1, wherein the control signal supply unit acquires, as the setting information, phase information of a PWM signal output to each of the output units, and generates the control signal so as to adjust the PWM signal.

3. 2. The semiconductor device according to claim 1, wherein the control signal supplying section acquires frequency information of a PWM signal to be output to each of the output sections as the setting information, and generates the control signal so as to adjust the PWM signal.

4. a storage unit configured to store the current value information acquired up to a predetermined number of times before the latest current value in association with the output unit; 2. The semiconductor device according to claim 1, wherein the processing unit is configured to supply, to the control signal supply unit as the adjustment current value information, an average value calculated based on the current value information stored in the memory unit and the newly acquired current value information when the current value information is newly acquired.

5. A semiconductor device according to any one of claims 1 to 4, a plurality of output sections configured to have a driver MOS in which a MOS transistor and a driver section that drives the MOS transistor are integrated; the semiconductor device is configured to output a PWM signal to each output section; A multi-phase DC / DC converter configured to combine output currents of a plurality of said outputs.

6. A multiphase DC / DC converter according to claim 5 is provided, a power supply device configured to supply a load with a load current that is a combination of the output currents;

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