Semiconductor integrated circuit

Abstract

To provide a semiconductor integrated circuit that can suppress characteristic variation due to a secular change.SOLUTION: A memory 130 stores a first adjustment value CAL1. A main circuit 110 generates a main signal S1 adjusted according to the first adjustment value CAL1 stored in the memory 130 in a normal mode. A backup circuit 120 is a replica of the main circuit 110, and is capable of generating a backup signal S2 corresponding to the main signal S1 in an internal calibration mode upon failure of the main circuit 110. A first switch SW1 is provided at a power supply line of the backup circuit 120 and is turned ON upon failure of the main circuit 110 or in the internal calibration mode. A correction circuit 140 generates the first adjustment value CAL1 so that properties of the main signal S1 is brought closer to properties of the backup signal S2 in the internal calibration mode, and stores the first adjustment value CAL1 into the memory 130.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor integrated circuits. [Background technology]

[0002] The accuracy of reference circuits, such as reference voltage sources, reference current sources, and reference oscillators, integrated into semiconductor integrated circuits is improving. However, the characteristics of these reference circuits (voltage value, current value, oscillation frequency) tend to drift over time for various reasons.

[0003] The causes of drift include mechanical stress and electrical stress due to the voltage and current applied to semiconductor integrated circuits. When these stresses are combined with environmental factors such as temperature and humidity, the deterioration of electrical characteristics over time accelerates.

[0004] In particular, the state in which an electrical bias is applied to a circuit's transistors is a major factor in the deterioration of circuit characteristics over time. Electrical bias causes changes in characteristics due to factors such as TDDB (Time Dependent Dielectric Breakdown: breakdown of oxide (insulating) film) over time, hot carriers due to hot electron injection, and NBTI (Negative Bias Temperature Instability). Changes in resistance during the process of metal wire breakage or short circuit due to electromigration and ion migration also affect circuit characteristics over time.

[0005] Fluctuations in characteristics and destruction of semiconductor integrated circuits due to aging are a major problem in applications that require high safety and reliability, such as automotive equipment, industrial equipment, medical equipment, aerospace equipment, and military equipment (including consumer products that affect human life).

[0006] In devices and systems that require a high level of safety, methods to enhance safety through redundant systems are used as functional safety. For example, in ASIL (Automotive Safety Integrity Level), TMR (Triple Module Redundancy) and DMR (Dual-Mode Redundancy) are used in designs with the highest safety levels. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 2017-208667

[0008] [overview] The present disclosure has been made in light of the above-mentioned circumstances, and an exemplary purpose of an embodiment thereof is to provide a semiconductor integrated circuit capable of suppressing fluctuations in characteristics due to aging.

[0009] A semiconductor integrated circuit according to one embodiment includes a memory that stores a first adjustment value, a main circuit that generates a main signal adjusted according to the first adjustment value stored in the memory in a normal mode, a first auxiliary circuit that is a replica of the main circuit and is capable of generating a first auxiliary signal equivalent to the main signal when the main circuit fails or in an internal calibration mode, a first switch that is provided in a power supply line of the first auxiliary circuit and turns on when the main circuit fails or in the internal calibration mode, and a correction circuit that generates a first adjustment value and stores it in the memory in the internal calibration mode so that the characteristics of the main signal approach the characteristics of the first auxiliary signal.

[0010] Any combination of the above components, or mutual substitution of the components or expressions of the present disclosure between methods, devices, systems, etc., are also valid aspects of the present disclosure. [Brief explanation of the drawings]

[0011] [Figure 1]FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to an embodiment. [Figure 2] FIG. 2 is a diagram illustrating the normal mode of the semiconductor integrated circuit of FIG. [Figure 3] FIG. 3 is a diagram for explaining an abnormal mode of the semiconductor integrated circuit of FIG. [Figure 4] FIG. 4 is a diagram illustrating an internal calibration mode of the semiconductor integrated circuit of FIG. [Figure 5] FIG. 5 is a circuit diagram of a redundant circuit according to the first embodiment. [Figure 6] FIG. 6 is a circuit diagram of a redundant circuit according to the second embodiment. [Figure 7] FIG. 7 is a circuit diagram of a redundant circuit according to a third embodiment.

[0012] [Detailed explanation] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. Furthermore, this summary is not an exhaustive overview of all possible embodiments, nor does it limit essential elements of the embodiments. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0013] A semiconductor integrated circuit according to one embodiment includes a memory that stores a first adjustment value, a main circuit that generates a main signal adjusted according to the first adjustment value stored in the memory in a normal mode, a first auxiliary circuit that is a replica of the main circuit and is capable of generating a first auxiliary signal equivalent to the main signal when the main circuit fails or in an internal calibration mode, a first switch that is provided in a power supply line of the first auxiliary circuit and turns on when the main circuit fails or in the internal calibration mode, and a correction circuit that generates a first adjustment value and stores it in the memory in the internal calibration mode so that the characteristics of the main signal approach the characteristics of the first auxiliary signal.

[0014] With this configuration, by using the spare circuit in the standby multiple redundant system as a generator of a reference signal for internal calibration, it is possible to add a function to correct characteristic fluctuations due to aging without a significant increase in cost while maintaining the functional safety of the multiple redundant system. As a result, in addition to the safety of the equipment and system, a long lifespan is achieved and high reliability is achieved at low cost.

[0015] In one embodiment, the semiconductor integrated circuit may further include an input terminal for receiving an external calibration signal corresponding to the main signal from an external device in an external calibration mode. The memory may be capable of storing a second adjustment value, the first auxiliary circuit may be configured to generate a first auxiliary signal adjusted according to the second adjustment value stored in the memory, and the correction circuit may be configured to optimize the first adjustment value in the external calibration mode so that the main signal approaches the external calibration signal and optimize the second adjustment value so that the first auxiliary signal approaches the external calibration signal, and store the optimized first adjustment value and second adjustment value in the memory.

[0016] This configuration provides a high-precision trimming function before shipping in addition to a function to correct characteristic fluctuations due to aging. Also, by providing a first switch in the power supply line of the first auxiliary circuit and keeping it off during normal operation, it is possible to delay aging of the first auxiliary circuit and ensure its performance as a calibration signal generator in internal calibration mode.

[0017] In one embodiment, the semiconductor integrated circuit may further include a second switch that is a replica of the first switch and is provided on the power supply line of the main circuit. By adding the second switch, the electrical operating conditions of the main circuit and the backup circuit can be made uniform, and the difference in characteristic fluctuations between the main circuit and the backup circuit can be reduced even in circuits that are susceptible to fluctuations in the power supply voltage.

[0018] In one embodiment, the semiconductor integrated circuit may further include a third switch that is provided on a power supply line of the correction circuit and is turned on when the correction circuit is in operation.

[0019] In one embodiment, the memory may be capable of storing a third adjustment value. The semiconductor integrated circuit may further include a second auxiliary circuit that is a replica of the main circuit and is capable of generating a second auxiliary signal equivalent to the main signal adjusted according to the third adjustment value when the main circuit fails or in an internal calibration mode. In the internal calibration mode, the correction circuit may generate and store the third adjustment value in the memory so that characteristics of the second auxiliary signal approach characteristics of the first auxiliary signal.

[0020] In one embodiment, the main circuit and the first auxiliary circuit are a reference voltage source, a voltage regulator, or a reference current source, and the characteristic may be a voltage level or a current amount.

[0021] In one embodiment, the main circuit and the first auxiliary circuit may be oscillators and the characteristic may be a frequency.

[0022] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be designated by the same reference numerals, and redundant descriptions will be omitted where appropriate. Furthermore, the embodiments are illustrative and do not limit the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0023] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0024] Similarly, "a state in which component C is provided between component A and component B" includes not only cases in which components A and C, or components B and C, are directly connected, but also cases in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the functions or effects achieved by their combination.

[0025] 1 is a circuit diagram of a semiconductor integrated circuit 10 according to an embodiment. The semiconductor integrated circuit 10 is designed for use in applications requiring high reliability, and includes a redundant circuit 100 and a functional block 20. The redundant circuit 100 generates a signal Sout that is of high importance in the semiconductor integrated circuit 10. The type of this signal Sout is not particularly limited, but examples include a reference signal such as a reference voltage or a reference current, a power supply voltage, and a clock signal.

[0026] The functional block 20 is configured to receive the output signal Sout of the redundancy circuit 100 and execute processing according to the type of the semiconductor integrated circuit 10. The type and function of the functional block 20 are not limited in any way in this disclosure.

[0027] The redundant circuit 100 is designed as a standby dual redundant type to enhance reliability against failures, and includes a main circuit 110 and a backup circuit 120. The main circuit 110 generates a main signal S1 corresponding to the output signal Sout.

[0028] The backup circuit 120 is a replica of the main circuit 110 and is capable of generating a backup signal S2 equivalent to the main signal S1 when the main circuit 110 fails.

[0029] In normal mode, the output selector 150 outputs the main signal S1 generated by the main circuit 110 as the output signal Sout. When the main circuit 110 fails, the output selector 150 outputs the backup signal S2 generated by the backup circuit 120 as the output signal Sout. The output selector 150 may include multiple switches, but the actual configuration is not limited to this. If the output signal Sout is an analog signal, the switches may be analog switches (also called transfer gates or CMOS switches). If the output signal Sout is a digital signal or a pulse signal, the switches may be configured with logic gates.

[0030] The state of the output selector 150 may be controlled by a host controller external to the semiconductor integrated circuit 10. Specifically, switching from the main circuit 110 to the backup circuit 120 may be performed when an error in the semiconductor integrated circuit 10 is detected or when the output signal of the semiconductor integrated circuit 10 exceeds an allowable range.

[0031] Alternatively, the state of the output selector 150 may be controlled by the semiconductor integrated circuit 10 itself. Specifically, the output signal Sout may be monitored, and if the characteristics of the output signal Sout exceed an allowable range, switching may be performed from the main circuit 110 to the backup circuit 120.

[0032] The above is the basic configuration of the standby dual type redundant circuit 100.

[0033] In this embodiment, the standby circuit 120 is not only used as a backup for the main circuit in a standby dual redundant system, but also as a reference circuit for correcting aging deterioration of the main circuit 110. The operation mode for correcting aging deterioration of the main circuit 110 is called an internal calibration mode.

[0034] In relation to the correction of aging deterioration, the redundancy circuit 100 further includes a memory 130, a correction circuit 140, and a selector 160.

[0035] The memory 130 is a nonvolatile memory and stores a first adjustment value CAL1. In normal mode, the main circuit 110 generates a main signal S1 adjusted according to the first adjustment value CAL1 stored in the memory 130. Aging deterioration of the main circuit 110 can be canceled out by changing the first adjustment value CAL1.

[0036] Since the standby circuit 120 is a replica of the main circuit 110, the standby circuit 120 outputs a standby signal S2 that can be adjusted according to a second adjustment value CAL2 stored in a memory 130, similar to the main circuit 110.

[0037] In the manufacturing process or inspection process of the redundant circuit 100, the first adjustment value CAL1 and the second adjustment value CAL2 are optimized so that the characteristics of the main signal S1 and the backup signal S2 match the design values, and the optimized first adjustment value CAL1 and second adjustment value CAL2 are written as initial values ​​into the memory 130. Examples of the characteristics of the main signal S1 and the backup signal S2 include the voltage level, the amount of current, and the frequency.

[0038] The first switch SW1 is provided on the power supply line of the backup circuit 120. The first switch SW1 is turned off in a normal mode in which the main circuit 110 operates normally. The first switch SW1 is turned on during a period in which the backup circuit 120 should operate, specifically, when the main circuit 110 fails or in an internal calibration mode.

[0039] The correction circuit 140 becomes active in the internal calibration mode. The semiconductor integrated circuit 10 may transition to the internal calibration mode in response to an instruction from a host controller external to the semiconductor integrated circuit 10. For example, the host controller may use a timer to generate a trigger for the internal calibration mode every time a predetermined time elapses. Alternatively, the host controller may monitor the state of the semiconductor integrated circuit 10 or the state of the entire system including the semiconductor integrated circuit 10, and generate a trigger for the internal calibration mode if it detects any abnormality.

[0040] In the internal calibration mode, the first switch SW1 is turned on, and both the main circuit 110 and the backup circuit 120 operate. The correction circuit 140 generates a first adjustment value CAL1 so that the characteristics of the main signal S1 approach the characteristics of the backup signal S2. During the internal calibration mode, the selector 160 selects the adjustment value CAL0 generated by the correction circuit 140 instead of the first adjustment value CAL1 stored in the memory 130.

[0041] The correction circuit 140 may include, for example, a characteristic comparison circuit 142 and a correction circuit 144. The characteristic comparison circuit 142 detects an error between the characteristics of the reference auxiliary signal S2 and the main signal S1 that is the target of optimization. The correction circuit 144 optimizes the adjustment value CAL0 so that the error between the characteristics of the two signals S1 and S2 approaches zero.

[0042] The first adjustment value CAL1 in the memory 130 is updated with the optimized adjustment value CAL0.

[0043] The above is the configuration of the semiconductor integrated circuit 10. Next, the operation thereof will be described.

[0044] 2 is a diagram illustrating the normal mode of the semiconductor integrated circuit 10 of FIG. 1. In the normal mode, the selector 160 selects the first adjustment value CAL1 stored in the memory 130 and supplies it to the main circuit 110. The main circuit 110 generates a main signal S1 based on the first adjustment value CAL1. The main signal S1 is supplied to the functional block 20 via the output selector 150 as an output signal Sout.

[0045] In normal mode, the backup circuit 120 is in a standby state. The first switch SW1 is in an off state, and no power supply voltage is supplied to the backup circuit 120. In other words, no electrical bias is applied to the circuit elements, such as transistors and resistors, that make up the backup circuit 120. Therefore, while the backup circuit 120 is in standby mode, application of electrical stress to the backup circuit 120 can be prevented, and deterioration of the backup circuit 120 over time can be suppressed. This ensures performance as a reference circuit in internal calibration mode.

[0046] 3 is a diagram illustrating the abnormal mode of the semiconductor integrated circuit 10 of FIG. 1. In the abnormal mode, the first switch SW1 is turned on, the power supply voltage is supplied to the backup circuit 120, and the backup circuit 120 becomes active. The backup circuit 120 generates a backup signal S2 based on the second adjustment value CAL2. The backup signal S2 is supplied to the functional block 20 via the output selector 150 as the output signal Sout.

[0047] In the abnormal mode, the main circuit 110 may be stopped or may be left operating.

[0048] 4 is a diagram illustrating the internal calibration mode of the semiconductor integrated circuit 10 of FIG. 1. In the internal calibration mode, the first switch SW1 is turned on, a power supply voltage is supplied to the auxiliary circuit 120, and the auxiliary circuit 120 becomes active. The auxiliary circuit 120 generates an auxiliary signal S2 based on the second adjustment value CAL2. As described above, in the normal mode, the first switch SW1 is turned off, and deterioration over time of the auxiliary circuit 120 is suppressed. Therefore, the auxiliary signal S2 is considered to have characteristics close to the design values, and is therefore used as an internal calibration signal for generating the main signal S1.

[0049] The main signal S1 is supplied to the correction circuit 140 together with the auxiliary signal S2. In the internal calibration mode, the main circuit 110 operates according to the adjustment value CAL0 generated by the correction circuit 140, and the correction circuit 140 optimizes the adjustment value CAL0 so that the characteristics of the main signal S1 approach the characteristics of the auxiliary signal S2, which is a calibration signal. The first adjustment value CAL1 in the memory 130 is then updated by the optimized adjustment value CAL0.

[0050] During the internal calibration mode, the redundancy circuit 100 may stop generating the output signal Sout, or the output selector 150 may select the spare signal S2 or the main signal S1 as the output signal Sout.

[0051] The above is the operation of the semiconductor integrated circuit 10. With this semiconductor integrated circuit 10, it is possible to add a function to correct characteristic fluctuations due to aging without a significant increase in cost while maintaining functional safety through multiple redundant systems. As a result, in addition to safety, long life is achieved for devices and systems at low cost, and high reliability is achieved.

[0052] The present disclosure covers various devices and methods that can be understood as the block diagram or circuit diagram of Figure 1 or derived from the above description, and is not limited to a specific configuration. Below, more specific configuration examples and examples will be described not to narrow the scope of the present disclosure, but to aid in understanding and clarify the essence and operation of the present disclosure and the present invention.

[0053] 5 is a circuit diagram of a redundant circuit 100A according to a first embodiment. The redundant circuit 100A includes a second switch SW2 in addition to the redundant circuit 100 of FIG. 1. The second switch SW2 is a replica having the same characteristics as the first switch SW1, and is provided on the power supply line of the main circuit 110. The first switch SW1 is turned on while the main circuit 110 is operating.

[0054] According to the first embodiment, by providing the first switch SW1, the main circuit 110 and the backup circuit 120 can have the same substantial circuit configuration and operating conditions, and the difference in characteristic fluctuations between the main circuit and the backup circuit due to fluctuations in the power supply voltage can be suppressed.

[0055] 6 is a circuit diagram of a redundant circuit 100B according to a second embodiment. A semiconductor integrated circuit 10B including the redundant circuit 100B has an input terminal (external input pin) IN. In an external calibration mode, an external calibration signal Sref corresponding to the main signal S1 is input from the outside to the input terminal IN. The external calibration mode is performed, for example, in a manufacturing process or an inspection process of the semiconductor integrated circuit 10B, and is used to generate initial values ​​for the first adjustment value CAL1 and the second adjustment value CAL2.

[0056] In the external calibration mode, the correction circuit 140B optimizes the first adjustment value CAL1 so that the main signal S1 approaches the external calibration signal Sref. The correction circuit 140B also optimizes the second adjustment value CAL2 so that the auxiliary signal S2 approaches the external calibration signal Sref. The optimized first adjustment value CAL1 and second adjustment value CAL2 are stored in the memory 130.

[0057] Specifically, when calibrating the main signal S1 in the external calibration mode, the switch SW12 of the selector 160 and the switches SW21 and SW24 of the selector 146 are turned on.

[0058] Specifically, when the preliminary signal S2 is calibrated in the external calibration mode, the switch SW11 of the selector 160 and the switches SW22 and SW24 of the selector 146 are turned on.

[0059] When calibrating the main signal S1 in the internal calibration mode, the switch SW12 of the selector 160 and the switches SW21 and SW23 of the selector 146 are turned on.

[0060] The semiconductor integrated circuit 10B further includes a third switch SW3. The third switch SW3 is provided on the power supply line of the correction circuit 140B and is turned on when the correction circuit 140B is in operation.

[0061] According to the second embodiment, in addition to the function of correcting characteristic variations due to aging, it is possible to provide a high-precision trimming function at the time of shipment.

[0062] Fig. 7 is a circuit diagram of a redundant circuit 100C according to a third embodiment. The redundant circuit 100C in Fig. 7 is a standby triple redundant circuit or a combination of a parallel dual redundant system and a standby dual redundant system, and includes two systems: a first standby circuit 120_1 and a second standby circuit 120_2. The first standby circuit 120_1 corresponds to the standby circuit 120 in Fig. 1.

[0063] The memory 130C can store a third adjustment value CAL3. The second backup circuit 120_2 is a replica of the main circuit 110 and can generate a second backup signal S2_2 corresponding to the main signal S1 adjusted according to the third adjustment value CAL3 when the main circuit 110 fails or in an internal calibration mode.

[0064] In the internal calibration mode, the correction circuit 140C generates a third adjustment value CAL3 and stores it in the memory 130 so that the characteristics of the second preliminary signal S2_2 approach the characteristics of the first preliminary signal S2_1.

[0065] The embodiments described using specific terms merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted to the embodiments as long as they do not deviate from the spirit of the present invention as defined in the claims.

[0066] (Addendum) The present specification discloses the following techniques.

[0067] (Item 1) a memory for storing a first adjustment value; a main circuit that generates a main signal adjusted in accordance with the first adjustment value stored in the memory in a normal mode; a first backup circuit that is a replica of the main circuit and is capable of generating a first backup signal corresponding to the main signal when the main circuit fails or in an internal calibration mode; a first switch that is provided on a power supply line of the first auxiliary circuit and that is turned on when the main circuit fails or in the internal calibration mode; a correction circuit that generates the first adjustment value and stores the first adjustment value in the memory in the internal calibration mode so that the characteristics of the main signal approach the characteristics of the first auxiliary signal; A semiconductor integrated circuit comprising:

[0068] (Item 2) further comprising an input terminal for receiving an external calibration signal corresponding to the main signal from the outside in the external calibration mode; the memory is capable of storing a second adjustment value; the first auxiliary circuit is configured to generate the first auxiliary signal adjusted according to the second adjustment value stored in the memory; 2. The semiconductor integrated circuit according to claim 1, wherein, in the external calibration mode, the correction circuit optimizes the first adjustment value so that the main signal approaches the external calibration signal, optimizes the second adjustment value so that the first auxiliary signal approaches the external calibration signal, and stores the optimized first adjustment value and second adjustment value in the memory.

[0069] (Item 3) 3. The semiconductor integrated circuit according to item 1 or 2, further comprising a second switch that is a replica of the first switch and is provided on a power supply line of the main circuit.

[0070] (Item 4) 4. The semiconductor integrated circuit according to any one of items 1 to 3, further comprising a third switch provided in a power supply line of the correction circuit and turned on when the correction circuit is in operation.

[0071] (Item 5) the memory is capable of storing a third adjustment value; The semiconductor integrated circuit comprises: a second auxiliary circuit that is a replica of the main circuit and is capable of generating a second auxiliary signal that corresponds to the main signal and is adjusted according to the third adjustment value when the main circuit fails or in the internal calibration mode; 5. The semiconductor integrated circuit according to claim 1, wherein in the internal calibration mode, the correction circuit generates the third adjustment value and stores the third adjustment value in the memory so that the characteristics of the second preliminary signal approach the characteristics of the first preliminary signal.

[0072] (Item 6) 6. The semiconductor integrated circuit according to any one of items 1 to 5, wherein the main circuit and the first auxiliary circuit are a reference voltage source, a voltage regulator, or a reference current source, and the characteristic is a voltage level or a current amount.

[0073] (Item 7) 6. The semiconductor integrated circuit according to any one of items 1 to 5, wherein the main circuit and the first auxiliary circuit are oscillators, and the characteristic is a frequency. [Explanation of symbols]

[0074] 10. Semiconductor Integrated Circuits 20 Functional Blocks 100 redundant circuits 110 Main Circuit 120 spare circuit 120_1 First auxiliary circuit 120_2 Second auxiliary circuit SW1 First switch 130 memory 140 Correction circuit 142 Characteristics comparison circuit 144 Correction Circuit 146 Selector 150 Output Selector 160 Selector S1 Main signal S2 Auxiliary signal S2_1 First auxiliary signal S2_2 Second auxiliary signal CAL1 First adjustment value CAL2 Second adjustment value CAL3 Third adjustment value

Claims

1. a memory for storing a first adjustment value; a main circuit that generates a main signal adjusted in accordance with the first adjustment value stored in the memory in a normal mode; a first backup circuit that is a replica of the main circuit and is capable of generating a first backup signal corresponding to the main signal when the main circuit fails or in an internal calibration mode; a first switch that is provided on a power supply line of the first auxiliary circuit and that is turned on when the main circuit fails or in the internal calibration mode; a correction circuit that generates the first adjustment value and stores the first adjustment value in the memory so that the characteristics of the main signal approach the characteristics of the first auxiliary signal in the internal calibration mode; A semiconductor integrated circuit comprising:

2. further comprising an input terminal for receiving an external calibration signal corresponding to the main signal from the outside in the external calibration mode; the memory is capable of storing a second adjustment value; the first auxiliary circuit is configured to generate the first auxiliary signal adjusted according to the second adjustment value stored in the memory; 2. The semiconductor integrated circuit according to claim 1, wherein, in the external calibration mode, the correction circuit optimizes the first adjustment value so that the main signal approaches the external calibration signal, optimizes the second adjustment value so that the first auxiliary signal approaches the external calibration signal, and stores the optimized first adjustment value and second adjustment value in the memory.

3. 3. The semiconductor integrated circuit according to claim 1, further comprising a second switch that is a replica of said first switch and is provided on a power supply line of said main circuit.

4. 3. The semiconductor integrated circuit according to claim 1, further comprising a third switch provided in a power supply line of said correction circuit, said third switch being turned on when said correction circuit is in operation.

5. the memory is capable of storing a third adjustment value; The semiconductor integrated circuit comprises: a second auxiliary circuit that is a replica of the main circuit and is capable of generating a second auxiliary signal that corresponds to the main signal and is adjusted according to the third adjustment value when the main circuit fails or in the internal calibration mode; 3. The semiconductor integrated circuit according to claim 1, wherein the correction circuit generates the third adjustment value in the internal calibration mode so that characteristics of the second preliminary signal approach characteristics of the first preliminary signal, and stores the third adjustment value in the memory.

6. 3. The semiconductor integrated circuit according to claim 1, wherein the main circuit and the first auxiliary circuit are a reference voltage source, a voltage regulator, or a reference current source, and the characteristic is a voltage level or an amount of current.

7. 3. The semiconductor integrated circuit according to claim 1, wherein the main circuit and the first auxiliary circuit are oscillators, and the characteristic is a frequency.

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