Power supply controller for enhancing control loop stability and method herein

Abstract

To provide a control approach to improve system stability without degrading system bandwidth in a power converter.SOLUTION: A switch mode power supply controller includes circuitry to reduce gain variation of switching frequency as a function of control current. The controller may reduce gain variation of frequency by limiting the frequency according to on-time and off-time control relationships. In an analog implementation, the frequency is limited according to a switching period of an oscillator. On each cycle, an analog off-time modulator (OTM) may determine the oscillator off-time; while a comparator and sense element may determine, at least in part, the oscillator on-time. Together the oscillator off-time and on-time may set the switching period.SELECTED DRAWING: Figure 1B

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 648,398, filed May 16, 2024, which is incorporated herein by reference in its entirety.

[0002]

[0002] The present invention relates to power supply control devices, and more particularly to controlling switches in switching power converters. [Background technology]

[0003]

[0003] Switching mode power converters, also known as power converters or switch mode power supplies (SMPS), are commonly used due to their high efficiency, small size, and light weight. A flyback converter is an SMPS topology that provides isolation between the primary and secondary windings of an energy transfer element (e.g., a magnetic component or a coupled inductor). Components and circuits connected to and referenced to the primary winding are often referred to as primary-side components / circuits. Similarly, components and circuits connected to and referenced to the secondary winding are often referred to as secondary-side components / circuits. With this approach, a flyback converter is configured having a primary side and a secondary side.

[0004] A switching power supply / converter controller may be part of a closed-loop system for regulating output power as a function of one or more system signals (e.g., output voltage). A switching power converter controller, or simply "controller," may control switching. For example, a controller may control the switching of a primary switch in a flyback converter.

[0005]

[0005] During operation, a switch (e.g., a primary switch) is gated according to a switching cycle based on a system or controller configuration (e.g., a flyback configuration). The duty cycle (typically the ratio of the on-time of the switch to the total switching period), switching frequency, or number of pulses per unit time of the switch can be varied to regulate the output (e.g., output power) based on a detected feedback signal.

[0006]

[0006] System performance, including system stability, dynamic range, and system bandwidth, may depend at least in part on the manner in which a controller drives switches on and off. In many cases, system bandwidth may be degraded at the expense of improving system stability. Summary of the Invention

[0007] This disclosure presents a control approach for improving system stability without degrading system bandwidth in a power converter. The controller improves stability by reducing the variation in switching frequency in relation to one or more control or feedback signals. For example, the control signal may be a control current or a switch current, and the controller may control the switching period according to a control relationship (e.g., a control equation) for the on-time and off-time.

[0008] The controller may include circuitry for monitoring and controlling the on- and off-periods of an oscillator switching cycle according to a control relationship between the on- and off-periods. For example, during a selected cycle, an off-period modulator (OTM) may at least partially determine the oscillator off-period, while a comparator and detection element may at least partially determine the oscillator on-period.

[0009]

[0009] Non-limiting and non-exhaustive embodiments of a power converter for enhancing control loop stability are described with reference to the following figures, in which like reference numerals refer to like parts throughout the various drawings unless otherwise specified. [Brief explanation of the drawings]

[0010] [Figure 1A] FIG. 1A illustrates a flyback converter in accordance with the teachings herein. [Figure 1B]

[0011] FIG. 1B shows a schematic diagram of a controller and primary switch according to an embodiment of the present disclosure. [Figure 2A]

[0012] FIG. 2A illustrates a flyback control model according to an embodiment of the present disclosure. [Figure 2B]

[0013] FIG. 2B illustrates a flyback control model according to another embodiment of the present disclosure. [Figure 2C]

[0014] FIG. 2C illustrates a current control loop according to an embodiment of the present disclosure. [Figure 2D]

[0015] FIG. 2D illustrates a voltage control loop according to an embodiment of the present disclosure. [Figure 2E]

[0016] FIG. 2E illustrates a feedforward path according to an embodiment of the present disclosure. [Figure 3A]

[0017] FIG. 3A illustrates waveforms of a modulator signal, an oscillator signal, and a drive signal according to an embodiment of the present disclosure. [Figure 3B]

[0018] FIG. 3B illustrates waveforms of the modulator signal, oscillator signal, and drive signal according to an embodiment of the present disclosure. [Figure 3C]

[0019] FIG. 3C illustrates waveforms of the modulator signal, oscillator signal, and drive signal according to an embodiment of the present disclosure. [Figure 3D]

[0020] FIG. 3D illustrates waveforms of a modulator signal, an oscillator signal, and a drive signal according to an embodiment of the present disclosure. [Figure 4]

[0021] FIG. 4 illustrates an example circuit implementation of an oscillator according to an embodiment of the present disclosure. [Figure 5]

[0022] FIG. 5 illustrates an example circuit implementation of an off-period modulator according to an embodiment of the present disclosure. [Figure 6]

[0023] FIG. 6 illustrates an example circuit implementation of the control logic according to an embodiment of the present disclosure. [Figure 7]

[0024] FIG. 7 illustrates an example circuit implementation of a line interface circuit according to an embodiment of the present disclosure. [Figure 8]

[0025] FIG. 8 illustrates a gate-level circuit implementation of a switched current reference generator according to an embodiment of the present disclosure. [Figure 9A]

[0026] FIG. 9A shows a waveform according to an embodiment of the present disclosure. [Figure 9B]

[0027] FIG. 9B shows a waveform according to an embodiment of the present disclosure. [Figure 9C]

[0028] FIG. 9C shows a waveform according to an embodiment of the present disclosure. [Figure 9D]

[0029] FIG. 9D shows a waveform according to an embodiment of the present disclosure. [Figure 10A]

[0030] FIG. 10A shows a flowchart for driving the primary switch and for determining the oscillator turn-on period in accordance with the teachings herein. [Figure 10B]

[0031] FIG. 10B illustrates a flowchart for determining the oscillator switch-off period in accordance with the teachings herein. [Figure 10C]

[0032] FIG. 10C illustrates a conceptual flow diagram in accordance with the teachings herein. [Figure 11A]

[0033] FIG. 11A shows a plot of frequency versus control current according to a controller with large gain variations. [Figure 11B]

[0034] FIG. 11B shows a plot of frequency versus control current in accordance with the teachings herein. [Figure 12A]

[0035] FIG. 12A shows a plot of oscillator off-period versus input voltage showing different options for the scaling factor to compensate for the minimum off-period. [Figure 12B]

[0036] FIG. 12B compares plots of output power versus input voltage. DETAILED DESCRIPTION OF THE INVENTION

[0011]

[0037] Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Those skilled in the art will appreciate that the elements in the figures are drawn for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to better illustrate various embodiments of the teachings herein.

[0012]

[0038] Additionally, common but well-understood elements that are useful or necessary in commercially suitable embodiments are often not shown in the figures so as not to clutter the illustrations of these various embodiments of power converters for enhancing control loop stability.

[0013]

[0039] In the following description, numerous specific details are set forth to provide a thorough understanding of a power converter for enhancing control loop stability. However, it will be apparent to those skilled in the art that the specific details may not necessarily be used to practice the teachings herein. In other instances, well-known materials or methods have not been described in detail so as not to obscure the present disclosure.

[0014]

[0040] As mentioned above, a flyback converter is a type of switched-mode power supply topology. A flyback converter is an SMPS topology that includes isolation between the primary and secondary windings of an energy transfer element (e.g., a magnetic component or a coupled inductor). Components and circuits connected to and referenced to the primary winding are often referred to as primary-side components / circuits. Similarly, components and circuits connected to and referenced to the secondary winding are often referred to as secondary-side components / circuits. With this approach, a flyback converter is configured with a primary side and a secondary side.

[0015]

[0041] Additionally, as discussed above, the switches may be gated or controlled according to a switching cycle based on the system or controller configuration. During operation, switching power supplies often use one or more controllers to regulate and deliver power based on signal information, such as output voltage and / or current.

[0016]

[0042] In a flyback configuration, the controller may include a primary-side controller and / or a secondary-side controller, and may need to communicate signal information from the secondary side to the primary side. For example, to regulate the output power on the secondary side, the primary-side controller may need to receive the value of the output voltage on the secondary side.

[0017]

[0043] One way to communicate signal information is through an optocoupler. For example, a control current (e.g., a phototransistor current) can be generated by the optocoupler proportional to the output voltage.

[0018]

[0044] A control current (e.g., phototransistor current) may be provided to the primary-side controller, in response to which the primary-side controller may vary the switching of the primary-side switch to regulate / adjust the power (e.g., output power) and / or output voltage.

[0019]

[0045] One aspect of control is alternating current (AC) response and control loop stability. Control loop stability can be determined at least in part by the gain relationship of frequency as a function of control current. Unfortunately, the gain relationship can exhibit large variations as a function of control current, thereby complicating control loop stability and / or reducing the usable range of control current.

[0020]

[0046] Therefore, there is a need to develop a control circuit that reduces gain variation as a function of control current.

[0021]

[0047] According to the teachings herein, a switching power supply controller includes circuitry for reducing gain variation of the switching frequency as a function of the control current. The controller may reduce the gain variation of the frequency by limiting the frequency according to on-time and off-time control equations. In an analog implementation, the frequency is limited according to the switching period of an oscillator. In each cycle, an analog off-time modulator (OTM) may determine the oscillator off-time, while a comparator and detection element may at least partially determine the oscillator on-time. Together, the oscillator off-time and on-time may set the switching period.

[0022]

[0048] 1A illustrates a flyback converter 100 according to the teachings herein. The flyback converter 100 includes an energy transfer element 114. As described above, the energy transfer element 114 (e.g., a transformer and / or a coupled inductor / inductance) may provide isolation (i.e., galvanic isolation) between a primary side 115 and a secondary side 117. The primary side 115 is referenced to a primary ground GND, and the secondary side 117 is referenced to a secondary ground RTN.

[0023]

[0049] The flyback converter 100 further includes a feedback circuit 103 and a switcher circuit 105. The switcher circuit 105 may be an integrated switcher circuit 105 including a primary switch S1 and a controller 108. The switcher circuit 105 may receive a power supply voltage at a pin BP and may be connected to ground GND via a source pin S. Additionally, a control current Ic may be received at a control pin C, and a switch current I SW may be received at the drain of switch S1, also referred to as drain pin D.

[0024]

[0050] Additionally, the switcher circuit generates a current I v The current I v may be proportional to the input voltage VIN and may be referred to as the feedforward signal IV without departing from the scope of this disclosure.

[0025]

[0051] In accordance with the teachings herein, the controller 108 includes an off-period modulator that can at least partially determine the switching frequency of the switch S1.

[0026]

[0052] The feedback circuit 103 includes an optocoupler 102. The optocoupler 102 may communicate information related to the output voltage V from the secondary side 117 to the switcher circuit 105 on the primary side 115 by generating a current I (i.e., a phototransistor current I). The current I is a feedback signal indicative of the output voltage V and may also be referred to as a control current I without departing from the scope of this disclosure.

[0027]

[0053] 1B shows a schematic diagram of a controller 108 and a primary switch S1 according to an embodiment of the present disclosure. The controller 108 includes a line interface circuit 116, a switch current reference generator 118, an oscillator 120, an off-period modulator 122, and control logic 124. The line interface circuit 116 supplies a current I to the oscillator 120. VS and may provide a feedforward signal I without departing from the scope of this disclosure. VS It may also be called.

[0028]

[0054] The primary switch S1 may receive a drive signal DR in response to which a switch current I SW The drive signal DR may be a pulse modulated signal characterized by a square wave.

[0029]

[0055] The current sensing element 188 senses the switch current I SW The signal ISENS may be a current and may also be referred to as current ISENS without departing from the scope of this disclosure.

[0030]

[0056] The switch current reference generator 118 may provide the reference UCR. The reference UCR may be variable. For example, the reference UCR may vary according to the waveform of the drive signal DR.

[0031]

[0057] Oscillator 120 may generate oscillator signal OSC, which may be a pulse-modulated signal further characterized by a rectangular waveform.

[0032]

[0058] According to the teachings herein, the control logic 124 may provide a drive signal DR to the primary switch S1 such that the switching period of the drive signal DR is equal to the switching period of the oscillator signal.

[0033]

[0059] 2A illustrates a flyback control model 200 according to an embodiment of the flyback converter 100. The control model 200 represents a higher level of abstraction of the functionality of an embodiment of the flyback converter 100. The flyback control model 200 includes a primary switch S1, an energy transfer element 114, a behavioral feedback circuit 212, a behavioral off-period modulator 214, a behavioral oscillator 216, a comparator 218, an edge-triggered set-reset (SR) latch 222, a behavioral current-sensing element 288, and a load 210.

[0034]

[0060] The output power is delivered to the load 210 with a regulated output voltage VOUT and a load current IOUT, which may also be referred to as the output current IOUT without departing from the scope of this disclosure.

[0035]

[0061] The behavioral feedback circuit 212 may be a behavioral representation of the feedback circuit 103. The behavioral representation is intended to provide a simplified description of the function or behavior of an element to aid in understanding the present disclosure. The behavioral feedback circuit 212 provides a feedback signal (i.e., a control current Ic) that is indicative of the output voltage VOUT. Although the feedback signal (i.e., the control current Ic) is shown as a current, other types of feedback signals (e.g., a voltage) are possible. The behavioral feedback circuit 212 provides the control current Ic to the behavioral off-period modulator 214.

[0036]

[0062] The behavioral off-period modulator 214 may be a behavioral representation of the off-period modulator 122. The behavioral off-period modulator 214 may generate a modulator signal MOD including pulses of a modulation width TMOD expressed in units of time. Although the modulation width TMOD is shown as being generated from a modulator signal MOD that is a pulse signal, other configurations are possible. For example, the modulation width TMOD may be generated using other types of modulator signals (e.g., a sawtooth ramp). Alternatively, the modulation width TMOD can be generated from negative-going pulses. Furthermore, the modulation width TMOD may be generated using digital and / or software approaches. The modulation width TMOD is used to specify the off-period of the oscillator according to a specific relationship, which will be described in more detail below. The behavioral off-period modulator 214 provides the modulation width TMOD to the behavioral oscillator 216.

[0037]

[0063] The behavior oscillator 216 may be a behavior representation of the oscillator 120. The behavior oscillator 216 receives a modulation width TMOD and a drive on-period TON_DR. The behavior oscillator 216 provides an oscillator signal OSC to a set input of an edge-triggered SR latch 222. The drive on-period TON_DR is a function of the switch current I SW The duration is determined at least in part by

[0038]

[0064] The behavioral current sensing element 288 may be a behavioral representation of the current sensing element 188. The behavioral current sensing element 288 may be a behavioral representation of the switch current I SW and the switch current I SW The behavior current sensing element 288 may provide the sensed voltage VSENS to the non-inverting input of the comparator 218.

[0039]

[0065] Comparator 218 compares the reference UCR at its inverting input with the sense voltage VSENS and, in response, provides a reset signal RST to edge-triggered SR latch 222. The reference UCR may be a fixed or variable reference UCR. The reference UCR may include slope compensation for stability and / or ramp time modulation (RTM). One form of ramp time modulation (RTM) associated with a current limit threshold is described in U.S. Pat. No. 9,246,392, which is incorporated herein by reference in its entirety.

[0040]

[0066] The comparison between the reference UCR and the detection voltage VSENS is SW For example, comparing the reference UCR with the sensed voltage VSENS can be equivalent to comparing the switch current I SW and / or the switch current I SW to a reference value ITH.

[0041]

[0067] The edge-triggered SR latch 222 may provide a latch signal QDR in response to positive-rising edges at the set and reset inputs, and the drive signal DR follows the latch signal QDR. When the oscillator signal OSC transitions high, the latch signal QDR transitions high. Therefore, the drive signal DR transitions high again, switching the primary switch S1 on. When the comparator 218 changes state, causing the reset signal RST to transition high, the latch signal QDR transitions low. Therefore, the drive signal DR transitions low again, switching the primary switch S1 off.

[0042]

[0068] The primary switch S1 is electrically coupled to the primary winding 232 and is responsive to the drive signal DR to generate a switch current I having a periodic ramp waveform. SW The primary switch S1 may also be referred to as switch S1 and may provide a switch current I SW is the primary switch current I without departing from the scope of this disclosure. SW It may also be called.

[0043]

[0069] According to the teachings herein, the oscillator signal OSC has an oscillator on period TON_OSC and an oscillator off period TOFF_OSC. The oscillator period TOSC may be given by the sum of the oscillator on period TON_OSC and the oscillator off period TOFF_OSC.

[0044]

[0070] The drive signal DR has a drive-on period TON_DR and a drive-off period TOFF_DR. The drive period TDR can be given by the sum of the drive-on period TON_DR and the drive-off period TOFF_DR.

[0045]

[0071] As described above, the comparator 218 may provide a reset signal RST in response to the detection voltage VSENS exceeding the reference UCR, and the detection voltage VSENS and the reference UCR may be used to determine the primary current I SW and related to the reference value ITH and / or the primary current I SW and the reference value ITH. Therefore, the comparator 218 calculates the switch current I SWIn response to the voltage Vcc exceeding the threshold ITH, the reset signal RST (and the drive signal DR) may be provided.

[0046]

[0072] As described herein, the drive on period TON_DR is determined by the switch current I SW is related to the comparison of the switch current I with the threshold ITH. SW The reference UCR may be determined by comparing the switch current I with a threshold ITH. Similar to the reference UCR, the threshold ITH may be fixed and / or variable. For example, SW The threshold ITH can be varied so that is controlled according to the ramp period modulation (RTM).

[0047]

[0073] Alternatively, and additionally, the threshold ITH may be varied to stabilize the switching behavior of the drive signal DR. For example, the threshold ITH may be varied to provide slope compensation. Thus, the drive on-period TON_DR is proportional to the switch current I SW is related to the switch current I SW may determine the drive on period TON_DR (i.e., according to Equation 1).

number

[0048]

[0074] The oscillator on-period TON_OSC is controlled to be the larger of the fixed on-period TON_FIX (e.g., 4.4 microseconds) and the drive on-period TON_DR. Thus, during a switching cycle (e.g., oscillator switching cycle), the oscillator on-period TON_OSC may be determined by the following Equation 2:

number

[0049]

[0075] The off-period modulator 122 and the behavioral off-period modulation 214 may generate a signal having a modulation width TMOD. The modulation width TMOD may be a function of the output voltage VOUT. Alternatively, or additionally, the modulation width TMOD may be a function of a feedback signal (e.g., a control current Ic) indicative of the output voltage VOUT. Thus, the modulation width TMOD may be determined by the control signal Ic (i.e., Equation 3).

number

[0050]

[0076] The oscillator off-period TOFF_OSC is controlled to be the larger of the fixed off-period TOFF_FIX (e.g., 2.2 microseconds) and the modulation width TMOD. Thus, during a switching cycle (e.g., oscillator switching cycle), the oscillator off-period TOFF_OSC can be determined by Equation 4:

number

[0051]

[0077] According to the teachings herein, when the flyback converter 100 operates according to the flyback control model 200 and according to Equation 2 and Equation 4 (i.e., control equations Equation 2 and Equation 4), the gain G of frequency versus control current Ic can be improved for control loop stability and range (i.e., range of control current Ic).

[0052]

[0078] As shown in Equation 5, the gain G can be expressed as the derivative of the frequency f with respect to the control current I. When the frequency f is controlled according to Equations 2 and 4 as presented herein, the change in the gain G given by Equation 5 can be beneficially small.

number

number

[0053]

[0079] 2B shows a flyback control model 201 according to another embodiment of the flyback converter 100. Unlike the flyback control model 200, the flyback control model 200 includes a feedforward element 250. The feedforward element 250 may be a behavioral representation of the line interface circuit 116. The feedforward element 250 feeds the behavioral oscillator 216 with a current I v Provides the current I v may be proportional to the input voltage VIN. The oscillator may be configured to regulate the current I to reduce the variation of the output current IOUT as a function of the input voltage VIN. v Therefore, the fixed off-period TOFF_FIX can be varied in response to variations in the input voltage VIN, and Equation 4 can be recalculated according to Equation 7.

number

[0054]

[0080] 2C shows the current control loop 255 of the flyback control model 201. The current control loop 255 includes a behavioral current sensing element 288 and a comparator 218. The current control loop 255 controls the switch current I according to a reference UCR. SW For example, the switch current I SW may be controlled according to peak current control, average current control, current limiting, ramp period modulation, and the like.

[0055]

[0081] Switch current I SWmay be a function of system parameters and operating conditions. For example, the primary winding 232 may develop magnetizing and / or parasitic inductance. Furthermore, the switch current I SW may depend on the input voltage VIN. Therefore, the drive on period TON_DR is proportional to the switch current I SW and the switch current I SW is further dependent on system parameters and operating conditions.

[0056]

[0082] 2D shows a voltage control loop 260 of the flyback control model 201. The voltage control loop 260 includes a behavioral feedback circuit 212, a behavioral off-period modulator 214, and a behavioral oscillator 216. The voltage control loop 260 regulates the output voltage VOUT by negative feedback via a control current Ic. The control current Ic is a feedback signal indicative of the output voltage VOUT.

[0057]

[0083] In accordance with the teachings herein and Equation 4, the output voltage V may be adjusted through the relationship of the modulation width T as a function of the control current I. Although the teachings herein are described with reference to adjusting the output voltage V, other configurations are possible. For example, the teachings may also be applied to adjusting the load current I and / or adjusting both the load current I and the output voltage V.

[0058]

[0084] The behavior oscillator 216 provides an oscillator signal OSC to the set input of the edge-triggered SR latch 222. Thus, the oscillator period TOSC may be equal to the drive period TDR. Thus, the drive switching cycle (i.e., the drive period TDR) may begin simultaneously with the oscillator switching cycle (i.e., the oscillator period TOSC). As one skilled in the art will appreciate, system delays may create a phase shift between the drive switching cycle and the oscillator switching cycle, but the switching cycles may still operate and / or begin simultaneously.

[0059]

[0085] FIG. 2E shows the feedforward path 265 of the flyback control model 201. The feedforward path 265 includes the feedforward element 250 and the behavioral oscillator 216. The feedforward path 265 calculates the fixed oscillator off period TOFF_FIX as a function of the input voltage VIN (current I v Feedforward can beneficially reduce the variation in output power as a function of input voltage V (i.e., improve load regulation).

[0060]

[0086] FIG. 3A shows waveforms 301-303 of the modulator signal MOD, oscillator signal OSC, and drive signal DR, respectively. The embodiment of FIG. 3A corresponds to an exemplary maximum frequency condition. The modulation width TMOD is 1 microsecond (1 us). The drive on period TON_DR is 3 microseconds (3 us). The fixed on period TON_FIX is 4.4 microseconds (4.4 us). The fixed off period TOFF_FIX is 2.2 microseconds (2.2 us).

[0061]

[0087] Waveforms 301-303 are plotted against time over several switching periods of the oscillator. At time points 310, 313, and 317, the drive switching cycle begins simultaneously with the oscillator switching cycle. At time point 311, the modulator signal MOD begins pulsing with a modulation width TMOD. According to the teachings herein, the off-period modulator 122 and the dynamic off-period modulator 214 can modulate a signal (e.g., the modulator signal MOD) during the oscillator off period TOFF_OSC. Thus, the modulator signal MOD exhibits a pulse between time points 311-312 and a pulse between time points 315-316. The drive signal DR is activated between time points 313-314.

[0062]

[0088] According to the teachings herein and Equation 2, Equation 4, and Equation 7 (i.e., control equations Equation 2, Equation 4, and Equation 7), the oscillator has a switching cycle and frequency determined by a fixed on-period TON_FIX and a fixed off-period TOFF_FIX. The oscillator on-period TON_OSC is equal to 4.4 microseconds (4.4 us). The oscillator off-period TOFF_OSC is equal to 2.2 microseconds (2.2 us). The oscillator period TOSC is 6.6 microseconds (6.6 us). The drive on-period TON_DR is 3 microseconds (3 us). The drive period TDR is 6.6 microseconds (6.6 us).

[0063]

[0089] FIG. 3B illustrates waveforms 331-333 of the modulator signal MOD, oscillator signal OSC, and drive signal DR, respectively. The embodiment of FIG. 3B corresponds to an exemplary extended (i.e., adjusted) oscillator off-period condition. The modulation width TMOD is 2.5 microseconds (2.5 us). The drive on-period TON_DR is 3 microseconds (3 us). The fixed on-period TON_FIX is 4.4 microseconds (4.4 us). The fixed off-period TOFF_FIX is 2.2 microseconds (2.2 us).

[0064]

[0090] Waveforms 331-333 are plotted against time over several switching periods of the oscillator. At time points 334, 336, and 337, the drive switching cycle begins simultaneously with the oscillator switching cycle. At time point 335, the modulator signal MOD begins pulsing with a modulation width TMOD. According to the teachings herein, the off-period modulator 122 and the dynamic off-period modulator 214 can modulate a signal (e.g., the modulator signal MOD) during the oscillator off period TOFF_OSC. For example, the modulator signal MOD exhibits a pulse between time points 335-336.

[0065]

[0091] According to the teachings herein and Equations 2, 4, and 7, the oscillator has a switching cycle and frequency determined by the fixed on-period TON_FIX and the modulation width TMOD. The oscillator on-period TON_OSC is equal to 4.4 microseconds (4.4 us). The oscillator off-period TOFF_OSC is equal to 2.5 microseconds (2.5 us). The oscillator period TOSC is equal to 6.9 microseconds (6.9 us). The drive on-period TON_DR is equal to 3 microseconds (3 us). The drive period TDR is equal to 6.9 microseconds (6.9 us).

[0066]

[0092] FIG. 3C illustrates waveforms 341-343 of the modulator signal MOD, oscillator signal OSC, and drive signal DR, respectively. The embodiment of FIG. 3C corresponds to an exemplary extended oscillator on-period condition. The modulation width TMOD is one microsecond (1 us). The drive on-period TON_DR is five microseconds (5 us). The fixed on-period TON_FIX is four.4 microseconds (4.4 us). The fixed off-period TOFF_FIX is two.2 microseconds (2.2 us).

[0067]

[0093] Waveforms 341-343 are plotted against time over several switching periods of the oscillator. At time point 346, the drive switching cycle begins simultaneously with the oscillator switching cycle. At time point 344 and at time point 347, the modulator signal MOD begins pulsing with a modulation width TMOD. According to the teachings herein, the off-period modulator 122 and the dynamic off-period modulator 214 can modulate a signal (e.g., the modulator signal MOD) during the oscillator off period TOFF_OSC. For example, the modulator signal MOD exhibits a pulse between time points 344-345.

[0068]

[0094] According to the teachings herein and Equations 2, 4, and 7, the oscillator has a switching cycle and frequency determined by the drive on period TON_DR and the fixed off period TOFF_FIX. The oscillator on period TON_OSC is equal to five microseconds (5 us). The oscillator off period TOFF_OSC is equal to two.2 microseconds (2.2 us). The oscillator period TOSC is seven.2 microseconds (7.2 us). The drive on period TON_DR is five microseconds (5 us). The drive period TDR is seven.2 microseconds (7.2 us).

[0069]

[0095] FIG. 3D illustrates waveforms 351-353 of the modulator signal MOD, oscillator signal OSC, and drive signal DR, respectively. The embodiment of FIG. 3D corresponds to an exemplary increased fixed off-period TOFF_FIX due to an increase in the input voltage V (i.e., due to feedforward). For example, the increase in the fixed off-period TOFF_FIX may correspond to an input voltage V increasing from one hundred volts (100V) to four hundred volts (400V). The modulation width TMOD is one microsecond (1 us). The drive on-period TON_DR is three microseconds (3 us). The fixed on-period TON_FIX is four.4 microseconds (4.4 us). The fixed off-period TOFF_FIX is three.8 microseconds (3.8 us).

[0070]

[0096] Waveforms 351-353 are plotted versus time over several switching periods of the oscillator. In accordance with the teachings herein and Equations 2, 4, and 7, the oscillator has a switching cycle and frequency determined by a fixed on-period TON_FIX and a fixed off-period TOFF_FIX. The oscillator on-period TON_OSC is equal to 4.4 microseconds (4.4 us). The oscillator off-period TOFF_OSC is equal to 3.8 microseconds (3.8 us). The oscillator period TOSC is equal to 8.2 microseconds (8.2 us). The drive on-period TON_DR is 3 microseconds (3 us). The drive period TDR is 8.2 microseconds (8.2 us).

[0071]

[0097] 4 shows a circuit implementation of oscillator 120 according to an embodiment of the present disclosure. Oscillator 120 includes capacitor C2, a current steering stage 420, a waveform circuit 430, and a current controlled current source (CCCS) 440. Oscillator 120 receives power supply between ground GND and a power supply voltage VCC. Oscillator 120 generates a drive signal DR and a current I VS (feedforward signal I VS ) and provides an oscillator signal OSC. A capacitor C2 is electrically connected (electrically coupled) between the capacitor node NTRI and ground GND.

[0072]

[0098] The current ITRI is sourced to (i.e., provided to) and sunk from (i.e., removed from) the capacitor node NTRI to generate a current-controlled triangular wave. The voltage VTRI at the capacitor node NTRI may exhibit a waveform including a rising segment and a falling segment (e.g., triangular waveform 450). Thus, the oscillator 120 may also be referred to as a current-controlled triangular wave generator 120 without departing from the scope of this disclosure.

[0073]

[0099] The current steering stage 420 includes a differential pair 412, a p-channel field effect transistor (PFET) Q12, an n-channel field effect transistor (NFET) Q13, and a current mirror 415. The differential pair 412 includes PFET Q10 and PFET Q11 and receives a current IT1. The current IT1 is a tail current for the differential pair 412 and may therefore also be referred to as the tail current IT1. The current mirror 415 includes NFET Q14 and NFET Q15 and is electrically coupled to the differential pair 412 to steer a current ITRI at a node NTRI. The current IT1, the capacitance value of capacitor C2, and the relative scaling of the current mirror 415 can be adjusted so that the voltage VTRI exhibits a triangular waveform with rising and falling segments. The rising segment may have a duration equal to a fixed on-period TON_FIX, and the falling segment may have a duration equal to a fixed off-period TOFF_FIX.

[0074]

[0100] According to the teachings herein, the oscillator on period TON_OSC and the oscillator off period TOFF_OSC may be determined at least in part by the rising and falling segments. As described herein, the oscillator on period TON_OSC and the oscillator off period TOFF_OSC may extend beyond the duration of the rising and / or falling segments.

[0075]

[0101] Control signals G10-G13 are provided to the gates of PFET Q10, PFET Q11, PFET Q12, and NFET Q13, respectively. Control signal G13 follows drive signal DR, except that its waveform may be inverted (i.e., equation 8).

number

[0076]

[0102] Waveform circuit 430 may include logic circuits (e.g., combinational logic, sequential logic, gates, etc.). Waveform circuit 430 may receive signal OFF_END. Signal OFF_END may swing high during oscillator off period TOFF_OSC to indicate the completion of a modulator pulse. For example, referring to waveform 301, signal OFF_END may swing high after time point 312 and after time point 316.

[0077]

[0103] In response, waveform circuit 430 provides control signals G10-G12 to current steering stage 420 such that voltage VTRI is a controllable triangular wave with an extendable rise period and / or an extendable fall period. Waveform circuit 430 also receives voltage VTRI and, in response thereto, provides oscillator signal OSC having an oscillator on period TON_OSC and an oscillator off period TOFF_OSC.

[0078]

[0104] The current controlled current source (CCCS) 440 includes current mirrors 416-417 and an NFET Q20. The CCCS 440 generates a current I VS The current mirrors 416 and 417 receive the reference current IR1 as a current I VS and in response sinks a current I16 at node N16. NFET Q20 sinks a current I VS In response to the current I ADJ may be provided.

[0079]

[0105] In connection with feedforward, CCCS 440 may sink current I16 so that current steering stage 420 changes the slope of the falling segment of triangle wave 450. For example, current I VSIn response to an increase in V, the downward slope of the triangle wave 450 (i.e., the time derivative of the voltage V) may decrease, and thus the fixed off-period TOFF_FIX may increase. With this approach, the fixed off-period TOFF_FIX becomes a function of the input voltage V (i.e., Equation 9).

number

[0080]

[0106] 4 shows an analog triangular wave approach to generating the oscillator signal OSC, other configurations are possible. For example, the oscillator signal OSC may be implemented using a digital approach. A digital counter and / or a microcontroller with digital signal processing capabilities may be used to generate the oscillator signal OSC based at least in part on the timing waveform of the drive signal DR.

[0081]

[0107] 5 shows a circuit implementation of the off-period modulator 122 according to an embodiment of the present disclosure. The off-period modulator 122 includes a capacitor C1, a pull-down circuit 545, a CCCS 540, a comparator 530, and an SR latch 532. The off-period modulator 122 receives power supply between ground GND and a power supply voltage VCC. The off-period modulator 122 receives a drive signal DR, an oscillator signal OSC, a control current Ic, and provides a signal OFF_END.

[0082]

[0108] Capacitor C1 is electrically connected (electrically coupled) between capacitor node NOTM and ground GND. Current I0TM is sourced to capacitor C1 (at capacitor node NOTM) to generate the slope of the sawtooth waveform. For example, when current I0TM has a constant current value, voltage V0TM may follow a sawtooth waveform. Therefore, off-period modulator 122 may be referred to as a sawtooth wave generator 122 without departing from the scope of this disclosure.

[0083]

[0109] Pull-down circuit 545 includes OR gate 536 and NFET Q7, and pulls capacitor node NOTM to ground GND when any of drive signal DR, oscillator signal OSC, or signal OFF_END is high. OR gate 536 swings a control signal G7 to the gate of NFET Q7 according to the logical OR of three input signals: drive signal DR, oscillator signal OSC, and signal OFF_END.

[0084]

[0110] As described with reference to FIGS. 2A-2D, the modulator signal MOD can be identified as the logical inverse of the control signal G7 (ie, Equation 10).

number

[0085]

[0111] When the SR latch 532 is reset dominant, the signal OFF_END may optionally be removed as an input to the OR gate 536. Under this optional condition, the voltage VOTM may ramp for the entire duration of the oscillator off period TOFF_OSC.

[0086]

[0112] The CCCS 540 includes current mirrors 526-528. The current mirror 526 includes NFETs Q1-Q2. The NFET Q1 is diode-connected (i.e., the gate is connected to the drain) and receives a control current Ic. The NFET Q2 divides the control current Ic by a reference current I REF The control current Ic is mirrored for comparison.

[0087]

[0113] Control current Ic and reference current I REFThe difference between the control current Ic and the reference current Ic is provided to the current mirror 527. The current mirror 527 includes NFETs Q3 and Q4. The NFET Q3 is diode-connected (i.e., the gate is connected to the drain), and the control current Ic and the reference current Ic are connected to the NFET Q4. REF The current mirror 528 includes PFETs Q5-Q6, and the PFET Q6 is coupled to the current mirror 527 to provide a current I0TM. The current I0TM is the sum of the control current Ic and the reference current I REF It can be a mirrored current proportional to the difference (comparison result) between

[0088]

[0114] Thus, CCCS 540 is responsive to the control current Ic, and more specifically to the control current Ic and the reference current I REF and the control current Ic. Thus, during the oscillator off period TOFF_OSC, the voltage VOTM may follow a sawtooth waveform with a slope that depends at least in part on the control current Ic. Optionally, the current I ADJ is the reference current I REF can be sunk at the drain of NFET Q2 to reduce and / or adjust the magnitude of

[0089]

[0115] Comparator 530 compares the voltage VOTM at its non-inverting input with a modulation reference TH_OFF at its inverting input and provides a signal SET to a set input of SR latch 532. According to the embodiment of FIG. 5, the modulation width TMOD is the time interval during which the voltage VOTM is less than the modulation reference TH_OFF. The modulation reference TH_OFF may be a temperature-stable reference TH_OFF (e.g., a bandgap reference). Thus, in addition to being dependent on the control current Ic and the capacitance of capacitor C1, the modulation width TMOD may also be determined at least in part by the modulation reference TH_OFF.

[0090]

[0116] Furthermore, the capacitance of the capacitor C1 and the reference current I REF, the scaling of current mirrors 526-528, and modulation reference TH_OFF may determine the modulation width TMOD as a function of control current Ic. In response to voltage VOTM reaching and / or exceeding modulation reference TH_OFF, comparator 530 causes signal SET to swing high.

[0091]

[0117] The SR latch 532 receives the signal SET and the drive signal DR at its set and reset inputs, respectively. In response, the SR latch 532 provides the signal OFF_END. The drive signal DR resets the latch 532 during the oscillator on period TON_OSC. The signal SET swings high during the oscillator off period TOFF_OSC after a time interval determined by the modulation width TMOD. Thus, the signal OFF_END is swing high by the SR latch 532 after the duration of the modulation width TMOD.

[0092]

[0118] 6 shows an example circuit implementation of control logic 124 according to an embodiment of the present disclosure. Control logic 124 receives signal ISENS, oscillator signal OSC, and provides drive signal DR. Control logic 124 includes monostable 510, current-to-voltage converter 621, comparator 610, SR latch 632, and buffer 633. Buffer 633 may provide drive signal DR as a buffered copy of signal Q1.

[0093]

[0119] Monostable 510 receives oscillator signal OSC and, in response to a rising edge of oscillator signal OSC, provides a pulse signal SET1 to the set input of SR latch 632. Thus, when oscillator signal OSC transitions high, SR latch 632 causes signal Q1 to swing high, which in turn causes drive signal DR to swing high. In this manner, the switching cycle of drive switching signal DR can begin simultaneously with the oscillator switching cycle.

[0094]

[0120] The current-to-voltage converter 621 may include a resistor R1 for providing a sense voltage VSENS to a non-inverting input of a comparator 610. The comparator 610 compares the sense voltage VSENS with a reference UCR and provides a signal RES1 to a reset input of the SR latch 632. As described above in connection with the comparator 218, comparing the sense voltage VSENS with the reference UCR reduces the switch current I compared to the threshold ITH. SW Therefore, the switch current I SW When the voltage V reaches and / or exceeds the threshold ITH, the SR latch 632 pulls the signal Q1 low, which in turn pulls the drive signal DR low.

[0095]

[0121] 7 shows an example circuit implementation of the line interface circuit 116 according to an embodiment of the present disclosure. The line interface circuit 116 receives power from a power supply between ground GND and a power supply voltage VCC. The line interface circuit 116 outputs a current I V receives the current I V Current I proportional to VS The line interface circuit 116 includes a PFET Q30 and current mirrors 715-716. The PFET Q30 receives a gate bias VBP and flows a current I from its source to its drain. V The current mirror 716 includes NFETs Q23 to Q24. The current mirror 715 includes PFETs Q25 to Q26. The current I supplied from the drain of the PFET Q26 VS is the current I V PFET Q30, current mirror 716, and current mirror 715 are electrically coupled to be a scaled replica of

[0096]

[0122] 8 illustrates a gate-level circuit implementation of a switch current reference generator 118 according to an embodiment of the present disclosure. The switch current reference generator 118 receives a power supply voltage between ground GND and a power supply voltage VCC. The switch current reference generator 118 receives a drive signal DR and provides a reference UCR to a node NCR. The switch current reference generator 118 includes a logic circuit 801, a switched current 802, a switched current 803, and a capacitor 804. The capacitor 804 is connected between the node NCR and ground GND.

[0097]

[0123] Logic circuit 801 may drive switched current 802 and switched current 803 according to the switching cycle of drive signal DR and according to voltage references VTMAX, VTMIN. In response, switched current 802 and switched current 803 may sink and / or source current ICR at node NCR such that reference UCR varies. Reference UCR may vary according to ramp-period modulation (RTM).

[0098]

[0124] FIG. 9A shows waveforms 901-902, 903a-b, 904-907 of voltage VTRI, oscillator signal OSC, voltage VOTM, modulator signal MOD, signal OFF_END, drive signal DR, reference UCR, and sense voltage VSENS. The embodiment of FIG. 9A corresponds to an exemplary highest frequency condition. The modulation width TMOD is 1 microsecond (1 us). The drive on period TON_DR is 3 microseconds (3 us). The fixed on period TON_FIX is 4.4 microseconds (4.4 us). The fixed off period TOFF_FIX is 2.2 microseconds (2.2 us).

[0099]

[0125] Waveforms 901-902, 903a-b, and 904-907 are plotted against time over several switching periods (i.e., switching cycles) of the oscillator. For example, one oscillator switching period (cycle) is shown from time 920 to time 930, having an oscillator period TOSC. Referring to FIG. 4, waveform 901 (voltage VTRI) exhibits a triangular wave with rising segments 940 and 942 and falling segments 941 and 943. Rising segment 940 is shown between time 910 and time 914. Rising segment 942 is shown between time 920 and time 924. Falling segment 941 is shown between time 914 and time 920. Falling segment 943 is shown between time 924 and time 930.

[0100]

[0126] Waveform 902 (oscillator signal OSC) is a square waveform. While the triangle wave exhibits rising segments 940, 942, the oscillator signal OSC is high, and while the triangle wave exhibits falling segments 941, 943, the oscillator signal OSC is low.

[0101]

[0127] 5, waveform 903a (voltage VOTM) exhibits a sawtooth waveform. For example, waveform 903a increases with sawtooth segments between time 914 and time 916 and between time 924 and time 926. The duration between time 914 (924) and time 916 (926) is the modulation width TMOD. As previously described in connection with the description of FIG. 5, waveform 903a is consistent with the configuration of OR gate 536.

[0102]

[0128] 5 and 2B, waveform 903b (modulator signal MOD) shows a pulse waveform and may have a different y-axis scale than waveform 903a. For example, waveform 903b shows pulses between time points 914 and 916 and between time points 924 and 926.

[0103]

[0129] 5 and 2B, waveform 904 (signal OFF_END) shows a pulse waveform indicating the completion of modulation. In this example, "completion of modulation" refers to the completion of the pulse between time 914 (924) and time 916 (926).

[0104]

[0130] Waveform 904 shows the pulses for the remainder of the oscillator off period TOSC_OFF. For example, waveform 904 (signal OFF_END) remains high from time 916 to time 920 and from time 926 to time 930.

[0105]

[0131] According to the teachings herein, oscillator 120 of FIG. 4 may receive signal OFF_END to determine the state of off-period modulator 122 and to assert oscillator signal OSC in accordance with Equation 2, Equation 4, and Equation 7.

[0106]

[0132] In this case, the modulation width TMOD (1 us) is less than the fixed off period TOFF_FIX (2.2 us), and therefore, in accordance with Equations 2, 4, and 7, the oscillator off period TOSC_OFF is controlled by waveform 901 to be the fixed off period TOFF_FIX (2.2 us).

[0107]

[0133] 6 and 2B, waveform 905 (drive signal DR) is at least partially determined by waveform 906 (reference UCR) and waveform 907 (detected voltage VSENS). At time points 912 and 922, the detected voltage VSENS reaches and / or exceeds the reference UCR. Thus, comparator 218 and / or comparator 610 change state, causing the drive signal DR to transition from high to low. The reference UCR may vary according to RTM. For example, waveform 906 monotonically decreases during a switching cycle (e.g., during a drive switching cycle). The detected voltage VSENS increases as the switch current I SW Since the drive on period TON_DR is related to the switch current I SWThe drive on-period TON_DR (3 us) is less than the fixed on-period TON_FIX (4.4 us).

[0108]

[0134] The oscillator on-duration TON_OSC is greater than or equal to the fixed on-duration TON_FIX. Thus, in accordance with the teachings herein, waveform 902 (oscillator signal OSC) transitions low at time 914 and at time 924 so that the oscillator on-duration TON_OSC is equal to the fixed on-duration TON_FIX.

[0109]

[0135] Thus, the oscillator has a switching cycle and frequency determined by the fixed on-period TON_FIX and the fixed off-period TOFF_FIX. The oscillator on-period TON_OSC is equal to four point four microseconds (4.4 us). The oscillator off-period TOFF_OSC is equal to two point two microseconds (2.2 us). The oscillator period TOSC is six point six microseconds (6.6 us). The drive on-period TON_DR is three microseconds (3 us). The drive period TDR is six point six microseconds (6.6 us).

[0110]

[0136] FIG. 9B illustrates waveforms 961-962, 963a-b, 964-967 of voltage VTRI, oscillator signal OSC, voltage VOTM, modulator signal MOD, signal OFF_END, drive signal DR, reference UCR, and sense voltage VSENS. The embodiment of FIG. 9B corresponds to an extended (i.e., adjusted) oscillator off-period condition. The modulation width TMOD is four microseconds (4 us). The drive on-period TON_DR is three microseconds (3 us). The fixed on-period TON_FIX is four.4 microseconds (4.4 us). The fixed off-period TOFF_FIX is two.2 microseconds (2.2 us).

[0111]

[0137] Waveforms 961-962, 963a-b, and 964-967 are plotted against time over several switching periods (i.e., switching cycles) of the oscillator. For example, one oscillator switching period (cycle) is shown from time 971 to time 974. Referring to FIG. 4, waveform 961 (voltage VTRI) shows a triangular wave with rising segments (e.g., rising segment 945) and falling segments (e.g., falling segment 946). Rising segment 945 is shown between time 971 and time 972.

[0112]

[0138] According to the teachings herein, the falling segment 946 is extended in duration using the off-period extension TOFF_EXT. The falling segment 946 begins at time 972, and the voltage VTRI drops to time 973 for a duration equal to the fixed off-period TOFF_FIX. The voltage VTRI is then maintained low (extended) until the start of the subsequent switching cycle at time 974. In response to the signal OFF_END, the oscillator 120 extends the falling segment from time 973 to time 974.

[0113]

[0139] Thus, the oscillator off-period TOFF_OSC is determined (extended) by the off-period extension TOFF_EXT so as to be equal to that of the modulation width TMOD. In this manner, the oscillator off-period TOFF_OSC is determined at least in part by the duration of the falling segment 946 and the duration of the transition to the rising segment of the subsequent cycle (off-period extension TOFF_EXT).

[0114]

[0140] Waveform 962 (oscillator signal OSC) is a square waveform. While the triangle wave exhibits a rising segment (e.g., rising segment 945), the oscillator signal OSC is high. While the triangle wave exhibits a falling segment (e.g., falling segment 946) and during the off-period extension TOFF_EXT, the oscillator signal OSC is low.

[0115]

[0141] 5, waveform 963a (voltage VOTM) illustrates a sawtooth waveform. For example, waveform 963a increases with a sawtooth segment between time points 972 and 974. The duration between time points 972 and 974 is the modulation width TMOD. As previously described in connection with the description of FIG. 5, waveform 963a is consistent with the configuration of OR gate 536.

[0116]

[0142] 5 and 2B, waveform 963b (modulator signal MOD) shows a pulse waveform and may have a different y-axis scale than waveform 963a. For example, waveform 963b shows a pulse between time points 972 and 974.

[0117]

[0143] 5 and 2B, waveform 964 (signal OFF_END) shows a pulse waveform indicating the completion of modulation. In this example, "completion of modulation" refers to the completion of a pulse during the oscillator off period TOFF_OSC. For example, waveform 963b completes modulation at time point 974.

[0118]

[0144] Because the modulation width TMOD (4 us) is greater than the fixed off period (2.2 us), waveform 964 shows narrow pulses of short duration (e.g., 10 nanoseconds). In this case, the modulation width TMOD (4 us) is greater than the fixed off period TOFF_FIX (2.2 us). Therefore, in accordance with Equation 2, Equation 4, and Equation 7, the oscillator off period TOSC_OFF is determined by waveforms 963a-b and is expanded to be equal to the modulation width TMOD.

[0119]

[0145] 6 and 2B, the waveforms 965-967 are determined by waveform 965 (drive signal DR), waveform 966 (reference UCR), and waveform 967 (detection voltage VSENS). The drive on-duration TON_DR (3 us) is less than the fixed on-duration TON_FIX (4.4 us). As shown, waveform 965 may transition low at time 975, so the behavior of waveforms 965-967 is similar to that of waveforms 905-907.

[0120]

[0146] According to the teachings herein and Equations 2, 4, and 7, the oscillator has a switching cycle and frequency determined by the fixed on-period TON_FIX (4.4 us) and the modulation width TMOD (4 us). The oscillator on-period TON_OSC is equal to 4.4 microseconds (4.4 us). The oscillator off-period TOFF_OSC is equal to 4 microseconds (4 us). The oscillator period TOSC is 8.4 microseconds (8.4 us). The drive on-period TON_DR is 3 microseconds (3 us). The drive period TDR is 8.4 microseconds (8.4 us).

[0121]

[0147] FIG. 9C illustrates waveforms 981-982, 983a-b, 984-987 of voltage VTRI, oscillator signal OSC, voltage VOTM, modulator signal MOD, signal OFF_END, drive signal DR, reference UCR, and sense voltage VSENS. The embodiment of FIG. 9C corresponds to an exemplary extended oscillator on-period condition. The modulation width TMOD is one microsecond (1 us). The drive on-period TON_DR is five-one microseconds (5.1 us). The fixed on-period TON_FIX is four-fourth microseconds (4.4 us). The fixed off-period TOFF_FIX is two-two microseconds (2.2 us).

[0122]

[0148] Waveforms 981-982, 983a-b, and 984-987 are plotted against time over several switching periods (i.e., switching cycles) of the oscillator. For example, one oscillator switching period (cycle) is shown from time 988 to time 991. Referring to Figure 4, waveform 981 (voltage VTRI) exhibits a triangular wave with rising segments (e.g., rising segment 948) and falling segments (e.g., falling segment 949).

[0123]

[0149] In accordance with the teachings herein, rising segment 948 is extended. Rising segment 948 begins at time 988 such that waveform 981 (voltage VTRI) rises to time 989 for a duration equal to the fixed on-period TON_FIX. In response to waveform 985 (drive signal DR) remaining high, oscillator 120 maintains waveform 981 high from time 989 to time 990. The duration from time 989 to time 990 is an on-period extension TON_EXT that extends the oscillator on-period TON_OSC to be equal to the drive on-period TON_DR.

[0124]

[0150] Thus, the oscillator on-period TON_OSC may be determined by the duration of the rising segment 948 and the duration of the transition period to the falling segment 949. Waveform 982 (oscillator signal OSC) is a square waveform. The oscillator signal OSC is high while the triangle wave exhibits a rising segment (e.g., rising segment 948) and during the on-period extension TON_EXT. The rising segment 948 from time 988 to time 989 may have a duration equal to the fixed on-period TON_FIX. The on-period extension TON_EXT extends the oscillator on-period TON_OSC to be equal to the drive on-period TON_DR. As previously described in connection with FIGS. 9A and 9B, while the triangle wave exhibits a falling segment (e.g., falling segment 949), the oscillator signal OSC is low.

[0125]

[0151] The description of waveforms 983a, 983b, and 984-987 is similar to the description of waveforms 903a, 903b, and 904-907.

[0126]

[0152] According to the teachings herein and Equations 2, 4, and 7, the oscillator has a switching cycle and frequency determined by the drive on period TON_DR (5.1 us) and the fixed off period TOFF_FIX (2.2 us). The oscillator on period TON_OSC is equal to 5.1 microseconds (5.1 us) and the oscillator off period TOFF_OSC is equal to 2.2 microseconds (2.2 us). The oscillator period TOSC is 7.3 microseconds (7.3 us). The drive on period TON_DR is 5.1 microseconds (5.1 us). The drive period TDR is 7.3 microseconds (7.3 us).

[0127]

[0153] FIG. 9D illustrates waveforms 993-994, 995a-b, and 996-999 of voltage VTRI, oscillator signal OSC, voltage VOTM, modulator signal MOD, signal OFF_END, drive signal DR, reference UCR, and sense voltage VSENS. The embodiment of FIG. 9D corresponds to an example of an increased fixed off-period TOFF_FIX due to an increase in input voltage VIN (i.e., due to feedforward). The modulation width TMOD is one microsecond (1 us). The drive on-period TON_DR is three microseconds (3 us). The fixed on-period TON_FIX is four.4 microseconds (4.4 us). The fixed off-period TOFF_FIX is three.8 microseconds (3.8 us). The increased values ​​of the fixed off-period may correspond to an input voltage VIN increasing from one hundred volts (100V) to four hundred volts (400V).

[0128]

[0154] The waveforms 993-994, 995a-b, and 996-999 are explained as follows: v 9. The waveforms are similar to those of waveforms 901-902, 903a-b, and 904-907, except that the fixed off period TOFF_FIX is increased due to the dependence on .

[0129]

[0155] 9A, the oscillator on-period TON_OSC from time 931 to time 932 is determined by a fixed on-period TON_FIX, which is the duration of rising segment 938. Also, similar to FIG. 9A, the oscillator off-period TOFF_OSC from time 932 to time 933 is determined by a fixed off-period TOFF_FIX, which is the duration of falling segment 939. However, unlike FIG. 9A, the magnitude of the slope (i.e., the time derivative of voltage VTRI) is reduced, so that the duration of falling segment 939 (i.e., the fixed off-period TOFF_FIX) is proportional to the current I v It increases in response to

[0130]

[0156] According to the teachings herein and Equations 2, 4, and 7, the oscillator has a switching cycle and frequency determined by a fixed on-period TON_FIX and a fixed off-period TOFF_FIX. The oscillator on-period TON_OSC is equal to 4.4 microseconds (4.4 us). The oscillator off-period TOFF_OSC is equal to 3.8 microseconds (3.8 us). The oscillator period TOSC is 8.2 microseconds (8.2 us). The drive on-period TON_DR is 3 microseconds (3 us). The drive period TDR is 8.2 microseconds (8.2 us).

[0131]

[0157] 10A shows a flowchart 1000a for driving the primary switch S1 and for determining the oscillator on-switching period TON_OSC in accordance with the teachings herein. The flowchart 1000a can provide a time-based algorithm for implementing the flyback control models 200, 201 of FIGS. 2A-2E.

[0132]

[0158] Although flowchart 1000a is described in the context of determining the oscillator on-period TON_OSC, flowchart 1000a may also provide algorithms for software and / or digital implementation that do not require an oscillator signal. As one skilled in the art will appreciate, quantities such as the output voltage VOUT, the control current Ic, and the input voltage VIN may be provided to a digital signal processor (DSP) and / or microcontroller using analog-to-digital (A / D) converters.

[0133]

[0159] Flowchart 1000a may be obtained from the control relationship (i.e., Equation 2). Step 1001 may correspond to the initiation of a switching cycle using a timer (e.g., a clock) and / or a counter. Step 1001 may correspond to the start of a switching cycle (e.g., an oscillator switching cycle). The counter TIME is reset and then begins to increment. Step 1003 may correspond to turning on a switch (e.g., primary switch S1).

[0134]

[0160] Decision step 1004 may correspond to aspects of the current control loop 255. Variables such as the threshold ITH and / or the fixed on-duration TON_FIX may be programmed into the processor and / or determined during operation. SW is less than the threshold ITH and the counter TIME is less than the fixed on-period TON_FIX, remain at decision step 1004. Otherwise, continue to decision step 1005.

[0135]

[0161] Decision step 1005 is further related to the current control loop 255. The switch current I SW If TIME is greater than (or equal to) the threshold ITH and the counter TIME is less than the fixed on-period TON_FIX, proceed to step 1007. In step 1007, switch the primary switch S1 off and continue to decision step 1009.

[0136]

[0162] In decision step 1009, while the counter TIME is less than (or equal to) the fixed on-duration TON_FIX, remain in step 1009. Otherwise, proceed to step 1010 where the counter TIME is determined by the fixed on-duration TON_FIX.

[0137]

[0163] Decision step 1006 is further related to the current control loop 255 and to conditions where the drive on-duration TON_DR may exceed (be greater than) the fixed on-duration TON_FIX. SW is less than the threshold ITH and the counter TIME is greater than (or equal to) the fixed on-duration TON_FIX, remain in decision step 1006. Otherwise, proceed to step 1008.

[0138]

[0164] In step 1008, the switch is turned off and the process proceeds to step 1010, where the counter TIME is determined by the drive on period TON_DR. Step 1010 is a continuation step and may correspond to the state where the counter TIME has reached a duration equal to the oscillator on period TON_OSC in Equations 2, 4, and 7.

[0139]

[0165] 10B shows a flowchart 1000b for determining the oscillator off switch-off period TOFF_OSC in accordance with the teachings herein. Flowchart 1000b is further derived from the control relationships (i.e., Equation 4 and Equation 7) and can be applied to systems (e.g., software, digital, etc.) without the need for an oscillator. Step 1010 follows flowchart 1000a. Step 1012 corresponds to resetting a counter TIME.

[0140]

[0166] Decision step 1014 may correspond to comparing the modulation width TMOD(Ic) with a fixed off-period TOFF_FIX. The modulation width TMOD may be a function of the output voltage VOUT. The fixed off-period TOFF_FIX may be a function of the input voltage VIN. Time variables, such as the modulation width TMOD(VOUT) and the fixed off-period as a function of the input voltage TOFF_FIX(VIN), may be determined using a digital approach and / or a look-up table. While the counter TIME is less than the modulation width TMOD and the fixed off-period TOFF_FIX, remain at decision step 1014. Otherwise, continue to decision step 1015.

[0141]

[0167] Decision step 1015 may further correspond to comparing the modulation width TMOD(Ic) to the fixed off-period TOFF_FIX. If the counter TIME is greater than (or equal to) the modulation width TMOD and less than the fixed off-period TOFF_FIX, proceed to step 1019.

[0142]

[0168] In decision step 1019, while the counter TIME is less than (or equal to) the fixed off-period TOFF_OSC, remain in step 1019. Otherwise, proceed to step 1020, where the counter TIME is determined by the fixed off-period TOFF_FIX(VIN).

[0143]

[0169] Decision step 1016 may correspond to the modulation width TMOD being greater than the fixed off-period TOFF_FIX. Decision step 1016 remains while the counter TIME is less than the modulation width TMOD and greater than (or equal to) the fixed off-period TOFF_FIX. Otherwise, proceed to step 1020, where the counter TIME is determined by the modulation width TMOD.

[0144]

[0170] A return step 1020 may correspond to ending a switching cycle (eg, a drive period TDR and / or an oscillator period TOSC).

[0145]

[0171] As explained thus far in the description of flowcharts 1000a-b, the oscillator on-switching period TON_OSC and the off-switching period TOFF_OSC may be realized using a digital approach without the need for the oscillator signal OSC and a dedicated oscillator 120. Alternatively, the oscillator on-switching period TON_OSC and the off-switching period TOFF_OSC may be controlled / calculated values ​​(i.e., controlled on-switching period TON_OSC and controlled off-switching period TOFF_OSC) implemented using a digital approach (e.g., using a microcontroller, a DSP, and / or an A / D converter). The controlled on-switching period TON_OSC and the controlled off-switching period TOFF_OSC may then determine the drive period TDR.

[0146]

[0172] 10C illustrates a conceptual flow diagram 1000c in accordance with the teachings herein. Referring to FIG. 2A, step 1032 begins by adjusting the switch current I at the beginning of a variable switching cycle. SW Step 1033 may correspond to providing the switch current I during the drive on period TON_DR. SW For example, the detected voltage VSENS may be provided to the comparator 218.

[0147]

[0173] Step 1034 may correspond to turning off a switch (e.g., primary switch S1) at the end of the drive on period TON_DR. For example, the comparator 218 may turn off the primary switch S1 in response to the detected voltage VSENS reaching a threshold value (e.g., a reference UCR threshold value). Thus, step 1034 may further correspond to determining the drive on period TON_DR during the variable switching cycle.

[0148]

[0174] Step 1035 may correspond to determining a controlled on-period TON_OSC (e.g., oscillator on-period TON_OSC) according to Control Equation 2. According to Control Equation 2, the controlled on-period TON_OSC may be determined by comparing the drive on-period TON_DR determined during step 1034 to a fixed on-period TON_FIX (e.g., 4.4 microseconds).

[0149]

[0175] Step 1036 may correspond to providing an output feedback signal (e.g., a control current Ic) indicative of the output voltage V. Step 1037 may correspond to determining a modulation width TMOD in relation to the output feedback signal (e.g., the control current Ic).

[0150]

[0176] Step 1038 may correspond to determining a controlled off-period TOFF_OSC (e.g., oscillator on-period TOFF_OSC) according to Control Equation 4 and / or Control Equation 7. According to Control Equation 4 and Control Equation 7, the controlled off-period TOFF_OSC may be determined by comparing the modulation width TMOD determined in step 1037 to a fixed off-period TOFF_FIX.

[0151]

[0177] 11A shows plots 1102-1105 of frequency versus control current according to a controller with large variations in gain G. Plots 1102-1105 correspond to drive switching cycles with drive on periods TON_DR of 0.4 microseconds (0.4 us), 2 microseconds (2.0 us), 3 microseconds (3.0 us), and 4.4 microseconds (4.4 us), respectively.

[0152]

[0178] Plot 1105 may correspond to a reduced control range, for example, the control range is limited to values ​​of control current Ic from two hundred and twenty-five microamperes (225 uA) to three hundred and fifty microamperes (350 uA).

[0153]

[0179] The change in gain G determined by the slope (i.e., the derivative of frequency f with respect to control current Ic) may be too large for stable control over the range of drive on-period TON_DR and over the range of control current Ic.

[0154]

[0180] 11B shows plots 1112-1115 of frequency versus control current in accordance with the teachings herein. Plots 1112-1115 may correspond to the flyback control models 200, 201 of FIGS. 2A-2E according to Equation 2, Equation 4, and Equation 7.

[0155]

[0181] Plot 1115 shows the controllable gain G (i.e., the derivative of frequency f with respect to control current Ic) for control current Ic from 0 uA to 350 uA and for drive on-duration TON_DR ranging from 0.4 us to 4.4 us. By comparison with Figure 11A, plot 1115 shows an excellent relationship between frequency f and control current Ic.

[0156]

[0182] FIG. 12A shows a plot of oscillator off-period TOFF_OSC versus input voltage VIN showing different options for the scaling factor to compensate for the minimum off-period in response to the input voltage (TOFF COMP).

[0157]

[0183] FIG. 12B compares plots of output power POUT versus input voltage VIN showing exemplary performance based on selection of TOFF COMP.

[0158]

[0184] The foregoing description of illustrated examples of the present disclosure, including those described in the Abstract, is not intended to be exhaustive or to be limited to the precise forms disclosed. While specific embodiments and examples of power converters for enhancing control loop stability have been described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present disclosure. Indeed, it will be understood that specific and example voltages, currents, frequencies, output range values, times, and the like are presented for illustrative purposes, and that other values ​​may be used in other embodiments and examples in accordance with the teachings herein.

[0159]

[0185] The above description may refer to elements or features that are "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" or "electrically connected" means that an element / feature is directly or indirectly connected to another element / feature, and does not necessarily mean that they are mechanically connected. Similarly, unless expressly stated otherwise, "coupled" or "electrically coupled" means that an element / feature is directly or indirectly coupled to another element / feature, and does not necessarily mean that they are mechanically connected. Thus, while the various schematic diagrams depicted in the figures show example configurations of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (provided that the functionality of the depicted circuitry is not adversely affected). Furthermore, components may be omitted to provide a streamlined example of the teachings herein.

[0160]

[0186] In the context of this application, when a transistor is in an "off state" or "off," the transistor blocks current and / or does not substantially conduct current. Conversely, when a transistor is in an "on state" or "on," the transistor can substantially conduct current. By way of example, in one embodiment, the high-voltage transistor comprises an N-channel metal-oxide-semiconductor (NMOS) field-effect transistor (FET) in which a high voltage is supported between a first terminal, the drain, and a second terminal, the source. Furthermore, for purposes of this disclosure, "ground" or "ground potential" refers to a reference voltage or potential relative to which all other voltages or potentials in an electronic circuit or integrated circuit (IC) are defined or measured.

[0161]

[0187] Additionally, conditional expressions used herein, such as "may," "could," "may," "may," "for example," "for example," "etc.," among others, are generally intended to convey that certain embodiments include certain features, elements, and / or conditions, while other embodiments do not include certain features, elements, and / or conditions, unless expressly stated otherwise or understood otherwise in the context in which they are used. Thus, such conditional expressions are generally not intended to imply that features, elements, and / or conditions are required in any way by one or more embodiments, or that one or more embodiments necessarily include logic for determining whether or not these features, elements, and / or conditions are included in or implemented in any particular embodiment.

[0162]

[0188] While specific embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the present disclosure. For example, while the disclosed embodiments are shown in a given configuration, alternative embodiments may perform similar functions using different components and / or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and / or modified. Each of these elements may be implemented in a variety of different ways. Any suitable combination of elements and operations of the various embodiments described above may be combined to provide further embodiments. The scope of the present invention, therefore, is defined solely by reference to the appended claims.

[0163]

[0189] Although the claims presented in this application are in singly dependent form for purposes of filing in the USPTO, it is understood that any claim may depend on any one of the preceding claims of the same type unless it is clearly not technically feasible.

[0164] Embodiment

[0165]

[0190] While the present invention is defined in the appended claims, it should be understood that the invention may be further (alternatively) defined according to the following embodiments.

[0166] 1. A switching power converter configured to convert input power to output power and to regulate the output voltage, the switching power converter comprising: a feedback circuit configured to provide a feedback signal indicative of the output voltage; an off-period modulator configured to generate a modulator signal having a modulation width determined at least in part by a magnitude of the feedback signal; an oscillator configured to provide an oscillator signal according to an oscillator switching cycle including an oscillator on-period and an oscillator off-period, the oscillator on-period being equal to or greater than a fixed on-period and the oscillator off-period being determined at least in part by a modulation width; a switch configured to provide a switch current according to a drive signal switching cycle, the switch conducting the switch current during a drive on period, the drive signal switching cycle being determined by an oscillator switching cycle; A switching power converter comprising:

[0167] 2. The switching power converter is a flyback power converter; 2. The switching power converter of embodiment 1.

[0168] 3. When the drive on-period is less than the fixed on-period, the oscillator on-period is limited to the fixed on-period; 2. The switching power converter of embodiment 1.

[0169] 4. The fixed on-duration is between three microseconds (3us) and five microseconds (5us); 4. A switching power converter as recited in embodiment 3.

[0170] 5. When the drive on period is greater than the fixed on period, the oscillator on period is equal to the drive on period; 4. A switching power converter as recited in embodiment 3.

[0171] 6. When the modulation width is less than the fixed off period, the oscillator off period is limited to the fixed off period; 2. The switching power converter of embodiment 1.

[0172] 7. The fixed off period is between one microsecond (1 us) and three microseconds (3 us); 7. A switching power converter as recited in embodiment 6.

[0173] 8. When the modulation width is greater than the fixed off-period, the oscillator off-period is equal to the modulation width; 7. A switching power converter as recited in embodiment 6.

[0174] 9. The oscillator is configured to generate a triangle wave having a rising segment and a falling segment; 2. The switching power converter of embodiment 1.

[0175] 10. The oscillator on period is determined at least in part by the duration of the rising segment; 10. A switching power converter as recited in embodiment 9.

[0176] 11. The duration of the rising segment is between three microseconds (3us) and five microseconds (5us); 11. A switching power converter as recited in embodiment 10.

[0177] 12. When the drive-on period is greater than the duration of the rising segment, the transition period to the falling segment is delayed; 11. A switching power converter as recited in embodiment 10.

[0178] 13. The oscillator on period is determined by the duration of the rising segment and the duration of the transition period to the falling segment; 13. A switching power converter as recited in embodiment 12.

[0179] 14. The oscillator off period is determined at least in part by the duration of the falling segment; 10. A switching power converter as recited in embodiment 9.

[0180] 15. The duration of the falling segment is between one microsecond (1 us) and three microseconds (3 us); 15. A switching power converter as recited in embodiment 14.

[0181] 16. When the modulation width is greater than the duration of the falling segment, the transition to the rising segment of the subsequent cycle is delayed; 15. A switching power converter as recited in embodiment 14.

[0182] 17. The oscillator off period is determined at least in part by the duration of the falling segment and the duration of the transition to the rising segment of the subsequent cycle; 17. A switching power converter as recited in embodiment 16.

[0183] 18. The off-period modulator is configured to generate a sawtooth waveform during a falling segment; 18. A switching power converter as recited in embodiment 17.

[0184] 19. The modulation width is determined by comparing the sawtooth wave with a modulation threshold. 19. A switching power converter as recited in embodiment 18.

[0185] 20. The output power is based at least in part on the load current; the input power is based at least in part on the input voltage; 18. A switching power converter as recited in embodiment 17.

[0186] 21. In response to an increase in input voltage, the duration of the falling segment is increased; 21. A switching power converter as described in embodiment 20.

[0187] 22. The oscillator off period is varied to reduce variation in drive signal switching cycles as a function of load current; 21. A switching power converter as described in embodiment 20.

[0188] 23. The feedback signal is a control current; The oscillator off period is varied to reduce variation in the drive signal switching cycle as a function of the control current; 23. A switching power converter as recited in embodiment 22.

[0189] 24. The duration of the falling segment is increased to reduce the variation of the output power as a function of the input voltage; 24. A switching power converter as described in embodiment 23.

[0190] 25. A switching power converter configured to receive an input voltage and to provide an output voltage to a load, the switching power converter comprising: a switch configured to provide a switch current according to a drive signal switching cycle including a drive on period; a current control loop configured to control a drive on-duration in response to the switch current; a voltage control loop configured to control a drive-off period in response to a feedback signal indicative of an output voltage, the voltage control loop comprising: an off-period modulator configured to generate a modulator signal having a modulation width based at least in part on the magnitude of the feedback signal; an oscillator configured to provide an oscillator signal according to an oscillator switching cycle including an oscillator on-period that is equal to or greater than a fixed on-period and an oscillator off-period that is determined at least in part by a modulation width, wherein the drive signal switching cycle is determined by the oscillator switching cycle; a voltage control loop comprising: A switching power converter comprising:

[0191] 26. The switch current provides energy to the energy transfer element so that the switch current increases during the drive on period; 26. A switching power converter as described in embodiment 25.

[0192] 27. The current control loop is configured to control the drive on period in response to the peak value of the switch current exceeding a threshold value; 27. A switching power converter as recited in embodiment 26.

[0193] 28. The current control loop comprises a comparator configured to compare the switch current with a threshold value. 28. A switching power converter as described in embodiment 27.

[0194] 29. The threshold is a constant. 28. A switching power converter as described in embodiment 27.

[0195] 30. The threshold varies as a function of time; 28. A switching power converter as described in embodiment 27.

[0196] 31. The threshold is based at least in part on the output load current; 28. A switching power converter as described in embodiment 27.

[0197] 32. Further comprising a feedforward path configured to provide a feedforward signal to the oscillator; The feedforward signal is indicative of the input voltage. 26. A switching power converter as described in embodiment 25.

[0198] 33. The feedforward path is configured to provide a feedforward signal to the oscillator to reduce fluctuations in the output load current; 33. A switching power converter as described in embodiment 32.

[0199] 34. The oscillator off period increases as a function of the input voltage. 34. A switching power converter as described in embodiment 33.

[0200] 35. The oscillator is configured to increase the oscillator off period to reduce fluctuations in output power to the load. 35. A switching power converter as described in embodiment 34.

[0201] 36. A method for regulating an output voltage in accordance with a variable pulse width modulation (PWM) switching cycle including a PWM on period and a PWM off period, the method comprising: providing a switch current by turning on the switch at the beginning of a variable PWM switching cycle; providing a switch current feedback signal indicative of the switch current during the drive on period; switching the switch off at the end of the drive on period in response to the switch current feedback signal reaching a threshold value; determining a PWM on-period by comparing the drive on-period to a fixed on-period; providing an output feedback signal indicative of the output voltage; determining a modulation width relative to the output feedback signal; determining a PWM off-period by comparing the modulation width to a fixed off-period; A method comprising:

[0202] 37. Further comprising generating a variable PWM switching cycle using a current-controlled triangle wave generator. 37. The method of embodiment 36.

[0203] 38. Generating variable PWM switching cycles using a current-controlled triangle wave generator includes charging a capacitor with a current that is the difference between a fixed current and a current proportional to an output feedback signal; 38. The method of embodiment 37.

[0204] 39. Providing a feedforward signal indicative of an input power supply voltage; Varying the fixed off period relative to the feedforward signal; 37. The method of embodiment 36, further comprising:

[0205] 40. The switch current feedback signal is a voltage; 37. The method of embodiment 36.

[0206] 41. The threshold is constant. 37. The method of embodiment 36.

[0207] 42. The threshold is variable. 37. The method of embodiment 36.

[0208] 43. Thresholds change over time. 43. The method of embodiment 42.

[0209] 44. Switching the switch off at the end of the drive on period in response to the switch current feedback signal reaching a threshold includes providing slope compensation for the threshold. 37. The method of embodiment 36.

[0210] 45. Switching the switch off at the end of the drive on period in response to the switch current feedback signal reaching a threshold includes varying the threshold to adjust the ramp period of the switch current; 37. The method of embodiment 36.

[0211] 46. ​​Determining the PWM on-period by comparing the drive on-period to the fixed on-period includes limiting the PWM on-period to the fixed on-period when the fixed on-period is greater than the drive on-period; 37. The method of embodiment 36.

[0212] 47. Determining the PWM on-period by comparing the drive on-period to the fixed on-period includes limiting the PWM on-period to the drive on-period when the fixed on-period is less than the drive on-period; 37. The method of embodiment 36.

[0213] 48. Providing an output feedback signal indicative of the output voltage includes providing a photodiode current using an optocoupler; 37. The method of embodiment 36.

[0214] 49. Determining the PWM off-period by comparing the modulation width to the fixed off-period includes limiting the PWM off-period to the modulation width when the modulation width is greater than the fixed off-period. 37. The method of embodiment 36.

[0215] 50. Determining the PWM off-period by comparing the modulation width to the fixed off-period includes limiting the PWM off-period to the fixed off-period when the modulation width is less than the fixed off-period; 37. The method of embodiment 36.

[0216] 51. A switching power converter configured to convert input power to output power and to regulate a load current, the switching power converter comprising: a feedback circuit configured to provide a feedback signal indicative of the load current; an off-period modulator configured to generate a modulator signal having a modulation width determined at least in part by a magnitude of the feedback signal; an oscillator configured to provide an oscillator signal according to an oscillator switching cycle including an oscillator on-period and an oscillator off-period, the oscillator on-period being equal to or greater than a fixed on-period and the oscillator off-period being determined at least in part by a modulation width; a switch configured to provide a switch current according to a drive signal switching cycle, the switch conducting the switch current during a drive on period, the drive signal switching cycle being determined by an oscillator switching cycle; A switching power converter comprising:

[0217] 52. The switching power converter is a flyback power converter. A switching power converter as described in embodiment 51.

[0218] 53. When the drive on-period is less than the fixed on-period, the oscillator on-period is substantially equal to the fixed on-period; A switching power converter as described in embodiment 51.

[0219] 54. The fixed on-duration is between three microseconds (3us) and five microseconds (5us). A switching power converter as described in embodiment 53.

[0220] 55. When the drive on period is greater than the fixed on period, the oscillator on period is equal to the drive on period; A switching power converter as described in embodiment 53.

[0221] 56. When the modulation width is less than the fixed off period, the oscillator off period is limited to the fixed off period. A switching power converter as described in embodiment 51.

[0222] 57. The fixed off period is between one microsecond (1 us) and three microseconds (3 us); A switching power converter as described in embodiment 56.

[0223] 58. When the modulation width is greater than the fixed off-period, the oscillator off-period is equal to the modulation width. A switching power converter as described in embodiment 56.

[0224] 59. The oscillator is configured to generate a triangle wave having a rising segment and a falling segment; A switching power converter as described in embodiment 51.

[0225] 60. The oscillator on period is determined at least in part by the duration of the rising segment; A switching power converter as described in embodiment 59.

[0226] 61. The duration of the rising segment is between three microseconds (3us) and five microseconds (5us); A switching power converter as described in embodiment 60.

[0227] 62. When the drive-on period is greater than the duration of the rising segment, the transition period to the falling segment is delayed. A switching power converter as described in embodiment 60.

[0228] 63. The oscillator on period is determined by the duration of the rising segment and the duration of the transition period to the falling segment; A switching power converter as described in embodiment 62.

[0229] 64. The oscillator off period is determined at least in part by the duration of the falling segment; A switching power converter as described in embodiment 59.

[0230] 65. The duration of the falling segment is between one microsecond (1 us) and three microseconds (3 us); A switching power converter as described in embodiment 64.

[0231] 66. When the modulation width is greater than the duration of the falling segment, the transition to the rising segment of the subsequent cycle is delayed; A switching power converter as described in embodiment 64.

[0232] 67. The oscillator off period is determined at least in part by the duration of the falling segment and the duration of the transition to the rising segment of the subsequent cycle; A switching power converter as described in embodiment 66.

[0233] 68. The off-period modulator is configured to generate a sawtooth waveform during the falling segment; A switching power converter as described in embodiment 67.

[0234] 69. The modulation width is determined by comparing the sawtooth wave with a modulation threshold. A switching power converter as described in embodiment 68.

[0235] 70. The output power is based at least in part on the load current; the input power is based at least in part on the input voltage; A switching power converter as described in embodiment 67.

[0236] 71. In response to an increase in input voltage, the duration of the falling segment is increased; A switching power converter as described in embodiment 70.

[0237] 72. The oscillator off period is varied to reduce variations in the drive signal switching cycle; A switching power converter as described in embodiment 70.

[0238] 73. The feedback signal is a control current; The oscillator off period is varied as a function of the control current; A switching power converter as described in embodiment 72.

[0239] 74. The duration of the falling segment is increased to reduce the variation of the output power as a function of the input voltage; A switching power converter as described in embodiment 73.

[0240] 75. A method for regulating a load current in accordance with a variable pulse width modulation (PWM) switching cycle including a PWM on period and a PWM off period, the method comprising: providing a switch current by turning on the switch at the beginning of a variable PWM switching cycle; providing a switch current feedback signal indicative of the switch current during the drive on period; switching the switch off at the end of the drive on period in response to the switch current feedback signal reaching a threshold value; determining a PWM on-period by comparing the drive on-period to a fixed on-period; providing an output feedback signal indicative of the load current; determining a modulation width relative to the output feedback signal; determining a PWM off-period by comparing the modulation width to a fixed off-period; A method comprising:

[0241] 76. Further comprising generating a variable PWM switching cycle using a current-controlled triangle wave generator. 76. The method of embodiment 75.

[0242] 77. Generating variable PWM switching cycles using a current-controlled triangle wave generator includes charging a capacitor with a current that is the difference between a fixed current and a current proportional to an output feedback signal; 77. The method of embodiment 76.

[0243] 78. Providing a feedforward signal indicative of an input power supply voltage; Varying the fixed off period relative to the feedforward signal; 76. The method of embodiment 75, further comprising:

[0244] 79. The switch current feedback signal is a voltage; 76. The method of embodiment 75.

[0245] 80. The threshold is constant. 76. The method of embodiment 75.

[0246] 81. The threshold is variable. 76. The method of embodiment 75.

[0247] 82. Thresholds change over time. 76. The method of embodiment 75.

[0248] 83. Switching the switch off at the end of the drive on period in response to the switch current feedback signal reaching a threshold includes providing slope compensation for the threshold. 76. The method of embodiment 75.

[0249] 84. Switching the switch off at the end of the drive on period in response to the switch current feedback signal reaching a threshold includes varying the threshold to adjust the ramp period of the switch current; 76. The method of embodiment 75.

[0250] 85. Determining the PWM on-period by comparing the drive on-period to the fixed on-period includes matching the PWM on-period to the fixed on-period when the fixed on-period is greater than the drive on-period; 76. The method of embodiment 75.

[0251] 86. Determining the PWM on-period by comparing the drive on-period to the fixed on-period includes matching the PWM on-period to the drive on-period when the fixed on-period is less than the drive on-period; 76. The method of embodiment 75.

[0252] 87. Providing an output feedback signal indicative of the load current includes providing a photodiode current using an optocoupler; 76. The method of embodiment 75.

[0253] 88. Determining the PWM off-period by comparing the modulation width to the fixed off-period includes matching the PWM off-period to the modulation width when the modulation width is greater than the fixed off-period; 76. The method of embodiment 75.

[0254] 89. Determining the PWM off period by comparing the modulation width to the fixed off period includes matching the PWM off period to the fixed off period when the modulation width is less than the fixed off period; 76. The method of embodiment 75.

Claims

1. 1. A switching power converter configured to convert input power to output power and to regulate an output voltage, the switching power converter comprising: a feedback circuit configured to provide a feedback signal indicative of the output voltage; an off-period modulator configured to generate a modulator signal having a modulation width determined at least in part by a magnitude of the feedback signal; an oscillator configured to provide an oscillator signal according to an oscillator switching cycle including an oscillator on-period and an oscillator off-period, the oscillator on-period being equal to or greater than a fixed on-period, and the oscillator off-period being at least partially determined by the modulation width; a switch configured to provide a switch current according to a drive signal switching cycle, the switch conducting the switch current during a drive on period, the drive signal switching cycle being determined by the oscillator switching cycle; A switching power converter comprising:

2. the switching power converter is a flyback power converter; 10. The switching power converter of claim 1.

3. When the drive on-period is less than the fixed on-period, the oscillator on-period is limited to the fixed on-period.

10. The switching power converter of claim 1.

4. the fixed on-duration is between three microseconds (3 us) and five microseconds (5 us); 4. The switching power converter of claim 3.

5. When the drive on period is greater than the fixed on period, the oscillator on period is equal to the drive on period.

4. The switching power converter of claim 3.

6. When the modulation width is less than a fixed off-period, the oscillator off-period is limited to the fixed off-period.

10. The switching power converter of claim 1.

7. the fixed off period is between one microsecond (1 us) and three microseconds (3 us); 7. The switching power converter of claim 6.

8. When the modulation width is greater than the fixed off-period, the oscillator off-period is equal to the modulation width.

7. The switching power converter of claim 6.

9. the oscillator is configured to generate a triangle wave having a rising segment and a falling segment; 10. The switching power converter of claim 1.

10. the oscillator on period is determined at least in part by the duration of the rising segment; 10. The switching power converter of claim 9.

11. the duration of the rising segment is between three microseconds (3 us) and five microseconds (5 us); 11. The switching power converter of claim 10.

12. When the drive-on period is greater than the duration of the rising segment, a transition period to the falling segment is delayed.

11. The switching power converter of claim 10.

13. the oscillator on period is determined by the duration of the rising segment and the duration of the transition period to the falling segment; 13. The switching power converter of claim 12.

14. the oscillator off period is determined at least in part by the duration of the falling segment; 10. The switching power converter of claim 9.

15. the duration of the descending segment is between one microsecond (1 us) and three microseconds (3 us); 15. The switching power converter of claim 14.

16. When the modulation width is greater than the duration of the falling segment, the transition to the rising segment of the subsequent cycle is delayed.

15. The switching power converter of claim 14.

17. the oscillator off period is determined at least in part by the duration of the falling segment and the duration of the transition to the rising segment of the subsequent cycle; 17. The switching power converter of claim 16.

18. the off-period modulator is configured to generate a sawtooth waveform during the falling segment; 18. The switching power converter of claim 17.

19. the modulation width is determined by comparing the sawtooth wave with a modulation reference; 20. The switching power converter of claim 18.

20. the output power is based at least in part on a load current; the input power is based at least in part on an input voltage; 18. The switching power converter of claim 17.

21. the duration of the falling segment is increased in response to an increase in the input voltage; 21. The switching power converter of claim 20.

22. the oscillator off period is varied to reduce variation in the drive signal switching cycle as a function of the load current; 21. The switching power converter of claim 20.

23. the feedback signal is a control current; the oscillator off period is varied to reduce variation in the drive signal switching cycle as a function of the control current; 23. The switching power converter of claim 22.

24. the duration of the falling segment is increased to reduce variation in the output power as a function of the input voltage; 24. The switching power converter of claim 23.

25. 1. A method for regulating an output voltage according to a variable switching cycle including a controlled on-period and a controlled off-period, the method comprising: providing a switch current by turning on a switch at a beginning of the variable switching cycle; providing a switch current feedback signal indicative of the switch current during a drive-on period; turning off the switch at the end of the drive-on period in response to the switch current feedback signal reaching a threshold value; determining the controlled on-duration by comparing the drive on-duration to a fixed on-duration; providing an output feedback signal indicative of the output voltage; determining a modulation width in relation to the output feedback signal; determining the controlled off-period by comparing the modulation width to a fixed off-period; A method comprising:

26. further comprising generating the variable switching cycle using a current controlled triangle wave generator.

26. The method of claim 25.

27. generating the variable switching cycle using the current-controlled triangle wave generator includes charging a capacitor with a current having a difference between a fixed current and a current proportional to the output feedback signal; 27. The method of claim 26.

28. providing a feedforward signal indicative of an input power supply voltage; Varying the fixed off-period relative to the feedforward signal; 26. The method of claim 25, further comprising:

29. the switch current feedback signal is a voltage; 26. The method of claim 25.

30. The threshold is constant.

26. The method of claim 25.

31. and switching off the switch at the end of the drive on period in response to the switch current feedback signal reaching the threshold value includes providing slope compensation for the threshold value.

26. The method of claim 25.

32. and switching off the switch at the end of the drive on period in response to the switch current feedback signal reaching the threshold value includes varying the threshold value to adjust a ramp period of the switch current.

26. The method of claim 25.

33. determining the controlled on-period by comparing the drive on-period to the fixed on-period includes limiting the controlled on-period to the fixed on-period when the fixed on-period is greater than the drive on-period; 26. The method of claim 25.

34. determining the controlled on-period by comparing the drive on-period to the fixed on-period includes limiting the controlled on-period to the drive on-period when the fixed on-period is less than the drive on-period; 26. The method of claim 25.

35. providing the output feedback signal indicative of the output voltage includes providing a photodiode current using an optocoupler.

26. The method of claim 25.

36. determining the controlled off-period by comparing the modulation width to the fixed off-period includes limiting the controlled off-period to the modulation width when the modulation width is greater than the fixed off-period; 26. The method of claim 25.

37. determining the controlled off-period by comparing the modulation width to the fixed off-period includes limiting the controlled off-period to the fixed off-period when the modulation width is less than the fixed off-period; 26. The method of claim 25.

Images