Method for manufacturing semiconductor chip, wafer laminate, and semiconductor chip

Abstract

To easily divide a wafer by a narrow scribe lane.SOLUTION: A method for manufacturing a semiconductor chip includes the steps of: preparing a wafer in which a plurality of semiconductor chips is arranged in a matrix in a first surface and at least one test circuit is provided in scribe lanes between the plurality of semiconductor chips; and performing etching on regions corresponding to the scribe lanes until the wafer is penetrated from a second surface opposite to the first surface. The test circuit has a layer structure partially formed of a first insulating film and the semiconductor chips have a layer structure partially formed of a second insulating film, and the first and second insulating layers are not continuous with each other.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor chip, a wafer stack, and a semiconductor chip. [Background technology]

[0002] In the manufacture of semiconductor chips, the semiconductor chips are formed in chip areas defined by division lines (also called scribe lanes) arranged in a grid pattern on the surface of a wafer. After the semiconductor chips are formed in the chip areas, the wafer is divided along the scribe lanes to separate the semiconductor chips.

[0003] Known methods for dividing a wafer to separate semiconductor chips include, for example, a method of physically cutting the wafer with a cutting blade, or a method of cutting the wafer with a laser beam.

[0004] On the other hand, as the size of semiconductor chips decreases, there is a demand for dividing wafers along narrower scribe lanes. For example, Patent Document 1 below discloses dividing wafers along narrower scribe lanes by using plasma etching. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-207737 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the technology disclosed in Patent Document 1, the wafer is etched from the surface side where the semiconductor chips are provided, so it is necessary to remove various films deposited on the area to be etched, which makes the process of dividing the wafer complicated.

[0007] Therefore, the present invention has been made in consideration of the above problems, and an object of the present invention is to provide a new and improved method for manufacturing semiconductor chips, a wafer stack, and semiconductor chips that enable wafers to be more easily divided along narrow scribe lanes. [Means for solving the problem]

[0008] In order to solve the above problem, according to one aspect of the present invention, there is provided a method for manufacturing a semiconductor chip, comprising the steps of: preparing a wafer having a plurality of semiconductor chips arranged in a matrix on a first surface and at least one test circuit provided in a scribe lane between the plurality of semiconductor chips; and etching an area corresponding to the scribe lane from a second surface opposite the first surface to a surface that penetrates the wafer, wherein an insulating film that forms part of the layered structure of the test circuit is discontinuous with an insulating film that forms part of the layered structure of the plurality of semiconductor chips.

[0009] In addition, in order to solve the above-mentioned problems, according to another aspect of the present invention, there is provided a wafer stack comprising: a wafer provided on a support plate, having a plurality of semiconductor chips arranged in a matrix on a surface facing the support plate; an opening provided through the wafer in an area between the plurality of semiconductor chips; and a test circuit provided inverted on the support plate exposed by the opening, wherein an insulating film forming part of the layered structure of the test circuit is discontinuous with an insulating film forming part of the layered structure of the plurality of semiconductor chips.

[0010] In addition, in order to solve the above problem, according to another aspect of the present invention, a semiconductor chip is provided, comprising a chip body and a semiconductor circuit provided on the chip body, and the surface of the chip body on which the semiconductor circuit is provided has an edge corner portion that protrudes toward the outside or a chamfered edge corner portion. [Effects of the Invention]

[0011] As described above, according to the present invention, it is possible to more easily divide a wafer using narrow scribe lanes. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a plan view showing a planar configuration of a wafer stack used in a method for manufacturing a semiconductor chip according to an embodiment of the present invention; [Figure 2] 1 is a cross-sectional view showing a cross-sectional configuration of a wafer stack used in a method for manufacturing a semiconductor chip according to an embodiment of the present invention. [Figure 3] 1 is a cross-sectional view illustrating one step in the method for manufacturing a semiconductor chip according to the present embodiment. [Figure 4] 1 is a cross-sectional view illustrating one step in the method for manufacturing a semiconductor chip according to the present embodiment. [Figure 5] 1 is a cross-sectional view illustrating one step in the method for manufacturing a semiconductor chip according to the present embodiment. [Figure 6] 1 is a cross-sectional view illustrating one step in the method for manufacturing a semiconductor chip according to the present embodiment. [Figure 7] FIG. 7 is a cross-sectional view showing an example of a semiconductor chip manufactured by the manufacturing method shown in FIGS. [Figure 8] FIG. 7 is a cross-sectional view showing another example of a semiconductor chip manufactured by the manufacturing method shown in FIGS. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant explanations will be omitted.

[0014] <1. Wafer stack> First, a wafer stack used in a method for manufacturing semiconductor chips according to one embodiment of the present invention will be described with reference to Figures 1 and 2. Figure 1 is a plan view showing the planar configuration of a wafer stack 10 used in the method for manufacturing semiconductor chips according to this embodiment. Figure 2 is a cross-sectional view showing the cross-sectional configuration of the wafer stack 10 used in the method for manufacturing semiconductor chips according to this embodiment.

[0015] 1, the wafer stack 10 according to this embodiment includes a wafer 100 and a plurality of semiconductor chips 110 on the surface of the wafer 100. Specifically, the wafer stack 10 includes the wafer 100, a plurality of semiconductor chips 110 arranged in a matrix on the wafer 100, and scribe lanes 120 arranged between the plurality of semiconductor chips 110.

[0016] The wafer 100 is a thin plate-like substrate made of a semiconductor such as silicon (Si). The wafer 100 may be a disk-shaped substrate thinly sliced ​​from a cylindrical ingot, or may be a substrate further cut into a rectangular plate from the disk-shaped substrate. Although not shown, the outer edge of the wafer 100 may be provided with a straight line (orientation flat) or a notch that serves as a guide for aligning the orientation of the wafer 100 during the manufacturing process of the semiconductor chip 110.

[0017] The wafer 100 may be, for example, a silicon (Si) wafer, a silicon carbide (SiC) wafer, or a compound semiconductor (GaN, InP, GaAs, GaP, etc.) wafer. The wafer 100 may also be a sapphire wafer or a quartz wafer with a semiconductor layer stacked on the surface.

[0018] The semiconductor chip 110 is an electronic component including an electronic circuit that realizes complex functions. Specifically, the semiconductor chip 110 may be an IC (Integrated Circuit) chip or the like including an electronic circuit in which semiconductor elements formed on the semiconductor constituting the wafer 100 are connected by fine wiring. The semiconductor chip 110 may be, for example, a rectangular shape with a side length of approximately 100 μm. Each of the semiconductor chips 110 arranged in a matrix on the surface of the wafer 100 may be, for example, the same electronic component having the same pattern. By forming a plurality of semiconductor chips 110 collectively on the surface of the wafer 100, manufacturing costs can be reduced.

[0019] The scribe lanes 120 are provided extending in a grid pattern between the semiconductor chips 110. The scribe lanes 120 are planned dividing lines for the wafer 100 when dividing the wafer into individual semiconductor chips 110 formed on the surface of the wafer 100. By digging the scribe lanes 120 by etching, the semiconductor chips 110 are separated from each other and divided into individual chips. The scribe lanes 120 are provided with a width of, for example, about 5 μm to 10 μm.

[0020] Furthermore, alignment marks AL and test circuits TE are provided in the scribe lane 120. The alignment marks AL and test circuits TE are provided inside the scribe lane 120 in the form of islands.

[0021] The alignment mark AL is provided for alignment during the manufacturing process of the semiconductor chip 110. The alignment mark AL may be a cross mark, a diffraction grating mark, a Fresnel zone plate, or the like. By detecting the alignment mark AL, multiple exposure processes during the manufacturing process of the semiconductor chip 110 can be superimposed with high positional accuracy.

[0022] The test circuit TE is formed to inspect the quality of the semiconductor chip 110. The test circuit TE includes, for example, a partial circuit for evaluating the performance and characteristics of the semiconductor chip 110. The test circuit TE may also include patterns such as wiring and contacts for evaluating the manufacturing process of the semiconductor chip 110, and may also include an electronic circuit for evaluating the performance and characteristics of semiconductor elements included in the semiconductor chip 110.

[0023] The alignment marks AL and the test circuits TE are provided in the shape of islands inside the scribe lanes 120, so that the constituent materials of the wafer 100 are exposed in the scribe lanes 120 between the alignment marks AL and the test circuits TE and the semiconductor chips 110. Therefore, the scribe lanes 120 where the constituent materials of the wafer 100 are exposed are dug out by etching, so that the semiconductor chips 110 are separated from one another and singulated. The distance between the alignment marks AL and the test circuits TE and the semiconductor chips 110 (i.e., the width over which the constituent materials of the wafer 100 are exposed) may be, for example, 0.5 μm to 1 μm.

[0024] Note that the constituent materials of wafer 100 being exposed means that no insulating film or metal film, etc. has been intentionally formed on wafer 100, and natural oxide films, etc. that automatically form on the surface of wafer 100 will be ignored.

[0025] 2, the semiconductor chip 110 and the test circuit TE are provided such that the insulating film 111 constituting a part of the layer structure of the semiconductor chip 110 and the insulating film 121 constituting a part of the layer structure of the test circuit TE are spaced apart from each other and discontinuous. Note that the alignment marks AL are not shown in FIG.

[0026] The insulating film 111 of the semiconductor chip 110 may be an interlayer insulating film or a sealing film of the semiconductor chip 110, and the metal film 112 provided on the insulating film 111 of the semiconductor chip 110 may be an input / output terminal of the semiconductor chip 110. Furthermore, the insulating film 121 of the test circuit TE may be an interlayer insulating film or a sealing film of the test circuit TE, and the metal film 122 provided on the insulating film 121 of the test circuit TE may be an input / output terminal of the test circuit TE.

[0027] When the insulating film 111 of the semiconductor chip 110 and the insulating film 121 of the test circuit TE are discontinuous with each other, the semiconductor chip 110 and the test circuit TE are substantially separated from each other. As a result, the constituent material of the wafer 100 is exposed in the scribe lane 120 between the semiconductor chip 110 and the test circuit TE, and as described above, the scribe lane 120 where the constituent material of the wafer 100 is exposed can be excavated by etching. As a result, the wafer 100 can be divided at the etched scribe lane 120, and the semiconductor chips 110 formed on the surface of the wafer 100 can be separated from each other and individualized.

[0028] At this time, the etching of the scribe lane 120 is performed from the back surface opposite to the front surface on which the semiconductor chip 110 and the test circuit TE are formed. Since the insulating films 111, 121 and the metal films 112, 122 are not provided on the back surface of the wafer 100, it is possible to directly etch the wafer 100 without etching the insulating films 111, 121 and the metal films 112, 122.

[0029] In the wafer stack 10 according to this embodiment, scribe lanes 120 including test circuits TE spaced apart from the semiconductor chips 110 are provided between a plurality of semiconductor chips 110 formed in a matrix on the surface of the wafer 100. Therefore, the wafer stack 10 can separate the wafers 100 into individual semiconductor chips 110 by etching the constituent material of the wafers 100 exposed in the scribe lanes 120. Because etching can process the wafers 100 at narrower widths than a cutting blade or a laser beam, the wafer stack 10 can separate the wafers 100 at narrower scribe lanes 120. Therefore, the wafer stack 10 according to this embodiment can increase the number of semiconductor chips 110 that can be formed from a single wafer 100 by narrowing the scribe lanes 120.

[0030] Furthermore, the wafer stack 10 can be more easily divided into wafers 100 by etching the wafers 100 from the back surface opposite to the front surface on which the semiconductor chips 110 and the test circuits TE are formed.

[0031] <2. Semiconductor Chip Manufacturing Method> Next, a method for manufacturing the semiconductor chip 110 according to this embodiment will be described with reference to Figures 3 to 6. Figures 3 to 6 are cross-sectional views illustrating each step of the method for manufacturing the semiconductor chip 110 according to this embodiment.

[0032] First, as shown in Fig. 3, the wafer stack 10 shown in Fig. 1 and Fig. 2 is prepared. Next, a support plate 200 that covers the semiconductor chips 110 and the test circuits TE is attached to a first surface S1 of the wafer 100 on which the semiconductor chips 110 and the test circuits TE are formed. The support plate 200 is, for example, a plate-like member that is the same as or larger than the wafer 100. The support plate 200 may be made of the same constituent material as the wafer 100, such as silicon, to match the thermal expansion coefficient with that of the wafer 100.

[0033] Next, as shown in FIG. 4, a mask layer 300 is provided on a second surface S2 of the wafer 100 opposite the first surface S1, and an opening H1 corresponding to the scribe lane 120 is provided in the mask layer 300. The mask layer 300 is made of a resist material compatible with photolithography. Photolithography is capable of forming finer patterns and has high positioning accuracy. Therefore, by making the mask layer 300 of a resist material compatible with photolithography, the opening H1 corresponding to the scribe lane 120 is formed in the mask layer 300 with a narrow width and high accuracy.

[0034] 5, the wafer 100 is etched from the second surface S2 through the wafer 100 until the support plate 200 is exposed. As a result, openings H2 corresponding to the scribe lanes 120 are formed in the wafer 100, and the wafer 100 is divided along the scribe lanes 120. At this time, the insulating film 111 and the metal film 112 of the semiconductor chip 110 are discontinuous with the insulating film 111 and the metal film 112 of the other semiconductor chips 110 and the insulating film 121 and the metal film 122 of the test circuit TE, so that each semiconductor chip 110 is separated into individual pieces. In this way, the wafer 100 is divided by etching, which enables finer processing, and therefore each semiconductor chip 110 is separated into individual pieces along the narrower scribe lanes 120.

[0035] The wafer 100 can be etched by either dry etching or wet etching. However, to etch a narrower scribe lane 120, it is desirable to etch the wafer 100 by dry etching with vertical anisotropy, such as plasma etching. In this case, the occurrence of side cuts and the like that would widen the etching width of the scribe lane 120 is suppressed.

[0036] 6, the mask layer 300 provided on the second surface S2 of the wafer 100 is removed. At this time, the wafer 100, on the surface facing the support plate 200, has a plurality of semiconductor chips 110 arranged in a matrix, and a test circuit TE provided in an inverted manner between the plurality of semiconductor chips 110. The plurality of semiconductor chips 110 are separated by openings H2 provided through the wafer 100, and the insulating film 111 is provided so as to be discontinuous with the insulating film 121 of the test circuit TE. As a result, the plurality of semiconductor chips 110 are separated from one another. Therefore, the plurality of semiconductor chips 110 are peeled off from the support plate 200, and individual semiconductor chips 110 are manufactured.

[0037] 3. Semiconductor chips Next, features of the semiconductor chip 110 manufactured by the manufacturing method shown in Figures 3 to 6 will be described with reference to Figures 7 and 8. Figure 7 is a cross-sectional view showing an example of the semiconductor chip 110 manufactured by the manufacturing method shown in Figures 3 to 6. Figure 8 is a cross-sectional view showing another example of the semiconductor chip 110 manufactured by the manufacturing method shown in Figures 3 to 6.

[0038] 3 to 6, the wafer 100 is etched from the second surface S2 opposite to the first surface S1 on which the insulating film 111 and the metal film 112 are provided. Therefore, the edge corner E2 on the second surface S2 side, where etching starts, has a shape that is nearly a right angle according to the taper angle of the opening H2 formed by etching.

[0039] On the other hand, the edge corner E1 on the first surface S1 side, where etching is completed, does not achieve a shape close to a right angle due to variations in the progress of etching within the opening H2. Specifically, if the etching is under-etching, burrs 101 protruding toward the opening H2 side are generated as etching residues at the edge corner E1 on the first surface S1 side, as shown in Figure 7. Furthermore, if the etching is over-etching, chipped portions 102 chamfered on the side opposite the opening H2 are generated as a result of excessive etching at the edge corner E1 on the first surface S1 side, as shown in Figure 8.

[0040] Therefore, by analyzing the shapes of the edge corners E1 and E2 on each surface of the semiconductor chip 110, it is possible to identify the etching direction when dividing the wafer 100.

[0041] Although the preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings, the present invention is not limited to these examples. It is clear that a person skilled in the art to which the present invention pertains can conceive of various modifications and alterations within the scope of the technical ideas set forth in the claims, and it is understood that these also naturally fall within the technical scope of the present invention. [Explanation of symbols]

[0042] 10...wafer stack, 100...wafer, 110...semiconductor chip, 111...insulating film, 112...metal film, 120...scribe lane, 121...insulating film, 122...metal film, 200...support plate, 300...mask layer, TE...test circuit, AL...alignment mark, S1...first surface, S2...second surface

Claims

1. preparing a wafer having a plurality of semiconductor chips arranged in a matrix on a first surface thereof and at least one test circuit provided in a scribe lane between the plurality of semiconductor chips; etching a region corresponding to the scribe lane from a second surface opposite the first surface to a surface that penetrates the wafer; Including, A method for manufacturing a semiconductor chip, wherein an insulating film that forms part of a layer structure of the test circuit is discontinuous with an insulating film that forms part of a layer structure of the plurality of semiconductor chips.

2. The method for manufacturing semiconductor chips according to claim 1 , further comprising the step of attaching a support plate covering the plurality of semiconductor chips and the test circuit to the first surface of the prepared wafer.

3. forming openings corresponding to the scribe lanes in a mask layer provided on the second surface of the wafer to which the support plate is attached by photolithography; The method for manufacturing a semiconductor chip according to claim 2 , wherein the etching is performed on the opening.

4. The method for manufacturing semiconductor chips according to claim 3 , further comprising the step of separating the plurality of semiconductor chips into individual chips by peeling the plurality of semiconductor chips from the support plate after the etching is performed.

5. 5. The method for manufacturing a semiconductor chip according to claim 1, wherein the etching is vertically anisotropic etching.

6. 5. The method for manufacturing semiconductor chips according to claim 1, wherein the test circuit is provided in an island shape inside the scribe lane and separated from the plurality of semiconductor chips.

7. 5. The method for manufacturing a semiconductor chip according to claim 1, wherein a constituent material of the wafer is exposed in a region between the test circuit and the plurality of semiconductor chips.

8. 5. The method for manufacturing a semiconductor chip according to claim 1, wherein the insulating films of the plurality of semiconductor chips are interlayer insulating films or sealing films of the plurality of semiconductor chips.

9. a wafer provided on a support plate, the wafer having a plurality of semiconductor chips arranged in a matrix on a surface facing the support plate; an opening formed through the wafer in a region between the plurality of semiconductor chips; a test circuit provided in an inverted manner on the support plate exposed through the opening; Equipped with a wafer stack, wherein an insulating film that constitutes a part of the layer structure of the test circuit is discontinuous with an insulating film that constitutes a part of the layer structure of the plurality of semiconductor chips;

10. A chip body; a semiconductor circuit provided on the chip body; Equipped with A semiconductor chip, wherein the surface of the chip body on which the semiconductor circuit is provided has an edge corner that protrudes outward or a chamfered edge corner.

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