Method for manufacturing semiconductor wafer and semiconductor wafer
By arranging semiconductor chips in a matrix with aligned test areas, the method reduces scribe lane width to 0.5 μm to 10 μm, addressing the challenge of narrow chip separation and enabling efficient transfer to alignment substrates.
JP2025175637APending Publication Date: 2025-12-03KK TOKAI RIKA DENKI SEISAKUSHO
Patent Information
- Application Number
- JP2024081844
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-05-20
- Publication Date
- 2025-12-03
AI Technical Summary
Technical Problem
Existing semiconductor wafers face challenges in reducing the width of scribe lanes where accessory patterns are formed, particularly those extending in directions where the wafer cannot be cleaved.
Method used
A method and structure for manufacturing semiconductor wafers that include forming semiconductor chips in a matrix within chip areas and test circuits in test areas along the edges, with the shot areas arranged to align the matrix direction of chips, allowing for narrower scribe lanes.
Benefits of technology
This approach enables the reduction of scribe lane width to 0.5 μm to 10 μm, facilitating efficient division of semiconductor chips without gaps, and supports seamless transfer to alignment substrates for further applications.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure 2025175637000001_ABST
Abstract
To reduce the widths of scribe lanes in various different directions provided in a grid pattern on a semiconductor wafer.SOLUTION: A method for manufacturing a semiconductor wafer includes the step of: forming a plurality of semiconductor chips in a matrix in chip regions included in a plurality of shot regions on a wafer body, and forming a test circuit in a test region provided along the edge side of each chip region, the plurality of shot regions being on the wafer body such that the directions of the matrix of the semiconductor chips are aligned with one another among the plurality of shot regions.SELECTED DRAWING: Figure 3
Need to check novelty before this filing date? Find Prior Art
Citation Information
Patent Citations
Semiconductor wafer and manufacturing method of the same
JP2016134427A