Minimizing reflected power in adjustable edge sheath system

Abstract

To provide a method for controlling reflected power in a plasma processing system.SOLUTION: A method includes the steps of: applying RF power from first generators 147, 149 to an ESC; applying RE power from a second generator 403 to an edge electrode 415 that surrounds the ESC and is disposed below an edge ring 167 that surrounds the ESC, the RF power obtained from the second generator 403 having a voltage set based on the amount of use of the edge ring 167, where the second generator 403 automatically introduces a phase adjustment so that a phase of the RF power obtained from the second generator 403 substantially matches a phase of the RF power obtained from the first generators 147, 149; and adjusting a variable capacitor of a match circuit through which the RF power obtained from the second generator 403 is applied to tune the phase adjustment to a target phase adjustment setting.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor device fabrication. [Background technology]

[0002] Plasma etching processes are often used in the fabrication of semiconductor devices on semiconductor wafers. In plasma etching processes, semiconductor wafers containing semiconductor devices under fabrication are exposed to plasma generated within a plasma processing volume. The plasma interacts with one or more materials on the semiconductor wafer to remove one or more materials from the semiconductor wafer and / or modify one or more materials, allowing the one or more materials to subsequently be removed from the semiconductor wafer. Plasma can be generated using specific reactant gases that react with one or more materials to be removed / modified from the semiconductor wafer without significantly interacting with other materials on the wafer that are not removed / modified. Plasma is generated by energizing the specific reactant gases using radio frequency signals. These radio frequency signals are transmitted through a plasma processing volume containing the reactant gases, and the semiconductor wafer is held exposed to the plasma processing volume. The transmission path of the radio frequency signals through the plasma processing volume can affect how the plasma is generated within the plasma processing volume. For example, reactant gases may be more energized in areas of the plasma processing volume where greater amounts of radio frequency signals are transmitted, thereby causing spatial non-uniformities in plasma characteristics throughout the plasma processing volume. The spatial non-uniformities in plasma characteristics may manifest as spatial non-uniformities in ion density, ion energy, and / or reactive constituent density, among other plasma characteristics. Correspondingly, the spatial non-uniformities in plasma characteristics may cause spatial non-uniformities in plasma processing results on a semiconductor wafer. Therefore, the manner in which radio frequency signals are transmitted through a plasma processing volume may affect the uniformity of plasma processing results on a semiconductor wafer. It is in this regard that the present disclosure has been developed. Summary of the Invention

[0003] Broadly, embodiments of the present disclosure provide a method and system for minimizing reflected power in a tunable edge sheath (TES) system whereby the edge electrode is powered separately and independently from the main electrode of an electrostatic chuck (ESC). First, a TES voltage set point is set. The TES RF generator automatically generates a voltage to match the TES voltage set point by adjusting its RF power (i.e., by adjusting its power amplifier output).

[0004] The TES RF generator automatically determines the phase delta, which is the phase difference between the 400 kHz signal derived from the primary RF generator and the 400 kHz signal derived from the TES RF generator. The TES RF generator automatically determines and sets its phase actuator position required to minimize the phase delta (between the TES RF signal and the primary RF signal) to zero or near zero. At this point, the TES RF generator is operating to generate a TES voltage as close as possible to the TES voltage setpoint while further minimizing the phase delta. However, the TES RF generator does not make any adjustments to minimize reflected power (i.e., gamma).

[0005] To minimize reflected power (gamma), the capacitor tap position is adjusted in the matcher of the TES system. There is a specific capacitor tap position where the reflected power is minimized. The capacitor tap position is adjusted in a stepwise manner until the minimum reflected power (gamma) is achieved. At each capacitor tap adjustment step, the TES RF generator automatically adjusts the power amplifier and phase actuator positions to maintain the set point and minimize the phase delta.

[0006] The capacitor tap position search is complete when the minimum reflected power (gamma) is achieved. At this point, for a particular TES voltage setpoint, the TES RF generator has operated its power amplifier as necessary to not only 1) achieve the TES voltage setpoint, but also 2) minimize the phase delta and hold the phase actuator position, while simultaneously achieving the minimum reflected power (gamma).

[0007] During processing, it may be necessary to adjust the TES setpoint voltage. For example, wear of the edge ring may require the TES setpoint voltage to be adjusted. When adjusting the TES setpoint voltage, system parameters must be changed to optimize for the above objectives. When changing the TES setpoint voltage, the TES RF generator automatically adjusts the power amplifier and phase actuator to maintain the setpoint voltage and minimize the phase delta. However, this will likely result in reflected power (gamma) not being minimized. Therefore, a new capacitor tap position must be found that minimizes the reflected power (gamma). This search for a new capacitor tap position can be accomplished using the same techniques described above.

[0008] It has further surprisingly been discovered that when the TES setpoint voltage is changed for a given recipe (i.e., for a given chemistry, pressure, temperature, etc.) and the capacitor tap position is set to minimize reflected power, the phase actuator position that minimizes the phase delta remains substantially the same. Thus, the phase actuator position (which results in minimum reflected power) can define a target phase adjustment for any TES voltage setpoint for a given recipe, and the capacitor tap position can be optimized by automatically adjusting the phase actuator position until it returns to the target phase adjustment.

[0009] In an example embodiment, a method for controlling reflected power in a plasma processing system is provided, the method including the steps of applying RF power derived from a first generator to an ESC; applying RF power derived from a second generator to an edge electrode surrounding the ESC and disposed below an edge ring surrounding the ESC, the RF power derived from the second generator having a voltage set based on edge ring usage, the second generator automatically introducing a phase adjustment such that the phase of the RF power derived from the second generator matches the phase of the RF power derived from the first generator; and adjusting a variable capacitor in a matching circuit to which the RF power derived from the second generator is applied to adjust the phase adjustment to a target phase adjustment setting.

[0010] In some implementations, the method further includes determining edge ring usage and initiating adjustment of a variable capacitor of the matching circuit when edge ring usage reaches a target level.

[0011] In some implementations, the target level and target phase adjustment settings are captured via a user interface.

[0012] In some implementations, the target level varies according to one or more criteria.

[0013] In some implementations, the target phase adjust setting defines a predefined phase adjust amount by which to adjust the phase of the RF power obtained from the secondary generator.

[0014] In some implementations, adjusting the variable capacitor to regulate the phase adjustment includes performing incremental tap adjustments on the variable capacitor until the phase adjustment reaches a target phase adjustment setting.

[0015] In some implementations, the phase adjustment is adjusted to the target phase adjustment setting when the target phase adjustment setting is reached or is within a predefined target phase adjustment setting range.

[0016] In some implementations, adjusting the variable capacitor to tune the phase adjustment to a target phase adjustment setting minimizes reflection of RF power back to the secondary generator.

[0017] In some implementations, the target phase adjustment setting that minimizes the reflection of RF power back to the secondary generator remains substantially the same with respect to changes in the set voltage based on edge ring usage.

[0018] In some implementations, the edge ring usage is determined by at least one of the number of hours of RF exposure of the edge ring and the voltage of the RF power obtained from the second generator, which is set based on the number of hours of RF exposure.

[0019] In some implementations, a method for minimizing reflected power in a plasma processing system is provided, the method including: applying RF power derived from a first generator to an ESC; applying RF power derived from a second generator to an edge electrode surrounding the ESC, the RF power derived from the second generator having a voltage set to a predefined first voltage, the second generator introducing a phase adjustment by a predefined phase adjustment amount such that a phase of the RF power derived from the second generator substantially matches a phase of the RF power derived from the first generator; changing the voltage of the RF power derived from the second generator from the predefined first voltage to a predefined second voltage, changing the phase adjustment from the predefined phase adjustment amount; and adjusting a capacitance of a matching circuit to which the RF power derived from the second generator is applied in response to changing the voltage to return the changed phase adjustment to the predefined phase adjustment amount.

[0020] In some implementations, the method further includes determining an edge ring usage amount positioned on top of the edge electrode and surrounding the ESC, and initiating a voltage change of the RF power obtained from the second generator when the edge ring usage amount reaches a target level.

[0021] In some implementations, the target level and predefined phase adjustment amount are captured via a user interface.

[0022] In some implementations, the target level varies according to one or more criteria.

[0023] In some implementations, adjusting the capacitance of the matching circuit includes performing incremental tap adjustments of the capacitance until the changed phase adjustment reaches a predefined phase adjustment amount.

[0024] In some implementations, the phase adjustment is returned to a predefined phase adjustment amount when the predefined phase adjustment amount is reached or is within a predefined range of the predefined phase adjustment amount.

[0025] In some implementations, adjusting the capacitance to return the phase adjustment to a predefined amount of phase adjustment minimizes reflection of RF power back to the second generator.

[0026] In some implementations, the predefined amount of phase adjustment that minimizes the reflection of RF power back to the secondary generator remains substantially the same with respect to changes in the set voltage based on edge ring usage.

[0027] In some implementations, the edge ring usage is determined by at least one of the number of hours of RF exposure of the edge ring and the voltage of the RF power obtained from the second generator, which is set based on the number of hours of RF exposure. [Brief explanation of the drawings]

[0028] [Figure 1] 1 shows a vertical cross-sectional view through a portion of a plasma processing system 100 for use in semiconductor chip manufacturing, according to some embodiments.

[0029] [Figure 2]1 shows a vertical cross-sectional view of a plasma processing system for use in semiconductor chip manufacturing, according to some embodiments.

[0030] [Figure 3] 1 illustrates an example electrical schematic of a TES impedance matching system, according to some embodiments.

[0031] [Figure 4] 4 is a graph illustrating the relationship between reflected power and capacitor tap position in a TES impedance matching system 401 according to some embodiments.

[0032] [Figure 5] 4 is a graph illustrating reflected power versus phase actuator position of the TES RF signal generator 403 according to some embodiments.

[0033] [Figure 6] 10 is a graph illustrating phase actuator position versus capacitor tap position in accordance with some embodiments.

[0034] [Figure 7] Illustrates a method for optimizing TES matching capacitor tap locations to minimize reflected power (i.e., gamma) in consideration of changing the TES voltage setpoint to compensate for edge ring wear, according to an implementation of the present disclosure.

[0035] [Figure 8] 3 shows an example schematic diagram of the control system of FIG. 2 according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0036] In the following description, numerous specific details are set forth in order to provide an understanding of embodiments of the present disclosure. However, it will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail in order to avoid unnecessarily obscuring the present disclosure.

[0037] In plasma etching systems for semiconductor wafer fabrication, spatial variations in etching results across a semiconductor wafer can be characterized by radial etch uniformity and azimuthal etch uniformity. Radial etch uniformity can be characterized by the variation in etch rate as a function of radial position on the semiconductor wafer, extending outward from the center of the semiconductor wafer to the edge of the semiconductor wafer at a given azimuthal position on the semiconductor wafer. And azimuthal etch uniformity can be characterized by the variation in etch rate as a function of azimuthal position on the semiconductor wafer, centered on the center of the semiconductor wafer at a given radial position on the semiconductor wafer. In some plasma processing systems, such as those described herein, the semiconductor wafer is positioned over an electrode where a radio frequency signal is generated to generate a plasma within a plasma generation zone overlying the semiconductor wafer, and the plasma characteristics are controlled to perform a prescribed etching process on the semiconductor wafer.

[0038] 1 shows a vertical cross-sectional view through a portion of a plasma processing system 100 for use in semiconductor chip manufacturing, according to some embodiments. The plasma processing system 100 includes an electrode 109, which in some embodiments is formed from aluminum. A ceramic layer 110 is formed on a top surface of the electrode 109. The ceramic layer 110 is configured to receive and support a wafer W during plasma processing operations on the wafer W. In some implementations, the ceramic layer 110, the electrode 109, and associated components define an electrostatic chuck (ESC).

[0039] A first radio frequency signal generator 147 (e.g., about 60 MHz) and a second radio frequency signal generator 149 (e.g., about 400 kHz) provide radio frequency power to the electrode 109 through an impedance match system 143. By applying radio frequency power into gas species introduced into the processing space above the wafer, a plasma 180 is produced for wafer processing, such as for etching.

[0040] The edge ring 167 surrounds the ceramic layer 110 and is configured to facilitate extension of the plasma sheath radially outward beyond the peripheral edge of the wafer W to improve processing results near the periphery of the wafer W.

[0041] An adjustable edge sheath (TES) system is implemented to include a TES electrode 415 disposed (embedded) within the coupling ring 161. A TES radio frequency signal generator 403 provides radio frequency power to the TES electrode 415 through a TES impedance match system 401. The TES system can control properties of the plasma 180 near the peripheral edge of the wafer W, such as controlling the nature of the plasma sheath, the plasma density, and the attraction or repulsion of ions. Broadly, by applying radio frequency power to the TES electrode 415, the TES system enables tuning of the plasma at the edge of the wafer to improve radial uniformity.

[0042] For a given process recipe, process recipe parameters, including parameters for the TES system, are set to provide radial uniformity. For example, in the illustrated implementation, for an edge ring 167 having a starting thickness J1, radio frequency power is provided by the TES radio frequency signal generator 403 at a first voltage V1 configured to adjust the plasma sheath, as shown at S1, to have a height H1 above the top surface of the wafer W at the edge or peripheral area of ​​the wafer W.

[0043] However, during plasma processing, the edge ring 167 is partially consumed, or worn away, such that the thickness of the edge ring 167 gradually decreases over its lifetime as RF time and processing cycles accumulate. As a result, for example, over a number of RF hours, the thickness of the edge ring 167 may decrease from a thickness J1 to a thickness J2. As the thickness of the edge ring 167 decreases and voltage V1 is applied during processing, the level of the plasma sheath also decreases. For example, when the thickness of the edge ring 167 is worn down to a thickness J2, the plasma sheath drops to a level indicated as S2, dropping to a height H2 across the entire top surface of the wafer W at the edge of the wafer.

[0044] This reduction in edge ring thickness and the resulting change in plasma sheath level at the wafer edge can cause radial non-uniformity at the edge, for example, there can be a difference in etch rate at the edge relative to the center of the wafer (etch rate and etch depth non-uniformity) and the feature profile will tilt at the edge (etch direction non-uniformity).

[0045] Therefore, to counteract the effects of edge ring wear / consumption and maintain the plasma sheath level despite the loss of edge ring thickness, the voltage applied to the TES electrode 415 can be increased to a second voltage V2. In the illustrated implementation, when voltage V2 (higher than voltage V1) is applied by the TES radio frequency signal generator 403 and the edge sheath thickness is reduced to thickness J2, the plasma sheath is restored to the plasma sheath indicated by reference symbol S1. That is, even though the thickness of the edge ring 167 has decreased, the plasma sheath level is maintained by applying a high voltage in the TES system.

[0046] However, increasing the voltage applied to the TES electrode 415 changes the impedance of the system, resulting in increased reflection of radio frequency power. To minimize reflected radio frequency power, the capacitance setting of the TES impedance matching system 401 can be adjusted, as discussed in more detail below.

[0047] Note that the TES radio frequency signal generator 403 is configured to automatically adjust the phase of the radio frequency signal it generates to match the phase of the radio frequency signal generated by the radio frequency signal generator 149 (e.g., at 400 kHz). As a result, as the voltage applied to the TES electrode 415 is increased, the TES radio frequency signal generator 401 automatically adjusts to maintain phase alignment with the radio frequency signal obtained from the radio frequency signal generator 149. It has been discovered that adjusting the capacitance setting in the TES impedance matching system to minimize reflected radio frequency power is an adjustment of the capacitance setting (which is automatic) that causes the phase adjustment by the TES radio frequency signal generator 403 to substantially return to the original phase adjustment amount for the original voltage (before it was increased to compensate for edge ring wear). As a result, the phase adjustment amount can be used to optimize the capacitance setting in the TES impedance matching system.

[0048] FIG. 2 shows a vertical cross-section through a plasma processing system 100 for use in semiconductor chip manufacturing, according to some embodiments. The system 100 includes a chamber 101 formed by walls 101A, a top member 101B, and a bottom member 101C. The walls 101A, top member 101B, and bottom member 101C collectively form an interior region 103 within the chamber 101. The bottom member 101C includes an exhaust port 105 through which exhaust gases resulting from plasma processing operations are directed. In some embodiments, during operation, a suction force is applied at the exhaust port 105, such as by a turbo pump or other vacuum device, to draw process exhaust gases out of the interior region 103 of the chamber 101. In some embodiments, the chamber 101 is formed from aluminum. However, in various embodiments, the chamber 101 can be formed from virtually any material that provides sufficient mechanical strength, acceptable thermal performance, and is chemically compatible with other materials exposed and matched during plasma processing operations within the chamber 101, such as stainless steel, among others. At least one wall 101A of the chamber 101 includes a door 107 for transferring semiconductor wafers W into and out of the chamber 101. In some embodiments, the door 107 is configured as a slit valve door.

[0049] In some embodiments, a semiconductor wafer W is a semiconductor wafer undergoing a fabrication procedure. For ease of discussion, a semiconductor wafer W is hereinafter referred to as a wafer W. However, it should be understood that in various embodiments, a wafer W can be virtually any type of substrate that undergoes a plasma-based fabrication process. For example, in some embodiments, a wafer W as referred to herein can be a substrate formed from silicon, sapphire, GaN, GaAs, or SiC, or other substrate materials, and can include glass panels / substrates, metal foils, metal sheets, polymeric materials, etc. Also, in various embodiments, a wafer W as referred to herein can vary in shape, shape, and / or size. For example, in some embodiments, a wafer W as referred to herein can correspond to a circular semiconductor wafer on which integrated circuit devices are fabricated. In various embodiments, a circular wafer W can have a diameter of 200 mm (millimeters), 300 mm, 450 mm, or another size. Also, in some embodiments, a wafer W as referred to herein can correspond to a non-circular substrate, such as a rectangular substrate for a flat panel display, among other shapes.

[0050] The plasma processing system 100 includes an electrode 109 positioned on a facility plate 111. In some embodiments, the electrode 109 and the facility plate 111 are formed from aluminum. However, in other embodiments, the electrode 109 and the facility plate 111 can be formed from another electrically conductive material with sufficient mechanical strength and compatible thermal and chemical performance characteristics. A ceramic layer 110 is formed on the top surface of the electrode 109. In some embodiments, the ceramic layer has a vertical thickness of about 1.25 millimeters (mm) as measured perpendicular to the top surface of the electrode 109. However, in other embodiments, the ceramic layer 110 can have a vertical thickness greater than or less than 1.25 mm. The ceramic layer 110 is configured to receive and support a wafer W during plasma processing operations thereon. In some embodiments, the top surface of an electrode 190 located radially outward of the ceramic layer 110 and the peripheral side surface of the electrode 190 are coated with a ceramic spray coat.

[0051] The ceramic layer 110 includes an arrangement of one or more clamping electrodes 112 for generating an electrostatic force that holds the wafer W against the top surface of the ceramic layer 110. In some embodiments, the ceramic layer 110 includes an arrangement of two clamping electrodes 112 that operate in a bipolar manner to provide a clamping force to the wafer W. The clamping electrodes 112 are connected to a direct current (DC) source 117 that generates a controlled clamping voltage that holds the wafer W against the top surface of the ceramic layer 110. Electrical wires 119A, 119B are connected between the DC power supply 117 and the facility plate 111. Electrical wires / conductors are routed through the facility plate 111 and the electrode 109 to electrically connect the electrical wires 119A, 119B to the clamping electrodes 112. The DC source 117 is connected to a control system 120 through one or more signal conductors 121.

[0052] The electrode 109 also includes an array of temperature control fluid channels 123 through which a temperature control fluid flows to control the temperature of the electrode 109 and, in turn, the temperature of the wafer W. The temperature control fluid channels 123 are plumbed (fluidly connected) to ports on the facility plate 111. Temperature control fluid supply and return lines are connected to corresponding ports on the facility plate 111, as indicated by arrows 126, and to a temperature control fluid circulation system 125. The temperature control fluid circulation system 125 includes a temperature control fluid supply, a temperature control fluid pump, and a heat exchanger, among other equipment, to provide a controlled flow of temperature control fluid through the electrode 109 to obtain and maintain a predetermined wafer W temperature. The temperature control fluid circulation system 125 is connected to the control system 120 through one or more signal conductors 127. In various embodiments, different types of temperature control fluids can be used, such as water or a refrigerant liquid / gas. Also, in some embodiments, the temperature control fluid channels 123 are configured to allow for spatially varying temperature control of the wafer W, such as in two dimensions (x and y) across the wafer W.

[0053] Ceramic layer 110 also includes an array of backside gas supply ports (not shown) fluidly connected to corresponding backside gas supply channels within electrode 109. The backside gas supply channels within electrode 109 are routed through electrode 109 to the interface between electrode 109 and facility plate 111. One or more backside gas supply lines are connected to ports on facility plate 111, as indicated by arrow 130, and to a backside gas supply system 129. Facility plate 111 is configured to supply one or more backside gases from the one or more backside gas supply lines to the backside gas supply channels within electrode 109. Backside gas supply system 129 includes, among other equipment, a backside gas source, a mass flow controller, and a flow control valve to provide a controlled flow of backside gas through the array of backside gas supply ports within ceramic layer 110. In some embodiments, backside gas supply system 129 also includes one or more components for controlling the temperature of the backside gas. In some embodiments, the backside gas is helium. Additionally, in some embodiments, a backside gas supply system 129 can be used to supply clean dry air (CDA) to an array of backside gas supply ports in the ceramic layer 110. The backside gas supply system 129 is connected to the control system 120 through one or more signal conductors 131.

[0054] Three lift pins 132 extend through the facility plate 111, the electrode 109, and the ceramic layer 110 to provide vertical movement of the wafer W relative to the top surface of the ceramic layer 110. In some embodiments, the vertical movement of the lift pins 132 is controlled by corresponding electromechanical and / or pneumatic lifting devices 133 connected to the facility plate 111. The three lifting devices 133 are connected to the control system 120 through one or more signal conductors 134. In some embodiments, the three lift pins 132 are positioned to have substantially equal azimuthal spacing about a vertical centerline of the electrode 109 / ceramic layer 110, which extends perpendicular to the top surface of the ceramic layer 110. It should be understood that the lift pins 132 are raised to accept and remove a wafer W into and from the chamber 101. The lift pins 132 are also lowered to allow a wafer W to rest on the top surface of the ceramic layer 110 during processing.

[0055] Additionally, in various embodiments, one or more of electrode 109, facility plate 111, ceramic layer 110, clamp electrode 112, lifting pins 132, or virtually any other component associated therewith, can be equipped to include one or more sensors, such as sensors for temperature, voltage, and current measurements, among others. Any sensors located within electrode 109, facility plate 111, ceramic layer 110, clamp electrode 112, lifting pins 132, or virtually any other component associated therewith, are connected to control system 120 via electrical wires, optical fibers, or through a wireless connection.

[0056] The facility plate 111 is set within an opening in, and supported by, a ceramic support 113. The ceramic support 113 is positioned on a support surface 114 of a cantilever arm assembly 115. In some embodiments, the ceramic support 113 has a substantially annular shape, thereby substantially defining the outer radial periphery of the facility plate 111, while also providing a support surface 116 on which a lowermost outer peripheral surface of the facility plate 111 rests. The cantilever arm assembly 115 extends through the wall 101A of the chamber 101. In some embodiments, a sealing mechanism 135 is provided within the wall 101A of the chamber 101, where the cantilever arm assembly 115 is positioned to provide a seal for the interior area 103 of the chamber 101, while also allowing the cantilever arm assembly 115 to move up and down in the z-direction in a controlled manner.

[0057] The cantilever arm assembly 115 has an open area 118 through which various instruments, wires, cables, and tubing are routed to support the operation of the system 100. The open area 118 within the cantilever arm assembly is exposed to the ambient atmospheric conditions outside the chamber 101, such as the air composition, temperature, pressure, and relative humidity. Additionally, a radio frequency signal feed rod 137 is positioned inside the cantilever arm assembly 115. More specifically, the radio frequency signal feed rod 137 is positioned inside an electrical conduit 139 such that it is spaced apart from the inner wall of the conduit 139. The sizes of the radio frequency signal feed rod 137 and the conduit 139 may vary. The area inside the conduit 139 between the inner wall of the conduit 139 and the radio frequency signal feed rod 137 is occupied by air along the entire length of the conduit 139. In some embodiments, the outer diameter (D rod ) and the inner diameter of the pipe 139 (D tube ) is related to the relation ln(D tube / D rod )≧e 1 is set to satisfy

[0058] In some embodiments, the radio frequency signal feed rod 137 is substantially centered within the tube 139, such that a substantially uniform radial thickness of air exists between the radio frequency signal feed rod 137 and the inner wall of the tube 139 along the entire length of the tube 139. However, in some embodiments, the radio frequency signal feed rod 137 is not centered within the tube 139, but rather, air gaps exist within the tube 139 at all locations between the radio frequency signal feed rod 137 and the inner wall of the tube 139 along the entire length of the tube 139. The delivery end of the radio frequency signal feed rod 137 is electrically and physically connected to the lower end of the radio frequency signal feed shaft 141. In some embodiments, the delivery end of the radio frequency signal feed rod 137 is bolted to the lower end of the radio frequency signal feed shaft 141. The upper end of the radio frequency signal feed shaft 141 is electrically and physically connected to the bottom of the facility plate 111. In some embodiments, the upper end of the radio frequency signal feed shaft 141 is bolted to the bottom of the facility plate 111. In some embodiments, both the radio frequency signal feed rod 137 and the radio frequency signal feed shaft 141 are formed from copper. In some embodiments, the radio frequency signal feed rod 137 is formed from copper, aluminum, or anodized aluminum. In some embodiments, the radio frequency signal feed shaft 141 is formed from copper, aluminum, or anodized aluminum. In other embodiments, the radio frequency signal feed rod 137 and / or the radio frequency signal feed shaft 141 are formed from another conductive material that provides for the transmission of radio frequency electrical signals. In some embodiments, the radio frequency signal feed rod 137 and / or the radio frequency signal feed shaft 141 are coated with a conductive material (such as silver or another conductive material) that provides for the transmission of radio frequency electrical signals. Also, in some embodiments, the radio frequency signal feed rod 137 is a solid rod. However, in other embodiments, the radio frequency signal feed rod 137 is a tube. It should also be understood that the area 140 surrounding the connection between the radio frequency signal feed rod 137 and the radio frequency signal feed shaft 141 is occupied by air.

[0059] The feed end of the radio frequency signal feed rod 137 is electrically and physically connected to an impedance matching system 143. The impedance matching system 143 is connected to a first radio frequency signal generator 147 and a second radio frequency signal generator 149. The impedance matching system 143 is also connected to the control system 120 through one or more signal conductors 144. The first radio frequency signal generator 147 is also connected to the control system 120 through one or more signal conductors 148. The second radio frequency signal generator 149 is also connected to the control system 120 through one or more signal conductors 150. The impedance matching system 143 includes an array of inductors and capacitors sized and connected to provide impedance matching so that radio frequency power can be transmitted along the radio frequency signal feed rod 137, along the radio frequency signal feed shaft 141, through the facility plate 111, through the electrode 109, and into the plasma processing zone 182 above the ceramic layer 110. In some embodiments, the first radio frequency signal generator 147 is a high-frequency radio frequency signal generator, and the second radio frequency signal generator 149 is a low-frequency radio frequency signal generator. In some embodiments, the first radio frequency signal generator 147 generates a radio frequency signal within a range ranging from about 50 megahertz (MHz) to about 70 MHz, or within a range ranging from about 54 MHz to about 63 MHz, or at about 60 MHz. In some embodiments, the first radio frequency signal generator 147 provides radio frequency power within a range ranging from about 5 kilowatts (kW) to about 25 kW, or within a range ranging from about 10 kW to about 20 kW, or within a range ranging from about 15 kW to about 20 kW, or at about 10 kW, or at about 16 kW. In some embodiments, the second radio frequency signal generator 149 generates a radio frequency signal within a range ranging from about 50 kilohertz (kHz) to about 500 kHz, or within a range ranging from about 330 kHz to about 440 kHz, or at about 400 kHz. In some embodiments, the second radio frequency signal generator 149 provides radio frequency power in a range ranging from about 15 kW to about 100 kW, or in a range ranging from about 30 kW to about 50 kW, or about 34 kW, or about 50 kW.In an example embodiment, the first radio frequency signal generator 147 is configured to generate a radio frequency signal having a frequency of approximately 60 MHz, and the second radio frequency signal generator 149 is configured to generate a radio frequency signal having a frequency of approximately 400 kHz.

[0060] Bonding ring 161 is configured and positioned to extend around the outer radial circumference of electrode 109. In some embodiments, bonding ring 161 is formed from a ceramic material. Quartz ring 163 is configured and positioned to extend around the outer radial circumference of both bonding ring 161 and ceramic support 113. In some embodiments, bonding ring 161 and quartz ring 163 are configured to have substantially aligned top surfaces when quartz ring 163 is positioned around both bonding ring 161 and ceramic support 113. In some embodiments, the substantially aligned top surfaces of bonding ring 161 and quartz ring 163 are substantially aligned with the top surface of electrode 109, which is outside the radial circumference of ceramic layer 110. In some embodiments, cover ring 165 is configured and positioned to extend around the outer radial circumference of the top surface of quartz ring 163. In some embodiments, cover ring 165 is formed from quartz. In some embodiments, the cover ring 165 is configured to extend vertically above the top surface of the quartz ring 163. In this manner, the cover ring 165 provides a peripheral boundary within which the edge ring 167 is positioned.

[0061] The edge ring 167 is configured to facilitate extension of the plasma sheath radially outward beyond the peripheral edge of the wafer W to improve processing results near the periphery of the wafer W. In various embodiments, the edge ring 167 is formed from a conductive material such as, among other materials, crystalline silicon, polycrystalline silicon (polysilicon), boron-doped single crystal silicon, aluminum oxide, quartz, aluminum nitride, silicon nitride, silicon carbide, or a silicon carbide layer on top of an aluminum oxide layer, or an alloy of silicon, or a combination thereof. It is understood that the edge ring 167 is formed as an annular-shaped structure, for example, as a ring-shaped structure. The edge ring 167 can perform many functions, including shielding components below the edge ring 167 from damage by ions of the plasma 180 formed within the plasma processing zone 182. The edge ring 167 also improves the uniformity of the plasma 180 at and along the outer peripheral area of ​​the wafer W.

[0062] A fixed outer support flange 169 is attached to the cantilever arm assembly 115. The fixed outer support flange 169 is configured to extend around the outer vertical side of the ceramic support 113, around the outer vertical side of the quartz ring 163, and around the lower outer vertical side of the cover ring 165. The fixed outer support flange 169 has an annular shape that defines the assembly consisting of the ceramic support 113, the quartz ring 163, and the cover ring 165. The fixed vertical portion 169 has an L-shaped vertical cross-section including a vertical portion and a horizontal portion. The vertical portion of the L-shaped cross-section of the fixed outer support flange 169 has an inner vertical surface positioned opposite the outer vertical side of the ceramic support 113, opposite the outer vertical side of the quartz ring 163, and opposite the lower outer vertical side of the cover ring 165. In some embodiments, the vertical portion of the L-shaped cross section of the fixed outer support flange 169 extends over the entire outer vertical side of the ceramic support 113, over the entire outer vertical side of the quartz ring 163, and over the lower outer vertical side of the cover ring 165. In some embodiments, the cover ring 165 extends radially outward above the top surface of the vertical portion of the L-shaped cross section of the fixed outer support flange 169. And in some embodiments, the upper outer vertical side of the cover ring 165 (located above the top surface of the vertical portion of the L-shaped cross section of the fixed outer support flange 169) is substantially vertically aligned with the outer vertical surface of the vertical portion of the L-shaped cross section of the fixed outer support flange 169. The horizontal portion of the L-shaped cross section of the fixed outer support flange 169 is positioned on and fastened to the support surface 114 of the cantilever arm assembly 115. The fixed outer support flange 169 is formed from an electrically conductive material. In some embodiments, the fixed outer support flange 169 is formed from aluminum or anodized aluminum. However, in other embodiments, the fixed outer support flange 169 can be formed from another conductive material, such as copper or stainless steel. In some embodiments, the horizontal portion of the L-shaped cross section of the fixed outer support flange 169 is bolted onto the support surface 114 of the cantilever arm assembly 115.

[0063] The articulating outer support flange 171 is configured and positioned to extend around the outer vertical surface 169D of the vertical portion of the L-shaped cross section of the fixed outer support flange 169 and around the upper outer vertical side of the covering ring 165. The articulating outer support flange 171 has an annular shape that bounds both the vertical portion of the L-shaped vertical cross section of the fixed outer support flange 169 and the upper outer vertical side of the covering ring 165. The articulating outer support flange 171 has an L-shaped vertical cross section that includes a vertical portion and a horizontal portion. The vertical portion of the L-shaped cross section of the articulating outer support flange 171 has an inner vertical surface that is positioned closest to and spaced apart from both the outer vertical side of the vertical portion of the L-shaped cross section of the fixed outer support flange 169 and the upper outer vertical side of the covering ring 165. In this manner, the articulating outer support flange 171 is movable vertically (z-direction) along both the vertical portion of the L-shaped vertical cross section of the fixed outer support flange 169 and the upper outer vertical side of the cover ring 165. The articulating outer support flange 171 is formed from an electrically conductive material. In some embodiments, the articulating outer support flange 171 is formed from aluminum or anodized aluminum. However, in other embodiments, the articulating outer support flange 171 can be formed from another electrically conductive material, such as copper or stainless steel.

[0064] A number of conductive straps 173 are connected between the articulating outer support flange 171 and the fixed outer support flange 169 around the outer radial periphery of both the articulating outer support flange 171 and the fixed outer support flange 169. In the example embodiment, the conductive straps 173 are shown as having an "outward" configuration, in that they bend outward, away from the fixed outer support flange 169. In some embodiments, the conductive straps 173 are formed from stainless steel. However, in other embodiments, the conductive straps 173 can be formed from another conductive material, such as aluminum or stainless steel, among others.

[0065] In some embodiments, 48 ​​conductive straps 173 are distributed in a substantially equally spaced manner around the outer radial circumference of the articulating outer support flange 171 and the fixed outer support flange 169. However, it should be understood that the number of conductive straps 173 may vary in different embodiments. In some embodiments, the number of conductive straps 173 is in a range ranging from about 24 to about 80, or from about 36 to about 60, or from about 40 to about 56. In some embodiments, the number of conductive straps 173 is less than 24. In some embodiments, the number of conductive straps 173 is greater than 80. The number of conductive straps 173 may affect the ground return path for radio frequency signals around the periphery of the plasma processing zone 182, and therefore may affect the uniformity of processing results across the wafer W. Additionally, the size of the conductive straps 173 may vary in different embodiments.

[0066] In some embodiments, the conductive straps 173 are connected to the stationary outer support flange 169 by a clamping force applied by fastening a clamping ring 175 to the top surface of the horizontal portion of the L-shaped cross section of the stationary outer support flange 169. In some embodiments, the clamping ring 175 is bolted to the stationary outer support flange 169. In some embodiments, the bolts securing the clamping ring 175 to the stationary outer support flange 169 are positioned in a location between the conductive straps 173. However, in some embodiments, one or more bolts securing the clamping ring 175 to the stationary outer support flange 169 can be positioned to extend through the conductive straps 173. In some embodiments, the clamping ring 175 is formed from the same material as the stationary outer support flange 169. However, in other embodiments, the clamping ring 175 and the stationary outer support flange 169 can be formed from different materials.

[0067] In some embodiments, the conductive straps 173 are connected to the articulating outer support flange 171 by a clamping force applied by fastening a clamping ring 177 to the lowermost surface of the horizontal portion of the L-shaped cross section of the articulating outer support flange 171. Alternatively, in some embodiments, a first end portion of each of the plurality of conductive straps 173 is connected to the upper surface of the horizontal portion of the articulating outer support flange 171 by a clamping ring 177. In some embodiments, the clamping ring 177 is bolted to the articulating outer support flange 171. In some embodiments, the bolts securing the clamping ring 177 to the articulating outer support flange 171 are positioned in a location between the conductive straps 173. However, in some embodiments, the bolt or bolts securing the clamping ring 177 to the articulating outer support flange 171 can be positioned to extend through the conductive straps 173. In some embodiments, the clamping ring 177 is formed from the same material as the articulating outer support flange 171. However, in other embodiments, the clamping ring 177 and the articulating outer support flange 171 can be formed from different materials.

[0068] A set of support rods 201 are positioned around the cantilever arm assembly 115 so as to extend vertically through the horizontal portion 169B of the L-shaped cross section of the fixed outer support flange 169. The upper ends of the support rods 201 are configured to engage the lowermost surface of the horizontal portion of the L-shaped cross section of the articulating outer support flange 171. In some embodiments, the lower end of each of the support rods 201 engages a resistance mechanism 203. The resistance mechanism 203 is configured to provide an upward force to the corresponding support rod 201 that resists downward movement of the support rod 201, while allowing some downward movement of the support rod 201. In some embodiments, the resistance mechanism 203 includes a spring that provides an upward force to the corresponding support rod 201. In some embodiments, the resistance mechanism 203 includes a material, such as a spring and / or rubber, having a spring constant sufficient to provide an upward force to the corresponding support rod 201. It should be appreciated that as the articulating outer support flange 171 moves downward to engage the set of support rods 201, the set of support rods 201 and corresponding resistance mechanisms 203 provide an upward force on the articulating outer support flange 171. In some embodiments, the set of support rods 201 includes three support rods 201 and corresponding resistance mechanisms 203. In some embodiments, the support rods 201 are positioned at substantially equal azimuthal intervals relative to the vertical centerline of the electrode 109. However, in other embodiments, the support rods 201 are positioned at unequal azimuthal intervals relative to the vertical centerline of the electrode 109. Also, in some embodiments, four or more support rods 201 and corresponding resistance mechanisms 203 are provided to support the articulating outer support flange 171.

[0069] 2 , the plasma processing system 100 further includes a C-shaped shroud member 185 positioned above the electrode 109. The C-shaped shroud member 185 is configured to interface with the articulating outer support flange 171. Specifically, the seal 179 is disposed on the top surface of the horizontal portion of the L-shaped cross section of the articulating outer support flange 171 such that it is engaged by the C-shaped shroud member 185 when the articulating outer support flange 171 moves upwardly toward the C-shaped shroud member 185. In some embodiments, the seal 179 is electrically conductive to assist in establishing electrical conduction between the C-shaped shroud member 185 and the articulating outer support flange 171. In some embodiments, the C-shaped shroud member 185 is formed from polysilicon. However, in other embodiments, the C-shaped shroud member 185 is formed from another type of conductive material that is chemically compatible with the processes occurring in the plasma processing zone 182 and has sufficient mechanical strength.

[0070] The C-shaped shroud is configured to extend around the plasma processing zone 182 to provide radial extension of the volume of the plasma processing zone 182 within an area defined within the C-shaped shroud member 185. The C-shaped shroud member 185 includes a lower wall 185A, an outer vertical wall 185B, and an upper wall 185C. In some embodiments, the outer vertical wall 185B and the upper wall 185C of the C-shaped shroud member 185 are solid, imperforate members, and the lower wall 185A of the C-shaped shroud member 185 includes a number of vent holes 186 through which processing gas flows from the interior of the plasma processing zone 182. In some embodiments, a throttling member 196 is positioned below the vent holes 186 in the C-shaped shroud member 185 to control the flow of processing gas through the vent holes 186. More specifically, in some embodiments, the throttling member 196 is configured to move up and down perpendicular to the z-direction relative to the C-shaped shroud member 185 to control the flow of process gas through the vent holes 186. In some embodiments, the throttling member 196 is configured to engage with and / or enter the vent holes 186.

[0071] The top wall 185C of the C-shaped shroud member 185 is configured to support the top electrodes 187A / 187B. In some embodiments, the top electrodes 187A / 187B include an inner top electrode 187A and an outer top electrode 187B. Alternatively, in some embodiments, the inner top electrode 187A is present and the outer top electrode 187B is not present, with the inner top electrode 187A extending radially to cover the location occupied by the outer top electrode 187B. In some embodiments, the inner top electrode 187A is formed from single crystal silicon and the outer top electrode 187B is formed from polysilicon. However, in other embodiments, the inner top electrode 187A and the outer top electrode 187B can be formed from other materials that are structurally, chemically, electrically, and mechanically compatible with the processes performed within the plasma processing zone 182. The inner top electrode 187A includes several throughports 197, defined as holes that extend through the entire vertical thickness of the inner top electrode 187A. The throughports 197 are distributed throughout the inner top electrode 187A relative to the xy plane to provide a flow of one or more process gases from a plenum region 188 above the top electrodes 187A / 187B to the plasma processing region 182 below the top electrodes 187A / 187B.

[0072] It should be understood that the distribution of the through ports 197 throughout the inner upper electrode 187A can be configured differently in different embodiments. For example, the total number of through ports 197 within the inner upper electrode 187A and / or the spatial distribution of the through ports 197 within the inner upper electrode 187A can vary between different embodiments. Also, the diameter of the through ports 197 can vary between different embodiments. Generally, it is of interest to reduce the diameter of the through ports 197 to a size small enough to prevent the plasma 180 from penetrating into the through ports 197 from the plasma processing zone 182. In some embodiments, when the diameter of the through ports 197 is reduced, the total number of through ports 197 within the inner upper electrode 187A is increased to maintain a defined overall flow rate of one or more process gases from the process gas plenum zone 188 through the inner upper electrode 187A to the plasma processing zone 182. Also, in some embodiments, the upper electrodes 187A / 187B are electrically connected to a reference ground potential. However, in other embodiments, the inner upper electrode 187A and / or the outer upper electrode 187B are electrically connected to a corresponding direct current (DC) power source or a corresponding radio frequency power source via a corresponding impedance matching circuit.

[0073] A plenum volume 188 is defined by a top member 189. One or more gas supply ports 192 are formed in fluid communication with the plenum volume 188 through the chamber 101 and the top member 189. The one or more gas supply ports 192 are fluidly connected (plumbed) to a process gas supply system 191. The process gas supply system 191 includes, among other equipment, one or more process gas sources, one or more mass flow controllers, and one or more flow control valves to provide a controlled flow of one or more process gases to the plenum volume 188 through the one or more gas supply ports 192, as indicated by arrows 193. In some embodiments, the process gas supply system 191 also includes one or more components for controlling the temperature of the one or more process gases. The process gas supply system 191 is connected to the control system 120 through one or more signal conductors 194.

[0074] The process gap (g1) is defined as the vertical (z-direction) distance as measured between the top surface of the ceramic layer 110 and the bottom surface of the inner upper electrode 187A. The size of the process gap (g1) can be adjusted by moving the cantilever arm assembly 115 vertically (z-direction). As the cantilever arm assembly 115 moves upward, the articulating outer support flange 171 effectively engages the lower wall 185A of the C-shaped shroud member 185, at which point the set of support rods 201 engage the articulating outer support flange 171, and as the cantilever arm assembly 115 continues to move upward, the articulating outer support flange 171 moves along with the fixed outer support flange 169 until the defined process gap (g1) is achieved. To then reverse this movement to remove the wafer W from the chamber, the cantilever arm assembly 115 is moved downward until the articulating outer support flange 171 moves away from the lower wall 185A of the C-shaped shroud member 185. In various embodiments, the size of the processing gap (g1) during plasma processing of the wafer W is controlled within a range of up to about 10 centimeters, or up to 8 centimeters, or up to 5 centimeters. Figure 2 shows the system 100 in a closed configuration with the wafer W positioned on the ceramic layer 110 for plasma processing.

[0075] During plasma processing operations within the plasma processing system 100, one or more process gases are supplied to the plasma processing zone 182 via the process gas supply system 191, the plenum zone 188, and the through-ports 197 within the inner upper electrode 187A. Radio frequency signals are also transmitted through the first and second radio frequency signal generators 147 and 149, the impedance matching system 143, the radio frequency signal supply rod 137, the radio frequency signal supply shaft 141, the facility plate 111, the electrode 109, and through the ceramic layer 110 into the plasma processing zone 182. The radio frequency signals convert the one or more process gases into a plasma 180 within the plasma processing zone 182. The ions and / or reactive constituents of the plasma interact with one or more materials on the wafer W, causing changes in the composition and / or shape of one or more specific materials present on the wafer W. Exhaust gases from the plasma processing system region 182 flow under the influence of suction applied to the exhaust port 105, as indicated by arrows 195, through vent holes 186 in the C-shaped shroud member 185, through the interior region 103 within the chamber 101, and to the exhaust port 105.

[0076] In various embodiments, the electrode 109 can be configured to have different diameters. However, in some embodiments, the diameter of the electrode 109 is widened to increase the surface of the electrode 109 upon which the edge ring 167 rests. In some embodiments, conductive gel 226 is disposed between the bottom of the edge ring 167 and the top of the electrode 109, and / or between the bottom of the edge ring 167 and the top of the coupling ring 161. In these embodiments, increasing the diameter of the electrode 109 provides a larger surface area upon which the conductive gel is disposed between the edge ring 167 and the electrode 109.

[0077] It should be appreciated that the combination of the articulating outer support flange 171, the conductive straps 173, and the fixed outer support flange 169 are at a reference ground potential and collectively form a ground return path for radio frequency signals transmitted from the electrode 109 through the ceramic layer 110 and into the plasma processing zone 182. The azimuthal uniformity of this ground return path around the periphery of the electrode 109 can affect the uniformity of the process results on the wafer W. For example, in some embodiments, the etch rate uniformity across the wafer W can be affected by the azimuthal uniformity of the ground return path around the periphery of the electrode 109. To this end, it should be appreciated that the number, configuration, and arrangement of the conductive straps 173 around the periphery of the electrode 109 can affect the uniformity of the process results across the wafer W.

[0078] Referring back to FIG. 2 , the adjustable edge sheath (TES) system is implemented to include a TES electrode 415 disposed (embedded) within the coupling ring 161. The TES system also includes several TES radio frequency signal supply pins 413 physically and electrically connected to the TES electrode 415. Each TES radio frequency signal supply pin 413 extends through a corresponding insulator feedthrough connection member 421 configured to electrically isolate the TES radio frequency signal supply pin 413 from surrounding structures, such as from the ceramic support 113 and cantilever arm assembly 115 structures. In some embodiments, O-rings 417 and 419 are disposed to ensure that the area inside the insulator feedthrough member 421 is not exposed to any materials / gases present within the plasma processing zone 182. In some embodiments, the TES radio frequency signal supply pins 413 are formed from copper, aluminum, or anodized aluminum, among others.

[0079] The TES radio frequency signal supply pins 413 extend into the open area 118 inside the cantilever arm assembly 115, where each of the TES radio frequency signal supply pins 413 is electrically connected to the TES radio frequency signal supply conductor 409 through a corresponding TES radio frequency signal filter 411. In some embodiments, three TES radio frequency signal supply pins 413 are positioned to physically and electrically connect to the TES electrodes 415 at azimuthal locations substantially equally spaced about the centerline of the electrode 109. However, it should be understood that other embodiments may have four or more TES radio frequency signal supply pins 413 physically and electrically connected to the TES electrodes 415. Also, some embodiments may have one or two TES radio frequency signal supply pins 413 physically and electrically connected to the TES electrodes 415. Each TES radio frequency signal supply pin 413 is electrically connected to a corresponding TES radio frequency signal filter 411, which in turn is electrically connected to the TES radio frequency signal supply conductor 409. In some embodiments, each TES radio frequency signal filter 411 is configured as an inductor. For example, in some embodiments, each TES radio frequency signal filter 411 is configured as a spirally wound conductor, such as a metal coil wound around a dielectric core structure. In various embodiments, the metal coil can be formed from a solid copper rod, copper tubing, aluminum rod, or aluminum tubing, among others. Also, in some embodiments, each TES radio frequency signal filter 411 can be configured as a combination of inductive and capacitive structures. To improve plasma processing result uniformity across the wafer W, each of the TES radio frequency signal filters 411 has substantially the same configuration.

[0080] In some embodiments, the TES radio frequency signal feed conductor 409 is formed as a ring-shaped (annular) structure that extends around the open area 118 inside the cantilever arm assembly 115 to allow physical and electrical connection between the TES radio frequency signal feed conductor 409 and the azimuthally distributed TES radio frequency signal filters 411. In some embodiments, the TES radio frequency signal feed conductor 409 is formed as a solid (non-tubular) structure. Alternatively, in some embodiments, the TES radio frequency signal feed conductor 409 is formed as a tubular structure. In some embodiments, the TES radio frequency signal feed conductor 409 is formed from copper, aluminum, or anodized aluminum, among others.

[0081] The TES radio frequency signal feed conductor 409 is electrically connected to the TES radio frequency feed cable 407. Additionally, a capacitor 408 is connected between the TES radio frequency signal feed conductor 409 and a reference ground potential, such as the structure of the cantilever arm assembly 115. More specifically, the capacitor 408 has a first terminal electrically connected to both the TES radio frequency feed cable 407 and the TES radio frequency signal feed conductor 409, and a second terminal electrically connected to the reference ground potential. In some embodiments, the capacitor 408 is a variable capacitor. In some embodiments, the capacitor 408 is a fixed capacitor. In some embodiments, the capacitor 408 is configured to have a capacitance within a range extending from approximately 10 picofarads to approximately 100 picofarads. The TES radio frequency feed cable 407 is connected to the TES impedance matching system 401. The TES impedance matching system 401 is connected to the TES frequency signal generator 403. The radio frequency signal generated by the TES radio frequency signal generator 403 is transmitted through the TES impedance match system 401 to the TES radio frequency feed cable 407, then to the TES radio frequency signal feed conductor 409, then through the TES radio frequency signal filter 411 to the corresponding TES radio frequency signal feed pin 413 and to the TES electrode 415 within the coupling ring 161. In some embodiments, the TES radio frequency signal generator 403 is configured and operative to generate a radio frequency signal within a frequency range extending from about 50 kilohertz to about 27 MHz. In some embodiments, the TES radio frequency signal generator 403 provides a radio frequency signal within a range extending from about 50 watts to about 10 kilowatts. The TES radio frequency signal generator 403 is also connected to the control system 120 through one or more signal conductors 405.

[0082] The TES impedance matching system 401 includes an array of inductors and capacitors sized and connected to provide impedance matching so that radio frequency power can be transmitted from the TES radio frequency signal generator 403 along the TES radio frequency feed cable 407, along the TES radio frequency signal feed conductors 409, through the TES radio frequency signal filter 411, through corresponding TES radio frequency signal feed pins 413, to the TES electrode 415 within the coupling ring 161, and into the plasma processing zone 182 above the edge ring 167. FIG. 3 shows an example electrical schematic of the TES impedance matching system 401, according to some embodiments. The TES impedance matching system 401 includes an input line 321 electrically connected to the TES radio frequency signal generator 403. The TES input line 321 is electrically connected to an input terminal of a first inductor 322. The output terminal of the first inductor 322 is electrically connected to an internal node 328. A second inductor 324 has an input terminal electrically connected to the internal node 328. The output terminal of the second inductor 324 is electrically connected to the internal node 329. The first capacitor 326 has an input terminal electrically connected to the second internal node 329. The output terminal of the first capacitor 326 is electrically connected to the input terminal of the third inductor 327. The output terminal of the third inductor 327 is electrically connected to the TES radio frequency supply cable 407. The second capacitor 323 has an input terminal electrically connected to the first internal node 328. The second capacitor 322 has an output terminal electrically connected to a reference ground potential. In some embodiments, the second capacitor 323 is a variable capacitor. The third capacitor 325 has an input terminal electrically connected to the second internal node 329. The third capacitor 325 has an output terminal electrically connected to a reference ground potential. It should be understood that the electrical configuration of the TES impedance matching system 401 shown in FIG. 3 is provided by way of example. In other embodiments, the TES impedance matching system 401 can have different inductor and / or capacitor configurations than the example shown in FIG.The TES impedance matching system 401 is also connected to the control system 120 through one or more signal conductors 404 .

[0083] By transmitting radio frequency signals / power through the TES electrodes 415 disposed (embedded) within the coupling ring 161, the TES system can control the properties of the plasma 180 near the peripheral edge of the wafer W. For example, in some embodiments, the TES system is operated to control the properties of the plasma 180 sheath near the edge ring 167, such as by controlling the shape and / or size (increasing the sheath thickness or decreasing the sheath thickness) of the plasma 180 sheath. Also, in some embodiments, controlling the shape of the plasma 180 sheath near the edge ring 167 can control various properties of the bulk plasma 180 across the wafer W. Also, in some embodiments, the TES system is operated to control the density of the plasma 180 near the edge ring 167. For example, in some embodiments, the TES system is operated to increase or decrease the density of the plasma 180 near the edge ring 167. Additionally, in some embodiments, the TES system is operated to control the bias voltage present on the edge ring 167, which in turn controls / affects the movement of ions and other charged constituents within the plasma 180 near the edge ring 167. For example, in some embodiments, the TES system is operated to control the bias voltage present on the edge ring 167 to attract more ions from the plasma 180 toward the edge of the wafer W. And, in some embodiments, the TES system is operated to control the bias voltage present on the edge ring 167 to repel ions from the plasma 180 and away from the edge of the wafer W. It should be understood that the TES system can be operated to perform a variety of different functions, separately or in combination, such as the functions described above, among others.

[0084] In some embodiments, the coupling ring 161 can be formed from a dielectric material such as quartz, or ceramic, or alumina (AL2O3), or polymer, among others.

[0085] The bottom surface of edge ring 167 has a portion bonded to the top surface of bonding ring 161 through a layer of thermally and electrically conductive gel to thermally lower bonding ring 161 to edge ring 167. The bottom surface of edge ring 167 also has another portion coupled to the top surface of electrode 109 through a layer of thermally and electrically conductive gel. Examples of thermally and electrically conductive gels include polyimide, polyketone, polyetherketone, polyethersulfone, polyethylene terephthalate, fluoroethylene propylene copolymer, cellulose, triacetate, and silicone, among others. In some embodiments, the thermally and electrically conductive gel is formed as a double-sided tape. In some embodiments, edge ring 167 has an inner diameter sized closest to the outer diameter of ceramic layer 110.

[0086] In various embodiments, the TES electrode 415 is formed from a conductive material such as platinum, steel, aluminum, or copper, among others. During operation, capacitive coupling occurs between the TES electrode 415 and the edge ring 167, causing the edge ring 167 to be powered and affect the processing of the wafer W near the outer periphery of the wafer W.

[0087] 4 is a graph illustrating the relationship between reflected power and capacitor tap position in a TES impedance match system 401, according to some embodiments. As previously noted, increasing the voltage applied to the TES electrode 415 compensates for the wear of the edge ring 167, thereby maintaining the position of the plasma sheath at the edge of the wafer W. However, increasing the voltage applied to the TES electrode 415 changes the impedance of the system, resulting in increased reflection of radio frequency power. To minimize reflected radio frequency power, the capacitance setting can be adjusted in the TES impedance match system 401, specifically by changing the capacitor tap position of the variable capacitor 323.

[0088] As shown in the illustrated graph, the reflected power (i.e., gamma) as a function of capacitor tap position for a first (lower) voltage applied to the TES electrode 415 by the TES RF signal generator 403 is shown by curve 431. As shown, the reflected power is minimized when the capacitor tap position is set to position P1, which has a reflected power Q1, corresponding to point 435 along curve 431.

[0089] However, when the voltage is increased to a second (higher) voltage to compensate for the wear of edge ring 167, the reflected power as a function of capacitor tap position is represented by curve 433. As a result, if the capacitor tap position remains unchanged at position P1, the reflected power increases from Q1 along curve 433 to Q3, which corresponds to point 437.

[0090] As a result, to minimize reflected power in the system, the capacitor tap position is adjusted to position P2, which corresponds to point 439 along curve 433 where reflected power is minimized. In this approach, reflected power is reduced from Q3 to Q2.

[0091] In some implementations, the capacitor tap position is adjusted in step increments until the reflected power is minimized. For example, the capacitor tap position is continuously adjusted in a direction that reduces the reflected power until further changes do not further reduce the reflected power. For example, the capacitor tap position may be adjusted in steps, with the reflected power determined / monitored at each adjustment reaching a minimum and then beginning to increase as the reflected power decreases. The capacitor tap position may then be set to a position corresponding to the minimum reflected power. In some implementations, a target minimum reflected power is determined in advance, and the capacitor tap position is adjusted in steps, with confirmation after each adjustment, until the target minimum reflected power is achieved. It should be understood that the target minimum reflected power may or may not be the same as the actual minimum reflected power.

[0092] 5 is a graph illustrating reflected power versus phase actuator position of the TES RF signal generator 403, according to some embodiments. The phase actuator position indicates the amount of phase adjustment / offset automatically performed by the TES RF signal generator 403 to align the phase with the RF signal produced by the first RF signal generator 147. As shown, at a first (lower) voltage applied by the TES RF signal generator 403, the reflected power (i.e., gamma) as a function of phase actuator position (or phase offset or phase adjustment amount) is represented by curve 501. In contrast, at a second (higher) voltage, the reflected power as a function of phase actuator position (or phase offset or phase adjustment amount) is represented by curve 503.

[0093] An unexpected result was that the reflected power was discovered to be minimal at substantially the same phase offset, even when the applied voltage was varied. Therefore, the phase actuator position of the TES RF signal generator 403 can be used to optimize the capacitor tap positions of the impedance matching system 401, as described above, to minimize the reflected power.

[0094] 4 and 5, when the capacitor tap position is set to P1 and a first (lower) voltage is applied, the phase actuator position is automatically set to an amount (angular amount) A1 to minimize the phase delta. The capacitor tap position P1 has already been set to minimize the reflected power as shown by point 435, which corresponds to point 505 along curve 501. As can be seen, at point 505 the reflected power is minimized, consistent with curve 501, which is also consistent with curve 431.

[0095] When the voltage is increased to a second (higher) voltage to compensate for edge erosion, the reflected power versus phase actuator position curve shifts to curve 503. However, if the capacitor tap position is unchanged and remains at P1, the phase actuator position is automatically adjusted by TES RF signal generator 403 by an amount A2 as a result of TES RF signal generator 403 automatically matching the phase of its RF signal to the RF signal of first RF signal generator 147, which requires a different phase offset due to the voltage change and resulting impedance change. In response, the voltage change moves the system from point 505 along curve 501 to point 507 along curve 503, which is a curve depicting reflected power versus phase actuator position at the second (higher) voltage employed to compensate for edge erosion. Point 507 along curve 503 corresponds to point 437 along curve 433 described previously. At these points, the reflected power increases to Q3 before adjusting the capacitor tap position.

[0096] Then, to minimize the reflected power, the capacitor tap position of variable capacitor 323 of TES impedance match system 401 is adjusted to position P2, as previously described. An unexpected result is that this causes TES RF signal generator 403 to adjust the phase of its RF signal to automatically match the phase of first RF signal generator 147, thereby returning the phase actuator position of TES RF signal generator 403 to A1. This is shown in the illustrative graph as movement along curve 503 from point 507 to point 509, where the reflected power is minimized and Q2 is reached. It will be recognized that point 509 along curve 503 corresponds to point 439 along curve 433.

[0097] Accordingly, with the above in mind, the phase offset applied by the TES RF signal generator 403 can be monitored and utilized to adjust the capacitor tap position of the variable capacitor 323 of the TES RF signal generator 401. Figure 6 is a graph illustrating phase actuator position versus capacitor tap position, according to some embodiments. Curve 601 illustrates the phase actuator position (automatically set to align the phase as described above) versus capacitor tap position when a first (lower) voltage is applied. Curve 603 illustrates the phase actuator position versus capacitor tap position when a second (higher) voltage is applied.

[0098] Under a first voltage condition, the capacitor tap position is set to P1 and the phase actuator position is automatically set to A1, thereby defining the target phase offset. This condition is represented by point 605 along curve 601. When a second voltage condition is applied, which entails increasing the voltage to compensate for edge ring wear, the phase actuator position transitions to A2 as the current condition is now represented by point 607 along curve 603. As a result, to minimize the reflected voltage under the new, increased voltage condition, the capacitor tap position is adjusted until the phase actuator position reaches A1, the target phase offset.

[0099] For example, the capacitor tap position can be adjusted in step increments from P1 to P2, checking the phase actuator position with each change, until a target phase offset A1, represented by point 609 along curve 603, is achieved. Knowing that the phase actuator position A1 results in the lowest reflected power, the capacitor tap position is adjusted until the phase actuator position reaches A1. In some implementations, the phase actuator position, or target phase offset for a given recipe, is in the range of approximately 80° to 230°, in some implementations, in the range of approximately 110° to 170°, and in some implementations, in the range of approximately 140° to 160°.

[0100] FIG. 7 illustrates a method for optimizing the TES matching capacitor tap position to minimize reflected power (i.e., gamma) in consideration of changing the TES voltage set point to compensate for edge ring wear, according to an implementation of the present disclosure. At method operation 701, the method begins by monitoring the number of RF hours experienced by the edge ring. At method operation 703, it is determined whether a predefined or target RF time interval has been achieved. For example, the system can be configured to adjust the TES voltage set point (the target voltage output by the TES RF signal generator 403) at regular intervals based on the number of hours of RF exposure (RF hours) experienced by the edge ring since installation or since the previous change in the TES voltage set point. Consequently, the RF time interval can be defined to determine when and how often the TES voltage set point is adjusted to compensate for edge ring wear. By way of example and without limitation, in some implementations, the RF time interval ranges from approximately 10 RF hours to 200 RF hours. In some implementations, the RF time interval is approximately 100 RF hours.

[0101] In some implementations, the RF time interval is constant and has a single value throughout the edge ring's lifetime. In contrast, in some implementations, the RF time interval has a different value that varies from one interval to the next over the edge ring's lifetime. For example, in some implementations, it is desirable to change the TES voltage setpoint more frequently as the edge ring wears out when the full RF time occurs during the edge ring's lifetime, resulting in a reduction in the RF time interval. In some implementations, successive RF time intervals are shorter than the preceding RF time interval during at least a portion of the edge ring's lifetime.

[0102] In some implementations, the target RF time interval can be specified via a user interface. For example, there can be a default target RF time interval (e.g., from 50 RF hours to 100 RF hours in some implementations), which can be adjusted by the user in predefined increments (e.g., from 1 RF time increment to 10 RF time increments in some implementations) and within a predefined range (e.g., from 1 RF time to 400 RF hours in some implementations). Furthermore, a user-defined function can be set via the user interface to determine the relationship of the voltage compensation offset (additional TES voltage above the initial setting point) as a function of the number of RF hours generated. For example, in some implementations, a user can input a voltage compensation offset value for a specific RF time value, and the system can be configured to automatically define a function that includes these points, e.g., by linearly interpolating between the points. Then, for any given number of RF hours generated (which may follow the target RF time interval), the system can determine the appropriate voltage compensation offset according to the function.

[0103] If the target RF time interval has not been reached, the method returns to method action 701 .

[0104] If the target RF time interval is reached, the method proceeds to method action 705 and adjusts the TES voltage set point to compensate for edge ring wear. Typically, this entails increasing the TES voltage set point.

[0105] At method operation 707, the capacitor tap positions of the TES impedance match system 401 are adjusted to reduce or minimize reflected power. At method operation 709, the TES phase adjustments are monitored, which are phase adjustments automatically applied by the TES RF signal generator 403 to match the RF signal of the TES RF signal generator 403 with the RF signal obtained from the first RF signal generator 147 or to create a zero phase delta with the RF signal obtained from the first RF signal generator 147.

[0106] At method operation 711, it is determined whether the TES phase adjustment is equal to or within a predefined range of the target phase adjustment. If not, the method returns to method operation 707; if so, the method returns to the start of method operation 701.

[0107] While in some implementations the TES voltage set point is adjusted at predefined intervals, it is recognized that in various implementations it can be adjusted at any interval, or even continuously or substantially continuously, as a function of edge ring RF time, number of processing cycles, or other monitored edge ring wear indicators. While in some implementations the adjustment of the capacitance of the TES impedance matching system 401 has been described as being made in discrete steps, such as through incremental adjustment of capacitor tap positions, it is recognized that the granularity of such adjustment is limited only by the adjustment capability of the variable capacitor. In various implementations, the capacitance adjustment can be made in any amount of discrete steps, or can be continuous or substantially continuous, as enabled by the variable capacitor of the TES impedance matching system 401.

[0108] For a given recipe, there may be a target phase adjustment for each recipe step. Additionally, the target phase adjustment may be editable through a user interface, such as through a recipe editor in the user interface. There may be default values ​​for the target phase adjustments that are provided when a new recipe is created. For example, there may be a model (based on empirical data) that predicts what the target phase adjustment should be for each recipe step. The user may have the option to choose to use this model when creating each recipe step, or may enter their own values.

[0109] It is recognized that any of the methods described in this disclosure can be implemented to be performed automatically by control system 120. In some embodiments, as has been described, capacitor tap locations can be automatically optimized to minimize reflected power in a TES system.

[0110] 8 shows an example schematic diagram of the control system 120 of FIG. 2 , according to some embodiments. In some embodiments, the control system 120 is configured as a process controller for controlling semiconductor fabrication processes performed in the plasma processing system 100. In various embodiments, the control system 120 includes a processor 1401, a storage hardware unit (HU) 1403 (e.g., memory), an input HU 1405, an output HU 1407, an input / output (I / O) interface 1409, an I / O interface 1411, a network interface controller (NIC) 1413, and a data communication bus 1415. The processor 1401, the storage HU 1403, the input HU 1405, the output HU 1407, the I / O interface 1409, the I / O interface 1411, and the NIC 1413 are in data communication with each other via the data communication bus 1415. The input HU 1405 is configured to receive data communications from several external devices. Examples of input HUs 1405 include data acquisition systems, data acquisition cards, etc. Output HUs 1407 are configured to transmit data communications to some external device. An example of output HUs 1407 is an equipment controller. Examples of NICs 1413 include network interface cards, network adapters, etc. Each of I / O interfaces 1409 and 1411 is defined to provide compatibility between different hardware units coupled to the I / O interface. For example, I / O interface 1409 can be defined to convert signals received from input HUs 1405 to a form, amplitude, and / or speed compatible with data communication bus 1415. I / O interface 1407 can also be defined to convert signals received from data communication bus 1415 to a form, amplitude, and / or speed compatible with output HUs 1407.Although various operations are described herein as being performed by processor 1401 of control system 120, it should be understood that in some embodiments, various operations may be performed by multiple processors of control system 120 and / or multiple processors of multiple computing systems in data communication with control system 120.

[0111] In some embodiments, the control system 120 is employed to control equipment in various wafer fabrication systems based in part on the sensed values. For example, the control system 120 may control one or more of a valve 1417, a filter heater 1419, a wafer support structure heater 1421, a pump 1423, and other equipment 1425 based on the sensed values ​​and other control parameters. The valve 1417 may include valves associated with controlling the backside gas supply system 129, the process gas supply system 191, and the temperature control fluid circulation system 125. The control system 120 receives sensed values ​​from, for example, a pressure gauge 1427, a flow meter 1429, a temperature sensor 1431, and / or other sensors 1433, such as voltage sensors, current sensors, etc. Furthermore, the control system 120 may be employed to control pressure conditions within the plasma processing system 100 while performing plasma processing operations on a wafer W. For example, the control system 120 can control the type and amount of one or more process gases delivered from the process gas delivery system 191 to the plasma processing zone 182. The control system 120 can also control the operation of the first radio frequency signal generator 147, the second radio frequency signal generator 149, the impedance matching system 143, the TES radio frequency signal generator 403, and the TES impedance matching system 401. The control system 120 can also control the operation of the DC supply 117 relative to the one or more clamping electrodes 112. The control system 120 can also control the operation of the lifting device 133 relative to the lifting pins 132 and the operation of the door 107. The control system 120 can also control the operation of the backside gas delivery system 129 and the temperature control fluid circulation system 125. The control system 120 also controls the vertical movement of the cantilever arm assembly 115. The control system 120 can also control the operation of the throttle member 196 and the operation of a pump that controls suction at the exhaust port 105. The control system 120 also controls the operation of the hold-down control mechanism 913 of the hold-down rod 911 of the TES system 1000. The control system 120 also receives input from the temperature probe of the TES system 1000.The control system 120 is equipped to provide programmatic and / or manual control of any function within the plasma processing system 100 .

[0112] In some embodiments, the control system 120 is configured to execute a computer program including a set of instructions for controlling process timing, process gas delivery system temperature, as well as pressure differentials, valve positions, process gas mixtures, process gas flow rates, backside cooling gas flow rates, chamber pressure, chamber temperature, wafer support structure temperature (wafer temperature), RF power levels, RF frequency, RF pulsing, impedance match system 143 settings, cantilever arm assembly position, bias power, and other parameters of a particular process. In some embodiments, other computer programs stored on storage associated with the control system 120 may be employed. In some implementations, a user interface is associated with the control system 120. The user interface includes a display device 1435 (e.g., a display screen and / or graphical software representation of equipment and / or process conditions) and a user input device 1437 such as a pointing device, keyboard, touch screen, microphone, etc.

[0113] Software for directing the operation of the control system 120 can be designed or configured in many different ways. Computer programs for directing the operation of the control system 120 to perform various wafer fabrication operations in a processing sequence can be written in any conventional computer-readable programming language, such as assembler language, C, C++, Pascal, Fortran, etc. The processor 1401 executes compiled object code or scripts to perform the tasks identified in the program. The control system 120 can be programmed to control various process control parameters related to process conditions, such as filter pressure differential, process gas composition and flow rate, backside cooling gas composition and flow rate, plasma conditions such as temperature, pressure, RF power level and RF frequency, bias voltage, cooling gas / fluid pressure, and chamber wall temperature, among others. Examples of sensors that may be monitored during wafer fabrication processing include, but are not limited to, a mass flow control module, a pressure sensor such as a pressure gauge 1427, and a temperature sensor 1431. Data obtained from these sensors, along with appropriately programmed feedback and control algorithms, may be used to control / adjust one or more process control parameters to maintain desired process conditions.

[0114] In some implementations, control system 120 is part of a broader fabrication control system. Such fabrication control systems may include semiconductor processing equipment, including processing tools, chambers, and / or wafer processing platforms, and / or specific processing components, such as wafer pedestals, gas flow systems, etc. These fabrication control systems may be integrated with electronics for controlling their operation before, during, and after wafer processing. Control system 120 may control various components or subsections of the fabrication control system. Depending on wafer processing requirements, control system 120 may be programmed to control any of the processes disclosed herein, including process gas delivery, backside cooling gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and motion settings, wafer transfer into and out of tools and other transfer tools, and / or load locks connected to or interfaced with specific systems.

[0115] Broadly, control system 120 may be defined as an electronic circuit having various integrated circuits, logic circuits, memory, and / or software that receives instructions, issues instructions, controls operations, enables wafer processing operations, enables endpoint measurements, etc. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to control system 120 in the form of various individual settings (or program files) that define operational parameters for performing specific processing of wafers W within system 100. The operational parameters, in some embodiments, may be part of a recipe defined by a process engineer to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon oxides, surfaces, circuits, and / or dies of a wafer.

[0116] In some implementations, control system 120 may be part of or coupled to a computer integrated with, coupled to, or otherwise networked to plasma processing system 100. For example, control system 120 may reside in the "cloud" of all or part of a semiconductor fab's host computer system, thereby enabling remote access to wafer processing. The computer may enable remote access to system 100 to monitor the current progress of a fabrication operation, examine the history of past fabrication operations, examine trends or performance indicators from multiple fabrication operations, modify parameters of a current process, set up processing steps following a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to system 100 over a network, which may include a local network or the Internet.

[0117] The remote computer may include a user interface that allows for entry or programming of parameters and / or settings, which are then communicated from the remote computer to system 100. In some examples, control system 120 receives instructions in the form of data that specify parameters for each process step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed within plasma processing system 100. Consequently, as described above, control system 120 may be distributed, such as by comprising one or more separate controllers that are networked and operate together toward a common purpose, such as the processing and control described herein. One example of a distributed controller for such purposes is one or more integrated circuits on plasma processing system 100 that are in communication with one or more remotely located integrated circuits (e.g., at the platform level or as part of a remote computer) that combine to control the processes performed on plasma processing system 100.

[0118] Without limitation, examples of systems with which control system 120 may interface may include a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers. As noted above, depending on the processing step or steps to be performed by the tool, control system 120 may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, nearby tools, adjacent tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to transport containers of wafers to and from tool locations and / or load ports within the semiconductor fabrication factory.

[0119] The embodiments described herein may also be implemented in conjunction with various computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, and the like. The embodiments described herein may also be implemented in conjunction with distributed computing environments in which tasks are performed by remote processing hardware units linked through a network. It should be understood that the embodiments described herein, particularly those relating to control system 120, may employ various computer-implemented operations involving data stored in computer systems. These operations are operations requiring physical manipulation of physical quantities. Any of the operations described herein that form part of the embodiments are useful machine operations. The embodiments also relate to hardware units or apparatus for performing these operations. An apparatus may be specially constructed for a special purpose computer. When defined as a special purpose computer, the computer may also perform other processes, program execution, or routines that are not part of the special purpose while still operating for the special purpose. In some embodiments, operations may be processed by a general purpose computer selectively activated or configured by one or more computer programs stored in a computer memory, cache, or obtained over a network. When data is obtained over a network, it may be processed by other computers on the network, for example, by a cloud of computing resources.

[0120] Various embodiments described herein can be implemented through process control instructions instantiated as computer-readable code on a non-transitory computer-readable medium. A non-transitory computer-readable medium is any data storage device that can store data that can thereafter be read by a computer system. Examples of non-transitory computer-readable media include hard drives, network attached storage (NAS), ROM, RAM, compact disc-ROMs (CD-ROMs), CD-recordables (CD-Rs), CD-rewritables (CD-RWs), magnetic tape, and other optical and non-optical data storage hardware units. Non-transitory computer-readable media can include computer-readable tangible media distributed across network-coupled computer systems so as to store and execute computer-readable code in a distributed fashion.

[0121] While the foregoing disclosure includes certain details for clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. For example, it should be understood that one or more features from any embodiment disclosed herein may be combined with one or more features of any other embodiment disclosed herein. Accordingly, the present embodiments should be considered illustrative and not restrictive, and what is claimed should not be limited to the details set forth herein, but may be modified within the scope of the described embodiments and equivalents.

Claims

1. 1. A method for controlling reflected power in a plasma processing system, comprising: applying RF power from a first generator to the ESC; applying RF power from a second generator to an edge electrode surrounding the ESC, the edge electrode being positioned below an edge ring surrounding the ESC, the RF power from the second generator having a voltage set based on edge ring usage, the second generator automatically introducing a phase adjustment such that the phase of the RF power from the second generator substantially matches the phase of the RF power from the first generator; adjusting a variable capacitor in a matching circuit to which the RF power obtained from the second generator is applied to adjust the phase adjustment to a target phase adjustment setting; A method for providing the above.

2. 10. The method of claim 1, determining the usage of the edge ring; when the usage of the edge ring reaches a target level, initiating adjustment of the variable capacitor of the matching circuit; A method further comprising:

3. 3. The method of claim 2, wherein the target level and the target phase adjustment settings are captured via a user interface.

4. The method of claim 3 , wherein the target level varies according to one or more criteria.

5. 2. The method of claim 1, wherein the target phase adjust setting defines a predefined phase adjust amount by which the phase of the RF power obtained from the secondary generator is adjusted.

6. 2. The method of claim 1, wherein adjusting the variable capacitor to adjust the phase adjustment comprises performing incremental tap adjustments on the variable capacitor until the phase adjustment reaches the target phase adjustment setting.

7. 10. The method of claim 1, wherein the phase adjust is adjusted to the target phase adjust setting when the target phase adjust setting is reached or is within a predefined range of the target phase adjust setting.

8. 2. The method of claim 1, wherein the step of adjusting the variable capacitor to align the phase to the target phase adjustment setting minimizes reflection of the RF power back to the secondary generator.

9. 2. The method of claim 1, wherein the target phase adjustment setting that minimizes the reflection of the RF power back to the second generator remains substantially the same with respect to changes in the voltage set based on the usage of the edge ring.

10. 2. The method of claim 1, wherein the usage of the edge ring is defined by at least one of a number of hours of RF exposure of the edge ring and the voltage of the RF power obtained from the second generator set based on the number of hours of RF exposure.

11. 1. A method for minimizing reflected power in a plasma processing system, comprising: applying RF power from a first generator to the ESC; applying RF power from a second generator to edge electrodes surrounding the ESC, the RF power from the second generator having a voltage set to a predefined first voltage, the second generator introducing a phase adjustment by a predefined phase adjustment amount such that the phase of the RF power from the second generator substantially matches the phase of the RF power from the first generator; changing the voltage of the RF power obtained from the second generator from the first predefined voltage to a second predefined voltage, the phase adjustment being changed from the predefined phase adjustment amount; adjusting a capacitance of a matching circuit in response to the change in the voltage to apply the RF power obtained from the second generator to return the changed phase adjustment to the predefined phase adjustment amount; A method for providing the above.

12. 12. The method of claim 11, determining the amount of edge ring usage placed on top of the edge electrode and surrounding the ESC; initiating a change in the voltage of the RF power obtained from the second generator when the usage of the edge ring reaches a target level; A method further comprising:

13. 13. The method of claim 12, wherein the target level and the predefined phase adjustment amount are entered via a user interface.

14. 14. The method of claim 13, wherein the target level varies according to one or more criteria.

15. 12. The method of claim 11, wherein the step of adjusting the capacitance of the matching circuit includes performing incremental tap adjustments on the capacitance until the changed phase adjustment reaches the predefined phase adjustment amount.

16. 12. The method of claim 11, wherein the phase adjustment is returned to the predefined phase adjustment amount when the phase adjustment reaches the predefined phase adjustment amount or when the phase adjustment is within a predefined range of the predefined phase adjustment amount.

17. 12. The method of claim 11, wherein the step of adjusting the capacitance to return the phase adjustment to the predefined amount of phase adjustment minimizes reflection of the RF power back to the second generator.

18. 12. The method of claim 11 , wherein the predefined amount of phase adjustment that minimizes the reflection of the RF power back to the second generator remains substantially the same with respect to changes in the voltage set based on edge ring usage.

19. 20. The method of claim 18, wherein the usage of the edge ring is defined by at least one of a number of hours of RF exposure of the edge ring and the voltage of the RF power obtained from the second generator set based on the number of hours of RF exposure.

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