Semiconductor integrated circuit

Abstract

To provide a semiconductor integrated circuit capable of restricting decrease in wiring efficiency of a switching circuit in a DAC circuit.SOLUTION: A semiconductor integrated circuit 1 outputs an output signal Dout at a voltage level according to the state of a first switch SW1 and a second switch SW2. A first compensation transistor M1 is connected between an output circuit 20 and a first switch transistor M3 in series, and a second compensation transistor M2 is connected between the output circuit 20 and a second switch transistor M4 in series. A second main electrode of the first compensation transistor M1, and the first switch transistor M3, a second main electrode of the second compensation transistor M2 and a first main electrode of the second switch transistor M4, and a second main electrode of the first switch transistor M3 and a second main electrode of the second switch transistor M4 are respectively combined on a semiconductor substrate 200.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor integrated circuits. [Background technology]

[0002] Semiconductor integrated circuits are used in which elements such as transistors are formed on a semiconductor substrate. For example, digital-to-analog conversion circuits (hereinafter also referred to as "DAC circuits") that convert digital signals into analog signals using switching circuits are formed on the semiconductor substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-324661

[0004] [overview] In semiconductor integrated circuits, it is possible to adopt a layout in which transistors of the same structure are formed in the same direction on a semiconductor substrate. However, forming transistors in the same direction in a semiconductor integrated circuit may result in longer wiring and a decrease in wiring efficiency. The present disclosure aims to provide a semiconductor integrated circuit that can suppress a decrease in wiring efficiency.

[0005] One aspect of the present disclosure is a semiconductor integrated circuit including: a switching circuit including a first switch controlled by a first signal and a second switch controlled by a second signal obtained by inverting the first signal; and an output circuit that outputs an output signal whose voltage level is set according to the on / off states of the first switch and the second switch, and that outputs the output signal obtained by digital-to-analog conversion of the first signal as a digital signal. The switching circuit includes a first switch transistor having a control electrode to which the first signal is input, a second switch transistor having a control electrode to which the second signal is input, a first compensation transistor connected in series between the output circuit and the first switch transistor, and a second compensation transistor connected in series between the output circuit and the second switch transistor. The first compensation transistor, the first switch transistor, the second switch transistor, and the second compensation transistor are formed in this order on a semiconductor substrate. The second main electrode of the first compensation transistor and the first main electrode of the first switch transistor are integrated on the semiconductor substrate, the second main electrode of the second compensation transistor and the first main electrode of the second switch transistor are integrated on the semiconductor substrate, and the second main electrode of the first switch transistor and the second main electrode of the second switch transistor are integrated on the semiconductor substrate. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a circuit diagram showing the configuration of a semiconductor integrated circuit according to an embodiment. [Figure 2] FIG. 2 is a time chart for explaining the operation of the semiconductor integrated circuit according to the embodiment. [Figure 3] FIG. 3 is a circuit diagram showing the configuration of a switching circuit of the semiconductor integrated circuit according to the embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view showing the layout of transistors that form the switching circuit of the semiconductor integrated circuit according to the embodiment. [Figure 5] FIG. 5 is a schematic plan view showing the layout of transistors that form the switching circuit of the semiconductor integrated circuit according to the embodiment. [Figure 6]FIG. 6 is a schematic plan view showing a layout of a comparative example of transistors that configure a switching circuit. [Figure 7] FIG. 7 is a time chart of the current flowing through the switching circuit of the semiconductor integrated circuit according to the embodiment. [Figure 8] FIG. 8 is a schematic diagram showing the layout of the first patterned cells and the second patterned cells of the semiconductor integrated circuit according to the embodiment. [Figure 9] FIG. 9 is a schematic diagram showing the layout of a plurality of pattern cells in the semiconductor integrated circuit according to the embodiment. [Figure 10] FIG. 10 is a schematic diagram showing the configuration of a circuit block of a semiconductor integrated circuit according to the embodiment. [Figure 11] FIG. 11 is a schematic diagram showing the configuration of a circuit block pair of a semiconductor integrated circuit according to the embodiment. [Figure 12] FIG. 12 is a schematic diagram showing the configuration of a constant current transistor of the semiconductor integrated circuit according to the embodiment. [Figure 13] FIG. 13 is a schematic diagram showing the configuration of a circuit group in a semiconductor integrated circuit according to the embodiment. [Figure 14] FIG. 14 is a schematic diagram showing an example in which the semiconductor integrated circuit according to the embodiment is configured with four circuit groups. [Figure 15A] FIG. 15A is a graph showing distortion characteristics in the semiconductor integrated circuit according to the embodiment. [Figure 15B] FIG. 15B is a graph showing distortion characteristics in a semiconductor integrated circuit using a switching circuit of a comparative example.

[0007] [Detailed explanation] Next, an embodiment will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each part, etc. may differ from the actual ones. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships or ratios.

[0008] Furthermore, the embodiments described below are merely examples of devices or methods for embodying the technical ideas, and are not intended to limit the shape, structure, arrangement, etc. of the components to those described below. Various modifications can be made to these embodiments within the scope of the claims.

[0009] 1, a semiconductor integrated circuit 1 according to an embodiment of the present invention includes a switching circuit 10, an output circuit 20, a constant current circuit 30, a digital signal circuit 40, a latch circuit 50, and an inverter 60. The switching circuit 10 includes a first switch SW1 controlled by a first signal S1, and a second switch SW2 controlled by a second signal S2 obtained by inverting the first signal S1. The output circuit 20 outputs an output signal Dout whose voltage level is set according to the on / off states of the first switch SW1 and the second switch SW2.

[0010] A first terminal of the first switch SW1 is connected via a first resistor R1 to a first power supply V1 that supplies current to the switching circuit 10. A second terminal of the first switch SW1 is connected to a constant current circuit 30. A first terminal of the second switch SW2 is connected to the first power supply V1 via a second resistor R2. A second terminal of the second switch SW2 is connected to the constant current circuit 30.

[0011] In the switching circuit 10, when the first signal S1 is at a high level, the first switch SW1 is turned on and a current flows through the first switch SW1, while when the second signal S2 is at a high level, the second switch SW2 is turned on and a current flows through the second switch SW2.

[0012] The constant current circuit 30 is set so that a constant current Im flows from the switching circuit 10 to the second power supply V2. The potential of the second power supply V2 is, for example, the ground potential. The constant current circuit 30 causes a constant current to flow through the first switch SW1 in the ON state or the second switch SW2 in the ON state.

[0013] The digital signal circuit 40 outputs a digital signal Din. The latch circuit 50 receives the digital signal Din and outputs a first signal S1. The inverter 60 inverts the first signal S1 to generate a second signal S2.

[0014] The output circuit 20 includes a first comparator 21 and a second comparator 22 .

[0015] The inverting input terminal (-) of the first comparator 21 is electrically connected to a first connection point P1, which is the connection point between the first switch SW1 and the first resistor R1. In the example shown in Fig. 1, the inverting input terminal (-) of the first comparator 21 and the first connection point P1 are connected via a third resistor R3. The non-inverting input terminal (+) of the first comparator 21 is connected to a third power supply V3.

[0016] The inverting input terminal (-) of the second comparator 22 is electrically connected to a second connection point P2, which is the connection point between the second switch SW2 and the second resistor R2. In the example shown in Fig. 1, the inverting input terminal (-) of the second comparator 22 and the second connection point P2 are connected via a fourth resistor R4. The non-inverting input terminal (+) of the second comparator 22 is connected to the third power supply V3.

[0017] The third resistor R3 and the fourth resistor R4 may be omitted. In other words, the first connection point P1 may be directly connected to the inverting input terminal (-) of the first comparator 21, and the second connection point P2 may be directly connected to the inverting input terminal (-) of the second comparator 22.

[0018] The output of the first comparator 21 is fed back to the inverting input terminal (-) of the first comparator 21 via a fifth resistor R5. In addition, the output of the first comparator 21 is input to the inverting input terminal (-) of the second comparator 22 via a seventh resistor R7.

[0019] The second comparator 22 outputs an output signal Dout. The output of the second comparator 22 is fed back to the inverting input terminal (-) of the second comparator 22 via a sixth resistor R6.

[0020] The semiconductor integrated circuit 1 is a DAC circuit that outputs an output signal Dout obtained by digital-to-analog converting a first signal S1 as a digital signal. The semiconductor integrated circuit 1 includes circuit cells 100 each including a latch circuit 50, an inverter 60, a switching circuit 10, and a constant current circuit 30, in accordance with the number of bits of the digital signal to be digital-to-analog converted. That is, in the semiconductor integrated circuit 1, one circuit cell 100 is used for one bit. In other words, the semiconductor integrated circuit 1 includes a number of circuit cells 100 corresponding to the number of bits of the digital signal to be digital-to-analog converted.

[0021] For example, a semiconductor integrated circuit 1 to which signals DATA[0], DATA[1], DATA[2], and DATA[3] are input as 4-bit digital signals includes four circuit cells 100. The first signals S1 of the four circuit cells 100 are signals DATA[0], DATA[1], DATA[2], and DATA[3], respectively. The second signals S2 of the four circuit cells 100 are inverted signals of signals DATA[0], DATA[1], DATA[2], and DATA[3], respectively. In the following description, the set of signals DATA[0], DATA[1], DATA[2], . . . , and DATA[n], each of which is a 1-bit signal, is referred to as signal DATA[n:0]. Signal DATA[3:0], which refers to the set of signals DATA[0], DATA[1], DATA[2], and DATA[3], is a 4-bit signal.

[0022] FIG. 2 shows the operation of the semiconductor integrated circuit 1 to which the signal DATA[3:0] is input. In FIG. 2, during a first period T10 from time t0 to time t1, the times at which the signals DATA[0] and DATA[2] are high and low coincide with each other, and the times at which the signals DATA[1] and DATA[3] are high and low coincide with each other. While the signals DATA[0] and DATA[2] are high, the signals DATA[1] and DATA[3] are low, and while the signals DATA[0] and DATA[2] are low, the signals DATA[1] and DATA[3] are high. During a second period T20 from time t1 to time t3, the signals DATA[3:0] are all low. During a third period T30 from time t3 onward, the signals DATA[3:0] are all high.

[0023] In the first period T10, a period in which the first switch SW1 is in the on state in any two circuit cells 100 and the second switch SW2 is in the on state in the other two circuit cells 100 is repeated. In the first period T10, the high level and the low level are distributed 50% each, so the voltage level of the output signal Dout is an intermediate level between the minimum level and the maximum level.

[0024] During the second period T20, the first switch SW1 is in the OFF state and the second switch SW2 is in the ON state in all four circuit cells 100. During the second period T20, the voltage level of the output signal Dout gradually decreases from time t1 to time t2, and is at the minimum level from time t2 to time t3.

[0025] During the third period T30, the first switch SW1 is in the on state and the second switch SW2 is in the off state in all four circuit cells 100. During the third period T30, the voltage level of the output signal Dout gradually increases from time t3 to time t4, and the voltage level of the output signal Dout is at its maximum level after time t4.

[0026] The above description exemplifies a simple combination of high and low levels of the signal DATA[3:0]. In the semiconductor integrated circuit 1, the level of the output signal Dout can be set between the intermediate level and the minimum level, or between the maximum level and the intermediate level, depending on the combination of levels of the signal DATA[3:0].

[0027] 3 shows the configuration of the switching circuit 10. The switching circuit 10 includes a first compensation transistor M1, a first switch transistor M3, a second compensation transistor M2, and a second switch transistor M4.

[0028] The first compensation transistor M1, the second compensation transistor M2, the first switch transistor M3, and the second switch transistor M4 that constitute the switching circuit 10 may each be an N-channel MOS (Metal-Oxide-Semiconductor) transistor. The following describes, as an example, a case where the transistors that constitute the switching circuit 10 are N-channel MOS transistors. In the following description, the first main electrode of the transistors that constitute the switching circuit 10 is the drain, the second main electrode is the source, and the control electrode is the gate.

[0029] The first compensation transistor M1 has a first main electrode connected to the first connection point P1 and a second main electrode connected to a first main electrode of the first switch transistor M3. A predetermined compensation voltage Vs is input to the control electrode of the first compensation transistor M1, and the first compensation transistor M1 maintains a conductive state.

[0030] The second compensation transistor M2 has a first main electrode connected to the second connection point P2 and a second main electrode connected to a first main electrode of the second switch transistor M4. A predetermined compensation voltage Vs is input to the control electrode of the second compensation transistor M2, and the second compensation transistor M2 maintains a conductive state.

[0031] A first main electrode of the first switch transistor M3 is connected to a second main electrode of the first compensation transistor M1, and the second main electrode is connected to the constant current circuit 30. A first signal S1 is input to a control electrode of the first switch transistor M3. In other words, the conductive state of the first switch transistor M3 corresponds to the on / off state of the first switch SW1.

[0032] The second switch transistor M4 has a first main electrode connected to the second main electrode of the second compensation transistor M2, and a second main electrode connected to the constant current circuit 30. A second signal S2 is input to a control electrode of the second switch transistor M4. In other words, the conductive state of the second switch transistor M4 corresponds to the on / off state of the second switch SW2.

[0033] A compensation voltage Vs that maintains the first compensating transistor M1 and the second compensating transistor M2 in a conductive state is input to the control electrodes of the first compensating transistor M1 and the second compensating transistor M2. Therefore, fluctuations in the potential of the second main electrode of the first compensating transistor M1 and the second compensating transistor M2 caused by fluctuations in the potential of the first main electrode are suppressed. This suppresses the effects of voltage fluctuations at the first main electrode on the first switch transistor M3 and the second switch transistor M4.

[0034] The constant current circuit 30 shown in FIG. 3 includes a constant current transistor M5. The constant current transistor M5 may be the same type of transistor as the transistors constituting the switching circuit 10, for example, an N-channel MOS transistor. A first main electrode of the constant current transistor M5 is connected to the second main electrodes of the first switch transistor M3 and the second switch transistor M4, and the second main electrode is connected to the second power supply V2. A predetermined constant voltage Vm is input to the control electrode of the constant current transistor M5 so that a constant constant current Im flows through the constant current circuit 30. For example, the constant voltage Vm may be set by a current mirror circuit or the like.

[0035] In the switching circuit 10, as shown in Fig. 4, a first compensation transistor M1, a first switch transistor M3, a second switch transistor M4, and a second compensation transistor M2 are formed in this order on a semiconductor substrate 200 along a first direction D1. In Fig. 4, the symbol "D" indicates a drain, the symbol "S" indicates a source, and the symbol "G" indicates a gate (the same applies hereinafter). Hereinafter, the configuration in which the first compensation transistor M1, the first switch transistor M3, the second switch transistor M4, and the second compensation transistor M2 are arranged will be referred to as a "transistor string." Furthermore, the transistor string in which the first compensation transistor M1, the first switch transistor M3, the second switch transistor M4, and the second compensation transistor M2 are arranged in this order will also be referred to as a "first transistor string."

[0036] The source of the first compensation transistor M1 and the drain of the first switch transistor M3 are connected together. In other words, the second main electrode of the first compensation transistor M1 and the first main electrode of the first switch transistor M3 are integrated on the semiconductor substrate 200.

[0037] The source of the second compensation transistor M2 and the drain of the second switch transistor M4 are connected together. In other words, the second main electrode of the second compensation transistor M2 and the first main electrode of the second switch transistor M4 are integrated on the semiconductor substrate 200.

[0038] The second main electrode of the first switch transistor M3 and the second main electrode of the second switch transistor M4 are connected together, that is, the second main electrode of the first switch transistor M3 and the second main electrode of the second switch transistor M4 are integrated on the semiconductor substrate 200.

[0039] 4, the first transistor row is configured to be line-symmetrical with respect to the boundary BD between the first switch transistor M3 and the second switch transistor M4, with the normal to the main surface of the semiconductor substrate 200 as the axis of symmetry. The main surface of the semiconductor substrate 200 is parallel to the first direction D1, and the normal to the main surface extends in a third direction D3 perpendicular to the first direction D1. The direction opposite to the first direction D1 is defined as a second direction D2. As described above, in the first transistor row, the arrangement of the first compensation transistor M1 to the first switch transistor M3 and the arrangement of the second switch transistor M4 to the second compensation transistor M2 are configured to be line-symmetrical with respect to the boundary BD. Hereinafter, an arrangement that is line-symmetrical with respect to the third direction D3 will also be referred to as a "symmetrical arrangement."

[0040] 5 shows the layout of the first transistor row as viewed from a third direction D3 (hereinafter also referred to as a "plan view"). As shown in Fig. 5, the first main electrode (drain) of the first compensation transistor M1 and the first connection point P1 are connected by a first connection wiring L1. The first main electrode (drain) of the second compensation transistor M2 and the second connection point P2 are connected by a second connection wiring L2. The second main electrode (source) of the first switch transistor M3 and the second main electrode (source) of the second switch transistor M4 are connected to the first main electrode (drain) of the constant current transistor M5 by a third connection wiring L3.

[0041] FIG. 6 shows a planar layout of transistors constituting a switching circuit of the comparative example (hereinafter referred to as a "comparison switching circuit 10M"). In the comparison switching circuit 10M, a first compensation transistor M1, a second compensation transistor M2, a first switch transistor M3, and a second switch transistor M4 are arranged in this order along a first direction D1. As shown in FIG. 6, the arrangement of the drain and source relative to the gate of each transistor constituting the comparison switching circuit 10M is the same. Hereinafter, transistors with the same arrangement of the drain and source relative to the gate are referred to as having the same orientation.

[0042] For this reason, the transistors in the comparison switching circuit 10M must be spaced apart. Also, a wiring L4 is required to connect the source of the second compensation transistor M2 and the drain of the second switch transistor M4. Furthermore, a wiring L5 is required to connect the source of the first switch transistor M3 and the drain of the constant current transistor M5, and a wiring L6 is required to connect the source of the second switch transistor M4 and the drain of the constant current transistor M5.

[0043] The switching circuit 10 shown in Fig. 5 has fewer wires than the comparative switching circuit 10M shown in Fig. 6. Therefore, the semiconductor integrated circuit 1 according to the embodiment can improve the wiring efficiency of the switching circuit 10. Since the characteristics of the switching circuit 10 tend to deteriorate when the wires are long, the semiconductor integrated circuit 1 can suppress the deterioration of the characteristics.

[0044] Furthermore, according to the semiconductor integrated circuit 1, there is no need to separate the transistors that make up the switching circuit 10. This allows the layout area of ​​the semiconductor integrated circuit 1 to be reduced.

[0045] In the first transistor row with a symmetrical arrangement, the transistor orientations of the first compensation transistor M1 and the first switch transistor M3 are the same, and the transistor orientations of the second compensation transistor M2 and the second switch transistor M4 are the same. Meanwhile, the orientations of the first compensation transistor M1 and the first switch transistor M3 are opposite to those of the second compensation transistor M2 and the second switch transistor M4. Therefore, the transistors' orientations are not the same, which can result in differences in their characteristics. Specifically, the differences in orientation can cause differences in the on-resistance of the transistors and changes in their parasitic capacitance. As a result, a symmetrical arrangement can cause variations in the switching characteristics of the current flowing through the transistors, potentially resulting in distortion in the output signal.

[0046] For example, as shown in FIG. 7, a difference occurs in the waveforms of the first switch current Im3 that flows when the first switch transistor M3 is in a conductive state and the second switch current Im4 that flows when the second switch transistor M4 is in a conductive state. The first switch current Im3 is a current that flows through the first switch transistor M3 when the first signal S1 is input to the control electrode of the first switch transistor M3. The second switch current Im4 is a current that flows through the second switch transistor M4 when the second signal S2 is input to the control electrode of the second switch transistor M4. The first switch current Im3 and the second switch current Im4 oscillate when switching is performed at high speed. In this case, for example, if the wiring connected to the first switch transistor M3 is relatively long, the oscillation period of the first switch current Im3 becomes longer. On the other hand, if the wiring connected to the second switch transistor M4 is relatively short, the oscillation period of the second switch current Im4 becomes shorter. Therefore, as shown in FIG. 7, a difference occurs in the current waveforms of the first switch current Im3 and the second switch current Im4. As a result, fluctuations occur in the output when the voltage is converted.

[0047] Therefore, it is preferable to take measures to suppress the influence of differences in transistor characteristics due to differences in orientation on the characteristics of the semiconductor integrated circuit 1. For example, the layout described below is effective for this purpose.

[0048] 8, a first pattern cell PTN1 and a second pattern cell PTN2 are arranged along a first direction D1. The first pattern cell PTN1 includes a first transistor row in which a first compensation transistor M1, a first switch transistor M3, a second switch transistor M4, and a second compensation transistor M2 are arranged in this order along the first direction D1, and a constant current circuit 30. The second pattern cell PTN2 includes a transistor row (hereinafter also referred to as a "second transistor row") in which a first compensation transistor M1, a first switch transistor M3, a second switch transistor M4, and a second compensation transistor M2 are arranged in this order along a second direction D2 opposite to the first direction D1, and a constant current circuit 30. The second transistor row is also arranged symmetrically, and the second pattern cell PTN2 also includes improved wiring efficiency and a reduced layout area.

[0049] The transistor orientations of the first transistor row included in the first pattern cell PTN1 and the second transistor row included in the second pattern cell PTN2 are reversed. Therefore, according to the layout shown in Figure 8, the characteristic peculiarities caused by the arrangement of the first transistor row and the characteristic peculiarities caused by the arrangement of the second transistor row are offset. This makes it possible to suppress the influence of different transistor orientations on the characteristics of the semiconductor integrated circuit 1.

[0050] 9, a plurality of first pattern cells PTN1 and a plurality of second pattern cells PTN2 may be arranged alternately along the first direction D1. For example, a pair of a first pattern cell PTN1 and a second pattern cell PTN2 may be considered as one pattern cell, and a semiconductor integrated circuit 1 including a plurality of pattern cells may be configured.

[0051] The above describes the layout of a pattern cell including the switching circuit 10 and the constant current circuit 30, but even in a configuration in which the latch circuit 50 and the digital signal circuit 40 are added to the above pattern cell, it is possible to suppress the effects of differences in the transistor orientation on the characteristics of the semiconductor integrated circuit 1. Hereinafter, a configuration including the switching circuit 10, the constant current circuit 30, the digital signal circuit 40, and the latch circuit 50 will be referred to as a "circuit block."

[0052] An example of the layout of circuit blocks is shown in Fig. 10. In a plan view, the first circuit block BLK1 shown in Fig. 10 includes a constant current circuit 30, a switching circuit 10, a latch circuit 50, and a digital signal circuit 40, which are arranged in this order perpendicular to a first direction D1. The semiconductor integrated circuit 1 can handle digital signals with any number of bits by including a number of circuit blocks corresponding to the number of bits.

[0053] 11 shows a circuit block pair consisting of two circuit blocks arranged in line symmetry with respect to a line of symmetry Ls parallel to the first direction D1. The circuit block pair shown in FIG. 11 is composed of a first circuit block BLK1 and a second circuit block BLK2. The first circuit block BLK1 and the second circuit block BLK2 are arranged so as to be upside down in FIG. 11. In other words, the second circuit block BLK2 has a layout that is line symmetrical with respect to the first circuit block BLK1 with respect to the line of symmetry Ls.

[0054] When the circuit blocks are laid out symmetrically with respect to the line of symmetry Ls, the layout of the circuits included in each of the two circuit blocks that make up the circuit block pair is inverted. Therefore, to ensure symmetry, it is effective to ensure symmetry in the arrangement of the circuit contact terminals, etc.

[0055] For example, the constant current circuits 30 included in each of the two paired circuit blocks are arranged opposite each other across the line of symmetry Ls and are configured to be line-symmetrical with respect to the line of symmetry Ls. Therefore, it is effective to arrange each of the constant current circuits 30 in a line-symmetrical manner with respect to the first direction D1. This improves the wiring efficiency of the switching circuit 10, reduces the layout area, and suppresses the effects on the characteristics of the semiconductor integrated circuit 1 caused by differences in the orientation of the transistors.

[0056] 12, when a contact terminal 500 is arranged at a first end 51 of the constant current transistor M5 of the constant current circuit 30, a contact terminal 500 is also arranged at a second end 52 of the constant current transistor M5. This allows the layout of the constant current transistor M5 of the paired circuit block to be inverted with respect to the symmetry line Ls. In this case, if the contact terminal 500 arranged at one end is not used, the contact terminal 500 at that end is a dummy terminal and is not connected to a wiring.

[0057] The circuit block pairs may form a plurality of circuit groups arranged along the first direction D1. Fig. 13 shows an example in which a circuit group G is formed by four circuit block pairs arranged along the first direction D1. For example, signals DATA[0] to DATA[7] are input to the switching circuits 10 of circuit blocks B0 to B7 that form the circuit group G, respectively. In other words, the circuit group G, which is formed by the 2x4 circuit blocks shown in Fig. 13, processes the 8-bit digital signal of signal DATA[7:0].

[0058] 14 shows an example in which a semiconductor integrated circuit 1 is configured with four circuit groups G, namely, a first circuit group G1 to a fourth circuit group G4. As shown in Fig. 14, a plurality of circuit groups may be arranged in a matrix on a semiconductor substrate 200. Each of the first circuit group G1 to the fourth circuit group G4 has the same configuration as the circuit group G shown in Fig. 13. Therefore, the semiconductor integrated circuit 1 shown in Fig. 14 processes a signal of 8 bits x 4 = 32 bits.

[0059] Below, we consider the case where the first to fourth circuit groups G1 to G4 each include eight switching circuits 10 and the same signal DATA is input to each circuit group. If the output currents of the first to fourth circuit groups G1 to G4 are I1 to I4, then if there is no variation in the characteristics of the circuit groups, then I1 = I2 = I3 = I4. However, if there is variation in the characteristics of the circuit groups, then variation will occur in the output currents.

[0060] If there is variation in the output current of the circuit groups, the processing result for a certain 32-bit signal DATA[31:0] will be different when the signal DATA[7:0] is input to the first circuit group G1 and when the signal DATA[7:0] is input to the second circuit group G2. In other words, the processing result of the semiconductor integrated circuit 1 will not be the same even though the results should be the same.

[0061] For this reason, the order in which the circuit groups G are driven may be intentionally changed. This allows for dispersion of variations in characteristics along the time axis and averages out processing results, compared to always driving the circuit groups in the same order. For example, the driving order can be changed in the order G1 → G2 → G3 → G4, G2 → G3 → G4 → G1, G3 → G4 → G1 → G2, G4 → G1 → G2 → G3, and so on. The driving order can be set arbitrarily, but setting the driving order randomly makes it possible to effectively filter out variations along the time axis.

[0062] The circuit blocks may be constructed as cells with a minimum layout area, which makes it easy to expand to various bit numbers.

[0063] As described above, the semiconductor integrated circuit 1 according to the embodiment can improve the wiring efficiency of the switching circuit 10 of the DAC circuit and suppress degradation of characteristics. FIG. 15A shows distortion characteristics in the semiconductor integrated circuit 1. FIG. 15B shows distortion characteristics of a semiconductor integrated circuit using the comparison switching circuit 10M. The characteristics shown in FIG. 15A show reduced second-order distortion and third-order distortion, circled in FIG. 15B, resulting in an improvement of approximately 6 dB in distortion characteristics. Thus, the semiconductor integrated circuit 1 reduces the wiring of the switching circuit 10 and improves wiring efficiency, thereby suppressing degradation of characteristics.

[0064] Furthermore, according to the semiconductor integrated circuit 1, it is not necessary to separate the transistors that make up the switching circuit 10, which makes it possible to reduce the layout area of ​​the semiconductor integrated circuit 1. According to the study by the present inventors, it is possible to reduce the size of the circuit block by about 1%.

[0065] (Other embodiments) Although the present invention has been described above by way of example, the description and drawings that form part of this disclosure should not be understood to limit the scope of the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0066] For example, in the above description, N-channel MOS transistors are used as the transistors that make up the switching circuit 10. However, the switching circuit 10 may be made up of other types of transistors. For example, the switching circuit 10 may be made up of P-channel MOS transistors or bipolar transistors.

[0067] Although the present disclosure has been described in detail above, it will be apparent to those skilled in the art that the present disclosure is not limited to the embodiments described herein. One or more elements of one embodiment may be combined with one or more elements of another embodiment. The present disclosure can be implemented in modified and altered forms without departing from the spirit and scope of the present disclosure as defined by the claims. Therefore, the description of the present disclosure is intended to be illustrative and not limiting.

[0068] [Note] The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0069] [Appendix 1] The semiconductor integrated circuit 1 includes a switching circuit 10 including a first switch SW1 controlled by a first signal S1 and a second switch SW2 controlled by a second signal S2 obtained by inverting the first signal S1, and an output circuit 20 that outputs an output signal whose voltage level is set according to the on / off states of the first switch SW1 and the second switch SW2, and outputs an output signal Dout obtained by digital-to-analog converting the first signal S1 as a digital signal. The switching circuit 10 includes a first switch transistor M3 having a control electrode to which the first signal S1 is input, a second switch transistor M4 having a control electrode to which the second signal S2 is input, a first compensation transistor M1 connected in series between the output circuit 20 and the first switch transistor M3, and a second compensation transistor M2 connected in series between the output circuit 20 and the second switch transistor M4. The first compensation transistor M1, the first switch transistor M3, the second switch transistor M4, and the second compensation transistor M2 are formed in this order on a semiconductor substrate 200. The second main electrode of the first compensation transistor M1 and the first main electrode of the first switch transistor M3 are integrated on the semiconductor substrate 200, the second main electrode of the second compensation transistor M2 and the first main electrode of the second switch transistor M4 are integrated on the semiconductor substrate 200, and the second main electrode of the first switch transistor M3 and the second main electrode of the second switch transistor M4 are integrated on the semiconductor substrate 200.

[0070] According to the semiconductor integrated circuit 1 described in Supplementary Note 1, it is possible to improve wiring efficiency and suppress deterioration of characteristics by reducing the wiring of the switching circuit 10. Furthermore, according to the semiconductor integrated circuit 1 described in Supplementary Note 1, it is not necessary to separate the transistors that make up the switching circuit 10, so it is possible to reduce the layout area of ​​the semiconductor integrated circuit 1.

[0071] [Appendix 2] In the semiconductor integrated circuit 1 described in Supplementary Note 1, the first compensation transistor M1, the first switch transistor M3, the second switch transistor M4, and the second compensation transistor M2 are arranged in line symmetry at the boundary between the first switch transistor M3 and the second switch transistor M4, with the normal to the main surface of the semiconductor substrate 200 as the axis of symmetry. According to the semiconductor integrated circuit 1 described in Supplementary Note 2, it is possible to reduce the wiring of the switching circuit 10 and also reduce the layout area.

[0072] [Appendix 3] The semiconductor integrated circuit 1 described in Supplementary Note 1 or 2 further includes a constant current circuit 30 electrically connected to the second main electrode of the first switch transistor M3 and the second main electrode of the second switch transistor M4. According to the semiconductor integrated circuit 1 described in Supplementary Note 3, a constant current flows through the first switch transistor M3 in a conductive state or the second switch transistor M4 in a conductive state.

[0073] [Appendix 4] The semiconductor integrated circuit 1 described in any one of Supplementary Notes 1 to 3 includes a first pattern cell PTN1 and a second pattern cell PTN2. The first pattern cell PTN1 includes a first compensation transistor M1, a first switch transistor M3, a second switch transistor M4, and a second compensation transistor M2 arranged in this order along a first direction D1, and includes a constant current circuit 30. The second pattern cell PTN2 includes a first compensation transistor M1, a first switch transistor M3, a second switch transistor M4, and a second compensation transistor M2 arranged in this order along a second direction D2 opposite to the first direction D1, and includes a constant current circuit 30. The semiconductor integrated circuit 1 described in Supplementary Note 4 can suppress effects on the characteristics of the semiconductor integrated circuit 1 caused by differences in transistor orientation.

[0074] [Appendix 5] The semiconductor integrated circuit 1 described in any one of Supplementary Notes 1 to 4 further includes a digital signal circuit 40 that outputs a digital signal, and a latch circuit 50 that receives the digital signal and outputs a first signal S1. According to the semiconductor integrated circuit 1 described in Supplementary Note 5, the digital signal and its inverted signal are input to the switching circuit 10.

[0075] [Appendix 6] In the semiconductor integrated circuit 1 described in Supplementary Note 5, the constant current circuit 30, the switching circuit 10, the latch circuit 50, and the digital signal circuit 40 are arranged perpendicular to the first direction D1 to form a circuit block. The semiconductor integrated circuit 1 described in Supplementary Note 6 includes circuit blocks in a number corresponding to the number of bits, thereby enabling support for digital signals of any number of bits.

[0076] [Appendix 7] The semiconductor integrated circuit 1 described in Supplementary Note 6 includes a circuit block pair consisting of two circuit blocks arranged symmetrically with respect to a symmetry line Ls parallel to the first direction D1. The semiconductor integrated circuit 1 described in Supplementary Note 7 can improve wiring efficiency, reduce layout area, and suppress effects on characteristics due to differences in transistor orientation.

[0077] [Appendix 8] In the semiconductor integrated circuit 1 described in Supplementary Note 7, the constant current circuits 30 included in each circuit block are arranged opposite each other across the line of symmetry Ls and are configured to be symmetrical with respect to the line of symmetry Ls. According to the semiconductor integrated circuit 1 described in Supplementary Note 8, it is possible to suppress the influence on characteristics caused by differences in the orientation of the transistors.

[0078] [Appendix 9] In the semiconductor integrated circuit 1 described in Supplementary Note 7 or 8, a circuit group G is configured in which a plurality of circuit block pairs are arranged along the first direction D1. According to the semiconductor integrated circuit 1 described in Supplementary Note 9, by constructing the circuit blocks as cells with a minimum layout area, it becomes easy to expand to various numbers of bits.

[0079] [Appendix 10] In the semiconductor integrated circuit 1 described in Supplementary Note 9, a plurality of circuit groups G are arranged in a matrix on the semiconductor substrate 200. According to the semiconductor integrated circuit 1 described in Supplementary Note 10, by changing the order in which the circuit blocks included in the circuit group G are driven, it is possible to distribute variations in characteristics in the time axis direction and average the processing results.

[0080] [Appendix 11] In the semiconductor integrated circuit 1 described in any one of Supplementary Notes 1 to 10, the first compensation transistor M1, the first switch transistor M3, the second switch transistor M4, and the second compensation transistor M2 are N-channel MOS transistors. [Explanation of symbols]

[0081] 1. Semiconductor integrated circuit 10 Switching Circuits 20 Output circuit 21 First Comparator 22 Second comparator 30 Constant current circuit 40 Digital Signal Circuit 50 Latch Circuit 60 inverter 100 circuit cells 200 Semiconductor substrate 500 contact terminals BLK1 First circuit block BLK2 Second circuit block D1 1st direction D2 2nd direction D3 Third direction G1 First Circuit Group G2 2nd Circuit Group G3 3rd Circuit Group G4 4th Circuit Group Ls Line of symmetry M1 First compensation transistor M2 Second compensation transistor M3 First switch transistor M4 Second switch transistor M5 constant current transistor P1 First connection point P2 Second connection point S1 1st signal S2 2nd signal SW1 First switch SW2 Second switch V1 1st power supply V2 2nd power supply V3 3rd power supply

Claims

1. a switching circuit including a first switch controlled by a first signal and a second switch controlled by a second signal obtained by inverting the first signal; an output circuit that outputs an output signal whose voltage level is set according to the on / off states of the first switch and the second switch; a semiconductor integrated circuit that outputs the output signal obtained by digital-to-analog converting the first signal into a digital signal, The switching circuit a first switch transistor having a control electrode to which the first signal is input; a second switch transistor having a control electrode to which the second signal is input; a first compensation transistor connected in series between the output circuit and the first switch transistor; a second compensation transistor connected in series between the output circuit and the second switch transistor; Including, the first compensation transistor, the first switch transistor, the second switch transistor, and the second compensation transistor are formed in this order on a semiconductor substrate; a second main electrode of the first compensation transistor and a first main electrode of the first switch transistor are integrated in the semiconductor substrate; a second main electrode of the second compensation transistor and a first main electrode of the second switch transistor are integrated in the semiconductor substrate; a second main electrode of the first switch transistor and a second main electrode of the second switch transistor are integrated in the semiconductor substrate; Semiconductor integrated circuit.

2. 2. The semiconductor integrated circuit according to claim 1, wherein the first compensation transistor, the first switch transistor, the second switch transistor, and the second compensation transistor are arranged in line symmetry at a boundary between the first switch transistor and the second switch transistor, with a normal to a main surface of the semiconductor substrate as an axis of symmetry.

3. 3. The semiconductor integrated circuit according to claim 1, further comprising a constant current circuit electrically connected to the second main electrode of said first switch transistor and the second main electrode of said second switch transistor.

4. a first pattern cell including the constant current circuit, in which the first compensation transistor, the first switch transistor, the second switch transistor, and the second compensation transistor are arranged in this order along a first direction; a second pattern cell including the constant current circuit, in which the first compensation transistor, the first switch transistor, the second switch transistor, and the second compensation transistor are arranged in this order along a second direction opposite to the first direction; Including, the first pattern cells and the second pattern cells are arranged along the first direction; 4. The semiconductor integrated circuit according to claim 3.

5. a digital signal circuit that outputs a digital signal; a latch circuit to which the digital signal is input and which outputs the first signal; The semiconductor integrated circuit according to claim 4 , further comprising:

6. 6. The semiconductor integrated circuit according to claim 5, wherein said constant current circuit, said switching circuit, said latch circuit, and said digital signal circuit are arranged perpendicular to said first direction to form a circuit block.

7. 7. The semiconductor integrated circuit according to claim 6, further comprising a circuit block pair consisting of two of said circuit blocks arranged symmetrically with respect to a line of symmetry parallel to said first direction.

8. 8. The semiconductor integrated circuit according to claim 7, wherein the constant current circuits included in each of the circuit blocks are arranged opposite each other across the line of symmetry and are configured symmetrically with respect to the line of symmetry.

9. 8. The semiconductor integrated circuit according to claim 7, wherein a plurality of said circuit block pairs are arranged in said first direction to form a circuit group.

10. The semiconductor integrated circuit according to claim 9 , wherein a plurality of said circuit groups are arranged in a matrix on said semiconductor substrate.

11. 2. The semiconductor integrated circuit according to claim 1, wherein said first compensation transistor, said first switch transistor, said second switch transistor, and said second compensation transistor are N-channel MOS transistors.

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