Semiconductor device

Abstract

To provide a semiconductor device having a high degree of freedom in a circuit design.SOLUTION: A semiconductor device includes: a silicon carbide layer provided with a penetration portion; an aluminum nitride layer disposed on the silicon carbide layer; a gallium nitride layer disposed on the aluminum nitride layer; a first electrode disposed in a first portion of a region directly above the penetration portion; an extraction electrode disposed in a second portion of the region directly above the penetration portion and penetrating the gallium nitride layer and the aluminum nitride layer; a second electrode disposed in the region including the region directly below the first electrode in the penetration portion and connected to the extraction electrode; an insulating film disposed on a lower surface of the silicon carbide layer and a side surface of the penetration portion; and a metal film disposed on a lower surface of the insulating film and not disposed in the penetration portion. A dielectric constant in the penetration portion is lower than a dielectric constant of the insulating film.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] In semiconductor devices that incorporate MMIC (Monolithic Microwave Integrated Circuit), HEMT (High Electron Mobility Transistor) and MIM (Metal-Insulator-Metal) capacitors may be integrated on a single semiconductor substrate. For such semiconductor devices, there is a demand for increased flexibility in circuit design. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-117066 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiment is to provide a semiconductor device with a high degree of freedom in circuit design. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a silicon carbide layer having a through portion, an aluminum nitride layer disposed on the silicon carbide layer, a gallium nitride layer disposed on the aluminum nitride layer, a first electrode disposed in a first portion of a region immediately above the through portion, a lead electrode disposed in a second portion of the region immediately above the through portion and penetrating the gallium nitride layer and the aluminum nitride layer, a second electrode disposed in a region including a region immediately below the first electrode within the through portion and connected to the lead electrode, an insulating film disposed on a lower surface of the silicon carbide layer and on a side surface of the through portion, and a metal film disposed on a lower surface of the insulating film but not within the through portion. The dielectric constant within the through portion is lower than the dielectric constant of the insulating film. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment. [Figure 3] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 4A to 4C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 5A to 5C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 6A to 6C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 7A to 7C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 8A to 8C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 9A to 9C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 10A to 10C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 11]FIG. 11 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 12] FIG. 12 is a cross-sectional view showing a semiconductor device according to the third embodiment. [Figure 13] FIG. 13 is a cross-sectional view showing a semiconductor device according to the fourth embodiment. [Figure 14] FIG. 14 is a cross-sectional view showing a semiconductor device according to the fifth embodiment. [Figure 15] FIG. 15 is a cross-sectional view showing a semiconductor device according to the sixth embodiment. [Figure 16] FIG. 16 is a cross-sectional view showing a semiconductor device according to the seventh embodiment. [Figure 17] FIG. 17 is a cross-sectional view showing a semiconductor device according to the eighth embodiment. [Figure 18] FIG. 18 is a cross-sectional view showing a semiconductor device according to the ninth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] First Embodiment In this embodiment, a semiconductor device including an MMIC in which a HEMT and an MIM are combined will be described, and a description of the HEMT will be omitted.

[0008] (Semiconductor Devices) First, the configuration of the semiconductor device according to this embodiment will be described. FIG. 1 is a plan view showing a semiconductor device according to this embodiment. FIG. 2 is a cross-sectional view showing the semiconductor device according to this embodiment. It should be noted that each figure is a schematic diagram and has been appropriately emphasized and simplified, and the same applies to other figures described later.

[0009] As shown in Figures 1 and 2, the semiconductor device 1 according to this embodiment includes a silicon carbide layer (hereinafter referred to as "SiC layer 11"), an aluminum nitride layer (hereinafter referred to as "AlN layer 12"), a gallium nitride layer (hereinafter referred to as "GaN layer 13"), a front surface electrode 21, an extraction electrode 22, a back surface electrode 23, an insulating film 25, a low dielectric constant member 26, and a metal film 27.

[0010] The SiC layer 11 has a through portion 17. The AlN layer 12 is disposed on the SiC layer 11. The AlN layer 12 is also disposed on the through portion 17 in the SiC layer 11. The AlN layer 12 has a through portion 18. The GaN layer 13 is disposed on the AlN layer 12. The GaN layer 13 is also disposed on the through portion 18 of the AlN layer 12. An aluminum gallium nitride layer (AlGaN layer, not shown) may be disposed on the GaN layer 13.

[0011] Surface electrode 21 is disposed on GaN layer 13 in a part (first portion) of the region directly above through portion 17. Surface electrode 21 is disposed in the region directly above through portion 18 of AlN layer 12. Surface electrode 21 is in contact with upper surface 13a of GaN layer 13. Extraction electrode 22 is disposed in another part (second portion) of the region directly above through portion 17, and penetrates GaN layer 13 and AlN layer 12 in the thickness direction.

[0012] The back electrode 23 is disposed in a region including the region directly below the surface electrode 21 and the region directly below the extraction electrode 22 within the through-hole 17. The back electrode 23 is connected to the extraction electrode 22. In this specification, "connection" means electrical connection. The back electrode 23 is in contact with the lower surface 12b of the AlN layer 12, and is also disposed within the through-hole 18. Within the through-hole 18, the back electrode 23 is in contact with the lower surface 13b of the GaN layer 13.

[0013] The insulating film 25 is disposed on the lower surface of the SiC layer 11 and on the side and bottom surfaces of the through-hole 17, and covers the lower surface 23b of the back electrode 23. The insulating film 25 is made of, for example, silicon nitride (SiN). The low-dielectric-constant member 26 is made of a material having a dielectric constant lower than that of the insulating film 25, and includes, for example, silicon oxide (SiO), such as silicon dioxide (SiO2). However, the material of the low-dielectric-constant member 26 is not limited to silicon oxide, and may be a so-called low-k material. The metal film 27 is continuously disposed on the lower surface 25b of the insulating film 25 and the lower surface 26b of the low-dielectric-constant member 26, and is not disposed within the through-hole 17.

[0014] In the semiconductor device 1 according to this embodiment, the front surface electrode 21 is in contact with the upper surface 13a of the GaN layer 13, and the back surface electrode 23 is in contact with the lower surface 13b of the GaN layer 13. The front surface electrode 21 faces the back surface electrode 23 via the GaN layer 13, thereby forming an MIM capacitor 31. The back surface electrode 23 of the MIM capacitor 31 is led out to the front surface side of the semiconductor device 1 via an extraction electrode 22. The GaN layer 13 functions as a dielectric layer for the MIM capacitor 31. A ground potential (GND) is applied to the metal film 27. The back surface electrode 23 of the MIM capacitor 31 is insulated from the metal film 27 by an insulating film 25 and a low-dielectric-constant member 26.

[0015] (Method of manufacturing a semiconductor device) Next, a method for manufacturing the semiconductor device according to this embodiment will be described. 3 to 10 are cross-sectional views showing a method for manufacturing a semiconductor device according to this embodiment.

[0016] First, a wafer 10 is prepared as shown in Fig. 3. In the wafer 10, a SiC layer 11, an AlN layer 12, a GaN layer 13, and an AlGaN layer (not shown) are stacked in this order. The wafer 10 may be prepared by manufacturing itself or may be provided by receiving it from another party.

[0017] The wafer 10 has a region where a HEMT is to be formed and a region where an MIM is to be formed. The AlGaN layer is removed from the region where the MIM is to be formed. As a result, the GaN layer 13 becomes the top layer of the wafer 10, as shown in FIG. 3. On the other hand, the AlGaN layer is left in the region where the HEMT is to be formed.

[0018] 4, etching is performed from the front surface 10a side of the wafer 10 to remove a portion of the GaN layer 13, and then the AlN layer 12 directly below it is removed. This forms through-holes 16 in the GaN layer 13 and the AlN layer 12. The through-holes 16 penetrate the GaN layer 13 and the AlN layer 12 in the thickness direction.

[0019] 5, a metal is selectively disposed on the GaN layer 13 to form a surface electrode 21. Furthermore, a metal is embedded in the through-hole 16 to form an extraction electrode 22. The lower surface of the surface electrode 21 contacts the upper surface 13a of the GaN layer 13. The upper portion of the extraction electrode 22 protrudes upward from the upper surface 13a of the GaN layer 13. The extraction electrode 22 penetrates the GaN layer 13 and the AlN layer 12, and its lower surface contacts the SiC layer 11.

[0020] 6, etching is performed from the back surface 10b side of the wafer 10 to remove the SiC layer 11 in the region including the region directly below the front surface electrode 21 and the region directly below the extraction electrode 22. As a result, a through hole 17 is formed in the back surface 10b of the wafer 10. The through hole 17 penetrates the SiC layer 11 in the thickness direction, and the lower surface 12b of the AlN layer 12 and the lower surface of the extraction electrode 22 are exposed at the bottom of the through hole 17.

[0021] 7, AlN layer 12 is removed from the area directly below front surface electrode 21 on the bottom surface of through portion 17. This forms through portion 18 in AlN layer 12. Lower surface 13b of GaN layer 13 is exposed at the bottom surface of through portion 18.

[0022] 8 , a back surface electrode 23 is formed on a part of or the entire bottom surface of the through portion 17. The upper surface of the back surface electrode 23 contacts the lower surface 12b of the AlN layer 12 and the lower surface of the extraction electrode 22. In this way, the back surface electrode 23 is connected to the extraction electrode 22. The back surface electrode 23 is also disposed in the through portion 18 of the AlN layer 12. In the through portion 18, the upper surface of the back surface electrode 23 contacts the lower surface 13b of the GaN layer 13.

[0023] 9, an insulating film 25 is formed on the entire back surface 10b of the wafer 10. The insulating film 25 is made of, for example, silicon nitride (SiN). The insulating film 25 is also formed on the inner surface of the through portion 17, and covers the lower surface 23b of the back surface electrode 23.

[0024] 10 , a low-dielectric-constant material, for example, silicon oxide, is embedded in the through portion 17 to form the low-dielectric-constant member 26. The lower surface 26b of the low-dielectric-constant member 26 is flush with the lower surface 25b of the insulating film 25 that is disposed on the lower surface of the SiC layer 11.

[0025] 2, a metal film 27 is formed on the entire lower surface 25b of the insulating film 25 and the entire lower surface 26b of the low dielectric constant member 26. The metal film 27 is separated from the back surface electrode 23 via the low dielectric constant member 26 and the insulating film 25. Thereafter, the wafer 10 is diced into individual pieces. In this manner, the semiconductor device 1 according to this embodiment is manufactured.

[0026] 4, it is preferable that the through portion 16 reaches the SiC layer 11, but a small amount of the AlN layer 12 may be left at the bottom of the through portion 16. In this case, when the through portion 17 is formed in the SiC layer 11 in the step shown in FIG. 6, the lower surface 12b of the AlN layer 12 is slightly removed to expose the lower surface of the extraction electrode 22.

[0027] (effect) In the semiconductor device 1 according to this embodiment, the GaN layer 13 is used as the dielectric layer of the MIM capacitor 31. Gallium nitride (GaN) has a high dielectric constant, so the thickness of the GaN layer 13 can be secured to achieve the necessary breakdown voltage while achieving a high capacitance in the MIM capacitor 31. As a result, the MIM capacitor 31 can be miniaturized while ensuring the required capacitance. Furthermore, by using the GaN layer 13 included in the wafer 10 as the dielectric layer of the MIM capacitor 31, the manufacturing cost of the semiconductor device 1 can be reduced.

[0028] Furthermore, since the back electrode 23 of the MIM capacitor 31 is insulated from the metal film 27, any potential can be applied to the back electrode 23 even when a reference potential, for example, a ground potential, is applied to the metal film 27. As a result, the degree of freedom in circuit design of the semiconductor device 1 is improved.

[0029] If the back electrode 23 is not provided and the metal film 27 is used as the back electrode of the MIM capacitor 31, the potential of the back electrode of the MIM capacitor 31 will be fixed to a reference potential, for example, a ground potential, which reduces the degree of freedom in circuit design.

[0030] Furthermore, in the semiconductor device 1, a low dielectric constant member 26 having a dielectric constant lower than that of the insulating film 25 is interposed between the back electrode 23 and the metal film 27 of the MIM capacitor 31. This reduces the parasitic capacitance between the back electrode 23 and the metal film 27, enabling the semiconductor device 1 to operate at a higher speed.

[0031] <Second embodiment> FIG. 11 is a cross-sectional view showing the semiconductor device according to this embodiment. 11, the semiconductor device 2 according to this embodiment differs from the semiconductor device 1 according to the first embodiment in that the insulating film 25 does not cover the lower surface 23b of the back surface electrode 23. The semiconductor device 2 can be manufactured, for example, by selectively etching the insulating film 25 to remove it from above the bottom surface of the through portion 17 after the step shown in FIG.

[0032] In the semiconductor device 2, only the low dielectric constant member 26 is interposed between the back electrode 23 and the metal film 27. This makes it possible to further reduce the parasitic capacitance between the back electrode 23 and the metal film 27 compared to the semiconductor device 1 according to the first embodiment. Other configurations, manufacturing methods, operations, and effects of this embodiment are the same as those of the first embodiment.

[0033] <Third embodiment> FIG. 12 is a cross-sectional view showing the semiconductor device according to this embodiment. As shown in FIG. 12, the semiconductor device 3 of this embodiment differs from the semiconductor device 2 of the second embodiment in that a metal film 27 is not disposed on the lower surface 26b of the low dielectric constant component 26.

[0034] In the semiconductor device 3, the metal film 27 is not disposed on the lower surface 26b of the low dielectric constant member 26, and therefore the metal film 27 is not disposed directly below the back surface electrode 23. This makes it possible to further reduce the parasitic capacitance between the back surface electrode 23 and the metal film 27 compared to the semiconductor device 2 according to the second embodiment. Other than the above, the configuration, manufacturing method, operation, and effects of this embodiment are the same as those of the second embodiment.

[0035] <Fourth embodiment> FIG. 13 is a cross-sectional view showing the semiconductor device according to this embodiment. 13, the semiconductor device 4 according to this embodiment differs from the semiconductor device 1 according to the first embodiment in that the low dielectric constant member 26 is not provided inside the through portion 17. In the semiconductor device 4, the inside of the through portion 17 is hollow, forming an air layer 28.

[0036] 9, the semiconductor device 4 can be manufactured by embedding a sacrificial member such as a polymer in the through portion 17, forming a metal film 27 on the lower surface 25b of the insulating film 25 and on a part of the lower surface of the sacrificial member, and then removing the sacrificial member. However, the manufacturing method of the semiconductor device 4 is not limited to this.

[0037] In the semiconductor device 4, air is present in the through portion 17. The dielectric constant of air is approximately 1, which is lower than the dielectric constant of silicon oxide, so the dielectric constant in the through portion 17 can be further reduced. As a result, the parasitic capacitance between the back electrode 23 and the metal film 27 can be further reduced compared to the semiconductor device 1 according to the first embodiment. Other than the above, the configuration, manufacturing method, operation, and effects of this embodiment are the same as those of the first embodiment.

[0038] <Fifth embodiment> FIG. 14 is a cross-sectional view showing the semiconductor device according to this embodiment. 14, the semiconductor device 5 according to this embodiment differs from the semiconductor device 4 according to the fourth embodiment in that the insulating film 25 does not cover the lower surface 23b of the back surface electrode 23. The semiconductor device 5 can be manufactured by selectively etching the insulating film 25 after the step shown in FIG.

[0039] In the semiconductor device 5, only air is present between the back electrode 23 and the metal film 27. This allows the parasitic capacitance between the back electrode 23 and the metal film 27 to be further reduced compared to the semiconductor device 4 according to the fourth embodiment. Other configurations, manufacturing methods, operations, and effects of this embodiment are the same as those of the fourth embodiment.

[0040] Sixth Embodiment FIG. 15 is a cross-sectional view showing the semiconductor device according to this embodiment. As shown in Figure 15, the semiconductor device 6 of this embodiment differs from the semiconductor device 4 of the fourth embodiment in that a metal film 27 is not arranged directly below the through portion 17.

[0041] In the semiconductor device 6, the metal film 27 is not disposed directly below the through portion 17, and therefore the metal film 27 is not disposed directly below the back surface electrode 23. This makes it possible to further reduce the parasitic capacitance between the back surface electrode 23 and the metal film 27 compared to the semiconductor device 4 according to the fourth embodiment. Other than the above, the configuration, manufacturing method, operation and effects of this embodiment are the same as those of the fourth embodiment.

[0042] Seventh Embodiment FIG. 16 is a cross-sectional view showing the semiconductor device according to this embodiment. 16, the semiconductor device 7 according to this embodiment differs from the semiconductor device 6 according to the sixth embodiment in that the insulating film 25 does not cover the lower surface 23b of the back surface electrode 23. This makes it possible to further reduce the parasitic capacitance between the back surface electrode 23 and the metal film 27. Other than the above, the configuration, manufacturing method, operation, and effects of this embodiment are the same as those of the sixth embodiment.

[0043] Eighth Embodiment FIG. 17 is a cross-sectional view showing the semiconductor device according to this embodiment. 17, the semiconductor device 8 according to this embodiment differs from the semiconductor device 1 according to the first embodiment in that an AlN layer 12 is used as the dielectric layer of the MIM capacitor. That is, in the semiconductor device 8, the front surface electrode 21 is in contact with the upper surface 12a of the AlN layer 12, and the back surface electrode 23 is in contact with the lower surface 12b of the AlN layer 12.

[0044] In this embodiment, an AlN layer 12 is used as the dielectric layer of the MIM capacitor. Depending on the characteristics required of the MIM capacitor, such an MIM capacitor may be suitable. The manufacturing method, configuration, and effects of this embodiment other than those described above are the same as those of the first embodiment.

[0045] <Ninth embodiment> FIG. 18 is a cross-sectional view showing the semiconductor device according to this embodiment. 18, the semiconductor device 9 according to this embodiment differs from the semiconductor device 1 according to the first embodiment in that the dielectric layer of the MIM capacitor is a laminated film made of an AlN layer 12 and a GaN layer 13. That is, in the semiconductor device 9, the front electrode 21 is in contact with the upper surface 13a of the GaN layer 13, and the back electrode 23 is in contact with the lower surface 12b of the AlN layer 12.

[0046] In this embodiment, a laminated film made of an AlN layer 12 and a GaN layer 13 is used as the dielectric layer of the MIM capacitor, and therefore the breakdown voltage of the MIM capacitor is higher than that of the semiconductor device 1 according to the first embodiment. Other than the above, the manufacturing method, configuration, and effects of this embodiment are the same as those of the first embodiment.

[0047] The above-described embodiments may be implemented in combination with one another. For example, in the semiconductor devices according to the second to seventh embodiments, only the AlN layer 12 may be used as the dielectric layer of the MIM capacitor as in the eighth embodiment, or a laminated film made of the AlN layer 12 and the GaN layer 13 may be used as the dielectric layer of the MIM capacitor as in the ninth embodiment.

[0048] According to the embodiment described above, a semiconductor device with a high degree of freedom in circuit design can be realized.

[0049] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0050] The present invention includes the following aspects.

[0051] (Appendix 1) a silicon carbide layer having a through portion; an aluminum nitride layer disposed on the silicon carbide layer; a gallium nitride layer disposed on the aluminum nitride layer; a first electrode disposed in a first portion of the region directly above the through portion; an extraction electrode disposed in a second portion directly above the through portion and penetrating the gallium nitride layer and the aluminum nitride layer; a second electrode disposed in a region including a region directly below the first electrode in the through-hole and connected to the extraction electrode; an insulating film disposed on a lower surface of the silicon carbide layer and on a side surface of the through portion; a metal film disposed on a lower surface of the insulating film and not disposed within the through-hole; Equipped with The semiconductor device has a dielectric constant in the through portion lower than the dielectric constant of the insulating film.

[0052] (Appendix 2) 2. The semiconductor device according to claim 1, further comprising a low-dielectric-constant member disposed in the through portion and having a dielectric constant lower than that of the insulating film.

[0053] (Appendix 3) 3. The semiconductor device according to claim 2, wherein the low dielectric constant material includes silicon oxide.

[0054] (Appendix 4) 2. The semiconductor device according to claim 1, wherein the through-hole is hollow.

[0055] (Appendix 5) 5. The semiconductor device according to claim 1, wherein the metal film is not disposed in a region directly below the through portion.

[0056] (Appendix 6) 6. The semiconductor device according to claim 1, wherein the insulating film covers a lower surface of the second electrode.

[0057] (Appendix 7) 6. The semiconductor device according to claim 1, wherein the insulating film does not cover a lower surface of the second electrode.

[0058] (Appendix 8) the first electrode is in contact with an upper surface of the gallium nitride layer; 8. The semiconductor device according to claim 1, wherein the second electrode is in contact with a lower surface of the gallium nitride layer.

[0059] (Appendix 9) the first electrode is in contact with an upper surface of the aluminum nitride layer; 8. The semiconductor device according to claim 1, wherein the second electrode is in contact with a lower surface of the aluminum nitride layer.

[0060] (Appendix 10) the first electrode is in contact with an upper surface of the gallium nitride layer; 8. The semiconductor device according to claim 1, wherein the second electrode is in contact with a lower surface of the aluminum nitride layer. [Explanation of symbols]

[0061] 1, 2, 3, 4, 5, 6, 7, 8, 9 Semiconductor device 10 wafers 10a surface 10b back side 11 SiC layer 12 AlN layer 12a Top side 12b Bottom side 13 GaN layer 13a Top side 13b Bottom side 16, 17, 18 Penetrations 21 Surface electrode 22 Extraction electrode 23 Back electrode 23b Bottom surface 25 insulating film 25b Bottom side 26 Low dielectric constant materials 26b Bottom surface 27 Metal Film 28 Air Layer 31 MIM capacitor

Claims

1. a silicon carbide layer having a through portion; an aluminum nitride layer disposed on the silicon carbide layer; a gallium nitride layer disposed on the aluminum nitride layer; a first electrode disposed in a first portion of the region directly above the through portion; an extraction electrode disposed in a second portion directly above the through portion and penetrating the gallium nitride layer and the aluminum nitride layer; a second electrode disposed in a region including a region directly below the first electrode within the through-hole and connected to the extraction electrode; an insulating film disposed on a lower surface of the silicon carbide layer and on a side surface of the through portion; a metal film disposed on a lower surface of the insulating film and not disposed within the through-hole; Equipped with The semiconductor device has a dielectric constant in the through portion lower than the dielectric constant of the insulating film.

2. The semiconductor device according to claim 1 , further comprising a low-dielectric-constant member disposed in the through portion and having a dielectric constant lower than that of the insulating film.

3. The semiconductor device according to claim 2 , wherein the low dielectric constant material includes silicon oxide.

4. 2. The semiconductor device according to claim 1, wherein the through-hole is hollow.

5. The semiconductor device according to claim 1 , wherein the metal film is not disposed directly below the through-hole.

6. The semiconductor device according to claim 1 , wherein the insulating film covers a lower surface of the second electrode.

7. The semiconductor device according to claim 1 , wherein the insulating film does not cover a lower surface of the second electrode.

8. the first electrode is in contact with an upper surface of the gallium nitride layer; 8. The semiconductor device according to claim 1, wherein the second electrode is in contact with the lower surface of the gallium nitride layer.

9. the first electrode is in contact with an upper surface of the aluminum nitride layer; 8. The semiconductor device according to claim 1, wherein the second electrode is in contact with the lower surface of the aluminum nitride layer.

10. the first electrode is in contact with an upper surface of the gallium nitride layer; 8. The semiconductor device according to claim 1, wherein the second electrode is in contact with the lower surface of the aluminum nitride layer.

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