Semiconductor device

Abstract

To prevent a wire from detaching from a pad.SOLUTION: A semiconductor device 1 includes a semiconductor element 10 comprising an element surface 11 and an element back surface 12 opposite the element surface 11, a source pad 22 P arranged on the element surface 11, a first conductive layer 201 stacked on the source pad 22 P, a second conductive layer 202 containing nickel, stacked on the first conductive layer 201 and at least partially exposed, and a wire 142, bonded to the second conductive layer 202 and composed of aluminum. The semiconductor element 10 has a thickness of 100 μm or less. The second conductive layer 202 is composed of a material that is harder than the first conductive layer 201.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 describes a semiconductor device that includes a semiconductor element having an electrode pad portion. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-154006

[0004] [overview] For example, when a wire is bonded to a pad, the wire may come off due to the load or the like.

[0005] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor element having a surface and a back surface opposite the surface, a pad disposed on the surface of the element, a first conductive layer stacked on the pad, a second conductive layer stacked on the first conductive layer, the second conductive layer containing Ni and having at least a portion exposed, and a wire made of Al bonded to the second conductive layer, wherein the semiconductor element has a thickness of 100 μm or less, and the second conductive layer is made of a material harder than the first conductive layer. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic perspective view showing a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a schematic perspective view of the semiconductor device of FIG. 1 as viewed from the back surface side. [Figure 3] FIG. 3 is a schematic plan view showing the inside of the semiconductor device of FIG. [Figure 4] FIG. 4 is a schematic plan view of a semiconductor element in the semiconductor device of FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view of the semiconductor device taken along line 5-5 in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view showing an enlarged view of a part of the wire bonding portion and its periphery in FIG. [Figure 7] 7A to 7C are schematic cross-sectional views illustrating the manufacturing process of an exemplary semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a comparative example in which ultrasonic waves and a load are applied to connect a wire to a source pad. [Figure 14] FIG. 14 is a schematic cross-sectional view of a comparative example in which a damaged layer is formed at the contact portion between the source pad and the bonded portion of the wire. [Figure 15] FIG. 15 is an explanatory diagram of a tensile test on a wire bonded to the source pad of FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a case where ultrasonic waves and a load are applied to a wire on a source pad having a first conductive layer and a second conductive layer arranged on the surface side. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a case where the formation of a damaged layer at the contact portion between the source pad and the junction of the wire can be suppressed. [Figure 18] FIG. 18 is a schematic cross-sectional view showing an enlarged view of a part of a wire bonding portion and its periphery in the semiconductor device according to the second embodiment. [Figure 19] FIG. 19 is a schematic cross-sectional view illustrating a manufacturing process of an exemplary semiconductor device according to the second embodiment. [Figure 20] FIG. 20 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 21] FIG. 21 is a schematic cross-sectional view showing a comparative example in which ultrasonic waves and a load are applied to connect a wire to a source pad in a state in which voids have occurred in the conductive bonding material. [Figure 22] FIG. 22 is an explanatory diagram of a tensile test on a wire bonded to the source pad of FIG. [Figure 23] FIG. 23 is a schematic cross-sectional view showing an enlarged view of a part of a wire bonding portion and its periphery in the semiconductor device according to the third embodiment. [Figure 24] FIG. 24 is a schematic cross-sectional view showing an enlarged view of a part of a wire bonding portion and its periphery in a semiconductor device according to a modified example. [Figure 25] FIG. 25 is a schematic plan view of a semiconductor element in a semiconductor device according to a modified example. [Figure 26] FIG. 26 is a schematic plan view showing the inside of a semiconductor device according to a modified example.

[0007] [Detailed explanation] Hereinafter, various embodiments of the semiconductor device will be described with reference to the drawings. Each of the embodiments shown below exemplifies a configuration and method for embodying the technical idea, and does not limit the material, shape, structure, arrangement, dimensions, etc. of each component to those described below. Various modifications can be made to each of the following embodiments.

[0008] In this specification, "a state in which component A is connected to component B" includes a case in which component A and component B are directly physically connected, as well as a case in which component A and component B are indirectly connected via another component that does not affect the electrical connection state.

[0009] The terms "first," "second," "third," etc., used herein are merely used as labels and are not necessarily intended to assign any ordering to their objects. For simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0010] First Embodiment [Package structure of semiconductor device] The package structure of the semiconductor device according to the first embodiment will be described with reference to Figures 1 and 2. Figure 1 schematically shows a perspective view of the package structure of the semiconductor device according to the first embodiment. Figure 2 schematically shows a perspective view of the package structure on the back side of the semiconductor device shown in Figure 1. In Figure 1, the internal structure of the package is schematically shown by dashed lines.

[0011] As shown in Fig. 1, the semiconductor device 1 has a generally rectangular flat plate shape with the thickness direction in the Z direction. In the example shown in Fig. 1, the semiconductor device 1 employs a TOLL (Transistor Outline Lead Less) package structure. Note that the package structure of the semiconductor device 1 is not limited to the TOLL shown in Fig. 1 and can be changed as desired.

[0012] The semiconductor device 1 includes a semiconductor element 10, a substrate 100 that supports the semiconductor element 10, a first terminal 110 and a second terminal 120 that are electrically connected to the semiconductor element 10, and a sealing resin 130 that seals the semiconductor element 10 and partially seals the substrate 100, the first terminal 110, and the second terminal 120. In the following description, "plan view" refers to a view of the semiconductor device 1 from the Z direction. Two directions that are perpendicular to the Z direction and are orthogonal to each other are referred to as the "X direction" and the "Y direction," respectively.

[0013] The sealing resin 130 constitutes part of the outer shape of the semiconductor device 1. The sealing resin 130 has a rectangular plate shape with its thickness direction in the Z direction. The sealing resin 130 includes a sealing surface 131, a sealing back surface 132 opposite the sealing surface 131, and first to fourth sealing side surfaces 133 to 136 as four sealing side surfaces connecting the sealing surface 131 and the sealing back surface 132. The first sealing side surface 133 and the second sealing side surface 134 constitute both end surfaces of the sealing resin 130 in the X direction. The third sealing side surface 135 and the fourth sealing side surface 136 constitute both end surfaces of the sealing resin 130 in the Y direction. The sealing resin 130 is made of an insulating material. In one example, the sealing resin 130 is made of a black epoxy resin.

[0014] 1 and 2, in a plan view, the substrate 100, the first terminal 110, and the second terminal 120 are arranged spaced apart from each other in the Y direction. The first terminal 110 and the second terminal 120 are arranged spaced apart from each other in the X direction.

[0015] The substrate 100, the first terminal 110, and the second terminal 120 each have a flat plate shape with the thickness direction in the Z direction. The substrate 100 is disposed closer to the third sealing side surface 135 than the first terminal 110 and the second terminal 120. The first terminal 110 is disposed closer to the second sealing side surface 134 than the second terminal 120. As shown in FIG. 2 , the substrate 100, the first terminal 110, and the second terminal 120 are each exposed from the sealing back surface 132 of the sealing resin 130. This improves the heat dissipation properties of the substrate 100, the first terminal 110, and the second terminal 120. The substrate 100 is disposed so as to protrude in the Y direction from the third sealing side surface 135. The first terminal 110 and the second terminal 120 are disposed so as to protrude in the Y direction from the fourth sealing side surface 136.

[0016] The substrate 100, the first terminal 110, and the second terminal 120 are made of conductive metal plates. In one example, the substrate 100, the first terminal 110, and the second terminal 120 are formed by, for example, punching or bending a metal plate. In one example, the substrate 100, the first terminal 110, and the second terminal 120 are made of a material containing at least one of aluminum (Al), copper (Cu), and nickel (Ni). In one example, the die pad 101 is made of a material containing Cu. In one example, the thickness of each of the substrate 100, the first terminal 110, and the second terminal 120 is 0.1 mm or more and 0.3 mm or less. The thickness of each of the substrate 100, the first terminal 110, and the second terminal 120 can be changed as desired.

[0017] [Internal structure of semiconductor device] The internal structure of the semiconductor device 1 will be described with reference to Fig. 3. Fig. 3 shows a schematic plan view of the internal structure of the semiconductor device 1.

[0018] 3, the substrate 100 includes a die pad 101 and a substrate terminal 102. The die pad 101 constitutes a portion of the substrate 100 that is closer to the fourth sealing side surface 136 than to the third sealing side surface 135. The die pad 101 and the substrate terminal 102 are arranged side by side in the X direction.

[0019] The semiconductor element 10 is mounted on the die pad 101. More specifically, the die pad 101 includes a recess 103 that defines a mounting area where the semiconductor element 10 is mounted. The recess 103 has a rectangular shape in a plan view. The area of ​​a bottom surface 103A of the recess 103 is larger than the area of ​​the semiconductor element 10 in a plan view. The semiconductor element 10 is bonded to the bottom surface 103A of the recess 103 of the die pad 101 by a conductive bonding material 104 (see FIG. 5 ). This electrically connects the semiconductor element 10 to the substrate 100. The conductive bonding material 104 is, for example, solder. The configuration of the die pad 101 can be changed as desired. For example, the recess 103 of the die pad 101 may have a shape other than a rectangular shape in a plan view. For example, the recess 103 may be omitted from the die pad 101.

[0020] The substrate terminal 102 constitutes a portion of the substrate 100 that protrudes in the Y direction from the third sealing side surface 135. The substrate terminal 102 and the exposed portion of the back surface of the substrate 100 may constitute an external terminal for electrically connecting the semiconductor element 10 to a circuit board or the like external to the semiconductor device 1.

[0021] The first terminal 110 includes a first wire bonding portion 111 and a plurality of (seven in the first embodiment) first extension portions 112. The first wire bonding portion 111 has a substantially rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction in a plan view. Each first extension portion 112 extends in the Y direction from the first wire bonding portion 111. The plurality of first extension portions 112 are arranged spaced apart from one another in the X direction. Therefore, the first terminal 110 has a comb-like shape in a plan view.

[0022] The first wire bonding portion 111 constitutes a portion of the first terminal 110 that is closer to the third sealing side surface 135 than the fourth sealing side surface 136. Through holes 113 are provided at both ends of the first wire bonding portion 111 in the X direction. The through holes 113 are filled with sealing resin 130. Each first extension portion 112 extends in the Y direction from the first wire bonding portion 111 toward the fourth sealing side surface 136. Each first extension portion 112 protrudes in the Y direction from the fourth sealing side surface 136.

[0023] The second terminal 120 has a rectangular shape with its longitudinal direction in the Y direction and its lateral direction in the X direction in a plan view. The second terminal 120 includes a second wire bonding portion 121 and a second extension portion 122. The second wire bonding portion 121 is disposed closer to the third sealing side surface 135 than the fourth sealing side surface 136. The second wire bonding portion 121 is disposed side by side with the first wire bonding portion 111 of the first terminal 110 in the X direction. The second extension portion 122 constitutes a portion that protrudes from the fourth sealing side surface 136 in the Y direction. The second extension portion 122 is disposed side by side with the first extension portion 112 of the first terminal 110 in the X direction.

[0024] The semiconductor element 10 mounted on the die pad 101 is electrically connected to the second terminal 120 by a wire 141. The wire 141 joins a gate pad 21P (described later) of the semiconductor element 10 to a second wire bonding portion 121 of the second terminal 120. The semiconductor element 10 is also electrically connected to the first terminal 110 by a plurality of wires 142 (five in FIG. 3 ). Each wire 142 joins a source pad 22P (described later) of the semiconductor element 10 to a first wire bonding portion 111 of the first terminal 110. The wire 141 and the plurality of wires 142 are sealed with a sealing resin 130.

[0025] [Configuration of semiconductor elements] The configuration of the semiconductor element 10 will be described with reference to FIGS. Fig. 4 schematically shows the planar structure of the semiconductor element 10. Fig. 5 schematically shows the cross-sectional structure of the semiconductor device 1 taken along line 5-5 in Fig. 3. Note that in Fig. 4, a conductive laminated portion 200, which will be described later, is omitted to make the drawing easier to understand.

[0026] As shown in Fig. 4, the semiconductor element 10 has a rectangular shape having long and short sides in a plan view. As shown in Fig. 3, the semiconductor element 10 is disposed on the die pad 101 with the long sides aligned in the X direction and the short sides aligned in the Y direction. The semiconductor element 10 is configured as, for example, a transistor. The semiconductor element 10 is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). In one example, the semiconductor element 10 is a MOSFET using silicon carbide (SiC).

[0027] The semiconductor element 10 may be a MOSFET using silicon (Si), a high electron mobility transistor (HEMT) made of a nitride semiconductor (e.g., gallium nitride (GaN)), or an insulated gate bipolar transistor (IGBT). The semiconductor element 10 is not limited to a transistor, and may be configured as, for example, a diode.

[0028] Semiconductor element 10 includes element front surface 11, element back surface 12 (see FIG. 6) opposite element front surface 11, and first to fourth element side surfaces 13 to 16 as four element side surfaces connecting element front surface 11 and element back surface 12. First element side surface 13 and second element side surface 14 constitute both end surfaces of semiconductor element 10 in the X direction. Third element side surface 15 and fourth element side surface 16 constitute both end surfaces of semiconductor element 10 in the Y direction.

[0029] The thickness of the semiconductor element 10 is, for example, 100 μm or less. In one example, the thickness of the semiconductor element 10 is less than 100 μm. In one example, the thickness of the semiconductor element 10 is 60 μm or less. Here, the thickness of the semiconductor element 10 can be defined as the distance between the element front surface 11 and the element back surface 12 in the Z direction.

[0030] The semiconductor element 10 includes a gate electrode 21, a source electrode 22, an insulating layer 23, and a drain electrode (not shown). The gate electrode 21 and the source electrode 22 are provided on a surface 11 of the element. The insulating layer 23 covers the surface 11 of the element and partially covers each of the gate electrode 21 and the source electrode 22. The drain electrode (not shown) is provided on a back surface 12 of the element.

[0031] The gate electrode 21 is disposed at an end of the element surface 11 in the X direction that is closer to the first element side surface 13. The gate electrode 21 is disposed at the center of the element surface 11 in the Y direction. The position of the gate electrode 21 can be changed as desired.

[0032] The source electrode 22 is disposed closer to the second element side surface 14 than the gate electrode 21 in a plan view. The source electrode 22 is provided over most of the element surface 11 in a plan view. In one example, a plurality of source electrodes 22 (10 in the first embodiment) are provided in a matrix (for example, 2 rows × 5 columns).

[0033] For example, Al, AlCu, etc. are used as the material of the source electrode 22. AlCu (Cu content: 0.5%) is used when resistance to electromigration and stress migration is required compared to simple Al.

[0034] The insulating layer 23 is configured to insulate the gate electrode 21 from the source electrode 22. That is, the insulating layer 23 is provided between the gate electrode 21 and the source electrode 22. In a plan view, the insulating layer 23 covers the outer periphery of the gate electrode 21. The insulating layer 23 includes a gate opening 23A that exposes a portion of the gate electrode 21 that is more inward than the outer periphery. The region of the gate electrode 21 exposed by the gate opening 23A forms a gate pad 21P.

[0035] The insulating layer 23 covers the outer periphery of each of the plurality of source electrodes 22 in a planar view. The insulating layer 23 includes a plurality of source openings 23B. The plurality of source openings 23B are provided corresponding to the plurality of source electrodes 22. Each source opening 23B exposes a portion of the corresponding source electrode 22 that is more inward than the outer periphery. The plurality of source openings 23B are arranged in a matrix (e.g., 2 rows x 5 columns) in a planar view to correspond to the plurality of source electrodes 22. The region of the source electrode 22 exposed by each source opening 23B constitutes a source pad 22P. Therefore, the plurality of source pads 22P are arranged in a matrix (e.g., 2 rows x 5 columns) in a planar view. Here, the source pad 22P is an example of a "pad arranged on the element surface."

[0036] 3, one wire 142 is bonded to two source pads 22P aligned in the Y direction and is also bonded to the first wire bonding portion 111 of the first terminal 110. Therefore, as shown in FIG. 5, the wire 142 is provided so as to straddle the insulating layer 23 that separates the two source pads 22P aligned in the Y direction. Similarly to the one wire 142, the other four wires 142 are also bonded to the two source pads 22P aligned in the Y direction and are also bonded to the first wire bonding portion 111. In this way, a plurality of wires 142 are bonded to a corresponding plurality of source pads 22P.

[0037] The wires 141 and 142 are bonding wires. The wires 141 and 142 are made of a conductive material including, for example, Al, Cu, Ag, Au, etc. In the first embodiment, the wires 141 and 142 are made of Al. This reduces the cost of the wires 141 and 142 compared to when the wires 141 and 142 are made of a precious metal. In particular, when the wire 142 needs to have a large diameter as a wire for large current, making the wire 142 of Al can enhance the effect of reducing the cost of the wire 142. Note that the conductive material of the wire 141 and the conductive material of the wire 142 may be different from each other.

[0038] The wire diameter of the wire 141 bonded to the gate pad 21P is smaller than the wire diameter of the wire 142 bonded to the source pad 22P. The wire diameter of the wire 141 that supplies a control current to the gate electrode 21 of the semiconductor element 10 can be smaller than the wire diameter of the wire 142 that supplies a drive current from the source electrode 22 of the semiconductor element 10. When the semiconductor device 1 is applied to a power circuit such as an inverter device that supplies current to a traction motor of a vehicle, a large current is supplied to the semiconductor element 10. In other words, the semiconductor element 10 can be considered a power semiconductor. Therefore, the wire diameter of the wire 142 bonded to the source pad 22P is set to accommodate the large current. In one example, the wire diameter of the wire 142 can be larger than 400 μm. In another example, the wire diameter of the wire 142 can be 500 μm or more. In the first embodiment, a wire 142 with a diameter of 508 μm is used. In other words, in the first embodiment, a wire 142 with a diameter of 20 mil is used. Here, 1 mil is 1 / 1000 of an inch, or approximately 25.4 μm. On the other hand, the diameter of the wire 141 bonded to the gate pad 21P can be 150 μm or less. In the first embodiment, the wire 141 has a diameter of 127 μm. In other words, in the first embodiment, the wire 141 has a diameter of 5 mil.

[0039] [Source pad and its surrounding configuration] The configuration of the source pad 22P and its periphery will be described with reference to FIG. FIG. 6 is an enlarged schematic cross-sectional view of the wire bonding portion and its periphery in FIG.

[0040] 6, the insulating layer 23 includes a first insulating film 231 and a second insulating film 232. The second insulating film 232 is stacked on the first insulating film 231. The first insulating film 231 is used as a passivation film to prevent moisture and other contaminants from penetrating into the semiconductor device 10. The first insulating film 231 is disposed across the source electrode peripheral portion 22E of the source electrode 22 and the device surface 11. The source electrode peripheral portion 22E of the source electrode 22 can be defined by the outer periphery of the source electrode 22, including the side surfaces of the source electrode 22, in a planar view. That is, the first insulating film 231 is disposed across the outer periphery of the surface of the source electrode 22, the side surfaces of the source electrode 22, and the device surface 11. The first insulating film 231 contains, for example, a nitride. In one example, the first insulating film 231 is made of a material containing silicon nitride (SiN). The thickness of the first insulating film 231 is, for example, 0.1 μm or more and 2 μm or less. Note that other insulating materials, such as silicon oxynitride (SiON), may also be used as the constituent material of the first insulating film 231.

[0041] The second insulating film 232 covers the entire first insulating film 231. In addition, in the first embodiment, the second insulating film 232 covers a part of the source electrode 22 and a part of the element surface 11. In the first embodiment, the second insulating film 232 shown in FIG. 6 forms the insulating layer outer surface 23C and the insulating layer inner surface 23D of the insulating layer 23. In other words, the first insulating film 231 is not exposed from the second insulating film 232. The insulating layer inner surface 23D of the insulating layer 23 forms the source opening 23B of the insulating layer 23.

[0042] The second insulating film 232 is made of, for example, a resin material. In one example, the second insulating film 232 may be made of polyimide resin. The thickness of the second insulating film 232 is thicker than the thickness of the first insulating film 231. In one example, the thickness of the second insulating film 232 is 5 to 50 times the thickness of the first insulating film 231. The thickness of the second insulating film 232 is, for example, 5 μm to 10 μm. The material of the second insulating film 232 is not particularly limited and can be changed as desired. In one example, the second insulating film 232 may be made of an inorganic insulating material such as SiN or silicon oxide (SiO2).

[0043] The semiconductor device 1 includes a conductive laminated portion 200 laminated on the source pad 22P. In the example shown in Fig. 6, the conductive laminated portion 200 is disposed over the source pad 22P and the insulating layer 23. The conductive laminated portion 200 has a structure in which a plurality of conductive layers are laminated.

[0044] The conductive stack 200 includes a first conductive layer 201 and a second conductive layer 202 . The first conductive layer 201 is stacked on the source pad 22P. In the first embodiment, the first conductive layer 201 is disposed over the source pad 22P and the insulating layer 23. More specifically, the first conductive layer 201 is disposed over the entire surface of the source pad 22P in a plan view. The first conductive layer 201 is disposed on the insulating layer inner surface 23D of the insulating layer 23. In one example, the first conductive layer 201 is disposed over the entire surface of the insulating layer inner surface 23D of the insulating layer 23. The first conductive layer 201 includes a first edge portion 201A including an outer periphery of the first conductive layer 201. The first edge portion 201A is located between the insulating layer outer surface 23C and the insulating layer inner surface 23D of the insulating layer 23. The first conductive layer 201 is made of a material containing, for example, titanium (Ti).

[0045] The second conductive layer 202 is stacked on the first conductive layer 201. In plan view, the second conductive layer 202 covers the source pad 22P and a portion of the insulating layer 23, similar to the first conductive layer 201. The second conductive layer 202 includes a second edge portion 202A that includes the outer periphery of the second conductive layer 202. In plan view, the second edge portion 202A is located between the insulating layer outer surface 23C and the insulating layer inner surface 23D of the insulating layer 23.

[0046] The second conductive layer 202 is made of a material harder than the material that makes up the source pad 22P. The second conductive layer 202 is also made of a material harder than the material that makes up the wire 142. Here, "the second conductive layer 202 is made of a material harder than the material that makes up the source pad 22P" means that the Vickers hardness of the second conductive layer 202 is greater than the Vickers hardness of the source pad 22P. Similarly, "the second conductive layer 202 is made of a material harder than the material that makes up the wire 142" means that the Vickers hardness of the second conductive layer 202 is greater than the Vickers hardness of the wire 142.

[0047] In the first embodiment, the material constituting the source pad 22P and the material constituting the wire 142 are both Al (with a Vickers hardness of 20 Hv or more and 40 Hv or less), and therefore the second conductive layer 202 is made of a material with a Vickers hardness of more than 40 Hv. The Vickers hardness can be measured by a Vickers test.

[0048] The second conductive layer 202 is made of a material harder than the first conductive layer 201. Here, "the second conductive layer 202 is made of a material harder than the first conductive layer 201" means that the Vickers hardness of the second conductive layer 202 is greater than the Vickers hardness of the first conductive layer 201. When the first conductive layer 201 is made of Ti, the Vickers hardness is 100 Hv or more and 200 Hv or less. Therefore, the second conductive layer 202 is made of a material whose Vickers hardness is greater than 200 Hv. In one example, the second conductive layer 202 is made of a material containing nickel (Ni). When the second conductive layer 202 is made of Ni, the Vickers hardness is 400 Hv or more and 500 Hv or less.

[0049] The thickness of the first conductive layer 201 is, for example, not less than 0.1 μm and not more than 0.5 μm. The thickness of the second conductive layer 202 is, for example, not less than 0.1 μm and not more than 0.5 μm. Here, the thickness of the first conductive layer 201 can be defined, for example, by the thickness (dimension in the Z direction) of the portion of the first conductive layer 201 that covers the source pad 22P. The thickness of the second conductive layer 202 can be defined, for example, by the thickness (dimension in the Z direction) of the portion of the second conductive layer 202 that covers the source pad 22P.

[0050] 6, the thickness of the first conductive layer 201 is equal to the thickness of the second conductive layer 202. The thicknesses of the first conductive layer 201 and the second conductive layer 202 can each be changed as desired. In one example, the thickness of the second conductive layer 202 may be thicker than the thickness of the first conductive layer 201. In another example, the thickness of the first conductive layer 201 may be thicker than the thickness of the second conductive layer 202.

[0051] As shown in FIG. 6 , the first insulating film 231 is covered with the second insulating film 232, and therefore the first conductive layer 201 and the first insulating film 231 are disposed at a distance from each other on the surface of the source electrode peripheral portion 22E of the source electrode 22. The first insulating film 231 is also disposed at a distance from the insulating layer outer surface 23C of the second insulating film 232 on the element surface 11. For example, if the first insulating film 231 is made of SiN and the second insulating film 232 is made of polyimide resin, the width of the second insulating film 232 (the dimension in the Y direction in FIG. 6 ) is smaller than the width of the first insulating film 231 (the dimension in the Y direction in FIG. 6 ). This offset is provided in advance between the end positions of the second insulating film 232 and the first insulating film 231, taking into account shrinkage of the polyimide resin during the manufacturing process. This prevents the end of the first insulating film 231 from being exposed from the second insulating film 232 even in the final state after the manufacturing process is completed.

[0052] The second conductive layer 202 is exposed on the source pad 22P. The wire 142 is bonded to the second conductive layer 202. In other words, the second conductive layer 202 is connected to the wire 142 both physically and electrically.

[0053] [Method of manufacturing a semiconductor device] A method for manufacturing the semiconductor device 1 according to the first embodiment will be described with reference to Figures 7 to 12. Figures 7 to 12 each show a schematic cross-sectional structure for explaining the manufacturing process of an exemplary semiconductor device 1 according to the first embodiment.

[0054] 7, the method for manufacturing the semiconductor device 1 includes preparing a semiconductor wafer 800. The semiconductor wafer 800 includes a wafer front surface 801 and a wafer back surface 802 opposite to the wafer front surface 801.

[0055] The semiconductor wafer 800 may be, for example, a Si wafer. The semiconductor wafer 800 includes some of the components of the multiple semiconductor elements 10. More specifically, electrodes, insulating layers, etc. have not yet been formed on the wafer surface 801 side of the semiconductor wafer 800. In other words, the semiconductor wafer 800 is one on which the electrodes, insulating layers, etc. of each semiconductor element 10 have not yet been formed. The thickness of the semiconductor wafer 800 is, for example, 725 μm (8-inch wafer).

[0056] As shown in FIGS. 8 and 9, the manufacturing method of the semiconductor device 1 includes forming the source electrode 22. In this step, as shown in FIG. 8, a source electrode material 22M for forming the source electrode 22 (see FIG. 9) is first deposited by sputtering on the wafer surface 801 of the semiconductor wafer 800, for example, AlCu (Cu content: 0.5%). The AlCu film has a thickness of, for example, 4 μm to 5 μm. Then, a resist 250 having a predetermined pattern corresponding to the area and shape required for the source pad 22P is disposed. When a positive resist is used, a photomask (not shown) is created so that areas other than the pad position are exposed, and then the resist 250 is obtained by exposure and development using lithography. Next, the portion of the source electrode material 22M that is not covered by the resist 250 is removed by dry etching using, for example, a chlorine-based gas. As a result, the source electrode 22 is formed as shown in FIG. 9. The gate electrode 21 (see FIG. 4) is formed by a similar process.

[0057] As shown in FIGS. 9 and 10 , the manufacturing method of the semiconductor device 1 includes forming a first insulating film 231. In this step, first, as shown in FIG. 9 , a first insulating film 810 is deposited on a portion of the wafer surface 801 and the source electrode 22. The thickness of the first insulating film 810 is, for example, 0.1 μm or more and 2 μm or less. The first insulating film 810 can be formed by chemical vapor deposition or the like. Next, a resist 820 is disposed in a region spanning the source electrode peripheral portion 22E of the source electrode 22 and the wafer surface 801. Then, the portion of the first insulating film 810 exposed from the resist 820 is removed by dry etching using, for example, a fluorocarbon gas. As a result, the first insulating film 231 shown in FIG. 10 is formed.

[0058] As shown in FIGS. 10 and 11, the manufacturing method of the semiconductor device 1 includes forming a second insulating film 232. In this step, first, as shown in FIG. 10, a second insulating film 830 is formed by applying an insulating resin to the source electrode 22, the first insulating film 231, and a portion of the element surface 11. The thickness of the second insulating film 830 is, for example, 5 μm or more and 10 μm or less. The second insulating film 830 is made of, for example, a polyimide resin. The polyimide resin may be photosensitive. When a negative polyimide is used as the photosensitive polyimide resin, a photomask (not shown) is first prepared so that the region covering the entire first insulating film 231 and portions of the source electrode 22 and the element surface 11 is exposed. Next, the second insulating film 830 of the source pad 22P is removed through lithographic exposure, development, and baking. This forms the second insulating film 232 shown in FIG. 11. Then, the insulating layer 23 including the first insulating film 231 and the second insulating film 232 is formed.

[0059] 11 and 12, the method for manufacturing the semiconductor device 1 includes forming a conductive laminated portion 200. Forming the conductive laminated portion 200 includes forming a first conductive layer 201 and forming a second conductive layer 202.

[0060] As shown in FIG. 11 , when forming the first conductive layer 201, a Ti film 840 is deposited by, for example, sputtering Ti. The Ti film 840 is formed over the entire semiconductor element 10 in a planar view. When forming the second conductive layer 202, a Ni film 850 is deposited on the Ti film 840 by, for example, sputtering Ni. The Ni film 850 is formed over the entire Ti film 840 in a planar view. The thickness of the Ti film 840 is, for example, not less than 0.1 μm and not more than 0.5 μm. The thickness of the Ni film 850 is, for example, not less than 0.1 μm and not more than 0.5 μm.

[0061] Next, a resist 860 is placed in accordance with the portions of the Ti film 840 and the Ni film 850 that are to remain. The resist 860 is formed so that a resist side surface 861 thereof is located between the insulating layer outer surface 23C and the insulating layer inner surface 23D of the insulating layer 23 (second insulating film 232) in a plan view. Next, the portions of the Ti film 840 and the Ni film 850 that are exposed from the resist 860 are removed by etching or the like. As a result, the first conductive layer 201 and the second conductive layer 202 shown in FIG. 12 are formed.

[0062] The partial removal of Ni film 850 and the partial removal of Ti film 840 may be performed by separately arranging resists and then separately etching, etc. This allows the position of first edge portion 201A of first conductive layer 201 and the position of second edge portion 202A of second conductive layer 202 to be set separately. The partial removal of Ti film 840 may also be performed before the formation of Ni film 850.

[0063] As shown in FIG. 12, the method for manufacturing the semiconductor device 1 includes grinding the back surface 802 of the semiconductor wafer 800 to obtain the element back surface 12. In this process, the wafer back surface 802 of the semiconductor wafer 800 is ground so that the thickness of the semiconductor wafer 800 is, for example, from 725 μm to 100 μm or less. The semiconductor wafer 800 is thinned by, for example, back grinding. In one example, the semiconductor wafer 800 is thinned by back grinding until the thickness of the semiconductor wafer 800 is 60 μm. This results in the device back surface 12.

[0064] Next, although not shown, the manufacturing method of the semiconductor device 1 includes a step of singulating. In this step, the semiconductor elements 10 are cut out as individual pieces from the semiconductor wafer 800 by dicing.

[0065] Next, although not shown, the manufacturing method of the semiconductor device 1 includes fixing the individual semiconductor elements 10 to the die pad 101 (see FIG. 3). More specifically, a conductive bonding material 104 is placed on the bottom surface 103A of the recess 103 of the die pad 101 (see FIG. 5). Next, the semiconductor element 10 is placed on the conductive bonding material 104. The conductive bonding material 104 is melted by a reflow process and then solidified. As a result, the semiconductor element 10 is bonded to the bottom surface 103A of the recess 103 of the die pad 101 by the conductive bonding material 104. As a result, the semiconductor element 10 is electrically connected to the substrate 100. In the first embodiment, the drain electrode of the semiconductor element 10 is electrically connected to the substrate 100.

[0066] As shown in FIG. 12 , the manufacturing method of the semiconductor device 1 includes forming the wire 142. This step includes bonding the wire 142 to the second conductive layer 202 and bonding the wire 142 to the first terminal 110. In the step of bonding the wire 142 to the second conductive layer 202, ultrasonic waves and a load are applied to the wire 142 while the wire 142 and the second conductive layer 202 are in contact with each other. This bonds the wire 142 to the second conductive layer 202. Similarly, in the step of bonding the wire 142 to the first terminal 110, ultrasonic waves and a load are applied to the wire 142 while the wire 142 and the first terminal 110 are in contact with each other. This bonds the wire 142 to the first terminal 110. Although not shown, the manufacturing method of the semiconductor device 1 also includes forming the wire 141. This step includes bonding the wire 141 to the gate pad 21P and bonding the wire 141 to the second terminal 120. Although not shown, the method for manufacturing the semiconductor device 1 also includes forming the sealing resin 130. Through the above steps, the semiconductor device 1 is manufactured.

[0067] [Operation of the first embodiment] The operation of the semiconductor device 1 of the first embodiment will be described with reference to FIGS. Here, as a comparative example to the first embodiment, a configuration in which the conductive laminated layer 200 is omitted, i.e., a configuration in which the wire 142 is directly bonded to the source pad 22P of the semiconductor element 10, will be described. FIGS. 13 and 14 show, as a comparative example, a process in which the wire 142 is bonded to the source pad 22P of the semiconductor element 10. FIG. 15 shows, as a comparative example, a state in which a tensile test is performed on the wire 142 bonded to the source pad 22P. In contrast, FIG. 16 shows, as the first embodiment, a process in which the wire 142 is bonded to the conductive laminated layer 200. FIG. 17 shows, as the first embodiment, a state in which a tensile test is performed on the wire 142 bonded to the conductive laminated layer 200 on the source pad 22P.

[0068] As shown in FIG. 13, in the process of bonding the wire 142 to the source pad 22P, first, with the tip of the wire 142 in contact with the source pad 22P, a load is applied to the tip of the wire 142 while ultrasonic waves are applied. As a result, a bond 300 is formed in the wire 142, as shown in FIG. 14. The load and ultrasonic waves physically destroy any native oxide film or the like formed at the contact point between the surface of the source pad 22P and the surface of the wire 142. As a result, the wire 142 and the source pad 22P are brought into contact with each other as pure metal layers free of oxide films or the like, and an adhesion nucleus is formed between the bond 300 and the source pad 22P. As a result, the bond 300 of the wire 142 is bonded to the source pad 22P.

[0069] Here, if the mechanical strength of the source pad 22P and the semiconductor element 10 is insufficient, a damaged layer 310 is formed in the contact portion of the source pad 22P with the junction 300, as shown in Fig. 14. The damaged layer 310 is a weakened portion of the source pad 22P.

[0070] 15, when a tensile test is performed on the wire 142, the wire 142, the bonding portion 300, and a portion of the damaged layer 310 come off the source pad 22P as a unit, leaving a crater-like depression in the source pad 22P. In other words, cratering occurs. In particular, when the thickness of the semiconductor element 10 is reduced from the viewpoint of heat dissipation, the mechanical strength of the semiconductor element 10 is likely to decrease, making the above-mentioned cratering more likely to occur. In this way, when the wire 142 is bonded to the source pad 22P, the wire 142 may come off the source pad 22P due to the load or the like.

[0071] In this regard, in the semiconductor device 1 of the first embodiment, as shown in FIG. 16, the first conductive layer 201 and the second conductive layer 202 are disposed on the surface side of the source pad 22P. This improves the mechanical strength of the laminated body formed of the second conductive layer 202, the first conductive layer 201, the source pad 22P, and the semiconductor element 10 compared to the comparative example. In addition, the second conductive layer 202 is made of a material containing Ni (Vickers hardness: 400 Hv or more and 500 Hv or less), which has a higher Vickers hardness than the first conductive layer 201. Therefore, even if ultrasonic waves are applied when the wire 142 is bonded to the second conductive layer 202, the formation of a damaged layer 310 in the second conductive layer 202 can be suppressed. This can suppress the occurrence of cratering.

[0072] [Effects of the first embodiment] (1-1) The semiconductor device 1 includes a semiconductor element 10 having an element front surface 11 and an element back surface 12 opposite to the element front surface 11, a source pad 22P disposed on the element front surface 11, a first conductive layer 201 stacked on the source pad 22P, a second conductive layer 202 stacked on the first conductive layer 201, containing Ni and at least a portion of which is exposed, and a wire 142 bonded to the second conductive layer 202 and made of Al. The semiconductor element 10 has a thickness of 100 μm or less, and the second conductive layer 202 is made of a material harder than the first conductive layer 201.

[0073] According to this configuration, the first conductive layer 201 and the second conductive layer 202 are stacked on the surface side of the source pad 22P, and the second conductive layer 202 is harder than the first conductive layer 201, which improves the mechanical strength of the stack of the semiconductor element 10, the first conductive layer 201, and the second conductive layer 202 against wire bonding. More specifically, Ni (Vickers hardness: 400 Hv or more and 500 Hv or less) is used as the second conductive layer 202.

[0074] In particular, the second conductive layer 202 is configured to contain Ni. Ni and Al have affinity when bonded. This can improve the bonding strength between the second conductive layer 202 and the wire 142. This can prevent cratering from occurring and also prevent the wire 142 from coming off the second conductive layer 202.

[0075] Furthermore, if the thickness of the semiconductor element 10 is reduced to 100 μm or less, the mechanical strength of the source pad 22P and the semiconductor element 10 may be insufficient. Even in this case, the second conductive layer 202 and the first conductive layer 201 are provided on the source pad 22P, so that the mechanical strength of the laminate of the semiconductor element 10, the first conductive layer 201, and the second conductive layer 202 can be ensured. This makes it possible to suppress the generation of a damaged layer 310 on the surface of the second conductive layer 202. Therefore, even when a tensile test is performed as shown in FIG. 17, the bonding strength between the wire 142 and the second conductive layer 202 against a force applied in a direction pulling the wire 142 can be improved.

[0076] (1-2) The first conductive layer 201 is made of a material containing Ti. According to this configuration, the first conductive layer 201 containing Ti functions as an adhesion layer that adheres the second conductive layer 202 containing Ni to the source pad 22P, thereby preventing the second conductive layer 202 from peeling off from the source pad 22P, thereby preventing a decrease in reliability.

[0077] (1-3) The first conductive layer 201 containing Ti can suppress the growth of Al hillocks in the source pad 22P containing Al. Hillocks are a phenomenon in which compressive stress acts inside Al when the temperature rises, causing protrusions on the surface of the source pad 22P. In other words, covering the surface of the source pad 22P with the first conductive layer 201 made of Ti can suppress the movement of Al atoms in the source pad 22P, thereby suppressing the growth of hillocks. This can suppress a decrease in reliability, such as the occurrence of cracks in the insulating layer 23 covering the source pad 22P.

[0078] (1-4) The thickness of the second conductive layer 202 is greater than the thickness of the first conductive layer 201. According to this configuration, second conductive layer 202 is harder than first conductive layer 201, which improves the mechanical strength of the laminate of semiconductor element 10, first conductive layer 201, and second conductive layer 202. This makes it possible to suppress the generation of damaged layer 310 on the surface of second conductive layer 202, thereby suppressing the occurrence of cratering.

[0079] In addition, when an adhesion nucleus is generated between the bonded portion 300 of the wire 142 and the second conductive layer 202, it is possible to prevent all of the second conductive layer 202 from reacting with the wire 142. This ensures that the remaining amount of the second conductive layer 202 that is to undergo the adhesion reaction is secured, stabilizing the reaction.

[0080] (1-5) The diameter of the wire 142 is greater than 400 μm. This configuration can prevent excessive temperature rise of the wire 142 even when a large current is supplied to the wire 142. In addition, the inductance of the wire 142 can be reduced.

[0081] For example, when the semiconductor device 1 is used in a power supply circuit such as an inverter, a large current must be passed through it. In this case, it is advisable to increase the diameter of the wire 142 bonded to the source pad 22P of the semiconductor element 10 to prevent the current density per unit cross-sectional area of ​​the wire 142 from becoming too high. In this case, it is necessary for the thick tip of the wire 142 to be physically and electrically connected to the second conductive layer 202. In other words, compared to when a thin wire is used, it is necessary to apply high-power ultrasonic waves to the tip of the wire 142 and perform wire bonding under conditions of a large load. This makes cratering more likely to occur.

[0082] In contrast to this, according to the first embodiment, as described above, the occurrence of cratering can be suppressed by providing the first conductive layer 201 and the second conductive layer 202 on the source pad 22P and making the second conductive layer 202 harder than the first conductive layer 201. Therefore, the occurrence of cratering can be suppressed while allowing a large current to flow.

[0083] (1-6) The semiconductor element 10 has a thickness of 60 μm or less. While this can improve the heat dissipation of the semiconductor element 10, it also tends to reduce the mechanical strength of the semiconductor element 10, making cratering more likely to occur. In this regard, in the first embodiment, as described above, the first conductive layer 201 and the second conductive layer 202 are provided on the source pad 22P, and the second conductive layer 202 is made harder than the first conductive layer 201. This makes it possible to suppress the occurrence of cratering even when the thickness of the semiconductor element 10 is 60 μm or less.

[0084] (1-7) The die pad 101 is made of a material containing Cu. This configuration can improve the heat dissipation performance from the semiconductor element 10 to the die pad 101.

[0085] Second Embodiment 18 to 22, the semiconductor device 1 of the second embodiment will be described. The semiconductor device 1 of the second embodiment differs from the semiconductor device 1 of the first embodiment mainly in that an electrode stack 400 is added. Below, differences from the first embodiment will be mainly described, and components common to the first embodiment will be assigned the same reference numerals and their description will be omitted.

[0086] [Configuration of semiconductor device] 18, the semiconductor device 1 according to the second embodiment includes an electrode stack 400 disposed on the element back surface 12 of the semiconductor element 10. In one example, the electrode stack 400 is disposed over the entire surface of the element back surface 12.

[0087] In the second embodiment, the electrode stack 400 is composed of a third conductive layer 401 arranged on the rear surface 12 of the element, a fourth conductive layer 402 stacked on the third conductive layer 401, a fifth conductive layer 403 stacked on the fourth conductive layer 402, and a sixth conductive layer 404 stacked on the fifth conductive layer 403.

[0088] The third conductive layer 401 is made of a material containing AlSi. In one example, the third conductive layer 401 is made of an AlSi layer. The fourth conductive layer 402 is made of a material containing Ti. In one example, the fourth conductive layer 402 is made of a Ti layer. The fifth conductive layer 403 is made of a material containing Ni. In one example, the fifth conductive layer 403 is made of a Ni layer. The sixth conductive layer 404 is made of a material containing Au. In one example, the sixth conductive layer 404 is made of an Au layer.

[0089] The thickness of the third conductive layer 401 can be, for example, 0.1 μm or more and 0.5 μm or less. The thickness of the fourth conductive layer 402 can be, for example, 0.05 μm or more and 0.4 μm or less. The thickness of the fifth conductive layer 403 can be, for example, 0.2 μm or more and 0.8 μm or less. The thickness of the sixth conductive layer 404 can be, for example, 0.01 μm or more and 0.1 μm or less. Here, the thicknesses of the third conductive layer 401, the fourth conductive layer 402, the fifth conductive layer 403, and the sixth conductive layer 404 can be defined by the thickness (dimension in the Z direction) of the portion of each film covering the element rear surface 12.

[0090] In one example, the thickness of the third conductive layer 401 is thicker than the thickness of the fourth conductive layer 402. The thickness of the third conductive layer 401 is thinner than the thickness of the fifth conductive layer 403. The thickness of the third conductive layer 401 is thicker than the thickness of the sixth conductive layer 404. Therefore, the thickness of the fifth conductive layer 403 is thicker than both the thickness of the fourth conductive layer 402 and the thickness of the sixth conductive layer 404. The thickness of the fourth conductive layer 402 is thicker than the thickness of the sixth conductive layer 404. In the second embodiment, the thickness of the third conductive layer 401 is 0.2 μm. The thickness of the fourth conductive layer 402 is 0.125 μm. The thickness of the fifth conductive layer 403 is 0.4 μm. The thickness of the sixth conductive layer 404 is 0.05 μm. The thicknesses of the third conductive layer 401, the fourth conductive layer 402, the fifth conductive layer 403, and the sixth conductive layer 404 can each be changed as desired.

[0091] [Method of manufacturing a semiconductor device] A manufacturing method of the semiconductor device 1 according to the second embodiment will be described with reference to Figures 19 and 20. Note that Figures 19 and 20 mainly describe a manufacturing method related to the electrode stack 400 of the semiconductor device 1 according to the second embodiment. Both Figures 19 and 20 show schematic cross-sectional structures for explaining the manufacturing process of an exemplary semiconductor device 1 according to the second embodiment.

[0092] 19, the manufacturing method of the semiconductor device 1 includes forming an electrode stack 400 on the element back surface 12. That is, the manufacturing step shown in Fig. 19 is performed after grinding the wafer back surface 802 of the semiconductor wafer 800 shown in Fig. 12 to obtain the element back surface 12 in the manufacturing method of the semiconductor device 1 of the first embodiment.

[0093] The electrode stack 400 includes third to sixth conductive layers 401 to 404, which are conductive layers that constitute the electrode stack 400. The third to sixth conductive layers 401 to 404 are deposited on the back surface 12 of the element by sputtering. Specifically, the step of depositing the electrode stack 400 includes forming a third conductive layer 401 on the back surface 12 of the element, forming a fourth conductive layer 402 on the third conductive layer 401, forming a fifth conductive layer 403 on the fourth conductive layer 402, and forming a sixth conductive layer 404 on the fifth conductive layer 403.

[0094] In the step of forming the third conductive layer 401 on the element rear surface 12, for example, AlSi (Si content: 3%) is sputtered to deposit the third conductive layer 401. The third conductive layer 401 is formed over the entire element rear surface 12 in plan view.

[0095] Subsequently, the step of depositing the electrode stack 400 includes forming a fourth conductive layer 402 on the third conductive layer 401. In this step, the fourth conductive layer 402 is deposited on the third conductive layer 401 by sputtering, for example, Ti onto the third conductive layer 401. The fourth conductive layer 402 is formed over the entire third conductive layer 401 in a plan view.

[0096] Subsequently, the step of depositing the electrode stack 400 includes forming a fifth conductive layer 403 on the fourth conductive layer 402. In this step, the fifth conductive layer 403 is deposited on the fourth conductive layer 402 by sputtering, for example, Ni onto the fourth conductive layer 402. The fifth conductive layer 403 is formed over the entire fourth conductive layer 402 in a plan view.

[0097] Subsequently, the step of depositing the electrode stack 400 includes forming a sixth conductive layer 404 on the fifth conductive layer 403. In this step, the sixth conductive layer 404 is deposited on the fifth conductive layer 403 by sputtering, for example, Au onto the fifth conductive layer 403. The sixth conductive layer 404 is formed over the entire fifth conductive layer 403 in a plan view. Through the above steps, the electrode stack 400 is formed.

[0098] Next, the manufacturing method of the semiconductor device 1 includes a step of singulating, in which the semiconductor elements 10 are cut out as individual pieces from the semiconductor wafer 800 by dicing. As shown in FIG. 20 , the manufacturing method of the semiconductor device 1 includes fixing the semiconductor element 10 to the die pad 101. More specifically, a conductive bonding material 104 is placed on the bottom surface 103A of the recess 103 of the die pad 101. The conductive bonding material 104 is, for example, solder. Next, the semiconductor element 10 is placed on the conductive bonding material 104. The conductive bonding material 104 is then melted by a reflow process and then solidified. As a result, the electrode stack 400 on the element back surface 12 side of the semiconductor element 10 is bonded to the bottom surface 103A of the recess 103 of the die pad 101 by the conductive bonding material 104. As a result, the semiconductor element 10 is electrically connected to the substrate 100.

[0099] Next, the manufacturing method of the semiconductor device 1 includes forming the wire 142 and forming the wire 141. These steps are the same as those in the first embodiment. Then, although not shown, the manufacturing method of the semiconductor device 1 also includes forming the sealing resin 130. Through the above steps, the semiconductor device 1 is manufactured.

[0100] [Operation of the second embodiment] Next, the operation of the semiconductor device 1 of the second embodiment will be described. As a comparative example to the second embodiment, a configuration will be described in which an electrode stack 400A, which is the electrode stack 400 shown in FIG. 18 without the third conductive layer 401, is bonded to a die pad 101 by a conductive bonding material 104. FIG. 21 shows a process in which a wire 142 is bonded to a conductive laminated portion 200 in the comparative example. FIG. 22 shows a state in which a tensile test is performed on the wire 142 bonded to a source pad 22P.

[0101] As shown in FIGS. 21 and 22, in the comparative example, voids 340 may occur in the conductive bonding material 104 during the reflow process performed to fix the semiconductor element 10 to the die pad 101.

[0102] 21, the conductive bonding material 104 that fixes the sixth conductive layer 404 and the die pad 101 has a portion where a void 340 exists and a portion where no void 340 exists. In the portion where no void 340 exists, the space between the die pad 101 and the sixth conductive layer 404 in the Z direction is filled with the conductive bonding material 104 without any gaps.

[0103] When ultrasonic waves are applied to a portion where no void 340 exists, the ultrasonic waves are transmitted in the following order: second conductive layer 202, first conductive layer 201, semiconductor element 10, fourth conductive layer 402, fifth conductive layer 403, sixth conductive layer 404, conductive bonding material 104, and die pad 101.

[0104] On the other hand, when ultrasonic waves are applied to a portion where a void 340 exists, the ultrasonic waves applied to the source pad 22P from the wire 142 are less likely to be transmitted to the die pad 101 due to the void 340. In this case, the die pad 101 cannot absorb the ultrasonic waves. Therefore, a damaged layer 310 is likely to be formed in the portion of the second conductive layer 202 that is in contact with the bonding portion 300 of the wire 142. Here, the damaged layer 310 is a weakened portion of the second conductive layer 202.

[0105] When a tensile test is performed to pull the wire 142, the joint 300 of the wire 142 and a part of the damaged layer 310 come off together from the second conductive layer 202, as shown in Figure 22. As a result, cratering occurs.

[0106] In this regard, the present inventors have found that when the third conductive layer 401 including an AlSi film is disposed between the element back surface 12 and the fourth conductive layer 402, fewer voids 340 are generated inside the conductive bonding material 104 during reflow bonding to bond the semiconductor element 10 to the die pad 101. Specifically, the present inventors have confirmed that providing an AlSi film as the third conductive layer 401 on the element back surface 12 reduces the void generation rate by 45.2% compared to the comparative example. Based on this finding, in the semiconductor device 1 of the second embodiment, the third conductive layer 401 including an AlSi film is disposed between the element back surface 12 and the fourth conductive layer 402. This reduces the generation of voids 340, thereby suppressing the occurrence of cratering.

[0107] [Effects of the second embodiment] According to the semiconductor device 1 of the second embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.

[0108] (2-1) The semiconductor device 1 includes a semiconductor element 10 having an element front surface 11 and an element back surface 12 opposite to the element front surface 11, a source pad 22P disposed on the element front surface 11, a first conductive layer 201 laminated on the source pad 22P, a second conductive layer 202 laminated on the first conductive layer 201, containing Ni and at least a portion of which is exposed, a wire 142 bonded to the second conductive layer 202 and made of Al, and an electrode laminate 400 disposed on the element back surface 12. The semiconductor element 10 has a thickness of 100 μm or less, and the second conductive layer 202 is made of a material harder than the first conductive layer 201. The electrode stack 400 includes a third conductive layer 401 containing AlSi arranged on the rear surface 12 of the element, a fourth conductive layer 402 containing Ti stacked on the third conductive layer 401, a fifth conductive layer 403 containing Ni stacked on the fourth conductive layer 402, and a sixth conductive layer 404 containing Au stacked on the fifth conductive layer 403.

[0109] According to this configuration, by disposing the third conductive layer 401 containing AlSi on the back surface 12 of the semiconductor element 10, it is possible to reduce the occurrence of voids 340 inside the conductive bonding material 104 during reflow, thereby suppressing the occurrence of cratering.

[0110] In addition, by using a film containing Au for the sixth conductive layer 404, it is possible to suppress oxidation of the film containing Ni, which is the fifth conductive layer 403. Therefore, the bond between the sixth conductive layer 404 and the conductive bonding material 104 is stabilized.

[0111] (2-2) The semiconductor element 10 is made of a material containing Si. Donor impurities such as phosphorus and arsenic are added at a concentration of, for example, 1×10 19 cm -3 5x10 or more 20 cm -3 Doped with the following concentration + layer, or acceptor impurities such as boron, for example, 1×10 19 cm -3 5x10 or more 20 cm -3 Doped p at the following concentrations + The layer is provided on the back surface 12 of the semiconductor device 10 .

[0112] This configuration makes it possible to achieve an ohmic junction between AlSi-Si or Ti-Si. That is, an ohmic junction can be formed between the electrode stack 400, which uses a film containing AlSi for the third conductive layer 401 and a film containing Ti for the fourth conductive layer 402, and the back surface 12 of the semiconductor element 10. When the semiconductor element 10 is a MOSFET, the back surface 12 of the element serves as a drain electrode.

[0113] In addition, AlSi (Si content: 3%) contained in the third conductive layer 401 can suppress the generation of alloy spikes and Si nodules at the interface with the Si semiconductor compared to simple Al, thereby stabilizing the bond between the back surface 12 of the semiconductor element 10 and the electrode stack 400.

[0114] In addition, Ti contained in the fourth conductive layer 402 forms Ti silicide with Si, thereby stabilizing the bond between the back surface 12 of the semiconductor element 10 and the electrode stack 400.

[0115] (2-3) The die pad 101 is made of a material containing Cu. The electrode stack 400 includes a fourth conductive layer 402 containing Ti and a fifth conductive layer 403 containing Ni. According to this configuration, by using a film containing Ti for the fourth conductive layer 402 and a film containing Ni for the fifth conductive layer 403, it is possible to suppress the diffusion of Cu contained in the die pad 101 into the semiconductor element 10.

[0116] (2-4) The conductive bonding material 104 contains Sn. This configuration allows the Sn contained in the conductive bonding material 104 to react with the Ni contained in the fifth conductive layer 403. As a result, the bonding between the electrode stack 400 and the conductive bonding material 104 becomes stable.

[0117] Third Embodiment A semiconductor device 1 of the third embodiment will be described with reference to Fig. 23. The semiconductor device 1 of the third embodiment differs from the semiconductor device 1 of the second embodiment mainly in that the conductive laminated portion 200 is not disposed on the surface of the source pad 22P. Below, differences from the second embodiment will be mainly described, and components common to the second embodiment will be assigned the same reference numerals and their description will be omitted.

[0118] As shown in FIG. 23 , the first insulating film 231 is covered with the second insulating film 232, and therefore the source opening 23B and the first insulating film 231 are disposed apart on the surface of the source electrode peripheral portion 22E of the source electrode 22. The first insulating film 231 is also disposed apart from the insulating layer outer surface 23C of the second insulating film 232 on the element surface 11. For example, if the first insulating film 231 is made of SiN and the second insulating film 232 is made of polyimide resin, the width dimension (dimension in the Y direction in FIG. 23 ) of the second insulating film 232 is smaller than the width dimension (dimension in the Y direction in FIG. 23 ) of the first insulating film 231. This offset is provided in advance between the end positions of the second insulating film 232 and the first insulating film 231, taking into account shrinkage of the polyimide resin during the manufacturing process. This prevents the end of the first insulating film 231 from being exposed from the second insulating film 232 even in the final state after the manufacturing process is completed.

[0119] The source electrode 22 is exposed because the conductive laminated portion 200 is omitted. Therefore, the wire 142 is bonded to the source electrode 22 (source pad 22P). In one example, the source electrode 22 is bonded to the wire 142 by applying ultrasonic waves and a load via the wire 142. As a result, the source electrode 22 is physically and electrically connected to the wire 142. According to the third embodiment, the same effects as those of (2-1) to (2-4) of the second embodiment can be obtained.

[0120] <Example of change> Each embodiment can be modified as follows: Each embodiment and the following modifications can be combined with each other to the extent that no technical contradiction occurs.

[0121] In the first and second embodiments, the positional relationship between the conductive laminated portion 200 and the first insulating film 231 and the second insulating film 232 can be changed as desired. Fig. 24 shows an enlarged cross-sectional structure of the source pad 22P and its surrounding area in the semiconductor device 1 of a modified example.

[0122] 24, the first conductive layer 201 is provided over the entire surface of the source pad 22P in plan view. The second conductive layer 202 is provided over the entire surface of the first conductive layer 201 in plan view.

[0123] The first insulating film 231 covers the side surfaces of the source pad 22P, the side surfaces of the first conductive layer 201, and the side surfaces of the second conductive layer 202, and also covers part of the surface of the second conductive layer 202. The second insulating film 232 covers the first insulating film 231, and also covers part of the element surface 11 and part of the surface of the second conductive layer 202.

[0124] In the manufacturing method of the semiconductor device 1 shown in FIG. 24, first, AlCu (Cu content: 0.5%) is sputtered onto the element surface 11 of the semiconductor element 10 as a material for forming the source electrode 22 (see FIG. 8). Next, a first conductive layer 201 and then a second conductive layer 202 are successively sputtered onto the AlCu. This results in, for example, a stacked film of the source pad 22P (AlCu), the first conductive layer 201 (Ti), and the second conductive layer 202 (Ni). Then, a resist 250 (see FIG. 8) having a predetermined pattern corresponding to the area and shape required for the source pad 22P is arranged. Next, portions of the source pad 22P, the first conductive layer 201, and the second conductive layer 202 not covered by the resist 250 are removed by dry etching using, for example, a chlorine-based gas.

[0125] Next, the manufacturing method of the semiconductor device 1 includes forming a first insulating film 231. This step is the same as the step of forming the first insulating film 231 in the first embodiment. As a result, the first insulating film 231 is formed so as to cover the side surfaces of the source pad 22P, the side surfaces of the first conductive layer 201, and the side surfaces of the second conductive layer 202, as well as to cover a portion of the surface of the second conductive layer 202.

[0126] Next, the manufacturing method of the semiconductor device 1 includes forming the second insulating film 232. This step is the same as the step of forming the second insulating film 232 in the first embodiment. As a result, the second insulating film 232 is formed so as to cover the first insulating film 231, as well as a part of the element surface 11 and a part of the surface of the second conductive layer 202.

[0127] According to this modification, the source pad 22P, the first conductive layer 201, and the second conductive layer 202 can be formed continuously and can be processed simultaneously, thereby simplifying the manufacturing process of the semiconductor device 1. This improves manufacturing throughput and reduces manufacturing costs.

[0128] In the first to third embodiments, the semiconductor element 10 can be changed arbitrarily. The configuration of semiconductor element 10 of the modified example will be described with reference to FIGS. Fig. 25 is a schematic plan view of a semiconductor element 10 according to a modified example. Fig. 26 is a schematic plan view of the interior of a semiconductor device 1 according to a modified example.

[0129] As shown in Fig. 25, the semiconductor element 10 has a rectangular shape having long and short sides in a plan view. As shown in Fig. 26, the semiconductor element 10 is disposed on the die pad 101 so that the long sides are aligned in the X direction and the short sides are aligned in the Y direction. The semiconductor element 10 is configured as, for example, a transistor. The semiconductor element 10 is, for example, a MOSFET.

[0130] Semiconductor element 10 includes element front surface 11, element back surface 12 opposite element front surface 11, and first to fourth element side surfaces 13 to 16 as four element side surfaces connecting element front surface 11 and element back surface 12. First element side surface 13 and second element side surface 14 constitute both end surfaces of semiconductor element 10 in the X direction. Third element side surface 15 and fourth element side surface 16 constitute both end surfaces of semiconductor element 10 in the Y direction.

[0131] The semiconductor element 10 includes a gate electrode 21 provided on an element surface 11, a plurality of (four in the example shown in FIG. 25 ) source electrodes 22, and a plurality of (two in the example shown in FIG. 25 ) Kelvin source electrodes 24. The semiconductor element 10 also includes an insulating layer 23 that covers the element surface 11 and partially covers each of the gate electrode 21, the plurality of source electrodes 22, and the plurality of Kelvin source electrodes 24.

[0132] The gate electrode 21 is disposed at an end of the element surface 11 in the X direction that is closer to the first element side surface 13. The gate electrode 21 is disposed closer to the center of the element surface 11 in the Y direction.

[0133] The source electrode 22 is disposed closer to the second element side surface 14 than the gate electrode 21 in a planar view. The source electrode 22 includes two source electrodes 221 and two source electrodes 222. The two source electrodes 221 are disposed closer to the first element side surface 13 than the two source electrodes 222. The two source electrodes 221 are disposed spaced apart in the Y direction. The two source electrodes 222 are disposed closer to the second element side surface 14 than the center of the semiconductor element 10 in the X direction in a planar view. The two source electrodes 222 are disposed spaced apart in the Y direction. The two source electrodes 221 and the two source electrodes 222 are disposed side by side in the X direction. The size of the source electrode 222 in the X direction is larger than the size of the source electrode 221 in the X direction. In one example, the size of the source electrode 222 in the X direction is about three times the size of the source electrode 221 in the X direction. The size of the source electrode 221 in the Y direction and the size of the source electrode 222 in the Y direction are the same.

[0134] The multiple Kelvin source electrodes 24 are arranged between the gate electrode 21 and the source electrode 22 in the X direction in a plan view. In one example, the multiple Kelvin source electrodes 24 are arranged at the same positions as each other in the X direction and spaced apart from each other in the Y direction. The arrangement of the multiple Kelvin source electrodes 24 can be changed as desired.

[0135] For example, Al, AlCu, etc. are used as materials for forming the gate electrode 21, the source electrode 22, and the Kelvin source electrode 24. AlCu (Cu content: 0.5%) is used when resistance to electromigration and stress migration is required compared to simple Al.

[0136] The insulating layer 23 is configured to insulate the gate electrode 21, the source electrode 22, and the Kelvin source electrode 24 from one another. That is, the insulating layer 23 is provided between the gate electrode 21 and the source electrode 22, between the gate electrode 21 and the Kelvin source electrode 24, or between the source electrode 22 and the Kelvin source electrode 24.

[0137] In a plan view, the insulating layer 23 covers the outer periphery of the gate electrode 21. The insulating layer 23 includes a gate opening 23A that exposes a portion of the gate electrode 21 that is more inward than the outer periphery. The region of the gate electrode 21 exposed by the gate opening 23A forms a gate pad 21P.

[0138] The insulating layer 23 covers the outer periphery of the source electrode 22 in a plan view. The insulating layer 23 includes a plurality of source openings 23B that individually expose a plurality of locations (four locations in the example shown in FIG. 25) for the two source electrodes 221 and the two source electrodes 222. The plurality of source openings 23B are arranged in a matrix (for example, 2 rows x 2 columns). The region of the source electrode 221 exposed by the source openings 23B constitutes a source pad 221P. The region of the source electrode 222 exposed by the source openings 23B constitutes a source pad 222P. The size of the source pad 222P in the X direction is larger than the size of the source pad 221P in the X direction. The size of the source pad 222P in the X direction is approximately three times the size of the source pad 221P in the X direction.

[0139] Insulating layer 23 covers the outer periphery of Kelvin source electrode 24 in plan view. Insulating layer 23 includes a plurality of Kelvin source openings 23E that individually expose a plurality of locations (two locations in the example shown in FIG. 25) to Kelvin source electrode 24. The plurality of Kelvin source openings 23E are arranged in the Y direction, for example, two in number. The region of Kelvin source electrode 24 exposed by each Kelvin source opening 23E constitutes a Kelvin source pad 24P.

[0140] As shown in FIG. 26 , the semiconductor device 1 includes a third terminal 150. The third terminal 150 is disposed between the first terminal 110 and the second terminal 120 in the X direction. The third terminal 150 includes a third wire bonding portion 151 and a third extension portion 152. The third wire bonding portion 151 is disposed closer to the third sealing side surface 135 than the fourth sealing side surface 136. The third wire bonding portion 151 is disposed side by side with the second wire bonding portion 121 of the second terminal 120 in the X direction. The third extension portion 152 constitutes a portion that protrudes from the fourth sealing side surface 136 in the Y direction. The third extension portion 152 is disposed side by side with the second extension portion 122 of the second terminal 120 in the X direction.

[0141] The gate pad 21P and the second terminal 120 are connected by a single wire 141. The single wire 141 is joined to a second wire joining portion 121 of the second terminal 120. Two source pads 221P aligned in the Y direction are connected to the first terminal 110 by one wire 142. The one wire 142 is bonded to the two source pads 221P aligned in the Y direction and also bonded to the first wire bonding portion 111 of the first terminal 110. For this reason, the wire 142 is provided so as to straddle the insulating layer 23 that separates the two source pads 221P aligned in the Y direction.

[0142] Two source pads 222P aligned in the Y direction are connected to the first terminal 110 by three wires 142. Similar to the single wire 142, the three wires 142 are bonded to the two source pads 222P aligned in the Y direction and also to the first wire bonding portion 111. In this way, a plurality of wires 142 are bonded to a corresponding plurality of source pads 22P.

[0143] The Kelvin source pad 24P and the third terminal 150 are connected by one wire 143. The one wire 143 is bonded to the two Kelvin source pads 24P aligned in the Y direction, and is also bonded to a third wire bonding portion 151 of the third terminal 150. Therefore, the wire 143 is provided so as to straddle the insulating layer 23 that separates the two Kelvin source pads 24P aligned in the Y direction.

[0144] Each of the wires 141 to 143 is a bonding wire. The wires 141 to 143 are made of a conductive material such as Al, Cu, Ag, or Au. In one example, the wires 141 to 143 are made of a conductive material containing Al. The conductive material of the wire 141 may be different from the conductive material of the wire 142 or 143. For large current wires that are required to be thick, Al is preferably used because noble metals are expensive.

[0145] The wire diameter of the wire 141 bonded to the gate pad 21P is smaller than the wire diameter of the wire 142 bonded to the source pad 22P. The wire diameter of the wire 141 that supplies a control current to the gate electrode 21 of the semiconductor element 10 can be smaller than the wire diameter of the wire 142 that supplies a drive current from the source electrode 22 of the semiconductor element 10. In addition, the wire diameter of the wire 143 bonded to the Kelvin source pad 24P is smaller than the wire diameter of the wire 142 that is bonded to the source pad 22P. The Kelvin source electrode 24 of the semiconductor element 10 has the properties of a Kelvin electrode, extracting only the source potential of the semiconductor element 10 and not extracting the source current. Therefore, the wire diameter of the wire 143 can be smaller than the wire diameter of the wire 142 that supplies a drive current from the source electrode 22 of the semiconductor element 10.

[0146] As an example, when the semiconductor device 1 is used as a power semiconductor, the wire diameter of the wire 142 bonded to the source pad 22P is set to accommodate a large current. In one example, the wire diameter of the wire 142 can be greater than 400 μm. In one example, the wire diameter of the wire 142 can be 500 μm or greater. In this modified example, the wire 142 has a wire diameter of 508 μm. In other words, in this modified example, the wire 142 has a diameter of 20 mil. Meanwhile, the wire diameter of the wire 141 bonded to the gate pad 21P and the wire 143 bonded to the Kelvin source pad 24P can be 150 μm or less. In this modified example, the wires 141 and 143 have a wire diameter of 127 μm. In other words, in this modified example, the wires 141 and 143 have a diameter of 5 mil.

[0147] According to this modification, the same effects as those of the first and second embodiments can be obtained. In the first and second embodiments, it is possible to arbitrarily change the material constituting the first conductive layer 201. As an example, the first conductive layer 201 can be made of a material that can suppress the migration of Al atoms, such as tantalum (Ta).

[0148] In the first and second embodiments, the configuration of the second conductive layer 202 can be changed as desired. For example, the second conductive layer 202 may have a stacked structure of multiple conductive layers. For example, the second conductive layer 202 can be replaced with a conductive metal having a higher hardness than the source pad 22P, which is made of a material containing Al. On the other hand, when the second conductive layer 202 is wire-bonded to the wire 142 made of Al, it is preferable to bond the second conductive layer 202 to a Ni layer. Therefore, the second conductive layer 202 may have a stacked structure of multiple conductive layers, with a Ni layer as the outermost layer and a conductive metal with a high hardness inserted between the Ni layer and the source pad 22P. In other words, the second conductive layer 202 may have a stacked structure of a first conductive layer and a second conductive layer. In this case, the first conductive layer is made of, for example, a conductive metal with a high hardness. The second conductive layer is provided on the first conductive layer. The second conductive layer is made of, for example, a material containing Ni.

[0149] In the first and second embodiments, the thickness of the first conductive layer 201 can be made thicker than the thickness of the second conductive layer 202. The first conductive layer 201 is disposed to mechanically suppress the movement of Al atoms that constitute the source pad 22P made of a material containing Al, and therefore, by making the first conductive layer 201 thicker, the occurrence of hillocks can be more effectively suppressed.

[0150] In the second and third embodiments, it is possible to arbitrarily change the material constituting the fourth conductive layer 402. As an example, the material constituting the fourth conductive layer 402 may be, for example, Ta, which functions as an adhesion layer and a barrier layer.

[0151] In the second and third embodiments, it is possible to arbitrarily change the material constituting the fifth conductive layer 403. For example, instead of Ni, a substance that can be alloyed with Sn contained in the solder can be used as the material constituting the fifth conductive layer 403.

[0152] In the second and third embodiments, it is possible to arbitrarily change the material constituting the sixth conductive layer 404. As an example, the material constituting the sixth conductive layer 404 may be a metal that can suppress oxidation of Ni, such as Ag.

[0153] In the second and third embodiments, the third conductive layer 401 may be omitted from the electrode stack 400. In this case, the rear surface 12 of the semiconductor element 10 can be mirror-finished to suppress voids. Here, a mirror finish refers to a surface with an arithmetic mean roughness Ra of 0.2 μm or less. The inventors of the present application have confirmed that this reduces the void generation rate by 42.5%.

[0154] According to this configuration, by mirror-finishing the back surface 12 of the semiconductor element 10 to an arithmetic mean roughness Ra of 0.2 μm or less, it is possible to reduce voids 340 that occur inside the conductive bonding material 104 during reflow. This allows the mechanical strength of the laminate of the second conductive layer 202, the first conductive layer 201, and the semiconductor element 10 to be maintained against ultrasonic waves during wire bonding, thereby suppressing the occurrence of cratering.

[0155] In the second and third embodiments, the arithmetic mean roughness Ra of the rear surface 12 when mirror-finished is 0.2 μm or less, but the smaller the arithmetic mean roughness Ra, the better. As an example, mirror-finishing by polishing using chemical mechanical polishing may be used instead of etching. In this case, the arithmetic mean roughness Ra of the rear surface 12 can be made smaller than that of etching. As an example, when the rear surface 12 is mirror-finished by polishing, the arithmetic mean roughness Ra of the rear surface 12 can be made 0.05 μm.

[0156] In the second and third embodiments, the use of an AlSi film as the third conductive layer 401 may be combined with a mirror finish. The inventors of the present application have confirmed that this reduces the void generation rate by 56.9%, thereby suppressing the occurrence of cratering.

[0157] In each embodiment, the gate pad 21P may be provided with a conductive laminated portion 200. In this case, the wire 141 is bonded to the second conductive layer 202 of the conductive laminated portion 200. In each embodiment, the first conductive layer 201 may be provided on the gate pad 21P.

[0158] One or more of the various examples described in the present disclosure may be combined to the extent that they are not technically inconsistent. The term "on" as used in this disclosure includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0159] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described in this disclosure being "up" and "down" of the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0160] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0161] [Appendix 1] A semiconductor element (10) having an element surface (11) and an element back surface (12) opposite to the element surface (11); a pad (22P) disposed on the element surface (11); a first conductive layer (201) laminated on the pad (22P); a second conductive layer (202) stacked on the first conductive layer (201), containing Ni and having at least a portion exposed; a wire (142) made of Al and bonded to the second conductive layer (202); Including, The semiconductor element (10) has a thickness of 100 μm or less, The second conductive layer (202) is made of a material harder than the first conductive layer (201). Semiconductor device (1).

[0162] [Appendix 2] The first conductive layer (201) is made of a material containing Ti. The semiconductor device (1) according to appendix 1.

[0163] [Appendix 3] The thickness of the second conductive layer (202) is greater than the thickness of the first conductive layer (201). The semiconductor device (1) according to appendix 1 or 2.

[0164] [Appendix 4] The thickness of the first conductive layer (201) is greater than the thickness of the second conductive layer (202). The semiconductor device (1) according to appendix 1 or 2.

[0165] [Appendix 5] The diameter of the wire (142) is greater than 400 μm. A semiconductor device (1) according to any one of appendices 1 to 4.

[0166] [Appendix 6] The diameter of the wire (142) is 500 μm or more. A semiconductor device (1) according to any one of appendices 1 to 4.

[0167] [Appendix 7] The thickness of the semiconductor element (10) is 60 μm or less. A semiconductor device (1) according to any one of appendices 1 to 6.

[0168] [Appendix 8] A semiconductor element (10) having an element surface (11) and an element back surface (12) opposite to the element surface (11); a pad (22P) disposed on the element surface (11); a first conductive layer (201) laminated on the pad; a second conductive layer (202) stacked on the first conductive layer (201), containing Ni and having at least a portion exposed; a wire (142) made of Al and bonded to the second conductive layer (202); an electrode laminate (400) disposed on the rear surface (12) of the element; Including, The semiconductor element (10) has a thickness of 100 μm or less, the second conductive layer (202) is made of a material harder than the first conductive layer (201); The electrode stack (400) is a third conductive layer (401) including AlSi arranged on the back surface (12) of the element; a fourth conductive layer (402) containing Ti laminated on the third conductive layer (401); a fifth conductive layer (403) containing Ni laminated on the fourth conductive layer (402); a sixth conductive layer (404) containing Au laminated on the fifth conductive layer (403); Contains Semiconductor device (1).

[0169] [Appendix 9] The first conductive layer (201) is made of a material containing Ti. The semiconductor device (1) according to appendix 8.

[0170] [Appendix 10] The thickness of the second conductive layer (202) is greater than the thickness of the first conductive layer (201). The semiconductor device (1) according to appendix 8 or 9.

[0171] [Appendix 11] The thickness of the first conductive layer (201) is greater than the thickness of the second conductive layer (202). The semiconductor device (1) according to appendix 8 or 9.

[0172] [Appendix 12] The diameter of the wire (142) is greater than 400 μm. The semiconductor device (1) according to any one of appendices 8 to 11.

[0173] [Appendix 13] The diameter of the wire (142) is 500 μm or more. The semiconductor device (1) according to any one of appendices 8 to 11.

[0174] [Appendix 14] The rear surface (12) of the element is a mirror surface with an arithmetic mean roughness Ra of 0.2 μm or less. The semiconductor device (1) according to any one of appendices 8 to 13.

[0175] [Appendix 15] The thickness of the semiconductor element (10) is 60 μm or less. The semiconductor device (1) according to any one of appendices 8 to 14.

[0176] [Appendix 16] A semiconductor element (10) having an element surface (11) and an element back surface (12) opposite to the element surface (11); a pad (22P) disposed on the element surface (11); a wire (142) made of Al and electrically connected to the pad (22P); an electrode laminate (400) disposed on the rear surface (12) of the element; a substrate (100) to which the semiconductor element is fixed via the electrode laminate (400) and solder (104); Including, The semiconductor element (10) has a thickness of 100 μm or less, The electrode stack (400) is a third conductive layer (401) including AlSi arranged on the back surface (12) of the element; a fourth conductive layer (402) containing Ti laminated on the third conductive layer (401); a fifth conductive layer (403) containing Ni laminated on the fourth conductive layer (402); a sixth conductive layer (404) containing Au laminated on the fifth conductive layer (403); Contains Semiconductor device (1).

[0177] [Appendix 17] The rear surface (12) of the element is a mirror surface with an arithmetic mean roughness Ra of 0.2 μm or less. 17. The semiconductor device (1) according to claim 16.

[0178] [Appendix 18] The semiconductor element (10) has a thickness of 60 μm or less. 18. The semiconductor device (1) according to claim 16 or 17.

[0179] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0180] 1...Semiconductor device 10...Semiconductor element 11...Element surface 12...Back side of element 13...First element side 14...Side of second element 15...Third element side 16...4th element side 21...Gate electrode 21P...Gate pad 22, 221, 222...Source electrode 22E...Source electrode peripheral portion 22M: Source electrode material 22P, 221P, 222P...Sauce Pad 23...insulating layer 231...first insulating film 232...Second insulating film 23A...Gate opening 23B...Source opening 23C...Outer surface of insulating layer 23D...Inner surface of insulating layer 23E…Kelvin Source Aperture 24...Kelvin source electrode 24P...Kelvin sauce pad 100...Substrate 101...Die pad 102...Board terminal 103...recess 103A...Bottom of recess 104...Conductive bonding material 110…1st terminal 111...first wire joint 112...1st extension section 113...Through hole 120…Second terminal 121...Second wire joint 122…Second extension part 130...Sealing resin 131...Sealing surface 132…Sealing back side 133...first sealing side 134…Second sealing side 135…Third sealing side 136…4th sealing side 141, 142, 143...Wires 150…3rd terminal 151...Third wire joint 152...Third extension section 200...Conductive laminated portion 201...First conductive layer 201A...First edge part 202...Second conductive layer 202A…Second edge part 250...Resist 300…Joint part 310...Damage layer 340...Void 400, 400A... Electrode laminate 401...Third conductive layer 402...Fourth conductive layer 403...5th conductive layer 404...6th conductive layer 800...Semiconductor wafers 801...wafer surface 802...Wafer backside 810...First insulating film 820...Resist 830...Second insulating film 840…Ti film 850...Ni film 860...Resist 861...Resist side

Claims

1. a semiconductor element having a front surface and a back surface opposite to the front surface; a pad disposed on the surface of the element; a first conductive layer laminated on the pad; a second conductive layer that is stacked on the first conductive layer, contains Ni, and has at least a portion exposed; a wire bonded to the second conductive layer and made of Al; Including, The semiconductor element has a thickness of 100 μm or less, The second conductive layer is made of a material harder than the first conductive layer. Semiconductor device.

2. The first conductive layer is made of a material containing Ti. The semiconductor device according to claim 1 .

3. The thickness of the second conductive layer is greater than the thickness of the first conductive layer.

3. The semiconductor device according to claim 1.

4. The thickness of the first conductive layer is greater than the thickness of the second conductive layer.

3. The semiconductor device according to claim 1.

5. The wire diameter is greater than 400 μm.

3. The semiconductor device according to claim 1.

6. The wire diameter is 500 μm or more.

3. The semiconductor device according to claim 1.

7. The thickness of the semiconductor element is 60 μm or less. The semiconductor device according to claim 6.

8. a semiconductor element having a front surface and a back surface opposite to the front surface; a pad disposed on the surface of the element; a first conductive layer laminated on the pad; a second conductive layer that is stacked on the first conductive layer, contains Ni, and has at least a portion exposed; a wire bonded to the second conductive layer and made of Al; an electrode stack disposed on a rear surface of the element; Including, The semiconductor element has a thickness of 100 μm or less, the second conductive layer is made of a material harder than the first conductive layer; The electrode stack is a third conductive layer including AlSi disposed on a rear surface of the element; a fourth conductive layer including Ti stacked on the third conductive layer; a fifth conductive layer including Ni stacked on the fourth conductive layer; a sixth conductive layer including Au stacked on the fifth conductive layer; Contains Semiconductor device.

9. The first conductive layer is made of a material containing Ti. The semiconductor device according to claim 8 .

10. The thickness of the second conductive layer is greater than the thickness of the first conductive layer.

10. The semiconductor device according to claim 8.

11. The thickness of the first conductive layer is greater than the thickness of the second conductive layer.

10. The semiconductor device according to claim 8.

12. The wire diameter is greater than 400 μm.

10. The semiconductor device according to claim 8.

13. The wire diameter is 500 μm or more.

10. The semiconductor device according to claim 8.

14. The rear surface of the element is a mirror surface with an arithmetic mean roughness Ra of 0.2 μm or less.

10. The semiconductor device according to claim 8.

15. The thickness of the semiconductor element is 60 μm or less. The semiconductor device according to claim 13.

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