Semiconductor device

Abstract

To improve reliability of a semiconductor device.SOLUTION: A semiconductor device having an n-type epitaxial layer EP, a plurality of p-type column regions PC formed in the epitaxial layer EP so as to be separated from each other in a plan view, and a gate electrode GE formed between the plurality of p-type column regions PC is used. Here, each p-type column region PC is formed in the epitaxial layer EP and includes sub-column regions SC1, SC2, and SC3 arranged in order from the side close to a main surface of the epitaxial layer EP in a depth direction. The distance between the maximum impurity concentration position of the sub-column region SC1 and a maximum impurity concentration position of the sub-column region SC2 is smaller than the distance between the maximum impurity concentration position of the sub-column region SC2 and the maximum impurity concentration position of the sub-column region SC3.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a technique that is effective when applied to a power semiconductor device. [Background technology]

[0002] In vertical power MOSFETs, which are power semiconductor devices, the adoption of a superjunction structure in which n-type columns and p-type columns are arranged alternately is being considered in order to maintain the breakdown voltage and reduce the on-resistance.

[0003] For example, Patent Document 1 (JP 2017-139439 A) describes a semiconductor device having a superjunction structure in which p-type columns are formed in a semiconductor substrate between multiple trench gates by multiple ion implantations. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-139439 Summary of the Invention [Problem to be solved by the invention]

[0005] When forming p-type columns using ion implantation, the width of the openings in the mask used to block ion implantation tends to vary, which in turn causes variations in the breakdown voltage characteristics of the MOSFET, resulting in problems such as reduced yield and reliability of the semiconductor device.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A brief summary of a representative embodiment of the present invention will be given below.

[0008] A semiconductor device according to one embodiment includes an n-type drift region, multiple p-type column regions formed in the drift region so as to be spaced apart from one another in a plan view, and gate electrodes formed between each of the multiple p-type column regions. Here, the p-type column region is formed in an epitaxial layer and is composed of a first sub-column region, a second sub-column region, and a third sub-column region arranged in that order from the side closest to the main surface of the drift region in the depth direction. Furthermore, the distance between the maximum impurity concentration position of the first sub-column region and the maximum impurity concentration position of the second sub-column region is smaller than the distance between the maximum impurity concentration position of the second sub-column region and the maximum impurity concentration position of the third sub-column region. [Effects of the Invention]

[0009] According to one embodiment disclosed in the present application, the reliability of a semiconductor device can be improved. [Brief explanation of the drawings]

[0010] [Figure 1] 1A and 1B are a cross-sectional view of a semiconductor device according to an embodiment and a graph showing the relationship between depth in a semiconductor substrate and impurity concentration; [Figure 2] 1 is a graph showing the relationship between the depth in a semiconductor substrate and the impurity concentration in a semiconductor device according to an embodiment. [Figure 3] 1 is a planar layout of a semiconductor device according to an embodiment. [Figure 4] 1 is a cross-sectional view of a semiconductor device during a manufacturing process according to an embodiment; [Figure 5] 5 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 4. [Figure 6] 6 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 5. [Figure 7] FIG. 7 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 6. [Figure 8]FIG. 8 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 7. [Figure 9] 9 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 8. [Figure 10] FIG. 10 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. [Figure 11] 11 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 10. [Figure 12] 12 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 11. [Figure 13] 10 is a graph showing an example of the relationship between the column width and the breakdown voltage of the semiconductor device according to the embodiment; [Figure 14] 10 is a graph showing an example of the relationship between the column width and the breakdown voltage of the semiconductor device according to the embodiment; [Figure 15] 10 is a graph showing an example of the relationship between the column width and the breakdown voltage of the semiconductor device according to the embodiment; [Figure 16] FIG. 10 is a cross-sectional view of a semiconductor device according to a first modified example of the embodiment. [Figure 17] FIG. 10 is a cross-sectional view of a semiconductor device according to a second modification of the embodiment. [Figure 18] 10 is a planar layout of a semiconductor device according to a third modification of the embodiment. [Figure 19] 10 is a planar layout of a semiconductor device according to a fourth modified example of the embodiment. [Figure 20] FIG. 10 is a cross-sectional view of a semiconductor device according to Comparative Example 1. [Figure 21] 10A and 10B are cross-sectional views of a semiconductor device according to Comparative Example 1 during a manufacturing process. [Figure 22] 10 is a graph showing the relationship between the depth in a semiconductor substrate and the impurity concentration in a semiconductor device according to Comparative Example 1. [Figure 23] 10 is a graph showing an example of the relationship between the column width and the breakdown voltage of the semiconductor device according to Comparative Example 1. [Figure 24] FIG. 10 is a cross-sectional view of a semiconductor device according to Comparative Example 2. [Figure 25] 10 is a graph showing an example of the relationship between the column width and the breakdown voltage of a semiconductor device according to Comparative Example 2. [Figure 26]FIG. 10 is a cross-sectional view of a semiconductor device according to Comparative Example 3. DETAILED DESCRIPTION OF THE INVENTION

[0011] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the mentioned number, and may be more or less than the mentioned number, unless otherwise specified or when it is clearly limited in principle to a specific number.

[0012] Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values ​​and ranges.

[0013] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0014] (Embodiment) <Structure of semiconductor device> FIG. 1 shows a cross-sectional view of a cell region of a semiconductor device according to this embodiment. The semiconductor device (semiconductor element) according to this embodiment is a vertical power MOSFET (Metal Oxide Semiconductor Field Effect Transistor, a MOS-type field effect transistor). A MOSFET is a type of MISFET (Metal Insulator Semiconductor Field Effect Transistor). As shown in FIG. 1, the semiconductor device according to this embodiment has a laminated semiconductor substrate SUB having a first main surface (upper surface) and a second main surface (lower surface) opposite to the first main surface. The laminated semiconductor substrate SUB has n + The epitaxial layer EP is an n-type semiconductor layer formed on the main surface (top surface) of the semiconductor substrate SB. + The epitaxial layer EP is in contact with the semiconductor substrate SB, which is a type semiconductor region. The epitaxial layer EP forms the drift region.

[0015] A plurality of trenches (gate trenches) GT are formed in the main surface of the epitaxial layer EP, reaching a depth of the epitaxial layer EP. The trenches GT extend, for example, in the Y direction, and are arranged in the X direction within the cell region. The trenches GT also extend in the Z direction (thickness direction, depth direction). The X direction and Y direction referred to in this application are directions along the main surface of the semiconductor substrate SB and the main surface of the epitaxial layer EP (the first main surface of the laminated semiconductor substrate SUB). The X direction, Y direction, and Z direction are directions orthogonal to each other in a plan view. Here, the X direction and Y direction may also be referred to as lateral directions. The Z direction is a direction perpendicular to each of the main surface of the epitaxial layer EP and the first and second main surfaces of the laminated semiconductor substrate SUB.

[0016] A gate electrode (trench gate) GE is buried in each trench GT via an insulating film IF1. That is, the side and bottom surfaces of the trench GT are continuously covered with the insulating film IF1 made of, for example, a silicon oxide film, and the epitaxial layer EP and the gate electrode GE are insulated by the insulating film IF1. The gate electrode GE is made of, for example, a polycrystalline silicon film. The distance in the Z direction between the first main surface and the bottom surface of the gate electrode GE is not less than 0.8 μm and less than 1.0 μm.

[0017] Body regions (p-type semiconductor regions, channel regions) BR are formed in the epitaxial layer EP between the trenches GT adjacent in the X direction. One body region BR formed between the trenches GT adjacent in the X direction contacts each side surface of the trenches GT adjacent in the X direction. The lower ends of the body regions BR are shallower than the lower ends of the trenches GT. In other words, the body regions BR are formed on the epitaxial layer EP (drift layer), which is an n-type semiconductor region.

[0018] In addition, in the epitaxial layer EP between the trenches GT adjacent to each other in the X direction, a source region (n + type semiconductor region, n + The source region SR is formed in the body region BR. The lower end of the source region SR is in contact with the body region BR. In other words, the source region SR is formed in the body region BR from the upper surface of the body region BR to a predetermined depth. The source region SR is in contact with the side surfaces of the trenches GT adjacent to each other in the X direction.

[0019] A p-type column region PC consisting of multiple sub-column regions SC1, SC2, and SC3 is formed in the epitaxial layer EP below the body region BR between adjacent trenches GT in the X direction. The sub-column regions SC1, SC2, and SC3 are arranged side by side in the Z direction, for example, directly below the central body region BR between adjacent trenches GT in the X direction. Here, the sub-column regions SC1, SC2, and SC3 are formed in this order from the body region BR side toward the semiconductor substrate SB side. In a direction perpendicular to the Z direction, the sub-column regions SC1, SC2, and SC3 have approximately the same width. In a direction perpendicular to the Z direction, the width of each of the sub-column regions SC1, SC2, and SC3 is 0.52 μm or more and 0.58 μm or less.

[0020] In the Z direction, the distance between sub-column region SC1 and sub-column region SC2 is shorter than the distance between sub-column region SC2 and sub-column region SC3. While sub-column region SC1 is in contact with body region BR in FIG. 1, sub-column region SC1 and body region BR may be spaced apart from each other. The distance in the Z direction between the first main surface and the maximum impurity concentration position of sub-column region SC1 is equal to or greater than 0.7 μm and less than 0.9 μm.

[0021] Since a plurality of trenches GT are repeatedly lined up in the X direction, a plurality of p-type column regions PC are also formed lined up in the X direction. That is, a plurality of p-type column regions PC are formed in the epitaxial layer EP so as to be spaced apart from one another in a plan view. The gate electrode GE is formed between adjacent p-type column regions PC. The p-type column regions PC and the trenches GT protruding from the bottom surfaces of the body regions BR toward the semiconductor substrate SB are spaced apart from one another in the X direction. The maximum position of the impurity concentration in the sub-column region SC1 is located closer to the first main surface of the laminated semiconductor substrate SUB than the bottom surfaces of the gate electrodes GE.

[0022] The epitaxial layer EP, which is an n-type semiconductor region between the p-type column regions PC adjacent to each other in the X direction, configures an n-type column region NC.

[0023] The n-type impurity concentration of the source region SR is higher than the n-type impurity concentrations of the n-type column region NC and the semiconductor substrate SB. The p-type impurity concentration of the diffusion region BC is higher than the p-type impurity concentration of the epitaxial layer EP. The trench GT and the gate electrode GE penetrate the source region SR and the body region BR and reach the epitaxial layer EP (drift region) below the body region BR.

[0024] An interlayer insulating film IL is formed on the epitaxial layer EP, the source region SR, and the gate electrode GE. A connection hole is formed in the interlayer insulating film IL, penetrating the interlayer insulating film IL in the Z direction, and the connection hole penetrates the source region SR to reach a depth partway into the body region BR. A recess constituting the connection hole and extending from the first main surface of the laminated semiconductor substrate SUB to a depth partway into the body region BR constitutes a trench TR.

[0025] Contact plugs CP made of, for example, aluminum (Al) or tungsten (W) are buried in the connection holes and the trenches TR. The contact plugs CP are formed between adjacent trenches GT in plan view and are located, for example, directly above the p-type column regions PC. In other words, the contact plugs CP are formed in positions overlapping the p-type column regions PC in plan view. The contact plugs CP penetrate the interlayer insulating film IL and reach the body region BR.

[0026] In the body region BR, a p + A diffusion region (body contact region) BC, which is a semiconductor region of the source region SR, is formed in the source region SR. The impurity concentration of the diffusion region BC is higher than the impurity concentration of any of the body region BR and the sub-column regions SC1, SC2, and SC3. A contact plug CP is connected to the side surface of the source region SR and the upper surface of the diffusion region BC.

[0027] On the interlayer insulating film IL and the contact plug CP, a wiring M1 made of, for example, aluminum (Al) is formed. The contact plug CP and the wiring M1 may be formed separately or may be integrated with each other.

[0028] In the X direction, the p-type column regions PC and the n-type column regions NC (n-type epitaxial layer EP) are arranged alternately. In other words, the plurality of p-type column regions PC and the drift regions (epitaxial layer EP) between the plurality of p-type column regions PC are arranged in parallel at predetermined intervals in a plan view. The p-type column regions PC and the n-type column regions NC arranged alternately in the horizontal direction form a superjunction structure. The n-type column region NC is made up of the gate electrode GE, the source region SR, the body region BR, the n-type column regions NC, and the epitaxial layer EP, and the semiconductor substrate SB. + The n-channel vertical power MOSFET is composed of the n-type semiconductor region (drain region).

[0029] FIG. 1 shows a cross-sectional view including a vertical power MOSFET, along with a graph illustrating the concentration distribution of p-type impurities in a laminated semiconductor substrate SUB. The vertical axis of the graph corresponds to the depth position of the laminated semiconductor substrate SUB in the cross-sectional view. That is, in the graph, the vertical axis indicates the depth from the first main surface of the laminated semiconductor substrate SUB, and the horizontal axis indicates the concentration of p-type impurities. FIG. 2 also shows the graph of FIG. 1 with its orientation reversed. That is, in the graph shown in FIG. 2, the vertical axis indicates the concentration of p-type impurities in the laminated semiconductor substrate SUB, and the horizontal axis indicates the depth from the first main surface of the laminated semiconductor substrate SUB. The vertical axis of the graph in FIG. 1 indicates a depth with a positive value that increases from the top to the bottom, while the horizontal axis of the graph in FIG. 2 indicates a depth with a positive value that increases from the left end to the right end. These graphs illustrate the concentration distribution in a region in which a p-type column region PC is formed.

[0030] In Figure 2, the solid line indicates the concentration distribution of impurities, including all of the impurities that make up sub-column regions SC1, SC2, and SC3. The dashed-dotted line indicates the concentration distribution of impurities introduced by ion implantation when forming sub-column region SC1. The dashed-two-dot line indicates the concentration distribution of impurities introduced by ion implantation when forming sub-column region SC2. The dashed line indicates the concentration distribution of impurities introduced by ion implantation when forming sub-column region SC3.

[0031] As shown in FIGS. 1 and 2, there are three maximum impurity concentration positions (concentration peaks) in the laminated semiconductor substrate SUB, corresponding to the sub-column regions SC1, SC2, and SC3, respectively. In the Z direction, the depth at which the impurity concentration of sub-column region SC1 is maximum is designated D1, the depth at which the impurity concentration of sub-column region SC2 is maximum is designated D2, and the depth at which the impurity concentration of sub-column region SC3 is maximum is designated D3. In the Z direction, the distance L1 between depths D1 and D2 is smaller than the distance L2 between depths D2 and D3. In other words, the distance L1 between the maximum impurity concentration position of sub-column region SC1 and the maximum impurity concentration position of sub-column region SC2 is smaller than the distance L2 between the maximum impurity concentration position of sub-column region SC2 and the maximum impurity concentration position of sub-column region SC3. For example, the depth at which the impurity concentration of sub-column region SC1 is maximum here is not the position at which the impurity concentration is maximum in the concentration distribution indicated by the dashed-dotted line in FIG. 2. The depth at which the impurity concentration of the sub-column region SC1 is maximum refers to the position at which the impurity concentration of the sub-column region SC1 is maximum in the region where the sub-column region SC1 overlaps with other sub-column regions such as SC2. Distance L1 is equal to or greater than 0.3 μm and less than 0.6 μm, and distance L2 is equal to or greater than 0.6 μm and less than 1.0 μm.

[0032] 2, the width N1 in the depth direction (Z direction) of the impurity region formed by the integration of sub-column region SC1 and sub-column region SC2 is greater than the width N2 in the depth direction of sub-column region SC3. Width N1 is the distance from the position showing the lowest impurity concentration between the maximum impurity concentration position of sub-column region SC2 and the maximum impurity concentration position of sub-column region SC3 to the position where the impurity concentration reaches this minimum impurity concentration in a region (region on the first main surface side) shallower than the maximum impurity concentration position (depth D1) of sub-column region SC1. Width N2 is the distance from the position showing the lowest impurity concentration between the maximum impurity concentration position of sub-column region SC2 and the maximum impurity concentration position of sub-column region SC3 to the position where the impurity concentration reaches this minimum impurity concentration in a region (region on the second main surface side) deeper than the maximum impurity concentration position (depth D3) of sub-column region SC3. Width N1 is equal to or greater than 0.5 μm and less than 1.0 μm, and width N2 is equal to or greater than 0.2 μm and less than 0.5 μm.

[0033] Furthermore, sub-column region SC1 and sub-column region SC2 are positioned relatively close to each other in the depth direction. Therefore, the impurity concentration in the region where sub-column region SC1 and sub-column region SC2 overlap is higher than the impurity concentration at the maximum impurity concentration in sub-column region SC3. Here, the impurity concentration of sub-column region SC1, indicated by the dashed-dotted line, is higher than the impurity concentration of sub-column region SC2, indicated by the dashed-dotted line, and the impurity concentration of sub-column region SC2, indicated by the dashed-dotted line, is higher than the impurity concentration of sub-column region SC3, indicated by the broken line. The impurity concentration in the region where sub-column region SC1 and sub-column region SC2 overlap is between two and five times the impurity concentration at the maximum impurity concentration in sub-column region SC3.

[0034] FIG. 3 shows a planar layout of the semiconductor device of this embodiment. FIG. 3 shows only the epitaxial layer EP, trench GT, insulating film IF1, gate electrode GE, p-type column region PC, and sub-column regions SC1, SC2, and SC3. In a planar view, sub-column region SC1 and the sub-column regions SC2 and SC3 located thereunder overlap each other. In this application, a planar view refers to viewing an object in the Z direction. In FIG. 3, sub-column regions SC1, SC2, and SC3 are indicated by dashed lines.

[0035] As shown in FIG. 3, the trench GT and the gate electrode GE extend in the Y direction. The sub-column regions SC1, SC2, and SC3 are formed at positions spaced apart from the trench GT and the gate electrode GE, and each has, for example, a circular planar shape. The p-type column regions PC, each consisting of the sub-column regions SC1, SC2, and SC3 formed side by side in the Z direction, are arranged side by side in the Y direction. Furthermore, one column of the p-type column regions PC arranged side by side in the Y direction is arranged at a position shifted by a half period in the Y direction with respect to another column of the p-type column regions PC positioned on either side of the gate electrode GE in plan view. In other words, the multiple p-type column regions PC are arranged at a distance from one another in a staggered pattern.

[0036] <Operation of vertical power MOSFET with superjunction structure> In this embodiment, a superjunction structure is adopted in which p-type column regions PC and n-type column regions NC (n-type epitaxial layers EP adjacent to the p-type column regions PC) are periodically arranged. By forming a vertical power MOSFET on such a laminated semiconductor substrate SUB, it is possible to reduce the on-resistance while ensuring a high breakdown voltage.

[0037] That is, in this case, during the off state, a depletion layer extends laterally within the n-type column region NC from the boundary region between the p-type column region PC and the n-type column region NC in the lateral direction, that is, from the pn junction extending in the Z direction. In other words, the depletion layers extending from the side surfaces of adjacent p-type column regions PC come into contact with each other, thereby cutting off the current path within the drift region.

[0038] For this reason, in a vertical power MOSFET with a superjunction structure, even if the impurity concentration in the epitaxial layer EP (drift region), which serves as the current path, is increased to reduce on-resistance, the depletion layer that spreads laterally from the pn junction ensures a high breakdown voltage, thereby reducing on-resistance while maintaining a high breakdown voltage.

[0039] In the semiconductor device shown in FIG. 1, the epitaxial layer EP, which is the drift region, is in contact with the bottom surface of the trench GT. When the vertical power MOSFET is in the on-state, a positive voltage is applied to the gate electrode GE, which generates an inversion layer (channel) in the body region BR at a location where the body region BR is in contact with the side surface of the trench GT. As a result, a current flows between the source region SR and the semiconductor substrate SB, which is the drain region, through the epitaxial layer EP and the inversion layer. To ensure this current path, the p-type column region PC and the trench GT must be spaced apart from each other. Furthermore, to ensure a sufficient breakdown voltage in the off state, the maximum position (depth D1) of the impurity concentration in the sub-column region SC1 is located closer to the first main surface of the laminated semiconductor substrate SUB than the bottom surface of the gate electrode GE.

[0040] As shown in Figure 3, by arranging multiple p-type column regions PC in a staggered pattern, the distance between adjacent p-type column regions PC in a plan view becomes approximately equal in all directions. This makes it easier for the depletion layers extending from the side surfaces of adjacent p-type column regions PC to come into contact with each other when the device is off, improving the reliability of ensuring breakdown voltage.

[0041] <Method of manufacturing a semiconductor device> A method for manufacturing the semiconductor device of this embodiment will be described below with reference to Figures 4 to 12. Figures 4 to 12 are cross-sectional views of the semiconductor device of this embodiment during the manufacturing process.

[0042] First, as shown in FIG. 4, an epitaxial layer EP made of an n-type semiconductor layer is formed on the main surface (upper surface). +A type semiconductor substrate SB, i.e., a laminated semiconductor substrate (semiconductor wafer) SUB having a laminated structure, is prepared. The n-type impurity concentration of the epitaxial layer EP is lower than the n-type impurity concentration of the semiconductor substrate SB. The laminated semiconductor substrate SUB, which is made up of the epitaxial layer EP and the semiconductor substrate SB, has a plurality of chip regions that will later be diced into individual semiconductor chips. In a plan view, a cell region in which elements are formed is located at the center of each chip region. Figures 4 to 12 show the structure of the cell region during the manufacturing process. The laminated semiconductor substrate SUB has a first main surface, which is the main surface of the epitaxial layer EP, and a second main surface, which is the lower surface of the semiconductor substrate SB.

[0043] The semiconductor substrate SB is formed by doping n-type impurities such as P (phosphorus) into single crystal silicon. The resistance of the semiconductor substrate SB is, for example, 1.5 mΩcm or less. The epitaxial layer EP is formed on the semiconductor substrate SB using an epitaxial growth method. The epitaxial layer EP is mainly made of Si (silicon). The epitaxial layer EP contains p-type impurities (for example, P (phosphorus)) during epitaxial growth.

[0044] Next, as shown in FIG. 5, a plurality of trenches GT are formed in the main surface of the epitaxial layer EP. That is, a plurality of insulating films (not shown) are stacked on the epitaxial layer EP. These insulating films include, for example, a silicon oxide film formed by an oxidation method and a silicon nitride film formed by a CVD (Chemical Vapor Deposition) method. Next, a photoresist film (not shown) is formed on the insulating films. The photoresist film has a resist pattern with through holes. Next, dry etching is performed using the photoresist film as a mask (an etching prevention mask, an etching mask). This removes parts of the plurality of insulating films, exposing the main surface of the epitaxial layer EP. Next, dry etching is performed using the photoresist film and the plurality of insulating films as masks. This forms a plurality of trenches GT that extend from the main surface of the epitaxial layer EP to a depth partway through the epitaxial layer EP.

[0045] The trenches GT each have a predetermined width and a predetermined depth and extend in the Y direction, and a plurality of trenches GT are arranged side by side in the X direction. The bottoms of the trenches GT do not reach the interface between the epitaxial layer EP and the semiconductor substrate SB. The trenches GT are gate trenches into which gate electrodes will be embedded in a later process.

[0046] Next, as shown in FIG. 6, the photoresist film and insulating film on the epitaxial layer EP are removed. Subsequently, an insulating film IF1 is formed, for example, by oxidation, to cover the side and bottom surfaces of the trench GT and the main surface of the epitaxial layer EP outside the trench GT. The insulating film IF1 is made of, for example, a silicon oxide film. Subsequently, a silicon film is formed on the insulating film IF1 by, for example, CVD, to completely fill the trench GT. Subsequently, the silicon film and insulating film IF1 on the main surface of the epitaxial layer EP except for the inside of the trench GT are removed by, for example, etch-back. As a result, a gate electrode GE made of the silicon film is formed in the trench GT via a gate insulating film made of the insulating film IF1.

[0047] Next, as shown in FIG. 7, ions are implanted into the main surface of the epitaxial layer EP to implant p-type impurities (e.g., B (boron)) into the epitaxial layer EP. By introducing the p-type impurities into the epitaxial layer EP in this manner, p-type body regions BR shallower than the trenches GT are formed between adjacent trenches GT. The body regions BR are in contact with the side surfaces of the trenches GT and extend along the side surfaces. The depth of the body regions BR is shallower than the depth of the gate electrodes GE.

[0048] 8, ions are implanted into the main surface of the epitaxial layer EP to implant n-type impurities (e.g., As (arsenic)) into the epitaxial layer EP (in the body region BR). By introducing the n-type impurities into the epitaxial layer EP in this manner, n trenches GT are formed between adjacent trenches GT at a depth shallower than the body region BR. +The source region SR is in contact with the side surface of the trench GT and the body region BR. The n-type impurity concentration of the source region SR is higher than the n-type impurity concentration of the epitaxial layer EP, which is the drift region.

[0049] Next, as shown in FIG. 9, an insulating film is formed on each of the epitaxial layer EP, the insulating film IF1, and the gate electrode GE, for example, using a CVD method. The insulating film is made of, for example, silicon oxide. Subsequently, a portion of the insulating film is opened using photolithography and dry etching. This partially exposes the main surface of the epitaxial layer EP (the first main surface of the laminated semiconductor substrate SUB) in which the source region SR is formed. This forms a hard mask (protective film) HM made of the insulating film. The opening OP formed in the hard mask HM by the above etching process is located above a region between adjacent trenches GT in the X direction.

[0050] Next, as shown in FIG. 10 , ion implantation is performed in multiple stages (multi-stages) using a hard mask HM as a mask (ion implantation blocking mask, impurity introduction mask). This introduces p-type impurities (e.g., B (boron)) into the epitaxial layer EP. Here, p-type impurities are implanted three times with different implantation energies into the epitaxial layer EP directly below the opening OP and below the body region BR. That is, multi-stage implantation is performed by changing the ion implantation energy in stages. By performing the ion implantation three times, sub-column regions SC1, SC2, and SC3 are formed at different depths in the epitaxial layer EP. The sub-column region SC1 is formed at a position shallower than the sub-column region SC2, and the sub-column region SC2 is formed at a position shallower than the sub-column region SC3. The sub-column regions SC1, SC2, and SC3 formed in the epitaxial layer EP in this way and aligned in the Z direction constitute one p-type column region PC. A plurality of p-type column regions PC are formed between adjacent trenches GT and are aligned in the Z direction (see FIG. 3).

[0051] Here, the sub-column regions SC1, SC2, and SC3 are not formed at equal intervals in the Z direction. That is, by using relatively strong energy in the ion implantation during the formation of the sub-column region SC3, the sub-column region SC3 is formed at a relatively deep position. That is, the distance between the maximum impurity concentration position of the sub-column region SC1 and the maximum impurity concentration position of the sub-column region SC2 is smaller than the distance between the maximum impurity concentration position of the sub-column region SC2 and the maximum impurity concentration position of the sub-column region SC3. Furthermore, the maximum impurity concentration position of the sub-column region SC1 is located closer to the first main surface of the laminated semiconductor substrate SUB than the bottom surface of the gate electrode GE. The sub-column regions SC1, SC2, and SC3 may be formed in any order.

[0052] Adjacent p-type column regions PC are spaced apart via an n-type epitaxial layer EP. The epitaxial layer EP between adjacent p-type column regions PC constitutes an n-type column region NC.

[0053] Next, as shown in FIG. 11, after removing the hard mask HM, an interlayer insulating film IL is formed on the insulating film IF1. The interlayer insulating film IL is made mainly of, for example, silicon oxide and can be formed by, for example, a CVD method. Next, the upper surface of the interlayer insulating film IL is polished and planarized by, for example, a CMP (Chemical Mechanical Polishing) method. Next, the interlayer insulating film IL is patterned by photolithography and dry etching. This forms a contact hole (opening) that penetrates the interlayer insulating film IL and exposes the main surface of the epitaxial layer EP in which the source region SR is formed.

[0054] Next, etching is performed using the interlayer insulating film IL as a mask to recess the main surface of the epitaxial layer EP exposed at the bottom of each of the plurality of contact holes, thereby forming a plurality of trenches TR that are deeper than the bottom surfaces of the source regions SR and shallower than the bottom surfaces of the body regions BR. The body regions BR are exposed at the bottom surfaces of the trenches TR.

[0055] Next, ion implantation is performed using the interlayer insulating film IL as a mask. Here, p-type impurities (e.g., BF2 (boron fluoride)) are implanted into the body region BR directly below each of the plurality of contact holes. In this way, p-type impurities are introduced into the body region BR. As a result, p-type impurities are implanted from the bottom surface of the trench TR to the middle depth of the body region BR at positions spaced apart from the trench GT. + A diffusion region (body contact region) BC, which is a semiconductor region of the source region SR, is formed. Then, the semiconductor wafer is subjected to a heat treatment. This heat treatment diffuses the impurities in the source region SR and the diffusion region BC.

[0056] In this manner, a superjunction structure is formed in which the p-type column regions PC and the n-type epitaxial layers EP (n-type column regions NC) are alternately arranged in the horizontal direction. The n-type column regions EP, SR, BR, NC, EP, and SB are formed as a gate electrode GE, a source region SR, a body region BR, a n-type column region NC, an epitaxial layer EP, and a semiconductor substrate SB. + The vertical semiconductor region constitutes a vertical power MOSFET.

[0057] Next, as shown in FIG. 12, metal films are formed on the interlayer insulating film IL. That is, for example, a TiN (titanium nitride) film, a Ti (titanium) film, and a W (tungsten) film are formed in this order by sputtering or the like. As a result, the insides of the connection holes are filled with these metal films. Subsequently, the metal films on the interlayer insulating film IL are removed by, for example, CMP, to expose the upper surface of the interlayer insulating film IL. As a result, contact plugs (conductive connection portions) CP made of the metal films remaining in the connection holes are formed. Note that in FIG. 12, the metal films constituting the contact plug CP are collectively shown as one contact plug CP.

[0058] Next, a metal film made of aluminum (Al) is formed on the interlayer insulating film IL and the contact plugs CP by a method such as sputtering. The metal film is then patterned using photolithography and dry etching to form multiple wirings M1 made of the metal film. One of the multiple wirings M1 forms a source electrode electrically connected to the source region SR and the diffusion region BC via the contact plugs CP. Another of the multiple wirings M1 forms a gate extraction electrode in a region not shown.

[0059] Next, although not shown in the drawings, a surface protection film is formed using, for example, a CVD method so as to cover the multiple wirings M1. The surface protection film is then patterned to expose a portion of the upper surface of each of the multiple wirings M1. This exposed portion becomes an external connection region (e.g., a gate pad, a source pad).

[0060] Next, a drain electrode (not shown) is formed to cover the second main surface of the laminated semiconductor substrate SUB. Here, for example, the second main surface side of the laminated semiconductor substrate SUB is facing upward, and a metal film is formed by sputtering or vapor deposition. This allows the drain electrode made of the metal film to be formed.

[0061] The semiconductor wafer is then cut by a dicing process to separate each of the multiple chip regions of the semiconductor wafer. That is, one semiconductor chip is obtained from one chip region, and multiple semiconductor chips are obtained from the semiconductor wafer. The semiconductor device of this embodiment can be formed by the above process.

[0062] <Effects of the embodiment> 20 shows a cross-sectional view of a semiconductor device of Comparative Example 1. The semiconductor device of Comparative Example 1 is a vertical power MOSFET with a superjunction structure. The semiconductor device of Comparative Example 1 includes a plurality of p-type column regions PCA, each having p-type sub-column regions SCA and SCB formed by ion implantation. The semiconductor device of Comparative Example 1 differs from the present embodiment in that the number of sub-column regions is two.

[0063] 21 shows a cross-sectional view of the semiconductor device in the manufacturing process of Comparative Example 1. Fig. 21 corresponds to the sub-column region formation process described in the above embodiment with reference to Fig. 10. In the manufacturing process of the semiconductor device in Comparative Example 1, ion implantation is performed using the hard mask HM as a mask to form sub-column regions SCA and SCB below the openings OP of the hard mask HM.

[0064] 22 is a graph showing the relationship between depth in a semiconductor substrate and impurity concentration in the semiconductor device of Comparative Example 1. The vertical axis of the graph indicates the concentration of p-type impurities in the laminated semiconductor substrate SUB, and the horizontal axis indicates the depth from the first main surface of the laminated semiconductor substrate SUB. These graphs show the concentration distribution in the region in which the p-type column region PCA is formed. In FIG. 22, the concentration distribution of the impurities introduced by ion implantation when forming the sub-column region SCA is shown by a two-dot chain line. The concentration distribution of the impurities introduced by ion implantation when forming the sub-column region SCB is shown by a dashed line.

[0065] In the case of power semiconductors that combine vertical power MOSFETs with low-voltage CMOS (Complementary MOS) transistors, the vertical power MOSFET must meet a double-sided standard for its breakdown voltage. Double-sided standardization here refers to a standard that specifies both a lower and upper limit for the breakdown voltage. In contrast, a single-sided standard specifies only a lower limit for the breakdown voltage. To protect internal circuit elements from the back-electromotive force generated when the inductive load drive circuit is turned off, the breakdown voltage of the vertical power MOSFET must be lower than the breakdown voltage of the circuit components. For example, the breakdown voltage of a vertical power MOSFET must be 35V or higher and 50V or lower. Therefore, to meet this double-sided standard, it is necessary to suppress variations in the breakdown voltage of vertical power MOSFETs.

[0066] However, the semiconductor device of Comparative Example 1 has a problem in that variations in breakdown voltage tend to occur.

[0067] 23 is a graph showing an example of the relationship between the column width and the breakdown voltage of the semiconductor device of Comparative Example 1. The horizontal axis of the graph represents the column width, and the vertical axis represents the breakdown voltage of the vertical power MOSFET. The width of the column region on the horizontal axis is specifically the opening width of the opening OP in the hard mask HM, which greatly affects the determination of the lateral width of the sub-column region.

[0068] As can be seen from the graph in FIG. 23, when the column width is small relative to the center of the graph, the p-type column region PCA becomes N-rich, meaning that the n-type impurities are relatively abundant, and the breakdown voltage decreases. In contrast, when the column width is large relative to the center of the graph, the p-type column region PCA becomes P-rich, meaning that the p-type impurities are relatively abundant, and the breakdown voltage also decreases. In the region corresponding to the center of the horizontal axis of the graph in FIG. 23 (the region surrounded by the dashed line), the charge balance between the n-type impurities and the p-type impurities is maintained, resulting in a high breakdown voltage. However, since the range of the column width where the charge balance is maintained is extremely small, in Comparative Example 1, variations in the column width are likely to cause variations in the breakdown voltage of the vertical power MOSFET. In other words, when variations in the column width are likely to occur, the breakdown voltage cannot be stabilized. The column width variations are caused by variations in the opening width of the opening OP in the hard mask HM and other variations in the manufacturing process.

[0069] Therefore, the present inventors considered configuring the p-type column region PCA with sub-column regions SCA, SCB, and SCC arranged at equal intervals in the Z direction, as shown in FIG. 24. FIG. 24 is a cross-sectional view of a semiconductor device of Comparative Example 2. FIG. 25 is a graph showing the relationship between the column width and the breakdown voltage of the semiconductor device of Comparative Example 2. FIG. 25 shows the column width dependency of the breakdown voltage obtained from an experiment conducted by the inventors. Even when three sub-column regions SCA, SCB, and SCC are formed at equal intervals as in Comparative Example 2, the breakdown voltage characteristics have a peak, as shown in FIG. 25. In other words, the breakdown voltage varies greatly depending on the column width, making it impossible to stabilize the breakdown voltage.

[0070] The present inventors also considered forming the sub-column region SCA on the first main surface side of the p-type column region PCA, among the sub-column regions, with a higher concentration and a larger width in the lateral direction than the sub-column region SCB below it, as shown in FIG. 26 . However, this results in a problem of increased on-resistance, an important characteristic of a vertical power MOSFET. That is, here, the sub-column region SCA adjacent in the X direction to the gate electrode GE protruding below the lower surface of the body region BR is formed with a high concentration and a larger width in the lateral direction. In this case, the width of the epitaxial layer EP (drift region) between the sub-column region SCA and the trench GT, which serves as a current path in the on-state vertical power MOSFET, is narrowed. As a result, the on-resistance of the vertical power MOSFET increases.

[0071] In contrast to this, in this embodiment, one p-type column region PC is made up of a plurality of sub-column regions including sub-column regions SC1, SC2, and SC3. The distance between the sub-column regions SC1 and SC2 is smaller than the distance between the sub-column regions SC2 and SC3.

[0072] FIG. 13 is a graph showing an example of the relationship between the column width and the breakdown voltage of the semiconductor device of this embodiment. The horizontal axis of the graph represents the column width, and the vertical axis represents the breakdown voltage of the vertical power MOSFET. As in FIG. 23, this horizontal axis actually represents the opening width of the opening OP (see FIG. 10) in the hard mask HM. As shown in the graph of FIG. 13, in this embodiment, there is a region (region surrounded by a dashed line) where the breakdown voltage is almost constant even if the column width (horizontal axis) changes, and fluctuations in the breakdown voltage can be prevented even if variations in the column width occur.

[0073] 14 and 15 each show a graph of the relationship between column width and breakdown voltage, as a result of an experiment conducted by the present inventors using the semiconductor device of this embodiment. The values ​​on the vertical axis in each of FIGS. 14 and 15 are the same as the values ​​on the vertical axis of the graph in FIG. 25 for Comparative Example 2. The value of one scale mark on the horizontal axis in each of FIGS. 14 and 15 is the same as the value of one scale mark on the horizontal axis of the graph in FIG. 25 for Comparative Example 2.

[0074] Comparing the graph of Fig. 14 with the graph of Comparative Example 2 of Fig. 25, the graph of this embodiment in Fig. 14 is flatter, and it is clear that the breakdown voltage is stable against variations in column width. Moreover, the graph of Fig. 15, which is another experimental example of this embodiment, is even flatter than the graph of Fig. 14, and it is clear that it is easier to stabilize the breakdown voltage.

[0075] Therefore, in the semiconductor device of this embodiment, the breakdown voltage variation can be improved compared to Comparative Examples 1, 2, and 3. In other words, the reliability of the semiconductor device can be improved from the viewpoint of satisfying the two-sided standard. Furthermore, by improving the breakdown voltage variation, the product tolerance (robustness) can be improved. Therefore, even if the width of the P column is prone to variation, a decrease in yield caused by variation in the product breakdown voltage characteristics can be suppressed.

[0076] <Variation 1> FIG. 16 shows a cross-sectional view of a semiconductor device according to a first modification of the present embodiment. Here, among the multiple sub-column regions, a sub-column region SC4 is further formed, which is located closer to the second main surface of the laminated semiconductor substrate SUB than the sub-column region SC3, which is the third sub-column region counting from the first main surface of the laminated semiconductor substrate SUB. Like the sub-column regions SC1, SC2, and SC3, the sub-column region SC4 is a p-type semiconductor region formed by the multi-stage ion implantation process described with reference to FIG. 10. The sub-column regions SC1, SC2, SC3, and SC4 aligned in the Z direction constitute one p-type column region PC. That is, each of the multiple p-type column regions PC has the sub-column region SC4 at a position farthest from the main surface of the epitaxial layer EP.

[0077] The maximum impurity concentration of sub-column region SC4 is equal to the maximum impurity concentration of sub-column region SC3. The distance between the depth of the maximum impurity concentration position in sub-column region SC3 and the depth of the maximum impurity concentration position in sub-column region SC4 is equal to, for example, the distance obtained by dividing the distance between the depth D1 of the maximum impurity concentration position in sub-column region SC1 and the depth D3 of the maximum impurity concentration position in sub-column region SC3.

[0078] 1 to 15, this modification can improve the breakdown voltage variation and the reliability of the semiconductor device. In addition, the number of sub-column regions constituting the p-type column region can be increased, thereby further increasing the breakdown voltage of the vertical power MOSFET.

[0079] <Variation 2> 17 shows a cross-sectional view of a semiconductor device according to Modification 2 of the present embodiment. Here, of the multiple sub-column regions, a sub-column region SC5 is further formed, located between sub-column region SC1 and sub-column region SC2. Like sub-column regions SC1, SC2, and SC3, sub-column region SC5 is a p-type semiconductor region formed by the multi-stage ion implantation process described with reference to FIG. 10. Sub-column regions SC1, SC2, SC3, and SC5 aligned in the Z direction constitute one p-type column region PC.

[0080] The impurity concentration in the region where sub-column regions SC1, SC2, and SC5 overlap is higher than the maximum impurity concentration of sub-column region SC3. The maximum impurity concentration position of sub-column region SC5 is located, for example, midway between depth D1 of the maximum impurity concentration position of sub-column region SC1 and depth D2 of the maximum impurity concentration position of sub-column region SC2.

[0081] 1 to 15, this modification can improve the breakdown voltage variation and enhance the reliability of the semiconductor device. Furthermore, by forming the sub-column region SC5, the breakdown voltage of the vertical power MOSFET can be further stabilized and the occurrence of breakdown voltage variation can be suppressed.

[0082] <Variation 3> 18 shows a planar layout of a semiconductor device according to Modification 3 of the present embodiment. As shown in Fig. 18, the plurality of p-type column regions PC may be arranged in rows and columns in the X and Y directions.

[0083] <Variation 4> 19 shows a planar layout of a semiconductor device according to Modification 4 of the present embodiment. As shown in Fig. 19, each of the multiple p-type column regions PC may extend in the Y direction and be aligned in the X direction. Here, the multiple p-type column regions PC and the epitaxial layers EP (drift regions) separated by the multiple p-type column regions PC are arranged in parallel and spaced apart at predetermined intervals.

[0084] The invention made by the present inventors has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention.

[0085] Although the above embodiment has been described with reference to a semiconductor device including a substrate and epitaxial layer made of Si (silicon), the semiconductor device may be made of SiC (silicon carbide) instead of Si. That is, the semiconductor substrate may be made of SiC.

[0086] Although the above embodiment has been described with respect to the case where an n-channel MOSFET is formed, the MOSFET may be a p-channel MOSFET. In the case where a p-channel MOSFET is formed, each of the semiconductor regions constituting the semiconductor device described above may be formed with an opposite conductivity type.

[0087] In addition, some of the contents described in the embodiment will be described below.

[0088] (Supplementary Note 1) (a) forming a semiconductor layer of a first conductivity type on a semiconductor substrate of the first conductivity type by epitaxial growth; (b) forming a trench from the main surface of the semiconductor layer to a depth of the semiconductor layer; (c) forming a gate electrode in the trench via an insulating film; (d) forming a semiconductor region of a second conductivity type opposite to the first conductivity type in the semiconductor layer, the semiconductor region contacting a side surface of the trench and being shallower than a bottom of the trench; (e) forming, in the semiconductor layer, a plurality of sub-column regions of the second conductivity type aligned in a first direction perpendicular to the main surface by performing ion implantation a plurality of times while changing energy in a stepwise manner using a protective film having openings formed on the semiconductor layer as a mask; and a plurality of sub-column regions formed side by side in the first direction constitute a plurality of column regions, each of the plurality of sub-column regions includes, in order from the side closest to the main surface, a first sub-column region, a second sub-column region, and a third sub-column region; a distance between a maximum position of the impurity concentration in the first sub-column region and a maximum position of the impurity concentration in the second sub-column region is smaller than a distance between the maximum position of the impurity concentration in the second sub-column region and a maximum position of the impurity concentration in the third sub-column region; a position where the impurity concentration in the first sub-column region is at a maximum is located closer to the main surface than a bottom surface of the gate electrode.

[0089] (Supplementary Note 2) In the method for manufacturing a semiconductor device according to (Supplementary Note 1), a region where the first sub-column region and the second sub-column region overlap has an impurity concentration higher than the impurity concentration at a maximum position of the impurity concentration in the third sub-column region;

[0090] (Supplementary Note 3) In the method for manufacturing a semiconductor device according to (Supplementary Note 2), the impurity concentration in the region where the first sub-column region and the second sub-column region overlap is two to five times the impurity concentration at a maximum position of the impurity concentration in the third sub-column region.

[0091] (Appendix 4) In the method for manufacturing a semiconductor device according to (Appendix 1), a width in the first direction of a first impurity region formed by integrating the first sub-column region and the second sub-column region is greater than a width in the first direction of the third sub-column region.

[0092] (Supplementary Note 5) In the method for manufacturing a semiconductor device according to (Supplementary Note 1), a distance between the maximum position of the impurity concentration in the first sub-column region and the maximum position of the impurity concentration in the second sub-column region is equal to or greater than 0.3 μm and less than 0.6 μm; a distance between the maximum position of the impurity concentration in the second sub-column region and the maximum position of the impurity concentration in the third sub-column region is equal to or greater than 0.6 μm and less than 1.0 μm;

[0093] (Supplementary Note 6) In the method for manufacturing a semiconductor device according to (Supplementary Note 4), the width of the first impurity region in the first direction is equal to or greater than 0.5 μm and less than 1.0 μm; the width of the third sub-column region in the first direction is equal to or greater than 0.2 μm and less than 0.5 μm.

[0094] (Supplementary Note 7) In the method for manufacturing a semiconductor device according to (Supplementary Note 1), a distance in the first direction between the main surface and the bottom surface of the gate electrode is equal to or greater than 0.8 μm and less than 1.0 μm; a distance in the first direction between the main surface and the position of maximum impurity concentration in the first sub-column region is not less than 0.7 μm and less than 0.9 μm.

[0095] (Supplementary Note 8) In the method for manufacturing a semiconductor device according to (Supplementary Note 1), the first sub-column region, the second sub-column region, and the third sub-column region have approximately the same width in a second direction perpendicular to the first direction.

[0096] (Supplementary Note 9) In the method for manufacturing a semiconductor device according to (Supplementary Note 1), the width of each of the first sub-column regions, the second sub-column regions, and the third sub-column regions in a second direction perpendicular to the first direction is not less than 0.52 μm and not more than 0.58 μm.

[0097] (Supplementary Note 10) In the method for manufacturing a semiconductor device according to (Supplementary Note 1), the plurality of sub-column regions further include a fourth sub-column region at a position farthest from the main surface, a maximum value of the impurity concentration of the fourth sub-column region is equal to the maximum value of the impurity concentration of the third sub-column region;

[0098] (Supplementary Note 11) In the method for manufacturing a semiconductor device according to (Supplementary Note 1), a fifth sub-column region is further provided between the first sub-column region and the second sub-column region, a region where the first sub-column region, the second sub-column region, and the fifth sub-column region overlap each other has an impurity concentration higher than the maximum value of the impurity concentration in the third sub-column region.

[0099] (Supplementary Note 12) In the method for manufacturing a semiconductor device according to (Supplementary Note 1), a superjunction structure is formed by the plurality of column regions and the semiconductor layer adjacent to the plurality of column regions. [Explanation of symbols]

[0100] BC diffusion region BR Body Region CP Contact Plug EP epitaxial layer GE gate electrode GT, TR trench HM Hard Mask IF1 insulating film IL Interlayer insulating film NC n-type column region OP opening PC, PCA p-type column region SB semiconductor substrate SC1, SC2, SC3, SC4, SC5, SCA, SCB, SCC subcolumn area SR Source Region SUB Multilayer semiconductor substrate

Claims

1. a semiconductor substrate; a first conductivity type drift region having a main surface formed on the semiconductor substrate; a plurality of column regions of a second conductivity type opposite to the first conductivity type, the column regions being spaced apart from each other in a plan view within the drift region; a gate electrode formed between each of the plurality of column regions; and the plurality of column regions are composed of a plurality of sub-column regions formed side by side in a first direction perpendicular to the main surface, each of the plurality of sub-column regions includes, in order from the side closest to the main surface, a first sub-column region, a second sub-column region, and a third sub-column region; a distance between a maximum position of the impurity concentration in the first sub-column region and a maximum position of the impurity concentration in the second sub-column region is smaller than a distance between a maximum position of the impurity concentration in the second sub-column region and a maximum position of the impurity concentration in the third sub-column region; a maximum position of the impurity concentration in the first sub-column region is located closer to the main surface than a bottom surface of the gate electrode.

2. 2. The semiconductor device according to claim 1, a region where the first sub-column region and the second sub-column region overlap has an impurity concentration higher than the impurity concentration at a maximum position of the impurity concentration in the third sub-column region.

3. 3. The semiconductor device according to claim 2, the impurity concentration in the region where the first sub-column region and the second sub-column region overlap is two to five times the impurity concentration at a maximum position of the impurity concentration in the third sub-column region.

4. 2. The semiconductor device according to claim 1, a width in the first direction of a first impurity region formed by integrating the first sub-column region and the second sub-column region is greater than a width in the first direction of the third sub-column region.

5. 2. The semiconductor device according to claim 1, a distance between the maximum position of the impurity concentration in the first sub-column region and the maximum position of the impurity concentration in the second sub-column region is equal to or greater than 0.3 μm and less than 0.6 μm; a distance between the maximum position of the impurity concentration in the second sub-column region and the maximum position of the impurity concentration in the third sub-column region is equal to or greater than 0.6 μm and less than 1.0 μm.

6. 5. The semiconductor device according to claim 4, the width of the first impurity region in the first direction is equal to or greater than 0.5 μm and less than 1.0 μm; the width of the third sub-column region in the first direction is equal to or greater than 0.2 μm and less than 0.5 μm.

7. 2. The semiconductor device according to claim 1, a distance in the first direction between the main surface and the bottom surface of the gate electrode is equal to or greater than 0.8 μm and less than 1.0 μm; a distance in the first direction between the main surface and a maximum position of the impurity concentration in the first sub-column region is equal to or greater than 0.7 μm and less than 0.9 μm.

8. 2. The semiconductor device according to claim 1, the first sub-column region, the second sub-column region, and the third sub-column region have substantially the same width in a second direction perpendicular to the first direction.

9. 2. The semiconductor device according to claim 1, the first sub-column region, the second sub-column region, and the third sub-column region each have a width in a second direction perpendicular to the first direction of 0.52 μm or more and 0.58 μm or less.

10. 2. The semiconductor device according to claim 1, the plurality of sub-column regions further include a fourth sub-column region at a position farthest from the main surface, a maximum value of the impurity concentration of the fourth sub-column region is equal to a maximum value of the impurity concentration of the third sub-column region.

11. 2. The semiconductor device according to claim 1, a fifth sub-column region between the first sub-column region and the second sub-column region, a region where the first sub-column region, the second sub-column region, and the fifth sub-column region overlap each other has an impurity concentration higher than the maximum value of the impurity concentration of the third sub-column region.

12. 2. The semiconductor device according to claim 1, the plurality of column regions and the drift regions separated by the plurality of column regions are arranged in parallel and spaced apart at predetermined intervals in a plan view.

13. 2. The semiconductor device according to claim 1, In a plan view, the column regions are arranged in a staggered pattern and spaced apart from one another.

14. 2. The semiconductor device according to claim 1, a superjunction structure is formed by the plurality of column regions and the drift region adjacent to the plurality of column regions.

15. 2. The semiconductor device according to claim 1, a semiconductor region of the second conductivity type formed on the drift region; a source region of the first conductivity type formed on the semiconductor region; an interlayer insulating film formed on the source region; a contact plug that penetrates the interlayer insulating film and the source region and reaches the semiconductor region, at a position that overlaps the column region in a plan view; The semiconductor device, wherein the gate electrode is formed to pass through the source region and the semiconductor region and reach the drift region.

Images