Substrate processing method and substrate processing apparatus

Abstract

To suppress variations in the amount of silicon etched in the depth direction of a pattern.SOLUTION: When etching silicon exposed on the side surfaces of a recessed pattern formed on a substrate inside a processing chamber by reacting it with a processing gas containing fluorine gas and ammonia gas, the temperature of the substrate is maintained at a first temperature at which the reaction between the processing gas and silicon is not promoted before the processing gas is supplied into the processing chamber, and the temperature of the substrate is raised from the first temperature in response to the supply of the processing gas into the processing chamber.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a substrate processing method and a substrate processing apparatus. [Background technology]

[0002] A technique has been proposed for etching a layer made of silicon (Si), silicon germanium (SiGe), or boron-doped silicon (SiB) formed on a wafer substrate using fluorine (F2) gas or ammonia (NH3) gas (see, for example, Patent Document 1).

[0003] In this technology, a process gas containing F2 gas and NH3 gas is supplied into a process chamber containing a wafer stage, and the F2 gas in the process gas reacts with, for example, a Si layer to generate silicon tetrafluoride (SiF4) without generating plasma from the process gas. The generated SiF4 easily sublimes, allowing the Si layer to be vaporized and removed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2017-224673 Summary of the Invention [Problem to be solved by the invention]

[0005] The technique according to the present disclosure suppresses the occurrence of variations in the amount of silicon etched in the depth direction of the pattern. [Means for solving the problem]

[0006] One aspect of the technology disclosed herein is a substrate processing method in which silicon exposed on the side surfaces of a recessed pattern formed on a substrate is etched by reacting it with a processing gas inside a processing chamber, the processing gas including at least fluorine gas and ammonia gas, and before the processing gas is supplied into the processing chamber, the temperature of the substrate is maintained at a first temperature at which reaction between the processing gas and the silicon is not promoted, and the temperature of the substrate is raised from the first temperature in response to the supply of the processing gas into the processing chamber. [Effects of the Invention]

[0007] According to the technique of the present disclosure, it is possible to suppress the occurrence of variations in the amount of silicon etched in the depth direction of the pattern. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a partial cross-sectional plan view schematically illustrating a configuration of a substrate processing apparatus according to an embodiment of the technology disclosed herein; [Figure 2] 1 is a cross-sectional view schematically showing the configuration of a process module that performs etching processing to remove silicon from a wafer. [Figure 3] FIG. 2 is an enlarged cross-sectional view illustrating the structure of a wafer to be etched. [Figure 4] 1A to 1C are process diagrams illustrating a conventional substrate processing method for etching a silicon layer. [Figure 5] 1A to 1C are process diagrams illustrating a substrate processing method according to an embodiment of the present invention for etching a silicon layer. [Figure 6] 6 is a graph showing a change in temperature of the mounting table when the substrate processing method of FIG. 5 is performed. [Figure 7] 10 is an enlarged cross-sectional view illustrating the structure of a modified example of a wafer to be subjected to an etching process. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] An embodiment of the technology according to the present disclosure will be described below with reference to the drawings. FIG. 1 is a partial cross-sectional plan view schematically illustrating the configuration of a substrate processing apparatus according to an embodiment of the technology according to the present disclosure. In FIG. 1, a substrate processing apparatus 10 includes a load / unload unit 11, a transfer module (hereinafter referred to as "TM") 12, and multiple process modules (hereinafter referred to as "PMs") 13. The load / unload unit 11 stores and loads wafers W as multiple substrates. The TM 12 transfers wafers W between the load / unload unit 11 and each PM 13. Each PM 13 performs various processes, such as etching and film formation, on wafers W loaded from the TM 12. In the substrate processing apparatus 10, the interior of the TM 12 is maintained in a vacuum atmosphere, and the interior of each PM 13 (more precisely, the interior of a chamber 28, described later) is also maintained in a vacuum atmosphere when various processes are performed on wafers W.

[0010] In the substrate processing apparatus 10, wafers W stored in the loading / unloading section 11 are transported by a transport arm 14 built into the TM 12, and the wafers W are placed on two mounting tables 15 arranged inside the PM 13. In the substrate processing apparatus 10, after various processes are performed on each wafer W in the PM 13, the processed wafers W are transported to the loading / unloading section 11 by the transport arm 14.

[0011] The loading / unloading section 11 has multiple load ports 17, a loader module (hereinafter referred to as "LM") 18, two load lock modules (hereinafter referred to as "LLM") 19, and a cooling storage 20. Each load port 17 functions as a mounting stage for mounting a FOUP 16, which serves as a container for accommodating multiple wafers W. The LM 18 receives wafers W from the FOUP 16 mounted on each load port 17, and stores processed wafers W received from each PM 13 in the FOUP 16. The LLM 19 temporarily holds wafers W for transferring wafers W between the LM 18 and the TM 12. The cooling storage 20 cools wafers W that have been subjected to heat processing, for example.

[0012] The LM 18 is a rectangular housing whose interior is under atmospheric pressure, with multiple load ports 17 arranged side by side on one side of the rectangular housing. The LM 18 also has a transfer arm (not shown) that is movable in the longitudinal direction of the rectangle. The transfer arm transfers wafers W from FOUPs 16 placed on each load port 17 to the LLM 19, or transfers wafers W from the LLM 19 to each FOUP 16.

[0013] Each LLM 19 temporarily holds the wafer W using a buffer plate 21 when transferring the wafer W between the LM 18 and the TM 12. Each LLM 19 also has a gate valve 22a for ensuring airtightness with respect to the LM 18 and a gate valve 22b for ensuring airtightness with respect to the TM 12. Furthermore, the LLM 19 has a gas introduction system and a gas exhaust system (neither of which are shown), and is configured so that the interior can be switched between an atmospheric pressure atmosphere and a vacuum atmosphere.

[0014] The TM 12 loads unprocessed wafers W from the load / unload section 11 into the PM 13 and unloads processed wafers W from the PM 13 to the load / unload section 11. The TM 12 is a rectangular housing with a vacuum atmosphere inside, and includes two transfer arms 14 that hold and move two wafers W, and a rotary table 23 that rotatably supports each transfer arm 14. The TM 12 also includes a rotary stage 24 on which the rotary stage 23 is mounted, and a guide rail 25 that guides the rotary stage 24 so that it can move in the longitudinal direction of the TM 12. The TM 12 is also connected to each LLM 19 and each PM 13 via a gate valve 22b and each gate valve 26 (described later). In the TM 12, the transfer arm 14 loads two wafers W from the LLM 19 to each PM 13 and unloads two processed wafers W from each PM 13 to another PM 13 or LLM 19.

[0015] The substrate processing apparatus 10 further includes a control unit 27. The control unit 27 includes a processing unit having a CPU that controls the operation of each component of the substrate processing apparatus 10, an input device (keyboard, mouse, etc.), an output device (printer, etc.), a display device (display, etc.), and a storage device (memory). The processing unit of the control unit 27 causes each component of the substrate processing apparatus 10 to perform various operations based on, for example, a processing recipe stored in the storage device.

[0016] 2 is a cross-sectional view schematically showing the configuration of a PM 13 that performs an etching process to remove Si from a wafer W. Although only one mounting table 15 is shown in FIG. 2, as described above, the PM 13 actually has two mounting tables 15. As shown in FIG. 2, the PM 13 has a sealed chamber 28 (processing chamber) that accommodates the wafer W therein, a gas supply mechanism 29 that supplies a processing gas into the chamber 28, and an exhaust mechanism 30 that exhausts the inside of the chamber 28.

[0017] Chamber 28 is composed of a main body 31 and a lid 32. Main body 31 has a generally cylindrical shape with an open top, and this opening is closed by lid 32. The joint between main body 31 and lid 32 is sealed with a seal member (not shown), ensuring airtightness inside chamber 28. A gas introduction nozzle 33 is inserted into the ceiling wall of lid 32 from above toward the inside of chamber 28. A load / unload port 34 is opened in main body 31 to load / unload wafer W between TM12, and gate valve 26 opens and closes load / unload port 34.

[0018] The mounting table 15 has a generally circular shape in a plan view and is installed at the bottom of the chamber 28. A temperature regulator 35 is provided inside the mounting table 15. The temperature regulator 35 is composed of, for example, a heater or a pipe through which a temperature-controlled medium circulates, and adjusts the temperature of the mounting table 15, thereby adjusting the temperature of the wafer W placed on the mounting table 15. An electrostatic chuck (ESC) 36 made of a dielectric material is also provided inside the mounting table 15. A DC power supply 37 is connected to the electrostatic chuck 36. When the DC power supply 37 applies a DC voltage to the electrostatic chuck 36, the electrostatic chuck 36 electrostatically chucks the wafer W placed on the mounting table 15 by electrostatic force. A temperature sensor (not shown) for detecting the temperature of the wafer W is provided near the wafer W placed on the mounting table 15.

[0019] The gas supply mechanism 29 includes an F2 gas supply source 38 that supplies F2 gas, an NH3 gas supply source 39 that supplies NH3 gas, an Ar gas supply source 40 that supplies argon (Ar) gas, and an N2 gas supply source 41 that supplies nitrogen (N2) gas. An F2 gas supply pipe 42 is connected to the F2 gas supply source 38, an NH3 gas supply pipe 43 is connected to the NH3 gas supply source 39, an Ar gas supply pipe 44 is connected to the Ar gas supply source 40, and an N2 gas supply pipe 45 is connected to the N2 gas supply source 41. These gas supply pipes 42 to 45 are connected to a collecting pipe 46, which is connected to the gas introduction nozzle 33. The gas supply mechanism 29 supplies process gases including F2 gas, NH3 gas, Ar gas, and N2 gas from the gas introduction nozzle 33 into the chamber 28 via the gas supply pipes 42 to 45 and the collecting pipe 46. A flow rate controller 47 that opens and closes each pipe and controls the flow rate of each gas is provided to the F2 gas supply pipe 42, the NH3 gas supply pipe 43, the Ar gas supply pipe 44, and the N2 gas supply pipe 45. The flow rate controller 47 is configured with, for example, an on-off valve and a mass flow controller (MFC). A shower plate may be provided above the chamber 28, and the process gas may be supplied into the chamber 28 in a shower-like manner via the shower plate.

[0020] Of the gases contained in the process gas, F2 gas and NH3 gas are used as etchants in etching the silicon layer, as described below, and Ar gas and N2 gas are used as purge gas and dilution gas. The process gas may also contain hydrogen fluoride (HF) gas. HF gas is used to remove native oxide films covering the patterns and surfaces of each layer on the wafer W and for termination processing after etching the silicon layer.

[0021] The exhaust mechanism 30 includes an exhaust pipe 49 connected to an exhaust port 48 that opens into the chamber 28, an automatic pressure control valve (APC) 50 provided on the exhaust pipe 49 for controlling the pressure inside the chamber 28, and a vacuum pump 51 for evacuating the inside of the chamber 28.

[0022] In the PM13, various components such as the chamber 28 and the mounting table 15 are made of aluminum (Al). The Al material constituting the chamber 28 may be solid, or may be anodized on the wall surface facing the inside of the main body 31. It is also preferable that a highly wear-resistant oxide coating (e.g., a thermally sprayed film made of alumina or yttria) is formed on the surface of the Al material constituting the mounting table 15 after the anodization.

[0023] 3A and 3B are enlarged cross-sectional views illustrating the structure of a wafer W to be etched in PM13 of Fig. 2, in which Fig. 3A is a diagram illustrating the configuration of a pattern formed on the wafer W, and Fig. 3B is an enlarged cross-sectional view of a portion of the pattern in Fig. 3A. While Fig. 3 shows only one pattern as an example, in reality, many patterns having similar configurations are formed on the wafer W.

[0024] As shown in FIG. 3(A), the wafer W has a multilayer structure 53 in which a large number of various layers are stacked on the surface of a base 52, and a concave pattern 54, for example, a hole, is formed so as to penetrate the multilayer structure 53 in the stacking direction (thickness direction of the multilayer structure 53). The depth of the pattern 54 is at least 4 μm or more, and may be 8 μm or more. Note that this pattern 54 is formed by etching in another PM 13 or the like before the wafer W is loaded into PM 13 (FIG. 2) where etching processing to remove Si is performed. Furthermore, the pattern formed in the multilayer structure 53 is a hole, but it may also be a trench.

[0025] As shown in Fig. 3(B), the stacked structure 53 is made up of a number of Si layers 55, silicon nitride (SiN) layers 56 (other layers), and silicon oxide (SiO2) layers 57. In the stacked structure 53, a SiN layer 56, a SiO2 layer 57, and a SiN layer 56 are interposed between a lower Si layer 55 and an upper Si layer 55, in this order from below (Fig. 3(B)). Therefore, the Si layer 55 is sandwiched between the SiN layers 56 on the top and bottom, and a SiO2 layer 57 is interposed between each of the SiN layers 56 that sandwich the Si layer 55. The silicon constituting the Si layer 55 may be either polysilicon (polycrystalline silicon) or episilicon (single crystal silicon).

[0026] As described above, the pattern 54 penetrates the stacked structure 53 in the stacking direction, so that the Si layer 55, the SiN layer 56, and the SiO2 layer 57 are exposed on the side surfaces of the pattern 54. In the following drawings, the Si layer 55 is shown with cross-hatching, the SiN layer 56 is shown with white outlines, and the SiO2 layer 57 is shown with dark lines.

[0027] In the technique disclosed herein, only the Si layers 55 in the stacked structure 53 are selectively etched, and the pattern 54 is partially (at the locations of the Si layers 55) expanded horizontally (left and right in the drawing). At this time, the F gas in the process gas and the Si in the Si layer 55 undergo a chemical reaction shown in the following formula (1) to produce SiF. In addition, the NH gas acts as a catalyst to promote the chemical reaction shown in the following formula (1).

[0028] Si + 2F2+ NH3→ SiF4↑ + NH3…(1)

[0029] Here, since the boiling point of SiF4 under atmospheric pressure is −95.5° C., SiF4 easily sublimates, and the sublimated SiF4 is exhausted from the chamber 28 by the exhaust mechanism 30. As a result, the Si layer 55 is etched and removed.

[0030] At this time, a part of the NH3 gas undergoes a chemical reaction with the F2 gas as shown in the following formula (2), producing hydrogen (H2) gas.

[0031] 3F2 + 2NH3 → 2NF3 + 3H2…(2)

[0032] The generated H2 gas reacts with the sublimated SiF4 and NH3 gases in a chemical reaction as shown in formula (3) below, producing ammonia fluorite silicon (AFS), a silicon-containing by-product.

[0033] SiF4+ H2+ F2+ 2NH3→ (NH4)2SiF4…(3)

[0034] This AFS also sublimes relatively easily, and like the sublimated SiF4, the sublimated AFS is also exhausted from the chamber 28 by the exhaust mechanism 30. Note that no plasma is used in any of the chemical reactions shown in the above formulas (1) to (3).

[0035] Among the chemical reactions represented by the above formulas (1) to (3), the chemical reaction represented by formula (1) is not promoted unless the wafer W reaches a relatively high temperature, for example, 80°C. For example, if the wafer W is maintained at room temperature or a slightly higher temperature, for example, 40°C, the chemical reaction represented by formula (1) is unlikely to occur. Therefore, in the past, in order to promote the chemical reaction represented by formula (1) and improve throughput, the wafer W was preheated to a temperature near 80°C before supplying a process gas containing F gas or NH gas into the chamber 28. Hereinafter, a temperature at which the chemical reaction represented by formula (1) is promoted, for example, 80°C, will be referred to as the "reaction promotion temperature," and a temperature at which the chemical reaction represented by formula (1) is unlikely to occur, for example, 40°C, will be referred to as the "reaction stop temperature."

[0036] 4 is a process diagram illustrating a conventional substrate processing method for etching a Si layer 55. In the conventional substrate processing method, the temperature of a wafer W is raised to a reaction acceleration temperature, and then a processing gas containing F gas and NH gas is supplied toward the wafer W. Meanwhile, in the wafer W, a pattern 54 formed in a stacked structure 53 has a depth of at least 4 μm or more, and not only is the absolute value of the depth of the pattern 54 large, but the aspect ratio is also high. Therefore, immediately after the supply of the processing gas starts, the etchant (indicated by "○" in the figure) serving as the processing gas has difficulty reaching the lower part of the pattern 54, and the etchant is unevenly distributed upward within the pattern 54 (FIG. 4(A)).

[0037] At this time, the temperature of the wafer W has already risen to the reaction promotion temperature, so the chemical reaction shown in the above formula (1) occurs, but due to the etchant unevenly distributed above, the chemical reaction shown in the above formula (1) actively progresses above the pattern 54. On the other hand, because there is almost no etchant below the pattern 54, the chemical reaction shown in the above formula (1) progresses only slightly (FIG. 4(B)).

[0038] As a result, in the depth direction of the pattern 54, the Si layers 55 are sufficiently etched in the upper part but are not etched very much in the lower part, resulting in variations in the amount of etching of the Si layers 55 in the depth direction of the pattern 54 (FIG. 4(C)). Such variations in the amount of etching of the Si layers 55 can cause product defects in semiconductor devices including the stacked structure 53, so it is necessary to suppress the variations in the amount of etching of the Si layers 55 in the depth direction of the pattern 54.

[0039] In contrast, in the technique according to the present disclosure, the temperature of the wafer W is raised from the reaction stop temperature to the reaction promotion temperature in response to the supply of the processing gas toward the wafer W.

[0040] 5 is a process diagram illustrating the substrate processing method of this embodiment for etching the Si layer 55. The following process is performed by the control unit 27 of the substrate processing apparatus 10 controlling the operation of each component of the PM 13.

[0041] In the substrate processing method of this embodiment, first, the wafer W is loaded into the chamber 28 of the PM 13 and placed on the mounting table 15. Thereafter, the exhaust mechanism 30 evacuates the chamber 28 to maintain a vacuum atmosphere inside the chamber 28. Then, the temperature of the mounting table 15 is maintained at a reaction stop temperature (first temperature) by the temperature regulator 35 of the mounting table 15. At this time, the temperature of the wafer W is also maintained at the reaction stop temperature due to heat transfer from the mounting table 15 to the wafer W.

[0042] Next, the gas supply mechanism 29 supplies a process gas containing F gas, NH gas, Ar gas, and N gas into the chamber 28. In response to the supply of the process gas into the chamber 28, the temperature regulator 35 of the mounting table 15 raises the temperature of the mounting table 15 from the reaction stop temperature. At this time, heat is transferred from the mounting table 15 to the wafer W, and the temperature of the wafer W also rises from the reaction stop temperature.

[0043] When not much time has passed since the process gas began to be supplied into the chamber 28, the etchant (indicated by "○" in the figure) serving as the process gas has difficulty reaching the lower part of the pattern 54, as in the conventional etching of each Si layer 55. Therefore, the etchant is unevenly distributed upward inside the pattern 54 (FIG. 5(A)). However, at this time, heat is not sufficiently transferred from the mounting table 15 to the wafer W, so the temperature of the wafer W remains at the reaction stop temperature, and the chemical reaction represented by the above formula (1) is unlikely to occur.

[0044] Then, while the chemical reaction represented by the above formula (1) is difficult to occur, the etchant diffuses within the pattern 54 over time, and the etchant becomes almost evenly distributed (evenly distributed) in the vertical direction of the pattern 54 (Figure 5(B)).

[0045] Thereafter, the temperature of the wafer W begins to rise from the reaction stop temperature due to heat transfer from the mounting table 15. At this time, the chemical reaction shown in formula (1) above proceeds not only above the pattern 54 but also below the pattern 54 due to the etchant that is distributed almost uniformly in the vertical direction of the pattern 54 (FIG. 5(C)).

[0046] As a result, the Si layers 55 are sufficiently etched not only above but also below the pattern 54 in the depth direction, thereby suppressing variations in the amount of etching of the Si layers 55 in the depth direction of the pattern 54 (FIG. 5(D)).

[0047] Fig. 6 is a graph showing the temperature change of the mounting table 15 when performing the substrate processing method of Fig. 5. As shown in Fig. 6, after the wafer W is loaded into the chamber 28 of the PM 13 and placed on the mounting table 15, the temperature of the mounting table 15 is adjusted to a reaction stop temperature (e.g., 40°C) by the temperature regulator 35.

[0048] After a predetermined time has elapsed, the gas supply mechanism 29 starts supplying the processing gas into the chamber 28, and simultaneously the temperature regulator 35 starts increasing the temperature of the mounting table 15. This predetermined time is a necessary and sufficient time for the temperature of the wafer W mounted on the mounting table 15 to reach the reaction stop temperature through heat transfer from the mounting table 15 and then to stabilize at the reaction stop temperature. This predetermined time is determined through a preliminary confirmation experiment or the like.

[0049] While the supply of the processing gas continues, the temperature of the mounting table 15 also continues to rise, but it takes time for heat to be transferred from the mounting table 15 to the wafer W. Therefore, the temperature of the wafer W does not rise immediately after the temperature of the mounting table 15 starts to rise, but is maintained at the reaction stop temperature for a while, for example, 30 seconds after the temperature of the mounting table 15 starts to rise. As a result, the chemical reaction represented by the above formula (1) is unlikely to occur on the wafer W, and the etchant, which is the processing gas, diffuses inside the pattern 54. As a result, about 30 seconds after the temperature of the mounting table 15 starts to rise, the etchant becomes approximately uniformly distributed in the vertical direction of the pattern 54, as shown in FIG. 5(B).

[0050] Then, about 30 seconds after the temperature of the mounting table 15 starts to rise, the temperature of the wafer W starts to rise due to heat transfer from the mounting table 15, and the chemical reaction shown in the above formula (1) starts to occur. At this time, since the etchant is present almost uniformly in the vertical direction of the pattern 54, each Si layer 55 starts to be etched almost uniformly.

[0051] However, if the supply of the processing gas continues even after the temperature of the wafer W starts to rise from the reaction stop temperature, the newly supplied etchant will undergo the chemical reaction represented by the above formula (1) when it reaches above the pattern 54, and will not reach below the pattern 54. Therefore, only the etching of the Si layers 55 above the pattern 54 is promoted, which may result in variations in the amount of etching of the Si layers 55 in the depth direction of the pattern 54.

[0052] Therefore, in this embodiment, the supply of the process gas is stopped when the temperature of the wafer W starts to rise. Specifically, the supply of the process gas is stopped 30 seconds after the temperature of the mounting table 15 starts to rise. As a result, when the temperature of the wafer W starts to rise from the reaction stop temperature, no new etchant is added to the inside of the pattern 54, and etching of each Si layer 55 is started only by the etchant that is approximately uniformly present in the vertical direction of the pattern 54. As a result, it is possible to suppress variations in the etching amount of each Si layer 55 in the depth direction of the pattern 54.

[0053] Even after 30 seconds have passed since the start of the temperature increase of the mounting table 15 and the supply of the processing gas has been stopped, the temperature regulator 35 continues to increase the temperature of the mounting table 15, and the temperature of the wafer W also increases toward the reaction promotion temperature (e.g., 80°C). In other words, the supply of the processing gas is stopped while the temperature of the mounting table 15 is increasing from the reaction stop temperature.

[0054] After that, 60 seconds have passed since the start of the temperature increase of the mounting table 15, and the temperature regulator 35 stops increasing the temperature of the mounting table 15. By this time, the temperature of the mounting table 15 has almost reached the reaction promotion temperature, and later, the temperature of the wafer W also reaches the reaction promotion temperature. This promotes the chemical reaction shown in the above formula (1), and etching of each Si layer 55 progresses.

[0055] Then, the temperature of the mounting table 15 is maintained at the reaction acceleration temperature for a predetermined time by the temperature regulator 35, and then the temperature regulator 35 starts to lower the temperature of the mounting table 15. This predetermined time is a necessary and sufficient time for the etchant present inside the pattern 54 to complete etching of each Si layer 55 on the wafer W whose temperature reaches the reaction acceleration temperature following the mounting table 15. This predetermined time is also determined through a preliminary confirmation experiment or the like.

[0056] Next, when the temperature of the mounting table 15 has dropped sufficiently, the wafer W mounted on the mounting table 15 is carried out of the chamber .

[0057] In the example shown in FIG. 6, in order to improve throughput by causing the chemical reaction represented by the above formula (1) to occur as soon as possible after the supply of the processing gas is started, the temperature of the mounting table 15 is raised from the reaction stop temperature at the same time as the supply of the processing gas is started.

[0058] However, by raising the temperature of the mounting table 15 from the reaction stop temperature after the supply of the processing gas is started, the start of the chemical reaction represented by the above formula (1) may be slightly delayed to allow enough time for the etchant to reach below the pattern 54. This ensures that the etchant is uniformly distributed in the vertical direction of the pattern 54, thereby reliably preventing variations in the etching amount of each Si layer 55 in the depth direction of the pattern 54.

[0059] The applicant also performed a conventional substrate processing method and the substrate processing method of the present embodiment, and compared the variations in the etching amount of each Si layer 55 in the depth direction of pattern 54. The etching amount here refers to the amount of each Si layer 55 etched horizontally from the side surface of pattern 54.

[0060] First, as Comparative Example 1, the applicant etched each Si layer 55 of pattern 54 by a conventional substrate processing method (FIG. 4) and confirmed the etching amount of each Si layer 55. As a result, the etching amount of the upper Si layer 55 of pattern 54 in Comparative Example 1 was 81.7 nm, while the etching amount of the central Si layer 55 was 63.2 nm, and the etching amount of the lower Si layer 55 was 60.5 nm. That is, it was confirmed that in Comparative Example 1, the etching amount of each Si layer 55 varies in the depth direction of pattern 54.

[0061] Next, the present applicant etched each Si layer 55 of pattern 54 using the substrate processing method of this embodiment ( FIG. 5 ) as an example, and confirmed the etching amount of each Si layer 55. As a result, the etching amount of the upper Si layer 55 of pattern 54 in the example was 49.0 nm, while the etching amount of the central Si layer 55 was 46.6 nm, and the etching amount of the lower Si layer 55 was 52.6 nm. That is, it was confirmed that the example had smaller variations in the etching amount of each Si layer 55 in the depth direction of pattern 54 than the conventional substrate processing method. Therefore, it was found that the substrate processing method of this embodiment can suppress variations in the etching amount of each Si layer 55 in the depth direction of pattern 54.

[0062] Furthermore, as Comparative Example 2, the applicant performed the substrate processing method of this embodiment by continuously supplying processing gas until 40 seconds had elapsed since the temperature of the mounting table 15 began to rise, thereby etching each Si layer 55 of the pattern 54, and confirmed the amount of etching of each Si layer 55.

[0063] In Comparative Example 2, the supply of the processing gas continues even after 30 seconds have passed since the start of heating the mounting table 15 and the temperature of the wafer W has begun to rise from the reaction stop temperature. Therefore, the etchant supplied after 30 seconds has passed reaches the pattern 54 of the wafer W whose temperature has risen from the reaction stop temperature, and when it reaches above the pattern 54, it reacts with the Si layers 55 above the pattern 54 and does not reach below. That is, in Comparative Example 2, the etching amount of the Si layer 55 above the pattern 54 is greater than the etching amount of the Si layer 55 below the pattern 54, and it is expected that the etching amount of each Si layer 55 in the depth direction of the pattern 54 will vary.

[0064] The results of Comparative Example 2 showed that the etching amount of the Si layer 55 above the pattern 54 was 88.6 nm, while the etching amount of the Si layer 55 at the center was 58.6 nm, and the etching amount of the Si layer 55 below the pattern 54 was 47.8 nm. That is, in Comparative Example 2, it was confirmed that, as expected, the etching amount of the Si layer 55 above the pattern 54 was greater than the etching amount of the Si layer 55 below the pattern 54. This shows that it is preferable to stop the supply of the process gas after the temperature of the wafer W starts to rise from the reaction stop temperature.

[0065] Although the preferred embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments, and various modifications and changes are possible within the scope of the gist of the present disclosure.

[0066] For example, the layered structure 53 of the wafer W to which the substrate processing method of this embodiment is applied is composed of multiple Si layers 55, SiN layers 56, and SiO2 layers 57, but it may not include the SiO2 layer 57. In this case, Si layers 55 and SiN layers 56 are alternately stacked (FIG. 7(A)). The substrate processing method of this embodiment may also be applied to etching a single Si layer 58 (FIG. 7(B)). In this case, when the substrate processing method of this embodiment is performed, a pattern 59 as a hole or trench penetrating the single Si layer 58 in the thickness direction is expanded horizontally (left and right in the figure).

[0067] Furthermore, although an electrostatic adsorption unit 36 ​​is provided inside the mounting table 15 of the PM 13 that performs the substrate processing method of this embodiment, the electrostatic adsorption unit 36 ​​does not need to be provided if heat transfer from the mounting table 15 to the wafer W is possible.

[0068] 6, the temperature regulator 35 stops increasing the temperature of the mounting table 15 60 seconds after the start of increasing the temperature of the mounting table 15. That is, the temperature increase time of the mounting table 15 is 60 seconds. However, if the temperature regulator 35 has a high temperature control capability and can increase the temperature of the mounting table 15 from the reaction stop temperature to the reaction promotion temperature in an even shorter time, the temperature increase time of the mounting table 15 may be further shortened. However, in this case, it is necessary to stop the supply of the process gas while the temperature of the mounting table 15 is increasing from the reaction stop temperature. [Explanation of symbols]

[0069] W wafer 10. Substrate processing equipment 13 PM 15 Mounting table 28 Chamber 35 Temperature regulator 53 Laminated structure 54,59 patterns 55,58 Si layer 56 SiN layer

Claims

1. A substrate processing method for etching silicon exposed on a side surface of a recessed pattern formed on a substrate by reacting the silicon with a processing gas in a processing chamber, the method comprising: the processing gas contains at least fluorine gas and ammonia gas; before the processing gas is supplied into the processing chamber, the temperature of the substrate is maintained at a first temperature at which a reaction between the processing gas and the silicon is not promoted; a temperature of the substrate being increased from the first temperature in response to the supply of the processing gas into the processing chamber;

2. 2. The substrate processing method according to claim 1, wherein the supply of the processing gas into the processing chamber is stopped during the temperature increase of the substrate from the first temperature.

3. The substrate is placed on a mounting table provided inside the processing chamber; 2. The substrate processing method according to claim 1, wherein the temperature of the mounting table is increased from the first temperature simultaneously with the start of supplying the processing gas into the processing chamber.

4. The substrate is placed on a mounting table provided inside the processing chamber; 2. The substrate processing method according to claim 1, wherein the temperature of the mounting table is increased from the first temperature after the supply of the processing gas into the processing chamber is started.

5. 2. The substrate processing method according to claim 1, wherein the pattern has a depth of 4 [mu]m or more.

6. 6. The substrate processing method according to claim 5, wherein the pattern has a depth of 8 [mu]m or more.

7. the substrate has a laminated structure in which a plurality of silicon layers are laminated; In the stacked structure, another layer is interposed between each of the silicon layers, The substrate processing method according to claim 1 , wherein the pattern is formed so as to penetrate the laminated structure in a lamination direction.

8. 8. The substrate processing method according to claim 7, wherein the other layer is made of silicon nitride.

9. the substrate has a single silicon layer; 2. The substrate processing method according to claim 1, wherein the pattern is formed so as to penetrate the single silicon layer in a thickness direction.

10. the mounting table has a temperature regulator, 5. The substrate processing method according to claim 3, wherein the temperature regulator increases the temperature of the substrate.

11. 2. The substrate processing method according to claim 1, wherein the etching reaction between the processing gas and the silicon is carried out without generating plasma from the processing gas.

12. The substrate processing method according to claim 1 , wherein the pattern is a trench or a hole.

13. A substrate processing apparatus comprising: a processing chamber that accommodates a substrate therein; and a temperature regulator that adjusts the temperature of the substrate; a processing gas is supplied into the processing chamber; and silicon exposed on a side surface of a recessed pattern formed on the substrate is etched by reacting with the processing gas inside the processing chamber, the processing gas contains at least fluorine gas and ammonia gas; Before the processing gas is supplied into the processing chamber, the temperature regulator maintains the temperature of the substrate at a first temperature at which a reaction between the processing gas and the silicon is not promoted; The substrate processing apparatus, wherein the temperature regulator increases the temperature of the substrate from the first temperature in response to the supply of the processing gas into the processing chamber.

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