Semiconductor device

Abstract

To provide a technique capable of suppressing power loss.SOLUTION: A semiconductor device includes a first main surface side gate structure that is provided on a first main surface and controls a first conductive channel in a base layer, and a second main surface side gate structure that is provided on a second main surface and controls a second conductive channel in a first collector layer. A first dense region in which three or more continuous second main surface side gate structures are arranged, and a first sparse region in which three or more continuous second main surface side gate structures are arranged at density lower than that of the first dense region are defined.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] In recent years, IGBTs (Insulated Gate Bipolar Transistors) have been proposed, in which gate structures are provided on both sides of a semiconductor substrate. For example, in the technology disclosed in Patent Document 1, a plurality of gate structures are provided on the front surface of a semiconductor substrate, and a plurality of gate structures are provided adjacent to each other on the back surface of the semiconductor substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-82725 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in conventional technology, only one region tends to function as an IGBT and the other tends to function as a diode, and each region is so narrow that it is difficult to inject carriers into that region, which leaves room for improvement in power loss.

[0005] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and aims to provide a technology that can suppress power loss. [Means for solving the problem]

[0006] A semiconductor device according to the present disclosure includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, and including a first conductivity type drift layer between the first main surface and the second main surface, a base layer of a second conductivity type provided on the first main surface side of the drift layer, a source layer of the first conductivity type provided on the first main surface side of the base layer, a first main surface side gate structure provided on the first main surface and controlling a first conductive channel in the base layer, and a first collector of the second conductivity type provided on the second main surface side of the drift layer. a second collector layer of the first conductivity type provided on the second main surface side of the first collector layer; and a second main surface side gate structure provided on the second main surface and controlling a second conductive channel in the first collector layer, wherein a plurality of the second main surface side gate structures are arranged along a predetermined arrangement direction, and a first dense region in which three or more consecutive second main surface side gate structures are arranged and a first sparse region in which three or more consecutive second main surface side gate structures are arranged at a density lower than that of the first dense region are defined. [Effects of the Invention]

[0007] According to the present disclosure, a first dense region in which three or more consecutive second principal surface side gate structures are arranged and a first sparse region in which three or more consecutive second principal surface side gate structures are arranged at a lower density than the first dense region are defined. This configuration can reduce power loss. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Figure 2] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a second embodiment. [Figure 3] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a third embodiment. [Figure 4] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a fourth embodiment. [Figure 5] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a fourth embodiment. [Figure 6]FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a fifth embodiment. [Figure 7] FIG. 13 is a cross-sectional view showing the configuration of a semiconductor device according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the accompanying drawings. Features described in each of the following embodiments are exemplary, and not all features are necessarily required. In addition, in the following description, similar components in multiple embodiments are denoted by the same or similar reference numerals, and different components will be mainly described. In addition, in the following description, specific positions and directions such as "upper," "lower," "left," "right," "front," or "back" may not necessarily correspond to positions and directions in actual implementation.

[0010] Furthermore, a certain portion having a higher concentration than another portion may mean, for example, that the average concentration of a certain portion is higher than the average concentration of another portion. Conversely, a certain portion having a lower concentration than another portion may mean, for example, that the average concentration of a certain portion is lower than the average concentration of another portion. Furthermore, in the following description, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may also be p-type and the second conductivity type may also be n-type. Furthermore, in the following description, n - has a lower n-type impurity concentration than n, + has a higher n-type impurity concentration than n, and p + means that the p-type impurity concentration is higher than p.

[0011] <First Embodiment> 1 is a cross-sectional view showing the configuration of a semiconductor device according to the present embodiment 1. The semiconductor device described below is an IGBT, but is not limited to this.

[0012] The semiconductor device of FIG. 1 includes a semiconductor substrate 51, interlayer insulating films 4 and 9, barrier metals 5a and 5b, an emitter electrode 6, a termination electrode 6a, a collector electrode 7, a first active trench gate 11, a second active trench gate 18, an insulating film 30, a semi-insulating film 33, and a termination protective film 34.

[0013] The semiconductor substrate 51 is a substrate having a first main surface (the upper surface in FIG. 1) and a second main surface (the lower surface in FIG. 1) opposite to the first main surface. The semiconductor substrate 51 includes at least one of a normal semiconductor wafer and an epitaxially grown layer. In this specification, for example, "at least one of A, B, C, ..., and Z" means any one of all combinations of one or more types selected from the group A, B, C, ..., and Z.

[0014] The semiconductor substrate 51 may be made of ordinary silicon (Si), or may be made of a wide bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond, etc. When the semiconductor substrate 51 is made of a wide bandgap semiconductor, stable operation of the semiconductor device under high temperatures and high voltages and high switching speeds are possible.

[0015] An active region is defined on the left side of FIG. 1, and a termination region is defined on the right side of FIG. 1. Semiconductor elements such as IGBTs are provided in the active region, and a structure for maintaining the breakdown voltage of the active region is provided in the termination region. Below, the configuration of the active region will be described, followed by the configuration of the termination region.

[0016] <Configuration of the active region> The semiconductor substrate 51 of the active region of FIG. - n-type drift layer 1, n-type carrier accumulation layer 2, n-type buffer layer 3, and n + a p-type source layer 13, a p-type base layer 15, a p-type collector layer 16, and an n + and an n-type collector layer 19. Note that the n-type carrier accumulation layer 2 and the n-type buffer layer 3 are not essential.

[0017] n - The n-type drift layer 1 is provided between the first and second major surfaces of the semiconductor substrate 51. The n-type carrier accumulation layer 2 is - The p-type base layer 15 is provided on the first main surface side of the n-type drift layer 1. The p-type base layer 15 is connected to the n-type carrier accumulation layer 2 via the n-type carrier accumulation layer 2. - The first electrode is provided on the first main surface side of the drift layer 1.

[0018] The source layer is n + The n-type source layer 13 is provided on the first main surface side of the p-type base layer 15. Although not shown, in a cross section different from the cross section of FIG. + The p-type source layer 13 is not provided, and the p-type base layer 15 extends to the first main surface side and is electrically connected to the emitter electrode 6.

[0019] The first active trench gate 11 is a first main surface side gate structure including a trench structure, and is provided on the first main surface side. The first active trench gate 11 includes a gate trench electrode 11a and a gate trench insulating film 11b. + The n-type carrier accumulation layer 2 is formed by passing through the p-type base layer 15 and the n-type source layer 13 from the upper surface of the p-type - The first active trench gates 11 are provided in trenches that reach the gate electrode 11b. The gate trench electrodes 11a are provided on the inner surfaces of the trenches via gate trench insulating films 11b, and are electrically connected to gate pads (not shown) via gate wiring G1. In the first embodiment, a plurality of first active trench gates 11 are arranged along a predetermined arrangement direction (the left-right direction in FIG. 1), but only one first active trench gate 11 may be provided.

[0020] The interlayer insulating film 4 is provided on the first active trench gate 11. The barrier metal 5a is formed on the n-type semiconductor layer exposed from the interlayer insulating film 4. + The barrier metal 5a is provided on the n-type source layer 13. The barrier metal 5a includes a metal such as Ti, TiN, or TiSi. + The source layer 13 is in ohmic contact with the source layer 13 .

[0021] The emitter electrode 6 is insulated from the gate trench electrode 11a by the interlayer insulating film 4 and is connected to the n-type gate electrode 11b via the barrier metal 5a. + The emitter electrode 6 is electrically connected to the n-type source layer 13. The emitter electrode 6 contains a metal such as aluminum or an aluminum alloy. The barrier metal 5a is not essential, and the emitter electrode 6 is + It may be directly connected to the source layer 13 .

[0022] The above has described the configuration provided in the active region on the first main surface side of semiconductor substrate 51. A similar configuration is also provided in the active region on the second main surface side of semiconductor substrate 51. Below, the configuration provided in the active region on the second main surface side of semiconductor substrate 51 will be described.

[0023] The n-type buffer layer 3 is - The p-type collector layer 16, which is the first collector layer, is provided on the second main surface side of the n-type drift layer 1. The p-type collector layer 16 is connected to the n-type buffer layer 3 via the n-type buffer layer 3. - The second electrode is provided on the second main surface side of the drift layer 1.

[0024] The second collector layer, n + The n-type collector layer 19 is provided on the second main surface side of the p-type collector layer 16. Although not shown, in a cross section different from the cross section of FIG. + The p-type collector layer 19 is not provided, and the p-type collector layer 16 extends to the second main surface side and is electrically connected to the collector electrode 7.

[0025] The second active trench gate 18 is a second main surface side gate structure including a trench structure, and is provided on the second main surface side. The second active trench gate 18 includes a gate trench electrode 18a and a gate trench insulating film 18b. + The n-type collector layer 19 is formed from the lower surface of the p-type collector layer 19 through the p-type collector layer 16 and the n-type buffer layer 3. -The second active trench gates 18 are provided in trenches that reach the first drift layer 1. The gate trench electrodes 18a are provided on the inner surfaces of the trenches via gate trench insulating films 18b, and are electrically connected to gate pads (not shown) via gate wiring G2. The second active trench gates 18 are arranged along the aforementioned arrangement direction (the left-right direction in FIG. 1).

[0026] In the first embodiment, a dense region 61, which is a first dense region, and a sparse region 62, which is a first sparse region, are defined for the plurality of second active trench gates 18. In the dense region 61, three or more consecutive second active trench gates 18 are arranged. In the sparse region 62, three or more consecutive second active trench gates 18 are arranged at a lower density than in the dense region 61. Note that, for example, "n consecutive second active trench gates 18" means including, among the plurality of arranged second active trench gates 18, the first second active trench gate 18, the second second active trench gate 18 closest to the first second active trench gate 18, the third second active trench gate 18 other than the first second active trench gate 18 and closest to the second second active trench gate 18, ..., the nth second active trench gate 18 other than the (n-2)th second active trench gate 18 and closest to the (n-1)th second active trench gate 18. In the following description, "contiguous" has the same meaning as above. "Density" refers to the number of three or more consecutive second active trench gates 18 per total spacing between the three or more consecutive second active trench gates 18.

[0027] As an example, in the first embodiment, the spacing between six or more second active trench gates 18, including three or more second active trench gates 18 in the dense region 61 and three or more second active trench gates 18 in the sparse region 62, is configured to monotonically increase in the direction from the dense region 61 to the sparse region 62. In the example of FIG. 1 , the spacing between six second active trench gates 18, including three second active trench gates 18 in the dense region 61 and three second active trench gates 18 in the sparse region 62, monotonically increases in the direction from the dense region 61 to the sparse region 62. As a result, the density of the three second active trench gates 18 in the sparse region 62 is lower than the density of the three second active trench gates 18 in the dense region 61.

[0028] 1, the dense region 61 is defined on the outer periphery side of the semiconductor substrate 51, that is, on the termination region side. Note that, as in the example of FIG. 1, an intermediate region 63 having a lower density than the dense region 61 and a higher density than the sparse region 62 may be provided. The intervals between the multiple second active trench gates 18 in the dense region 61, intermediate region 63, and sparse region 62 may be configured to monotonically increase as the distance increases from the dense region 61 through the intermediate region 63 to the sparse region 62.

[0029] The interlayer insulating film 9 is provided on the second active trench gate 18 (on the opposite side of the second active trench gate 18 from the semiconductor substrate 51). The collector electrode 7 is insulated from the gate trench electrode 18a by the interlayer insulating film 9 and is connected to the n-type gate electrode 18a via a barrier metal 5b similar to the barrier metal 5a. + The collector electrode 7 is electrically connected to the n-type collector layer 19. The barrier metal 5b is not essential. + It may be directly connected to the collector layer 19 .

[0030] <Configuration of the termination area> The semiconductor substrate 51 in the termination region of FIG. - a p-type drift layer 1, an n-type buffer layer 3, a p-type collector layer 16, and an n +p-type collector layer 19, p-type termination well layer 31, and p + and a contact layer 32.

[0031] p-type termination well layer 31 and p + The contact layer 32 is n - The p-type termination well layer 31 is selectively provided on the first main surface side of the n-type drift layer 1. In the first embodiment, the p-type termination well layer 31 is connected to the p-type base layer 15, and the lower end of the p-type termination well layer 31 is located lower than the lower end of the n-type carrier accumulation layer 2. + The contact layer 32 is provided on the edge of the semiconductor substrate 51 .

[0032] The insulating film 30 is formed between the p-type termination well layer 31 and the p + n where the contact layer 32 is not provided - The barrier metal 5a is provided on the p-type drift layer 1. The barrier metal 5a is provided on the p-type termination well layer 31 and the p-type + The terminal electrode 6a is provided on the contact layer 32. The terminal electrode 6a is connected to the p + The terminal electrode 6a is electrically connected to the contact layer 32. The barrier metal 5a is not essential. + It may be directly connected to the contact layer 32 .

[0033] The semi-insulating film 33 is provided on the emitter electrode 6 and the termination electrode 6a. The barrier metal 5a in the termination region is separated by the semi-insulating film 33. The semi-insulating film 33 includes, for example, a sinSiN (semi-insulating silicon nitride film). The termination protective film 34 is provided to cover the semi-insulating film 33.

[0034] On the second main surface side of the termination region, similar to the active region, an n-type buffer layer 3, a p-type collector layer 16, and an n + The n-type collector layer 19, the barrier metal 5b, and the collector electrode 7 are provided. However, the barrier metal 5b is not essential, and depending on the specifications of the semiconductor device, an n-type collector layer 19 may be provided in the termination region. + The mold collector layer 19 may not be provided.

[0035] A general IGBT manufacturing process is used as the manufacturing method of the semiconductor device according to the present embodiment 1. The process performed on the second main surface of the semiconductor substrate may be the same as the process performed on the first main surface of the semiconductor substrate, or may be different as appropriate.

[0036] <Operation> When a positive bias is applied to the gate trench electrode 11a from a gate pad (not shown) via the gate wiring G1, the portion of the p-type base layer 15 adjacent to the first active trench gate 11 is inverted to n-type, forming a first conductive channel. In other words, the first active trench gate 11 is configured to control the first conductive channel in the p-type base layer 15.

[0037] Similarly, when a positive bias is applied to the gate trench electrode 18a from a gate pad (not shown) via the gate wiring G2, the portion of the p-type collector layer 16 adjacent to the second active trench gate 18 is inverted to n-type, forming a second conductive channel. In other words, the second active trench gate 18 is configured to control the second conductive channel in the p-type collector layer 16.

[0038] When the first conduction channel is formed and a positive voltage is applied to the collector electrode 7, the entire configuration of FIG. 1 can function as an IGBT, regardless of whether the second conduction channel is formed. On the other hand, in the semiconductor device according to the first embodiment, when the load current flowing from the second main surface to the first main surface is zero or in the reverse direction, a positive bias is applied to the second active trench gate 18, thereby forming a second conduction channel in the p-type collector layer 16. With this configuration, when the second conduction channel is formed and a negative voltage is applied to the collector electrode 7, the entire configuration of FIG. 1 can function as a freewheeling diode, regardless of whether the first conduction channel is formed.

[0039] <Summary of the First Embodiment> In the sparse region 62, the area far from the second active trench gate 18 is large, so the entire sparse region 62 tends to function as an IGBT into which hole carriers are injected. On the other hand, in the dense region 61, the area far from the second active trench gate 18 is small, so the entire dense region 61 tends to function as a diode into which electrons are injected. In conventional technologies, there was a problem that only the dense region 61 or the sparse region 62 was provided, or each region was narrow and it was difficult to inject carriers into that region, resulting in increased power loss.

[0040] In contrast to this, in the first embodiment, dense regions 61 and sparse regions 62 are defined for the multiple second active trench gates 18, and three or more second active trench gates 18 are arranged in each of the dense regions 61 and the sparse regions 62. With this configuration, both the dense regions 61 and the sparse regions 62 can be made wider, making it easier for carriers to be injected into each, thereby suppressing power loss. Furthermore, the region where the dense regions 61 and the sparse regions 62 do not interfere with each other can be made larger, so power loss can also be suppressed from this perspective.

[0041] In the first embodiment, the dense region 61 is defined on the outer periphery of the semiconductor substrate 51, that is, on the termination region side. With this configuration, a structure in which n-type is dominant on the second main surface side of the termination region (the n-type buffer layer 3, the p-type collector layer 16, and the n + When a structure consisting of a collector layer 19 is provided, the structure can be prevented from interfering with the dense region 61.

[0042] Furthermore, in the first embodiment, the second main surface side gate structure including the trench structure is provided with second active trench gates 18. With this configuration, the distance between the second active trench gates 18 can be reduced, making it possible to easily provide a density gradient.

[0043] Preferably, the widest distance between the second active trench gates 18 is greater than 1 / 3 the thickness of the semiconductor substrate 51, and the narrowest distance between the second active trench gates 18 is smaller than 1 / 4 the thickness of the semiconductor substrate 51. With this configuration, it is possible to further suppress power loss in simulations.

[0044] <Embodiment 2> 2 is a cross-sectional view showing the configuration of a semiconductor device according to the present embodiment 2. In the present embodiment 2, similarly to the embodiment 1, dense regions 61 and sparse regions 62 are defined with respect to the plurality of second active trench gates 18.

[0045] In the second embodiment, as an example, three or more second active trench gates 18 in the dense region 61 are arranged at a first interval 18c, and three or more second active trench gates 18 in the sparse region 62 are arranged at a second interval 18d that is larger than the first interval 18c. In the example of Fig. 2, four second active trench gates 18 in the dense region 61 are arranged at the first interval 18c, and three second active trench gates 18 in the sparse region 62 are arranged at the second interval 18d that is larger than the first interval 18c. In the second embodiment, similar to the first embodiment, the dense region 61 is defined on the outer periphery side of the semiconductor substrate 51, that is, on the termination region side.

[0046] Although not shown, in the second embodiment, as in the first embodiment, an intermediate region having a lower density than the dense region 61 and a higher density than the sparse region 62 may be provided. Specifically, an intermediate region may be provided in which a plurality of second active trench gates 18 are arranged at a third interval that is larger than the first interval 18c and smaller than the second interval 18d.

[0047] <Summary of the second embodiment> According to the semiconductor device of the second embodiment described above, similarly to the first embodiment, three or more second active trench gates 18 are arranged in each of the dense region 61 and the sparse region 62, and therefore, power loss can be suppressed.

[0048] In the second embodiment, similarly to the first embodiment, dense region 61 is defined on the outer periphery of semiconductor substrate 51, that is, on the termination region side. With this configuration, when an n-type dominant structure is provided on the second main surface side of the termination region, interference of this structure with dense region 61 can be suppressed.

[0049] <Third Embodiment> 3 is a cross-sectional view showing the configuration of a semiconductor device according to the third embodiment. In the third embodiment, a dummy trench gate 20, which is a second-surface-side dummy gate structure that does not function as a second active trench gate 18, is provided on the second main surface side. The dummy trench gate 20 includes a dummy trench electrode 20a and a dummy trench insulating film 20b. + The n-type collector layer 19 is formed from the lower surface of the p-type collector layer 19 through the p-type collector layer 16 and the n-type buffer layer 3. - The dummy trench electrode 20a is provided in a trench that reaches the gate drift layer 1. The dummy trench electrode 20a is provided on the inner surface of the trench via a dummy trench insulating film 20b, and is electrically connected to the collector electrode 7 rather than the gate wiring G2.

[0050] In the third embodiment, similarly to the first embodiment, dense regions 61 and sparse regions 62 are defined with respect to the plurality of second active trench gates 18. In the third embodiment, as an example, the proportion of the second active trench gates 18 in the dense regions 61 is greater than the proportion of the second active trench gates 18 in the sparse regions 62.

[0051] The ratio of the second active trench gates 18 in the dense region 61 is the number of three or more second active trench gates 18 in the dense region 61 per total number of three or more second active trench gates 18 and dummy trench gates 20 in the dense region 61. The ratio of the second active trench gates 18 in the sparse region 62 is the number of three or more second active trench gates 18 in the sparse region 62 per total number of three or more second active trench gates 18 and dummy trench gates 20 in the sparse region 62.

[0052] 3, the proportion of second active trench gates 18 in the sparse region 62 is 3 / 4, and the proportion of second active trench gates 18 in the dense region 61 is 4 / 5. Note that in the example of FIG. 3, for convenience of explanation, the plurality of trench gates including the plurality of second active trench gates 18 and the plurality of dummy trench gates 20 are arranged at equal intervals. However, if the density of the sparse region 62 is lower than that of the dense region 61, the plurality of trench gates do not need to be arranged at equal intervals.

[0053] Although not shown, in the third embodiment, as in the first embodiment, an intermediate region may be provided which has a lower density than the dense region 61 and a higher density than the sparse region 62. Specifically, an intermediate region may be provided in which the proportion of the second active trench gates 18 is smaller than the proportion of the second active trench gates 18 in the dense region 61 and larger than the proportion of the second active trench gates 18 in the sparse region 62.

[0054] In the third embodiment, the sparse region 62 is defined on the outer periphery of the semiconductor substrate 51, that is, on the termination region side. + The n-type collector layer 19 is not provided, and instead an n-type buffer layer 3 and a p-type collector layer 16 are provided.

[0055] <Summary of the Third Embodiment> According to the semiconductor device of the third embodiment described above, similarly to the first embodiment, three or more second active trench gates 18 are arranged in each of the dense region 61 and the sparse region 62, and therefore, power loss can be suppressed.

[0056] Furthermore, in the third embodiment, sparse region 62 is defined on the outer periphery of semiconductor substrate 51, that is, on the termination region side. With this configuration, when a structure in which p-type is dominant (a structure consisting of n-type buffer layer 3 and p-type collector layer 16 as shown in FIG. 3 ) is provided on the second main surface side of the termination region, it is possible to prevent the structure from interfering with sparse region 62.

[0057] <Fourth Embodiment> 4 is a cross-sectional view showing the configuration of a semiconductor device according to the fourth embodiment. In the fourth embodiment, similar to the third embodiment, a dummy trench gate 20 that does not function as a second active trench gate 18 is provided on the second main surface side. However, the dummy trench gate 20 according to the fourth embodiment is not electrically connected to the collector electrode 7, but is connected to the n + The second active trench gates 18 are not in contact with the collector layer 19. In the fourth embodiment, similarly to the third embodiment, the proportion of the second active trench gates 18 in the dense region 61 is greater than the proportion of the second active trench gates 18 in the sparse region 62.

[0058] <Summary of the Fourth Embodiment> According to the semiconductor device of the fourth embodiment described above, similarly to the first embodiment, three or more second active trench gates 18 are arranged in each of the dense region 61 and the sparse region 62, and therefore, power loss can be suppressed.

[0059] Furthermore, in the fourth embodiment, similarly to the third embodiment, the sparse region 62 is defined on the outer periphery of the semiconductor substrate 51, that is, on the termination region side. With this configuration, when a p-type dominant structure is provided on the second main surface side of the termination region, it is possible to prevent the structure from interfering with the sparse region 62.

[0060] 5, the dummy trench gate 20 according to the fourth embodiment may be electrically connected to the collector electrode 7, similarly to the third embodiment. Even with this configuration, it is possible to suppress power loss.

[0061] <Fifth Embodiment> 6 is a cross-sectional view showing the configuration of a semiconductor device according to the fifth embodiment. Up to now, a configuration has been described in which a second active trench gate 18 is provided as a second main surface side gate structure including a trench structure. In the fifth embodiment, a planar gate 22 is provided as a second main surface side gate structure including a planar structure, rather than a second main surface side gate structure including a trench structure.

[0062] In the fifth embodiment, the p-type collector layer 16 is - The n-type drift layer 1 is selectively provided on the second main surface side. + The collector layer 19 is an n - The p-type collector layer 16 is selectively provided on the second main surface side of the p-type collector layer 16 so as to sandwich the p-type collector layer 16 between the p-type collector layer 16 and the drift layer 1.

[0063] The planar gate 22 includes a gate electrode 22a and a gate insulating film 22b. - Type drift layer 1 and n + The gate electrode 22a is provided via a gate insulating film 22b on the p-type collector layer 16 sandwiched between the planar gate 22 and the planar gate 22. When a positive bias is applied to the gate electrode 22a, the portion of the p-type collector layer 16 adjacent to the planar gate 22 is inverted to n-type, forming a second conductive channel.

[0064] In the fifth embodiment, similarly to the first embodiment, dense regions 61 and sparse regions 62 are defined for the plurality of planar gates 22. In the dense region 61, three or more consecutive planar gates 22 are arranged. In the sparse region 62, three or more consecutive planar gates 22 are arranged at a lower density than in the dense region 61. The spacing between the planar gates 22 corresponds to the spacing between the gate electrodes 22a. The density means the number of three or more consecutive planar gates 22 per total spacing between the three or more consecutive planar gates 22.

[0065] As an example of this, in this fifth embodiment, the spacing between six or more planar gates 22, including three or more planar gates 22 in the dense region 61 and three or more planar gates 22 in the sparse region 62, is configured to monotonically increase as it progresses in the direction from the dense region 61 to the sparse region 62.

[0066] <Summary of the Fifth Embodiment> According to the semiconductor device of the fifth embodiment described above, as in the first embodiment, three or more planar gates 22 are arranged in each of the dense region 61 and the sparse region 62, thereby making it possible to suppress power loss.

[0067] In the fifth embodiment, a planar gate 22 is provided as a second main surface side gate structure including a planar structure. With this configuration, when it is difficult to provide a trench structure on the second main surface side, the dense region 61 and the sparse region 62 can be provided by providing a planar structure on the second main surface side.

[0068] Note that the present embodiment 5 can be applied not only to embodiment 1 but also to embodiments 2 to 4. Furthermore, in the embodiments 1 to 5, the configuration in which the first active trench gate 11 is provided as the first main surface side gate structure including a trench structure has been described, but a first main surface side gate structure including a planar structure may also be provided.

[0069] <Sixth Embodiment> 7 is a cross-sectional view showing the configuration of a semiconductor device according to the sixth embodiment. In the sixth embodiment, a dense region 66, which is a second dense region, and a sparse region 67, which is a second sparse region, are defined for the plurality of first active trench gates 11. In the dense region 66, two or more consecutive first active trench gates 11 are arranged. In the sparse region 67, two or more consecutive first active trench gates 11 are arranged at a lower density than in the dense region 66.

[0070] The density means the number of two or more consecutive first active trench gates 11 per total spacing between the two or more consecutive first active trench gates 11. In the sixth embodiment, the sparse region 67 is provided on the first main surface side of the dense region 61, and the dense region 66 is provided on the first main surface side of the sparse region 62.

[0071] <Summary of the Sixth Embodiment> Unlike the dense region 61, which tends to function as a diode, the dense region 66 tends to function as an IGBT. On the other hand, unlike the sparse region 67, which tends to function as an IGBT, the sparse region 67 tends to function as a diode. Here, in the semiconductor device according to the sixth embodiment, the dense region 66 and the sparse region 67 are defined with respect to the plurality of first active trench gates 11, the sparse region 67 is provided on the first main surface side of the dense region 61, and the dense region 66 is provided on the first main surface side of the sparse region 62.

[0072] According to this configuration, the function of the diode can be improved in the dense region 61 and the sparse region 67, and the function of the IGBT can be improved in the sparse region 62 and the dense region 66. Note that the sixth embodiment can be applied not only to the first embodiment but also to the first to fifth embodiments.

[0073] In this disclosure in English, 'a' and 'an' mean one or more. Therefore, 'a', 'an', 'one or more' and 'at least one' can be used interchangeably.

[0074] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0075] Various aspects of the present disclosure are summarized below as appendices.

[0076] (Appendix 1) a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, the semiconductor substrate including a drift layer of a first conductivity type between the first main surface and the second main surface; a second conductivity type base layer provided on the first main surface side of the drift layer; a source layer of the first conductivity type provided on the first main surface side of the base layer; a first-surface-side gate structure provided on the first main surface and controlling a first conductive channel in the base layer; a first collector layer of the second conductivity type provided on the second main surface side of the drift layer; a second collector layer of the first conductivity type provided on the second main surface side of the first collector layer; a second main surface side gate structure provided on the second main surface and controlling a second conductive channel in the first collector layer; Equipped with a plurality of the second main surface side gate structures are arranged along a predetermined arrangement direction, a first dense region in which three or more consecutive second main surface side gate structures are arranged, and a first sparse region in which three or more consecutive second main surface side gate structures are arranged at a density lower than that of the first dense region;

[0077] (Appendix 2) 10. The semiconductor device according to claim 1, a semiconductor device in which the spacing between six or more second main surface side gate structures, including the three or more second main surface side gate structures in the first dense region and the three or more second main surface side gate structures in the first sparse region, monotonically increases in a direction from the first dense region to the first sparse region.

[0078] (Appendix 3) 10. The semiconductor device according to claim 1, the three or more second main surface side gate structures in the first dense region are arranged at a first interval; the three or more second-main-surface-side gate structures in the first sparse region are arranged at a second interval that is larger than the first interval.

[0079] (Appendix 4) 10. The semiconductor device according to claim 1, a collector electrode electrically connected to the second collector layer; a second-main-surface-side dummy gate structure provided on the second main surface side and electrically connected to the collector electrode; The semiconductor device further comprises:

[0080] (Appendix 5) 10. The semiconductor device according to claim 1, The semiconductor device further comprises a second-main-surface-side dummy gate structure provided on the second main surface side and not in contact with the second collector layer.

[0081] (Appendix 6) 10. The semiconductor device according to claim 1, a collector electrode electrically connected to the second collector layer; a second-surface-side dummy gate structure provided on the second main surface side and electrically connected to the collector electrode but not in contact with the second collector layer; The semiconductor device further comprises:

[0082] (Appendix 7) The semiconductor device according to any one of Supplementary Note 4 to Supplementary Note 6, a number of the three or more second main surface side gate structures in the first dense region per total number of the three or more second main surface side gate structures and the second main surface side dummy gate structures in the first dense region is greater than a number of the three or more second main surface side gate structures in the first sparse region per total number of the three or more second main surface side gate structures and the second main surface side dummy gate structures in the first sparse region.

[0083] (Appendix 8) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 7, The semiconductor device, wherein the first dense region is defined on the outer periphery of the semiconductor substrate.

[0084] (Appendix 9) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 7, The semiconductor device, wherein the first sparse region is defined on the outer periphery of the semiconductor substrate.

[0085] (Appendix 10) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 9, The second main surface side gate structure includes a trench structure.

[0086] (Appendix 11) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 9, The second main surface side gate structure includes a planar structure.

[0087] (Appendix 12) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 11, the widest interval between the second main surface side gate structures is greater than one-third of the thickness of the semiconductor substrate; a semiconductor device in which the narrowest distance between the second main surface side gate structures is smaller than ¼ of the thickness of the semiconductor substrate;

[0088] (Appendix 13) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 12, a plurality of the first main surface side gate structures are arranged along the arrangement direction, a second dense region in which two or more consecutive first main surface side gate structures are arranged, and a second sparse region in which two or more consecutive first main surface side gate structures are arranged at a density lower than that of the second dense region;

[0089] (Appendix 14) 14. The semiconductor device according to claim 13, the second sparse region is provided on the first main surface side of the first dense region, The second dense region is provided on the first main surface side of the first sparse region.

[0090] (Appendix 15) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 14, A semiconductor device in which, when a load current flowing from the second main surface to the first main surface is zero or in the reverse direction, a positive bias is applied to the second main surface side gate structure, thereby forming the second conductive channel in the first collector layer. [Explanation of symbols]

[0091] 1n - 7 collector electrode; 11 first active trench gate; 13 n + 15 p-type source layer, 15 p-type base layer, 16 p-type collector layer, 18 second active trench gate, 19 n + collector layer, 20 dummy trench gate, 22 planar gate, 51 semiconductor substrate, 61, 66 dense region, 62, 67 sparse region.

Claims

1. a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, the semiconductor substrate including a drift layer of a first conductivity type between the first main surface and the second main surface; a second conductivity type base layer provided on the first main surface side of the drift layer; a source layer of the first conductivity type provided on the first main surface side of the base layer; a first-surface-side gate structure provided on the first major surface and controlling a first conductive channel in the base layer; a first collector layer of the second conductivity type provided on the second main surface side of the drift layer; a second collector layer of the first conductivity type provided on the second main surface side of the first collector layer; a second-surface-side gate structure provided on the second major surface and controlling a second conductive channel in the first collector layer; Equipped with a plurality of the second main surface side gate structures are arranged along a predetermined arrangement direction, a first dense region in which three or more consecutive second main surface side gate structures are arranged, and a first sparse region in which three or more consecutive second main surface side gate structures are arranged at a density lower than that of the first dense region;

2. 2. The semiconductor device according to claim 1, a semiconductor device, wherein a spacing between six or more second main surface side gate structures including the three or more second main surface side gate structures in the first dense region and the three or more second main surface side gate structures in the first sparse region monotonically increases in a direction from the first dense region to the first sparse region.

3. 2. The semiconductor device according to claim 1, the three or more second main surface side gate structures in the first dense region are arranged at a first interval; the three or more second-surface-side gate structures in the first sparse region are arranged at a second interval that is larger than the first interval.

4. 2. The semiconductor device according to claim 1, a collector electrode electrically connected to the second collector layer; a second-main-surface-side dummy gate structure provided on the second main surface side and electrically connected to the collector electrode; The semiconductor device further comprises:

5. 2. The semiconductor device according to claim 1, The semiconductor device further comprises a second-main-surface-side dummy gate structure provided on the second main surface side and not in contact with the second collector layer.

6. 2. The semiconductor device according to claim 1, a collector electrode electrically connected to the second collector layer; a second-surface-side dummy gate structure provided on the second main surface side and electrically connected to the collector electrode but not in contact with the second collector layer; The semiconductor device further comprises:

7. 7. The semiconductor device according to claim 4, wherein: a number of the three or more second main surface side gate structures in the first dense region per total number of the three or more second main surface side gate structures and the second main surface side dummy gate structures in the first dense region is greater than a number of the three or more second main surface side gate structures in the first sparse region per total number of the three or more second main surface side gate structures and the second main surface side dummy gate structures in the first sparse region.

8. 7. The semiconductor device according to claim 1, The semiconductor device, wherein the first dense region is defined on the outer periphery of the semiconductor substrate.

9. 7. The semiconductor device according to claim 1, The semiconductor device, wherein the first sparse region is defined on the outer periphery of the semiconductor substrate.

10. 7. The semiconductor device according to claim 1, The second main surface side gate structure includes a trench structure.

11. 7. The semiconductor device according to claim 1, The second main surface side gate structure includes a planar structure.

12. 7. The semiconductor device according to claim 1, the widest interval between the second main surface side gate structures is greater than one-third of the thickness of the semiconductor substrate; the narrowest distance between the second main surface side gate structures is smaller than ¼ of the thickness of the semiconductor substrate.

13. 7. The semiconductor device according to claim 1, a plurality of the first main surface side gate structures are arranged along the arrangement direction, a second dense region in which two or more consecutive first main surface side gate structures are arranged, and a second sparse region in which two or more consecutive first main surface side gate structures are arranged at a density lower than that of the second dense region;

14. 14. The semiconductor device according to claim 13, the second sparse region is provided on the first main surface side of the first dense region, The second dense region is provided on the first main surface side of the first sparse region.

15. 7. The semiconductor device according to claim 1, a semiconductor device in which, when a load current flowing from the second main surface to the first main surface is zero or in a reverse direction, a positive bias is applied to the second main surface side gate structure, thereby forming the second conductive channel in the first collector layer.

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