Semiconductor module and manufacturing method thereof

Abstract

To reinforce the bonding strength between a semiconductor chip and a wiring board.SOLUTION: A semiconductor module includes a main electrode connection portion that connects a main electrode of a semiconductor chip to a wiring substrate, the main electrode connection portion has a first region in which a plurality of first bonding portions are provided, and a second region that is at a greater distance from a first end edge than the first region and in which a plurality of second bonding portions are provided, and the bonding strength of the first bonding portions per unit area is higher than the bonding strength of the second bonding portions per unit area.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor module and a manufacturing method. [Background technology]

[0002] BACKGROUND ART Techniques for connecting a semiconductor chip to a member such as a wiring board using conductive bumps are known (see, for example, Patent Documents 1 to 5). Patent Document 1: Japanese Patent Application Laid-Open No. 2008-227020 Patent Document 2: Japanese Patent Application Laid-Open No. 2001-85558 Patent Document 3: Japanese Patent Application Laid-Open No. 8-264540 Patent Document 4: Japanese Patent Application Laid-Open No. 2000-174064 Patent Document 5: International Publication No. 2010 / 061428 Summary of the Invention [Problem to be solved by the invention]

[0003] The bonding strength between the semiconductor chip and the wiring board is reinforced. [Means for solving the problem]

[0004] One aspect of the present invention provides a semiconductor module. The semiconductor module may include a semiconductor chip having a gate pad and a main electrode provided on the same main surface. Any of the semiconductor modules may include a wiring substrate. Any of the semiconductor modules may include a main electrode connection portion connecting the main electrode of the semiconductor chip to the wiring substrate. In any of the semiconductor modules, the multiple edge sides of the outer shape of the semiconductor chip in a top view may include a first edge closest to the gate pad. In any of the semiconductor modules, the main electrode connection portion may have a first region in which multiple first bonding portions are provided on an arrangement surface parallel to the main surface. In any of the semiconductor modules, the main electrode connection portion may have a second region that is farther from the first edge than the first region and in which multiple second bonding portions are provided. In any of the semiconductor modules, the bonding strength per unit area of ​​the first bonding portion may be higher than the bonding strength per unit area of ​​the second bonding portion.

[0005] In any of the semiconductor modules described above, the first region may have a recess that is recessed in a direction perpendicular to the first end side. In any of the semiconductor modules described above, the gate pad may be disposed opposite the recess.

[0006] Any of the above semiconductor modules may include a gate connection portion including a plurality of gate junctions that connect the gate pad and the wiring substrate.

[0007] In any of the semiconductor modules described above, the bonding strength per unit area of ​​the gate bonding portion may be the same as the bonding strength per unit area of ​​the first bonding portion.

[0008] In any of the semiconductor modules described above, the bonding strength per unit area of ​​the gate bonding portion may be smaller than the bonding strength per unit area of ​​the first bonding portion.

[0009] In any of the semiconductor modules described above, the plurality of edges of the semiconductor chip may include a second edge farthest from the first edge, and the second region may extend to a position in the main electrode connection portion closest to the second edge.

[0010] In any of the above semiconductor modules, the plurality of end sides of the semiconductor chip may include a second end side farthest from the first end side. In any of the above semiconductor modules, the main electrode connection portion may have a third region that is closer to the second end side than the second region and includes a plurality of third bonding portions on an arrangement surface parallel to the main surface of the semiconductor module. In any of the above semiconductor modules, the bonding strength per unit area of ​​the third bonding portions may be higher than the bonding strength per unit area of ​​the second bonding portions.

[0011] In any of the semiconductor modules described above, the number of the first joints per unit area may be greater than the number of the second joints per unit area.

[0012] In any of the semiconductor modules described above, at least one of the first joint portions may be longer than any of the second joint portions in a connection direction connecting the main surface and the wiring board.

[0013] In any of the semiconductor modules described above, the first bonding portion and the second bonding portion may have one or more bumps stacked in the connection direction. In any of the semiconductor modules described above, the number of rows of the bumps in at least one of the first bonding portions may be greater than the number of rows of the bumps in any of the second bonding portions.

[0014] In any of the semiconductor modules described above, at least one of the first joints may have a columnar portion. In any of the semiconductor modules described above, the first joints may have a plate-like portion that is stacked with the columnar portion in a connection direction connecting the main surface and the wiring board and has a width greater than that of the columnar portion.

[0015] In any of the semiconductor modules described above, at least one of the main electrode and the wiring board may have a gold-plated layer having a thickness of 0.5 μm or more that is joined to the first joint portion.

[0016] In any of the semiconductor modules described above, at least one of the main electrode and the wiring substrate may have a gold-plated layer disposed in a region bonded to the first joint portion and a nickel layer disposed below the gold-plated layer. In any of the semiconductor modules described above, the gold-plated layer may be nickel-free on a surface bonded to the first joint portion.

[0017] A second aspect of the present invention provides a method for manufacturing a semiconductor module including a semiconductor chip having a gate pad and a main electrode provided on the same main surface, a wiring substrate, and a main electrode connection portion connecting the main electrode of the semiconductor chip to the wiring substrate. In the manufacturing method, the main electrode connection portion may be provided on an arrangement surface parallel to the main surface with a first region having a plurality of first bonding portions and a second region that is farther from the gate pad than the first region and has a plurality of second bonding portions. In any of the manufacturing methods, the bonding strength per unit area provided by the first bonding portions may be higher than the bonding strength per unit area provided by the second bonding portions.

[0018] In any of the above manufacturing methods, a columnar portion may be provided on one of the main electrode and the wiring substrate. In any of the above manufacturing methods, a plate-like portion having a width greater than that of the columnar portion may be provided on the other of the main electrode and the wiring substrate. In any of the above manufacturing methods, at least one first joint may be formed by connecting the columnar portion and the plate-like portion.

[0019] In any of the above manufacturing methods, at least one of the main electrode and the wiring substrate may have a gold plating layer disposed in a region of the main electrode connecting portion that is bonded to the first region, and a nickel layer disposed below the gold plating layer. In any of the above manufacturing methods, the steps from forming the nickel layer and the gold plating layer to forming the first bonding portion on the gold plating layer may be performed at 250°C or less.

[0020] In any of the above manufacturing methods, the steps from forming the nickel layer and the gold plating layer to fixing the semiconductor chip to the wiring board may be performed at 250° C. or less.

[0021] The above summary of the invention does not list all of the necessary features of the present invention. In addition, subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0022] [Figure 1] 1 is a diagram illustrating an example of a semiconductor chip 100. FIG. [Figure 2] 1 is a diagram illustrating an example of a semiconductor module 200 according to an embodiment of the present invention. [Figure 3] 10A to 10C are diagrams illustrating an example of a method for manufacturing a semiconductor module 200 according to a reference example. [Figure 4] 2A and 2B are diagrams showing examples of the configuration of a main electrode connection portion 150 and a gate connection portion 160 according to an embodiment of the present invention. [Figure 5] 10 is a diagram showing another example of the arrangement of the gate junction portion 161. FIG. [Figure 6] 10A and 10B are diagrams showing other configuration examples of the main electrode connection portion 150. FIG. [Figure 7] 10A and 10B are diagrams showing other configuration examples of the main electrode connection portion 150. FIG. [Figure 8] 10A and 10B are diagrams showing other configuration examples of the main electrode connection portion 150 and the gate connection portion 160. FIG. [Figure 9]FIG. 1 is a diagram showing a first bonding portion 171, a second bonding portion 172, and a third bonding portion 173 in a cross section parallel to the connection direction. [Figure 10] 10 is a diagram showing an example of the structure of a first bonding portion 171 and a second bonding portion 172. FIG. [Figure 11] 10A and 10B are diagrams showing other examples of the first bonding portion 171, the second bonding portion 172, and the third bonding portion 173. FIG. [Figure 12] 12A to 12C are diagrams illustrating an example of a manufacturing process for the semiconductor module 200 shown in FIG. [Figure 13] 1A and 1B are diagrams illustrating an example of the structure of a main wiring 120. [Figure 14] 2 is an enlarged cross-sectional view of the vicinity of an edge of the semiconductor substrate 10. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0023] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. In this specification, the same parts in each drawing are given the same reference numerals, and their description may be omitted. Furthermore, for the sake of convenience, some components may not be illustrated.

[0024] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0025] In this specification, technical matters may be explained using a Cartesian coordinate system of X, Y, and Z axes. The Cartesian coordinate system merely specifies the relative positions of components and does not limit specific directions. For example, the Z-axis direction does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is written without specifying positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.

[0026] In this specification, orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0027] In this specification, when terms such as "same" or "equal" are used, this may include cases where there is an error due to manufacturing variations or the like. The error is, for example, within 10%. Furthermore, in this specification, when terms such as "parallel" or "perpendicular" are used, this may include an error of within 5°.

[0028] 1 is a diagram illustrating an example of a semiconductor chip 100. The semiconductor chip 100 of this example is a chip provided with a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET.

[0029] The semiconductor chip 100 has a semiconductor substrate 10. The semiconductor substrate 10 may be a silicon substrate or a compound semiconductor substrate such as a silicon carbide substrate. An N+ type emitter region, a P+ type collector region, a P- type base region, an N- type drift region, etc. of the IGBT are formed inside the semiconductor substrate 10.

[0030] The semiconductor chip 100 has a gate pad 30 and a main electrode 20 provided on the same main surface. The main surfaces of the semiconductor chip 100 are the two surfaces with the largest areas of the semiconductor chip 100. The two main surfaces are arranged facing each other. The gate pad 30 and the main electrode 20 are formed of a metal material such as Al or AlSi. The surfaces of the gate pad 30 and the main electrode 20 may be covered with a plating layer of nickel, gold, or the like. In this specification, the main surface on which the gate pad 30 and the main electrode 20 are provided may be referred to as the first main surface, and the other main surface may be referred to as the second main surface.

[0031] The main electrode 20 is connected to a main terminal of a power semiconductor element provided on the semiconductor substrate 10. The main terminal of a power semiconductor element is a terminal through which the main current of the power semiconductor element flows. In the case of an IGBT, the emitter region or collector region corresponds to the main terminal, and in the case of a MOSFET, the source region or drain region corresponds to the main terminal. For example, the main electrode 20 is an emitter electrode in an IGBT, but is not limited to this. In this specification, the case where the semiconductor chip 100 is an IGBT will be described, but if the semiconductor chip 100 is a MOSFET, the "emitter" in this specification may be read as the "source" and the "collector" may be read as the "drain."

[0032] A main electrode separate from the main electrode 20 is provided on the semiconductor substrate 10. The main electrode may be, for example, a collector electrode in an IGBT, but is not limited to this. The main electrode may be provided on a different main surface from the main electrode 20. In this case, the semiconductor chip 100 is a vertical device in which a main current flows in the thickness direction of the semiconductor substrate 10.

[0033] The gate pad 30 is connected to the gate electrode of the power semiconductor element provided on the semiconductor substrate 10. The gate electrode is arranged facing the base region of the power semiconductor element. A gate oxide film is provided between the gate electrode and the base region. When a predetermined on-voltage is applied to the gate electrode, the surface layer of the base region facing the gate electrode is inverted to an N-type region, forming a channel. This turns the power semiconductor element on. The gate pad 30 is connected to gate electrodes provided in each region of the semiconductor substrate 10. The gate electrodes may be trench-type electrodes formed from the surface to the interior of the semiconductor substrate 10.

[0034] 1 shows multiple edges (first edge 11, second edge 12, third edge 13, and fourth edge 14) of the outer shape of semiconductor chip 100 when viewed from above. A top view refers to a view from a direction perpendicular to the main surface of semiconductor chip 100 or semiconductor substrate 10. The outer shape of semiconductor chip 100 may be the outer shape of semiconductor substrate 10. In this example, semiconductor substrate 10 has first edge 11 and second edge 12 that are parallel to each other, third edge 13 and fourth edge 14 that are parallel to each other, and first edge 11 and third edge 13 that are perpendicular to each other.

[0035] In this example, the first end edge 11 is the end edge closest to the gate pad 30 among the multiple end edges. The second end edge 12 is the end edge farthest from the first end edge 11 among the multiple end edges of the semiconductor chip 100. The third end edge 13 and the fourth end edge 14 are end edges that connect the first end edge 11 and the second end edge 12, respectively.

[0036] FIG. 2 is a diagram showing an example of a semiconductor module 200 according to an embodiment of the present invention. FIG. 2 shows an enlarged view of a portion of the semiconductor module 200. The semiconductor module 200 includes a semiconductor chip 100 and a wiring substrate 110. The wiring substrate 110 has a base material formed of an insulating material, main wiring 120, and gate wiring 130. The main wiring 120 and gate wiring 130 are wirings formed on the base material from a metal material such as copper. The surfaces of the main wiring 120 and gate wiring 130 may be covered with a plating layer of nickel, gold, or the like.

[0037] The semiconductor chip 100 is fixed to a wiring substrate 110. In Fig. 2, the semiconductor chip 100 fixed to the wiring substrate 110 is indicated by a dashed line. The main electrodes 20 of the semiconductor chip 100 are connected to main wiring 120. The gate pads 30 are connected to gate wiring 130.

[0038] The semiconductor module 200 may have a housing that houses the semiconductor chip 100 and the wiring substrate 110. The space of the housing that houses the semiconductor chip 100 and the wiring substrate 110 may be sealed with an insulating material such as gel or epoxy resin.

[0039] 3 is a diagram showing an example of a manufacturing method for a semiconductor module 200 according to a reference example. First, in a preparation step S302, a semiconductor chip 100 and a main wiring 140 are prepared. The main wiring 140 is a wiring different from the main wiring 120 shown in FIG. 2. For example, the main wiring 140 is a wiring such as a plate-shaped lead frame. The main wiring 140 may be formed of a metal material such as copper.

[0040] In step S304, the main wiring 140 is connected to a main electrode provided on the second main surface 102 of the semiconductor chip 100. In this example, the main electrode is provided over the entire second main surface 102. The main wiring 140 may be connected to the main electrode so as to cover the entire main electrode. The main wiring 140 may be connected to the main electrode of the semiconductor chip 100 by a connection portion 142 such as solder. As an example, the semiconductor chip 100 is heated to about 200°C when bonding the main wiring 140. In each figure, the reference numeral for the connection portion 142 may be omitted.

[0041] In step S306, after the semiconductor chip 100 and the main wiring 140 are bonded, the heating of the semiconductor chip 100 is stopped and the temperature of the semiconductor chip 100 is lowered to about room temperature (e.g., 25°C). In step S306, the semiconductor chip 100 and the main wiring 140 may warp due to the difference in the linear expansion coefficients between the semiconductor chip 100 and the main wiring 140. For example, as shown in FIG. 3, the semiconductor chip 100 and the main wiring 140 may warp so as to be convex toward the semiconductor chip 100. As an example, warping of 30 μm or more in the height direction may occur between the center and the edge of the semiconductor chip 100.

[0042] In step S308, the main electrode connection portion 150 and the gate connection portion 160 are formed. The main electrode connection portion 150 connects the main electrode 20 of the semiconductor chip 100 to the main wiring 120 of the wiring substrate 110. The main electrode connection portion 150 has a plurality of main electrode junctions 170. The gate connection portion 160 connects the gate pad 30 to the gate wiring 130 of the wiring substrate 110. The gate connection portion 160 has a plurality of gate junctions 161. The main electrode junctions 170 and the gate junctions 161 are protrusions (bumps) formed of a conductive material such as gold or copper. The main electrode junctions 170 and the gate junctions 161 may be spherical, pillar-shaped, or have other shapes formed of a conductive material. The plurality of main electrode junctions 170 are distributed over the entire main electrode 20. The plurality of gate junctions 161 are distributed over the entire gate pad 30.

[0043] 3, the main electrode junction 170 and the gate junction 161 are formed on the first main surface 101 of the semiconductor chip 100. In other examples, the main electrode junction 170 and the gate junction 161 may be formed on the wiring substrate 110, or may be formed on both the semiconductor chip 100 and the wiring substrate 110.

[0044] In step S310, the semiconductor chip 100 is placed on the wiring substrate 110 via the main electrode bonding portion 170 and the gate bonding portion 161. In step S312, the entire surface of the semiconductor chip 100 is pressed toward the wiring substrate 110 while the semiconductor chip 100 and the wiring substrate 110 are heated. As a result, the semiconductor chip 100 is fixed to the wiring substrate 110 in a flattened state, and the semiconductor module 200 can be manufactured. In this specification, the direction in which the semiconductor chip 100 and the wiring substrate 110 are connected may be referred to as the connection direction. The connection direction is a normal direction perpendicular to the first main surface 101 of the semiconductor chip 100. If the first main surface 101 is warped, the normal direction at the center of the first main surface 101 may be the connection direction. Alternatively, the normal direction to the top surface of the main wiring 120 may be the connection direction.

[0045] Step S314 shows a state in which the temperature of the semiconductor chip 100 is lowered to approximately room temperature after the semiconductor module 200 is manufactured. When the temperature of the semiconductor chip 100 is lowered, stress is generated in the direction in which the semiconductor chip 100 warps, similar to step S306, depending on the difference in the linear expansion coefficient between the semiconductor chip 100 and the main wiring 140. As a result, as shown in FIG. 3, breakage may occur in some of the main electrode bonding portions 170 and gate bonding portions 161. Such breakage may cause the electrical connection between the semiconductor chip 100 or wiring substrate 110 and the main electrode bonding portions 170 or gate bonding portions 161 to become unsustainable.

[0046] The degree of warping of the semiconductor chip 100 increases toward the edge of the semiconductor chip 100. Therefore, the closer a bond is to the edge of the semiconductor chip 100, the more likely it is to break. Furthermore, the number of bonded portions tends to be fewer near the gate pad 30. Semiconductor elements such as IGBTs are formed in an active region overlapping with the main electrode 20. To increase the area of ​​the active region, the area of ​​the gate pad 30 tends to be smaller. This makes it difficult to increase the number of gate bonded portions 161 provided on the gate pad 30. Furthermore, because different potentials are applied to the gate pad 30 and the main electrode 20, they are spaced apart. A protective layer such as polyimide is formed between the gate pad 30 and the main electrode. Since bonded portions cannot be provided on the protective layer, the number of bonded portions around the gate pad 30 is reduced. Therefore, the number of bonded portions is reduced, particularly near the gate pad 30, making breakage more likely.

[0047] FIG. 4 is a diagram showing an example of the configuration of a main electrode connection portion 150 and a gate connection portion 160 according to an embodiment of the present invention. The structure other than the main electrode connection portion 150 and the gate connection portion 160 is the same as the example described in FIGS. 1 to 3 . In FIG. 4 , the semiconductor substrate 10, main electrode 20, and gate pad 30 of the semiconductor chip 100 are indicated by dashed lines. As described above, the main electrode connection portion 150 has a plurality of main electrode junctions 170 at a position overlapping with the main electrode 20. In the example of FIG. 4 , the plurality of main electrode junctions 170 are indicated by a plurality of first junctions 171 and a plurality of second junctions 172. The gate connection portion 160 has a plurality of gate junctions 161 at a position overlapping with the gate pad 30. In FIG. 4 , the first junctions 171, the second junctions 172, and the gate junctions 161 are schematically indicated by circles. The shape of each junction in a top view may be, but is not limited to, a circle.

[0048] The main electrode connection portion 150 has a first region 151 and a second region 152 on an arrangement plane parallel to the first main surface 101 of the semiconductor chip 100. A plurality of first bonding portions 171 are provided in the first region 151. A plurality of second bonding portions 172 are provided in the second region 152. The first bonding portions 171 and the second bonding portions 172 may be formed of the same material or different materials. The first bonding portions 171 and the second bonding portions 172 may have the same shape or different shapes. The first bonding portions 171 and the second bonding portions 172 may have the same size (i.e., area) on the arrangement plane parallel to the first main surface 101 or may have different sizes.

[0049] The second region 152 is farther from the first end side 11 than the first region 151. That is, the first region 151 is disposed between the second region 152 and the first end side 11 in a direction perpendicular to the first end side 11. As shown in FIG. 4 , the boundary between the first region 151 and the second region 152 may be a straight line parallel to the first end side 11. Of the main electrode connection portion 150 provided with the main electrode joint portion 170, the portion facing the first end side 11 may entirely be the first region 151.

[0050] In this example, the bonding strength per unit area of ​​the first bonding portion 171 on the arrangement surface parallel to the first main surface 101 is higher than the bonding strength per unit area of ​​the second bonding portion 172. The bonding strength refers to the strength that can maintain the electrical connection between the semiconductor chip 100 and the wiring substrate 110. The bonding strength may be expressed as the magnitude of stress in the connection direction. In other words, the bonding strength may be the upper limit of stress in the connection direction that can maintain the electrical connection between the semiconductor chip 100 and the wiring substrate 110. The bonding strength may also be expressed as the magnitude of warpage of the semiconductor chip 100 measured at room temperature (25°C) with the semiconductor chip 100 removed from the wiring substrate 110. In other words, the bonding strength may be the upper limit of the magnitude of warpage of the semiconductor chip 100 that can maintain the electrical connection between the semiconductor chip 100 and the wiring substrate 110. The bonding strength may be the lower of a connection strength that can maintain the connection between the semiconductor chip 100 and the wiring substrate 110 and each of the bonding portions, and a breaking strength that does not cause breakage in the bonding portions themselves.

[0051] By making the bonding strength per unit area of ​​the first bonding portion 171 higher than the bonding strength per unit area of ​​the second bonding portion 172, it is possible to suppress the occurrence of fractures and the like in the first region 151. This makes it possible to suppress the occurrence of fractures and the like in the vicinity of the gate pad 30, where fractures and the like are relatively likely to occur.

[0052] 4, the number of first bonding portions 171 per unit area is greater than the number of second bonding portions 172 per unit area. In other words, the density at which the first bonding portions 171 are provided (for example, the total number of first bonding portions 171 in the first region 151 / the area of ​​the first region 151) is higher than the density at which the second bonding portions 172 are provided (for example, the total number of second bonding portions 172 in the second region 152 / the area of ​​the second region 152).

[0053] The density of the first bonding portions 171 may be 1.2 times or more, 1.5 times or more, or even 2 times or more than that of the second bonding portions 172. In the example of FIG. 4, the density of the first bonding portions 171 is twice that of the second bonding portions 172. In the example of FIG. 4, the plurality of second bonding portions 172 are arranged in the second region 152 in a predetermined repeating pattern. The plurality of first bonding portions 171 may include those arranged in the same repeating pattern as the second bonding portions 172, and those arranged additionally.

[0054] 4, the bonding strength per unit area of ​​the gate bonding portions 161 is the same as the bonding strength per unit area of ​​the first bonding portions 171. The number of first bonding portions 171 per unit area may be the same as the number of gate bonding portions 161 per unit area. The arrangement interval between the first bonding portions 171 and the arrangement interval between the gate bonding portions 161 may be the same.

[0055] In the example of FIG. 4 , the second region 152 is provided up to the position in the main electrode connection portion 150 closest to the second end side 12. In this example, the entire portion of the main electrode connection portion 150 that is closer to the second end side 12 than the first region 151 is the second region 152. In the second region 152, the second bonding portions 172 are arranged at a relatively low density. This allows a sealant such as gel or epoxy resin to easily penetrate between the second bonding portions 172, making it easy to seal the semiconductor chip 100 and the wiring substrate 110. The second bonding portions 172 may be arranged uniformly in the second region 152. In other words, multiple second bonding portions 172 may be arranged in the second region 152 at equal intervals.

[0056] The first bonding portions 171 may be uniformly arranged in the first region 151. In another example, the first region 151 may have portions with different densities of the first bonding portions 171. The density of the first bonding portions 171 in any portion may be higher than the density of the second bonding portions 172. By providing portions with a relatively low density of the first bonding portions 171, the sealing material can more easily penetrate into those portions.

[0057] The first main surface 101 of the semiconductor chip 100 is virtually divided into two equal parts by a center line parallel to the first edge 11. The number of bonding portions (in this example, the number of first bonding portions 171, second bonding portions 172, and gate bonding portions 161) provided in the two equal regions may be the same. This allows the bonding strength in the two regions to be balanced while reinforcing the bonding strength in the vicinity of the gate pad 30. The number of bonding portions provided in the two regions may be different. The difference in the number of bonding portions provided in the two regions may be within ±5% or ±10%. In this case, too, the bonding strength in the vicinity of the gate pad 30 can be reinforced while balancing the bonding strength in the two regions.

[0058] The first region 151 may have a recess 156 that is recessed in the arrangement surface in a direction perpendicular to the first end side 11. In this example, the recess 156 is rectangular, but the shape of the recess 156 is not limited to this. The first bonding portion 171 is not arranged in the recess 156.

[0059] The gate pad 30 may be disposed opposite the recess 156 in a direction perpendicular to the first end side 11. In this case, the gate connection portion 160 is also disposed opposite the recess 156 in a direction perpendicular to the first end side 11. At least a portion of the gate pad 30 may be disposed inside the recess 156. The entire gate pad 30 may be disposed inside the recess 156. Similarly, at least a portion or the entire gate connection portion 160 may be disposed inside the recess 156.

[0060] Neither the first bonding portion 171 nor the gate bonding portion 161 is disposed in the recess 156 between the gate connection portion 160 and the first region 151. The width of the gate connection portion 160 may be greater than the distance between the second bonding portions 172. In other words, the shortest distance between the gate bonding portion 161 and the first bonding portion 171 may be greater than the distance between the second bonding portions 172.

[0061] In the example of FIG. 4 , the bonding strength in the first region 151 is increased by increasing the density of the first bonding portions 171. In another example, the bonding strength in the first region 151 may be increased by using a material different from that of the second bonding portions 172. For example, the first bonding portions 171 may be formed of a material harder than the second bonding portions 172. Alternatively, the first bonding portions 171 may be formed of a material that has higher connectivity with the main electrode 20 or the main wiring 120 than the second bonding portions 172. Furthermore, the bonding strength in the first region 151 may be increased by increasing the cross-sectional area of ​​the first bonding portions 171 on the arrangement surface compared to the cross-sectional area of ​​the second bonding portions 172. The bonding strength in the first region 151 may be increased by adjusting one or more parameters, such as the number per unit area of ​​the first bonding portions 171, the material, and the cross-sectional area.

[0062] 5 is a diagram showing another example of the arrangement of the gate bond portion 161. The structure other than the gate bond portion 161 is the same as any of the examples in this specification. In this example, the bond strength per unit area of ​​the gate bond portion 161 is smaller than the bond strength per unit area of ​​the first bond portion 171. The bond strength of the gate bond portion 161 may be the same as or different from the bond strength of the first bond portion 171.

[0063] 5, the number of gate junctions 161 per unit area is smaller than the number of first junctions 171 per unit area. In other words, the density at which the gate junctions 161 are provided (for example, the total number of gate junctions 161 in the gate connection portion 160 / the area of ​​the gate connection portion 160) is lower than the density at which the first junctions 171 are provided. According to this example, by providing the first region 151 around the gate pad 30, the bonding strength in the vicinity of the gate pad 30 can be reinforced, and the vicinity of the gate pad 30 can be easily sealed.

[0064] 6 is a diagram showing another example of the configuration of the main electrode connection portion 150. The structure other than the main electrode connection portion 150 is the same as any of the examples in this specification. The main electrode connection portion 150 of this example has a first region 151, a second region 152, and a third region 153 on an arrangement plane parallel to the first main surface 101.

[0065] The third region 153 is a region that is closer to the second end side 12 than the second region 152. That is, the third region 153 is disposed between the second region 152 and the second end side 12 in the direction perpendicular to the second end side 12. As shown in FIG. 6 , the boundary between the second region 152 and the third region 153 may be a straight line parallel to the second end side 12. Of the main electrode connection portion 150 provided with the main electrode joint portion 170, the portion facing the second end side 12 may entirely be the third region 153.

[0066] The third region 153 has a plurality of third bonding portions 173. In this example, the bonding strength per unit area of ​​the third bonding portions 173 is higher than the bonding strength per unit area of ​​the second bonding portions 172. As with the first bonding portions 171, the bonding strength of the third bonding portions 173 can be adjusted by adjusting at least one parameter of the density, material, and cross-sectional area of ​​the third bonding portions 173. For example, the density of the third bonding portions 173 may be higher than the density of the second bonding portions 172.

[0067] The bonding strength per unit area of ​​the third bonding portion 173 may be the same as or different from the bonding strength per unit area of ​​the first bonding portion 171. For example, the bonding strength per unit area of ​​the third bonding portion 173 may be lower than the bonding strength per unit area of ​​the first bonding portion 171.

[0068] The area of ​​the third region 153 may be smaller than the area of ​​the first region 151. No area without a bonded portion, such as the recess 156, is provided near the second end side 12. Therefore, the bonding strength can be reinforced with the relatively small third region 153.

[0069] 7 is a diagram showing another example of the configuration of the main electrode connection portion 150. The structure other than the main electrode connection portion 150 is the same as any of the examples in this specification. The main electrode connection portion 150 of this example has a first region 151, a second region 152, a third region 153, a fourth region 154, and a fifth region 155 on an arrangement plane parallel to the first main surface 101.

[0070] The fourth region 154 is a region that is closer to the third end side 13 than the second region 152. That is, the fourth region 154 is disposed between the second region 152 and the third end side 13 in the direction perpendicular to the third end side 13. As shown in FIG. 7 , the boundary between the second region 152 and the fourth region 154 may be a straight line parallel to the third end side 13.

[0071] The fourth region 154 has a plurality of fourth bonding portions 174. In this example, the bonding strength per unit area of ​​the fourth bonding portions 174 is higher than the bonding strength per unit area of ​​the second bonding portions 172. As with the first bonding portions 171, the bonding strength of the fourth bonding portions 174 can be adjusted by adjusting at least one parameter of the density, material, and cross-sectional area of ​​the fourth bonding portions 174. For example, the density of the fourth bonding portions 174 may be higher than the density of the second bonding portions 172.

[0072] The fifth region 155 is a region that is closer to the fourth end side 14 than the second region 152. That is, the fifth region 155 is disposed between the second region 152 and the fourth end side 14 in a direction perpendicular to the fourth end side 14. As shown in FIG. 7 , the boundary between the second region 152 and the fifth region 155 may be a straight line parallel to the fourth end side 14. In this example, the second region 152 is surrounded by the first region 151, the third region 153, the fourth region 154, and the fifth region 155.

[0073] The fifth region 155 has a plurality of fifth bonding portions 175. In this example, the bonding strength per unit area of ​​the fifth bonding portions 175 is higher than the bonding strength per unit area of ​​the second bonding portions 172. As with the first bonding portions 171, the bonding strength of the fifth bonding portions 175 can be adjusted by adjusting at least one parameter of the density, material, and cross-sectional area of ​​the fifth bonding portions 175. For example, the density of the fifth bonding portions 175 may be higher than the density of the second bonding portions 172.

[0074] The bonding strength per unit area of ​​the fourth bonding portion 174 and the fifth bonding portion 175 may be the same as or different from the bonding strength per unit area of ​​the first bonding portion 171. For example, the bonding strength per unit area of ​​the fourth bonding portion 174 and the fifth bonding portion 175 may be lower than the bonding strength per unit area of ​​the first bonding portion 171.

[0075] The area of ​​the fourth region 154 may be smaller than the area of ​​the first region 151. The area of ​​the fifth region 155 may be smaller than the area of ​​the first region 151.

[0076] Fig. 8 is a diagram showing another example of the configuration of the main electrode connection portion 150 and the gate connection portion 160. The main electrode connection portion 150 in Fig. 8 has a first region 151, a second region 152, a third region 153, a fourth region 154, and a fifth region 155. As with any of the examples shown in Figs. 4 to 7, the main electrode connection portion 150 does not have to have one or more of the third region 153, the fourth region 154, and the fifth region 155.

[0077] In this example, at least one first joint portion 171 is longer in the connection direction than any of the second joint portions 172. All of the second joint portions 172 may have the same length. All of the first joint portions 171 may be longer in the connection direction than the second joint portions 172. All of the first joint portions 171 may have the same length.

[0078] In FIG. 8, bonding portions that are longer than the second bonding portion 172 are marked with a cross. By lengthening the first bonding portion 171, the bonding strength in the first region 151 can be reinforced even if the semiconductor chip 100 is warped. Furthermore, the semiconductor chip 100 can be connected to the wiring substrate 110 even when the semiconductor chip 100 is warped. As explained in step S312 of FIG. 3, since the semiconductor chip 100 does not need to be connected to the wiring substrate 110 in a flattened state, no stress is generated in the first region 151 even when the temperature of the semiconductor chip 100 reaches approximately room temperature. Therefore, the bonding strength in the first region 151 can be reinforced.

[0079] The third bonding portion 173, the fourth bonding portion 174, and the fifth bonding portion 175 may also be longer than the second bonding portion 172. The gate bonding portion 161 may also be longer than the second bonding portion 172. In other words, long bonding portions may be arranged along the edge of the semiconductor chip 100. This reinforces the bonding strength of the first region 151, the third region 153, the fourth region 154, the fifth region 155, and the gate connection portion 160 near the edge of the semiconductor chip 100 where the amount of warpage is large. In this example, the first region 151 is not provided between the gate connection portion 160 and the second region 152. However, the first region 151 may also be provided between the gate connection portion 160 and the second region 152, as in the example of FIG. 4 .

[0080] FIG. 9 is a diagram illustrating the first bonding portion 171, the second bonding portion 172, and the third bonding portion 173 in a cross section parallel to the connection direction. The length of the first bonding portion 171 in the connection direction is defined as L1, the length of the second bonding portion 172 is defined as L2, and the length of the third bonding portion 173 is defined as L3. As described above, the length L1 is greater than the length L2. The length L1 may be 10 μm or more longer than the length L2, 20 μm or more longer, or 30 μm or more longer. The difference between the lengths L1 and L2 is preferably determined based on the amount of warpage of the semiconductor substrate 10. The length L3 may be the same as the length L1. Although not shown in FIG. 9, the lengths of the fourth bonding portion 174, the fifth bonding portion 175, and the gate bonding portion 161 may also be the same as the length L1 of the first bonding portion 171.

[0081] 10 is a diagram showing an example of the structure of the first bonding portion 171 and the second bonding portion 172. The third bonding portion 173, the fourth bonding portion 174, the fifth bonding portion 175, and the gate bonding portion 161 may have a structure similar to that of the first bonding portion 171.

[0082] In FIG. 10, the direction perpendicular to the connection direction is the width direction. One or more bumps 180 are stacked in the connection direction in the first bonding portion 171 and the second bonding portion 172. Each bump 180 may have a protruding portion that protrudes outward in the width direction. The portion where the two bumps 180 are connected is recessed inward in the width direction relative to the protruding portions of the bumps 180. The bump 180 located at either end in the connection direction may have a contact portion 181. The contact portion 181 may have a tapered shape whose cross-sectional area decreases with increasing distance from the stacked portion of the bumps 180 in the connection direction. In another example, the contact portion 181 may not be provided.

[0083] In this example, the number of stages of bumps 180 in at least one first bonding portion 171 is greater than the number of stages of bumps 180 in any of the second bonding portions 172. All of the second bonding portions 172 may have the same number of stages of bumps 180. All of the first bonding portions 171 may have a greater number of stages of bumps 180 than the second bonding portions 172. All of the first bonding portions 171 may have the same number of stages of bumps 180.

[0084] During the manufacturing process of the semiconductor module 200, the plurality of bumps 180 stacked in the first bonding portion 171 may be provided on either the semiconductor chip 100 or the wiring substrate 110. In another example, some of the plurality of bumps 180 stacked in the first bonding portion 171 may be provided on the semiconductor chip 100, and the remaining portion may be provided on the wiring substrate 110. In this case, the semiconductor chip 100 and the wiring substrate 110 are arranged so that the bumps 180 on the semiconductor chip 100 side and the bumps 180 on the wiring substrate 110 side are stacked. For example, each bump 180 of the second bonding portion 172 may be provided on the semiconductor chip 100 (or the wiring substrate 110). Furthermore, of the plurality of bumps 180 of the first bonding portion 171, the same number of bumps 180 as the number of bumps 180 on the second bonding portion 172 may be provided on the semiconductor chip 100 (or the wiring substrate 110). Of the plurality of bumps 180 of the first bonding portion 171, the remaining bumps 180 may be provided on the wiring substrate 110 (or the semiconductor chip 100).

[0085] 11 is a diagram showing another example of the first bonding portion 171, the second bonding portion 172, and the third bonding portion 173. The second bonding portion 172 and the third bonding portion 173 may have the same structure as the first bonding portion 171. Although not shown in FIG. 11, the fourth bonding portion 174, the fifth bonding portion 175, and the gate bonding portion 161 may also have the same structure as the first bonding portion 171.

[0086] At least one first bonding portion 171 has a columnar portion 182 and a plate-like portion 183. The columnar portion 182 has the same structure as any of the first bonding portions 171 described with reference to Figures 1 to 10. The columnar portion 182 shown in Figure 11 has the multi-stage bump structure described with reference to Figure 10.

[0087] The plate-like portion 183 is stacked on the columnar portion 182 in the connection direction. In this example, the columnar portion 182 contacts either the semiconductor chip 100 or the wiring substrate 110, and the plate-like portion 183 contacts the other of the semiconductor chip 100 and the wiring substrate 110. The plate-like portion 183 is a portion that is wider in a direction perpendicular to the connection direction than the columnar portion 182. The thickness of the plate-like portion 183 in the connection direction may be smaller than the length of the columnar portion 182 in the connection direction. The provision of the plate-like portion 183 increases the contact area between the first bonding portion 171 and the semiconductor chip 100 or the wiring substrate 110. This increases the bonding strength between the first bonding portion 171 and the semiconductor chip 100 or the wiring substrate 110.

[0088] The plate-like portion 183 may be formed of a material that has a higher connectivity with the columnar portion 182 than the main wiring 120. For example, the plate-like portion 183 is formed of the same material as the columnar portion 182. The main wiring 120 may be formed of a different material from the plate-like portion 183. By connecting different materials using the plate-like portion 183, which has a relatively large area, it becomes easier to reinforce the bonding strength. In another example, the plate-like portion 183 may be formed of the same material as the main wiring 120.

[0089] In the example of FIG. 11 , the second bonding portion 172 also has a columnar portion 182 and a plate-like portion 183. In another example, the second bonding portion 172 may have the columnar portion 182 but not the plate-like portion 183. In this case, similar to the examples of FIGS. 8 and 9 , the length L1 of the first bonding portion 171 may be greater than the length L2 of the second bonding portion 172. The length of the columnar portion 182 of the first bonding portion 171 may be the same as the length of the columnar portion 182 of the second bonding portion 172. In this case, the length L1 of the first bonding portion 171 is longer than the length L2 of the second bonding portion 172 by the thickness of the plate-like portion 183. In another example, similar to the example of FIG. 10 , the length of the columnar portion 182 of the first bonding portion 171 may be longer than the length of the columnar portion 182 of the second bonding portion 172. The third bond 173 , the fourth bond 174 , the fifth bond 175 and the gate bond 161 may have a structure similar to that of the first bond 171 .

[0090] 12 is a diagram showing an example of a manufacturing process for the semiconductor module 200 shown in FIG. 11. The steps before step S408 shown in FIG. 12 are the same as steps S302 to S306 shown in FIG.

[0091] In step S408, the columnar portion 182 is provided on the semiconductor chip 100 (or the wiring substrate 110), and the columnar portion 184 is provided on the wiring substrate 110 (or the semiconductor chip 100). The columnar portion 184 may be shorter than the columnar portion 182 in the connection direction.

[0092] In step S410, each columnar portion 184 is pressed to form a plate-like portion 183. In step S410, a pressing member 185 having a flat surface may be used to press multiple columnar portions 184 at once. This makes it easy to form plate-like portions 183 with a uniform thickness.

[0093] Through steps S408 and S410, a columnar portion 182 is provided on one of the main electrode 20 of the semiconductor chip 100 and the main wiring 120 of the wiring substrate 110. Furthermore, a plate-like portion 183 is provided on the other of the main electrode 20 and the main wiring 120.

[0094] In step S412, the semiconductor chip 100 and the wiring substrate 110 are aligned so that the respective columnar portions 182 and plate-like portions 183 are connected. In step S414, the semiconductor chip 100 and the wiring substrate 110 are bonded together. Step S414 allows the columnar portions 182 and the plate-like portions 183 to be connected together. This allows the formation of each bonding portion, including at least one first bonding portion 171. Through these steps, the semiconductor module 200 shown in FIG. 11 can be easily manufactured.

[0095] Fig. 13 is a diagram showing an example of the structure of the main wiring 120. Fig. 13 shows an enlarged view of the vicinity of the first joint portion 171. The main wiring 120 of this example has a substrate portion 122, a nickel layer 124, and a gold-plated layer 126. The substrate portion 122 is a portion made of a metal such as copper or aluminum.

[0096] The nickel layer 124 is formed on the base material 122. The nickel layer 124 may be a layer formed by plating the upper surface of the base material 122 with nickel. The nickel layer 124 may be thinner than the base material 122 in the connection direction.

[0097] The gold-plated layer 126 is formed on the nickel layer 124. The gold-plated layer 126 may be a layer obtained by plating the upper surface of the nickel layer 124 with gold. The gold-plated layer 126 may be thinner than the base material portion 122 in the connection direction.

[0098] The gold plating layer 126 is bonded to each of the main electrode joints 170 (first joints 171 and second joints 172 in FIG. 13 ). The main electrode joints 170 may be formed of gold. If nickel is exposed in the gold plating layer 126 at the portion that contacts the main electrode joints 170, the bond strength between the gold plating layer 126 and the main electrode joints 170 will be weakened. For this reason, it is preferable that nickel is not present on the surface of the gold plating layer 126 that is bonded to the main electrode joints 170. During the formation of the gold plating layer 126, nickel from the underlying nickel layer 124 may precipitate on the surface of the gold plating layer 126. For example, if the gold plating layer 126 is thin, nickel is more likely to precipitate. Furthermore, if the temperature at which the gold plating layer 126 is formed is high, nickel is more likely to precipitate. Furthermore, if the time required to form the gold plating layer 126 is long, nickel is more likely to precipitate. Adjusting these conditions can prevent nickel from precipitating on the surface of the gold plating layer 126. Nickel may be present on the surface of the gold plating layer 126 in a portion that is not in contact with the main electrode junction 170 .

[0099] The thickness T1 of the gold plating layer 126 in the connection direction may be 0.5 μm or more. This can prevent nickel from being deposited on the surface of the gold plating layer 126. The thickness T1 may be 0.7 μm or more, or 1 μm or more. The thickness T1 may be 3 μm or less, 2 μm or less, or 1.5 μm or less. Even if the gold plating layer 126 is thin, by providing a plate-like portion 183 on the surface of the gold plating layer 126 as shown in FIG. 11, it is possible to prevent nickel from being deposited on the surface of the plate-like portion 183. In this example, by making the gold plating layer 126 thicker, it is possible to prevent nickel from being deposited on the contact surface with the columnar portion 182 without providing the plate-like portion 183.

[0100] 13 illustrates the structure of the main wiring 120, but at least one of the main electrode 20 and the main wiring 120 may have a structure in which the gold plating layer 126, the nickel layer 124, and the base material 122 are stacked. The structure of this example may be applied to any of the examples described herein. Furthermore, in an example in which the thickness T1 of the gold plating layer 126 is 0.5 μm or greater, the main electrode connection portion 150 may have only the second region 152, without the first region 151, the third region 153, the fourth region 154, and the fifth region 155. Even in this case, the bonding strength of the entire main electrode connection portion 150 can be reinforced by suppressing nickel deposition on the surface of the gold plating layer 126.

[0101] At least one of the main electrode 20 and the main wiring 120 may have a structure in which a gold plating layer 126, a palladium layer, a nickel layer 124, and a substrate portion 122 are stacked. This structure may be applied to any of the examples described herein. The palladium layer is sandwiched between the gold plating layer 126 and the nickel layer 124. The palladium layer may be formed by palladium plating the surface of the nickel layer 124. By providing the palladium layer, it is possible to prevent nickel contained in the nickel layer 124 from precipitating on the surface of the gold plating layer 126. When a palladium layer is provided, the thickness of the gold plating layer 126 may be less than 0.5 μm. The thickness of the gold plating layer 126 may be 0.1 μm or less. The thickness of the gold plating layer 126 may be 0.01 μm or more.

[0102] The semiconductor module 200 described with reference to FIGS. 1 to 13 can be manufactured using steps similar to steps S302 to S312 in FIG. 3 and steps S408 to S414 in FIG. 12. However, in the step of providing the main electrode bonding portions 170 in the main electrode connection portion 150, such as step S308 or step S408, a first region 151 and a second region 152 are set in the main electrode connection portion 150. In addition, a third region 153, a fourth region 154, and a fifth region 155 may be appropriately set in the main electrode connection portion 150. As described above, the arrangement of the main electrode bonding portions 170 in each region is adjusted so that the bonding strength per unit area of ​​the first bonding portions 171 is higher than the bonding strength per unit area of ​​the second bonding portions 172. This adjustment is similar to the example described with reference to FIGS. 1 to 13.

[0103] 13 , in the process of manufacturing the semiconductor module 200 including the nickel layer 124 and the gold plating layer 126, the process from forming the nickel layer 124 and the gold plating layer 126 to connecting the first bonding portion 171 to the gold plating layer 126 may be performed at 250° C. or less. This makes it possible to prevent nickel from precipitating in the portion of the gold plating layer 126 that comes into contact with the first bonding portion 171. The connecting process of connecting the first bonding portion 171 to the gold plating layer 126 refers to the process of connecting at least a portion of the first bonding portion 171 to the gold plating layer 126.

[0104] For example, if the main wiring 120 is provided with a gold plating layer 126 and a nickel layer 124, and the main electrode 20 is provided with a first joint portion 171 as shown in FIG. 3, the connecting step is step S312 of connecting the first joint portion 171 to the main wiring 120. In this case, the temperature of the steps from after the nickel layer 124 and the gold plating layer 126 are formed to the end of step S312 may be 250°C or less. Also, if the main wiring 120 is provided with the gold plating layer 126 and the nickel layer 124, and the main wiring 120 is provided with a plate-shaped portion 183 that is part of the first joint portion 171 as shown in step S184 of FIG. 12, the connecting step is step S410 of forming the plate-shaped portion 183 on the main wiring 120. In this case, the temperature of the steps from after the nickel layer 124 and the gold plating layer 126 are formed to the end of step S410 may be 250°C or less.

[0105] When at least a portion of the first bonding portion 171 is formed on the gold plating layer 126, nickel is less likely to precipitate from the nickel layer 124 in the area covered with the first bonding portion 171. Therefore, by setting the temperature of the above process to 250°C or less, it is possible to prevent nickel from precipitating on the surface of the gold plating layer 126 that is in contact with the first bonding portion 171. The temperature may be 230°C or less, or may be 200°C or less.

[0106] The process from forming the nickel layer 124 and the gold plating layer 126 to fixing the semiconductor chip 100 to the wiring substrate 110 may be performed at 250°C or less. The fixing process for fixing the semiconductor chip 100 to the wiring substrate 110 is a process for fixing the semiconductor chip 100 to the wiring substrate 110 by the main electrode bonding portion 170 and the gate bonding portion 161. In the example of FIG. 3, step S312 corresponds to the fixing process, and in the example of FIG. 12, step S414 corresponds to the fixing process. The process from forming the nickel layer 124 and the gold plating layer 126 to completing the fixing process may be performed at 250°C or less. The temperature may be 230°C or less or 200°C or less. This manufacturing process further suppresses nickel deposition on the surface of the gold plating layer 126 in contact with the first bonding portion 171. In either example, the process for forming the gold plating layer 126 may also be performed at 250°C or less. The temperature may also be 230°C or less, or 200°C or less.

[0107] 14 is an enlarged cross-sectional view of the vicinity of an edge 18 of the semiconductor substrate 10. The edge 18 is any one of the first edge 11, the second edge 12, the third edge 13, and the fourth edge 14. A main electrode 20, a main electrode 21, and an interlayer insulating film 192 are formed on the semiconductor substrate 10. The main electrode 20 and the main electrode 21 are, for example, an emitter electrode and a collector electrode of an IGBT.

[0108] The main electrode 20 is formed on a predetermined surface of the semiconductor substrate 10 in an area where the interlayer insulating film 192 is not provided. The main electrode 21 may be formed on the entire surface of the semiconductor substrate 10 on the opposite side from the main electrode 20.

[0109] The interlayer insulating film 192 in this example is formed in a region that contacts the edge of the semiconductor substrate 10. The semiconductor chip 100 and the wiring substrate 110 are covered with a sealant 191 such as gel or epoxy resin. The sealant 191 is also injected into the region between the semiconductor substrate 10 and the main wiring 120.

[0110] The potential of the edge 18 of the semiconductor substrate 10 is approximately the same as the potential of the main electrode 21. The potential of the main wiring 120 is also approximately the same as the potential of the main electrode 20. The potential difference between the main electrode 20 and the main electrode 21 can be several hundred to several thousand volts. For this reason, it is preferable that the insulation between the vicinity of the edge 18 and the main wiring 120 is high.

[0111] In the semiconductor module 200 of this example, a protective film 193 is provided between the interlayer insulating film 192 and the main wiring 120. The protective film 193 is formed of a material with higher electrical insulation properties than the sealing material 191. The protective film 193 is, for example, a polyimide film. By replacing at least a portion of the sealing material 191 between the vicinity of the edge 18 and the main wiring 120 with the protective film 193, it is possible to improve the insulation between the vicinity of the edge 18 and the main wiring 120. In this example, the protective film 193 is provided in contact with the main wiring 120, but it may also be provided in contact with the interlayer insulating film 192.

[0112] On the other hand, the bonding strength of the main electrode bonding portion 170 near the protective film 193 may be weakened due to the provision of the protective film 193. For example, if the material of the protective film 193 (e.g., polyimide) is present in the contact portion between the main electrode bonding portion 170 and the main wiring 120 or the main electrode 20, the bonding strength will be weakened. In contrast, the semiconductor module 200 described with reference to FIGS. 1 to 13 can reinforce the bonding strength of the main electrode bonding portion 170 near the edge 18. This makes it possible to improve the insulation between the area near the edge 18 and the main wiring 120 while maintaining or improving the bonding strength.

[0113] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention. [Explanation of symbols]

[0114] 10 semiconductor substrate, 11 first edge, 12 second edge, 13 third edge, 14 fourth edge, 18 edge, 20 main electrode, 21 main electrode, 30 gate pad, 100 semiconductor chip, 101 first main surface, 102 second main surface, 110 wiring substrate, 120 main wiring, 122 base material portion, 124 nickel layer, 126 gold plating layer, 130 gate wiring, 140 main wiring, 142 connection portion, 150 main electrode connection portion, 151 first region, 152 second region, 15 3 third region, 154 fourth region, 155 fifth region, 156 recess, 160 gate connection portion, 161 gate junction portion, 170 main electrode junction portion, 171 first junction portion, 172 second junction portion, 173 third junction portion, 174 fourth junction portion, 175 fifth junction portion, 180 bump, 181 contact portion, 182 columnar portion, 183 plate-like portion, 184 columnar portion, 185 pressing member, 191 sealing material, 192 interlayer insulating film, 193 protective film, 200 semiconductor module

Claims

1. a semiconductor chip having a gate pad and a main electrode provided on the same main surface; A wiring board; a main electrode connection portion that connects the main electrode of the semiconductor chip to the wiring substrate; Equipped with the plurality of edges in the outer shape of the semiconductor chip in a top view include a first edge closest to the gate pad; In an arrangement plane parallel to the principal surface, the main electrode connection portion is a first region provided with a plurality of first bonding portions; a second region that is farther from the first end side than the first region and in which a plurality of second bonding portions are provided; and The bonding strength per unit area of ​​the first bonding portion is higher than the bonding strength per unit area of ​​the second bonding portion. Semiconductor module.

2. the first region has a recess that is recessed in a direction perpendicular to the first end side, The gate pad is disposed opposite the recess. The semiconductor module according to claim 1 .

3. a gate connection portion including a plurality of gate junctions connecting the gate pad and the wiring substrate; The semiconductor module according to claim 1 .

4. The bonding strength per unit area of ​​the gate bonding portion is the same as the bonding strength per unit area of ​​the first bonding portion. The semiconductor module according to claim 3 .

5. The bonding strength per unit area of ​​the gate bonding portion is smaller than the bonding strength per unit area of ​​the first bonding portion. The semiconductor module according to claim 3 .

6. the plurality of edges of the semiconductor chip include a second edge farthest from the first edge, The second region is provided up to a position closest to the second end side in the main electrode connection portion. The semiconductor module according to claim 2 .

7. the plurality of edges of the semiconductor chip include a second edge farthest from the first edge, the main electrode connection portion has a third region that is closer to the second end side than the second region in an arrangement plane parallel to the main surface and includes a plurality of third bonding portions; The bonding strength per unit area of ​​the third bonding portion is higher than the bonding strength per unit area of ​​the second bonding portion. The semiconductor module according to claim 2 .

8. the number of the first bonding portions per unit area is greater than the number of the second bonding portions per unit area; The semiconductor module according to claim 1 .

9. At least one of the first bonding portions is longer than any of the second bonding portions in a connection direction connecting the main surface and the wiring board. The semiconductor module according to claim 1 .

10. the first bonding portion and the second bonding portion have one or more bumps stacked in the connection direction; The number of stages of the bumps in at least one of the first bonding portions is greater than the number of stages of the bumps in any of the second bonding portions. The semiconductor module according to claim 9 .

11. At least one of the first joints comprises: A columnar part and a plate-like portion that is stacked with the columnar portion in a connection direction connecting the main surface and the wiring board and has a width greater than that of the columnar portion; The semiconductor module according to claim 1 , comprising:

12. At least one of the main electrode and the wiring substrate has a gold plating layer having a thickness of 0.5 μm or more and is bonded to the first bonding portion. The semiconductor module according to claim 1 .

13. At least one of the main electrode and the wiring substrate has a gold plating layer disposed in a region to be joined with the first joint portion, and a nickel layer disposed below the gold plating layer, The surface of the gold plating layer that is to be joined to the first joining portion is free of nickel. The semiconductor module according to claim 1 .

14. A method for manufacturing a semiconductor module including a semiconductor chip having a gate pad and a main electrode provided on the same main surface, a wiring substrate, and a main electrode connection portion that connects the main electrode of the semiconductor chip to the wiring substrate, the method comprising: In an arrangement plane parallel to the main surface, the main electrode connection portion a first region provided with a plurality of first bonding portions; a second region that is farther from the gate pad than the first region and in which a plurality of second junctions are provided; Established A manufacturing method in which the bonding strength per unit area of ​​the first bonding portion is made higher than the bonding strength per unit area of ​​the second bonding portion.

15. a columnar portion is provided on one of the main electrode and the wiring substrate; a plate-like portion having a width greater than that of the columnar portion is provided on the other of the main electrode and the wiring substrate; At least one first joint is formed by connecting the columnar portion and the plate-like portion. The method of claim 14.

16. At least one of the main electrode and the wiring board has a gold plating layer disposed in a region of the main electrode connecting portion that is joined to the first region, and a nickel layer disposed below the gold plating layer, The steps from forming the nickel layer and the gold plating layer to forming the first bonding portion on the gold plating layer are performed at 250° C. or less. The method of claim 14.

17. The steps from forming the nickel layer and the gold plating layer to fixing the semiconductor chip to the wiring substrate are performed at 250° C. or less. The method of claim 16.

Images