Semiconductor device

Abstract

To provide a semiconductor device with a reduced barrier height.SOLUTION: A Schottky barrier diode 1Q includes: an epitaxial layer 7 as a semiconductor layer formed on a main surface 3 of a semiconductor substrate 2, the epitaxial layer including a first-conductivity-type low-concentration layer 11 in contact with the main surface 3 and a first-conductivity-type high-concentration layer 10 on a surface 7a opposite to the main surface, the layer 10 containing impurities more densely than the layer 11; a Schottky metal 16 on a surface of the semiconductor layer, the Schottky metal forming a Schottky junction with the high-concentration layer 10; a second-conductivity-type impurity region 50 in a surface layer portion of the semiconductor layer so as to be in contact with the Schottky metal, the region forming a pn junction with the semiconductor layer; and a lattice defect region 60 including more lattice defects than the semiconductor layer. The impurity region includes an inner impurity region 55 disposed inside the lattice defect region so as to be in contact with the lattice defect region, and the high-concentration layer 10 includes a plurality of linear regions 45 arranged in a stripe pattern.SELECTED DRAWING: Figure 14

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including a Schottky barrier diode. [Background technology]

[0002] In Schottky barrier diodes, the barrier height is usually adjusted by selecting various barrier metals that form the Schottky barrier. Adjusting the barrier height adjusts the forward voltage drop and reverse leakage current. However, since the number of types of barrier metals is limited, it is not easy to adjust the desired barrier height.

[0003] In the Schottky barrier diode disclosed in Patent Document 1 below, a second barrier metal derived from a second barrier metal film is introduced into a silicide layer formed by a reaction between silicon derived from the substrate and a first barrier metal derived from a thin film of the first barrier metal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-257888 Summary of the Invention [Problem to be solved by the invention]

[0005] In the Schottky barrier diode of Patent Document 1, it is difficult to maintain a constant heat treatment temperature for forming the silicide layer, and there is a limit to the range of adjustment of the barrier height.

[0006] Therefore, one object of the present invention is to provide a semiconductor processing apparatus with a reduced barrier height. [Means for solving the problem]

[0007] The semiconductor device of the present disclosure includes a semiconductor substrate having a main surface, and a semiconductor layer formed on the main surface of the semiconductor substrate, the semiconductor layer including a low-concentration layer of a first conductivity type in contact with the main surface of the semiconductor substrate, and a high-concentration layer of the first conductivity type formed in a surface portion of the semiconductor layer on the side opposite to the main surface, the high-concentration layer having a higher impurity concentration than the low-concentration layer, and a Schottky electrode formed on the surface of the semiconductor layer and forming a Schottky junction with the high-concentration layer.

[0008] According to this configuration, the Schottky junction is formed in the semiconductor layer between the high-concentration layer, which has a higher impurity concentration than the low-concentration layer, and the Schottky electrode, thereby reducing the barrier height compared to a Schottky junction formed between the low-concentration layer and the Schottky electrode.

[0009] The above and other objects, features and advantages of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view of a main part of a Schottky barrier diode according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. [Figure 3] FIG. 3 is an enlarged view of region III shown in FIG. [Figure 4] FIG. 4 is a graph showing the relationship between the n-type impurity concentration in a portion of the epitaxial layer that forms a Schottky junction with the Schottky metal and the threshold voltage of the Schottky barrier diode. [Figure 5] FIG. 5 is a flowchart of a method for manufacturing the Schottky barrier diode. [Figure 6A] FIG. 6A is a cross-sectional view of a first modified example of the Schottky barrier diode. [Figure 6B] FIG. 6B is an enlarged view of the VIB region shown in FIG. 6A. [Figure 7A] FIG. 7A is a plan view of a main part of a second modified example of the Schottky barrier diode. [Figure 7B] FIG. 7B is a cross-sectional view taken along line VIIB-VIIB shown in FIG. 7A. [Figure 7C] FIG. 7C is an enlarged view of region VIIC shown in FIG. 7B. [Figure 8] FIG. 8 is a plan view of a main part of the Schottky barrier diode according to the second embodiment. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. [Figure 10] FIG. 10 is an enlarged view of the X region shown in FIG. [Figure 11] FIG. 11 is a plan view of a main part of a Schottky barrier diode according to a first modified example of the second embodiment. [Figure 12] FIG. 12 is a plan view of a main part of a Schottky barrier diode according to a second modification of the second embodiment. [Figure 13] FIG. 13 is a plan view of a main part of the Schottky barrier diode according to the third embodiment. [Figure 14] FIG. 14 is a cross-sectional view taken along line XIV-XIV shown in FIG. [Figure 15] FIG. 15 is an enlarged view of region XV shown in FIG. [Figure 16A] FIG. 16A is a circuit diagram for explaining a voltage drop around an inner impurity region included in a Schottky barrier diode according to a third embodiment. [Figure 16B] FIG. 16B is a cross-sectional view for explaining a voltage drop around the inner impurity region. [Figure 17] FIG. 17 is a flowchart of a method for manufacturing a Schottky barrier diode according to the third embodiment. [Figure 18A] FIG. 18A is a schematic view for explaining how impurity regions and lattice defect regions are formed in the method for manufacturing a Schottky barrier diode according to the third embodiment. [Figure 18B]FIG. 18B is a schematic diagram for explaining how the impurity regions and the lattice defect regions are formed. [Figure 18C] FIG. 18C is a schematic diagram for explaining how the impurity regions and the lattice defect regions are formed. [Figure 19] FIG. 19 is a cross-sectional view of a first modified example of the Schottky barrier diode according to the third embodiment. [Figure 20] FIG. 20 is a cross-sectional view of a second modified example of the Schottky barrier diode according to the third embodiment. [Figure 21] FIG. 21 is a cross-sectional view of a third modified example of the Schottky barrier diode according to the third embodiment. [Figure 22A] FIG. 22A is a schematic view for explaining how the impurity regions and the lattice defect regions are formed in a method for manufacturing a Schottky barrier diode according to a third modification of the third embodiment. [Figure 22B] FIG. 22B is a schematic view for explaining how the impurity regions and the lattice defect regions are formed in the method for manufacturing a Schottky barrier diode according to the third modification of the third embodiment. [Figure 22C] FIG. 22C is a schematic view for explaining how the impurity regions and the lattice defect regions are formed in the method for manufacturing a Schottky barrier diode according to the third modification of the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] First Embodiment Fig. 1 is a plan view of a main part of a Schottky barrier diode 1 as a semiconductor device according to a first embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is an enlarged view of region III shown in Fig. 2.

[0012] 1, a field insulating film 15, a Schottky metal 16, an anode electrode 17, and a passivation layer 20, which will be described later, are omitted. The configuration of the Schottky barrier diode 1 will be described below with reference to FIGS.

[0013] The Schottky barrier diode 1 is a Schottky barrier diode that uses 4H—SiC (a wide bandgap semiconductor with a breakdown field of approximately 2.8 MV / cm and a bandgap width of approximately 3.26 eV), and is, for example, a square chip in plan view. The length of each side of the chip-shaped Schottky barrier diode 1 is 0.5 mm to 20 mm. That is, the chip size of the Schottky barrier diode 1 is, for example, 0.5 mm / □ to 20 mm / □.

[0014] The Schottky barrier diode 1 includes a semiconductor substrate 2 made of n-type (first conductivity type) SiC. That is, the semiconductor substrate 2 is a SiC substrate. The off-angle of the semiconductor substrate 2 is preferably 4° or less. Note that, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. are used as n-type impurities.

[0015] The semiconductor substrate 2 has a first main surface 3 (see FIG. 2) on one side, a second main surface 4 (see FIG. 2) on the other side, and side surfaces 5a, 5b, 5c, and 5d connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape (a square shape in this embodiment) in a plan view (hereinafter simply referred to as "plan view") seen from their normal direction Z.

[0016] In this embodiment, the side surfaces 5a and 5c extend along a first direction X and face each other in a second direction Y that intersects with the first direction X. In this embodiment, the side surfaces 5b and 5d extend along the second direction Y and face each other in the first direction X. More specifically, the second direction Y is a direction perpendicular to the first direction X.

[0017] The Schottky barrier diode 1 further includes a cathode electrode 6 serving as an ohmic electrode formed so as to cover the entire second main surface 4 of the semiconductor substrate 2. The cathode electrode 6 is made of a metal that forms an ohmic junction with n-type SiC. Examples of metals that form an ohmic junction with n-type SiC include Ti / Ni / Ag and Ti / Ni / Au / Ag.

[0018] The Schottky barrier diode 1 further includes an epitaxial layer 7 made of n-type SiC formed on the first main surface 3 of the semiconductor substrate 2. The epitaxial layer 7 is an example of a semiconductor layer.

[0019] The thickness TS of the semiconductor substrate 2 may be 40 μm or more and 150 μm or less. The thickness TS may be 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, 90 μm or more and 100 μm or less, 100 μm or more and 110 μm or less, 110 μm or more and 120 μm or less, 120 μm or more and 130 μm or less, 130 μm or more and 140 μm or less, or 140 μm or more and 150 μm or less. The thickness TS is preferably 40 μm or more and 130 μm or less.

[0020] The thickness TE of the epitaxial layer 7 may be 1 μm or more and 50 μm or less. The thickness TE may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, or 45 μm or more and 50 μm or less. The thickness TE is preferably 5 μm or more and 15 μm or less.

[0021] The epitaxial layer 7 includes a low-concentration layer 11 in contact with the first main surface 3 of the semiconductor substrate 2, and a high-concentration layer 10 formed in a surface portion of the surface 7a of the epitaxial layer 7 opposite the first main surface 3. The high-concentration layer 10 is a region of the epitaxial layer 7 into which n-type impurities have been implanted. The low-concentration layer 11 is a region of the epitaxial layer 7 into which n-type impurities have not been implanted. Therefore, the high-concentration layer 10 and the low-concentration layer 11 are formed by implanting n-type impurities.

[0022] The n-type impurity concentration of the low concentration layer 11 is lower than the n-type impurity concentration of the semiconductor substrate 2. The n-type impurity concentration of the high concentration layer 10 is higher than the n-type impurity concentration of the low concentration layer 11. The n-type impurity concentration of the high concentration layer 10 may be equal to the impurity concentration of the semiconductor substrate 2. The n-type impurity concentration of the semiconductor substrate 2 is 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The n-type impurity concentration of the low concentration layer 11 may be 1.0×10 15 cm -3 Over 1.0 x 10 18 cm -3 The n-type impurity concentration of the low concentration layer 11 may be 1.0×10 15 cm -3 Over 1.0 x 10 17 cm -3 The n-type impurity concentration of the high concentration layer 10 is preferably less than 1.0×10 17 cm -3 Over 1.0 x 10 20 cm -3 The following is the result.

[0023] Examples of n-type impurities that can be used include nitrogen (N), phosphorus (P), and arsenic (As). The n-type impurity in the high-concentration layer 10 and the n-type impurity in the low-concentration layer 11 may be different. For example, arsenic may be used as the n-type impurity in the semiconductor substrate 2, phosphorus may be used as the n-type impurity in the high-concentration layer 10, and nitrogen may be used as the n-type impurity in the low-concentration layer 11.

[0024] The thickness T1 of the heavily doped layer 10 is smaller than the thickness TE of the epitaxial layer 7. The thickness T1 of the heavily doped layer 10 is, for example, not less than 0.1 μm and not more than 0.2 μm.

[0025] An active region 8 and a non-active region 9 are defined on the surface 7a of the epitaxial layer 7. The active region 8 is defined in the center of the epitaxial layer 7, spaced apart inward from the side surfaces 5a to 5d of the semiconductor substrate 2 in a plan view. The active region 8 is defined in a quadrilateral shape having four sides parallel to the side surfaces 5a to 5d of the semiconductor substrate 2 in a plan view.

[0026] The inactive region 9 is set between the side surfaces 5a to 5d of the semiconductor substrate 2 and the periphery of the active region 8. The inactive region 9 is set in an endless shape (a square ring shape in this embodiment) surrounding the active region 8 in a plan view.

[0027] The Schottky barrier diode 1 further includes a p+ type (second conductivity type) guard region 30 formed in a surface layer portion of the surface 7a of the epitaxial layer 7 in the inactive region 9. The guard region 30 is formed in an endless shape (for example, a square ring, a square ring with chamfered corners, or a circular ring) surrounding the active region 8 in a plan view. As a result, the guard region 30 is formed as a guard ring region. In this form, the active region 8 is defined by the inner end of the guard region 30.

[0028] Guard area 30 includes a wide first guard area 31 and a plurality of (two in the example of FIG. 1 ) second guard areas 32 that surround first guard area 31 and are narrower than first guard area 31. The plurality of second guard areas 32 are provided at equal intervals from the outer end of first guard area 31. Unlike the example of FIG. 1 , guard area 30 may be formed by a single endless area (for example, a square ring, a square ring with chamfered corners, or a circular ring).

[0029] High-concentration layer 10 is formed within active region 8. In the example of FIG. 2, high-concentration layer 10 is formed in the surface layer portion of surface 7a of epitaxial layer 7 throughout the entire active region 8. Therefore, high-concentration layer 10 contacts the entire inner end portion of first guard region 31 in plan view. In plan view, innermost second guard region 32 faces first guard region 31 with low-concentration layer 11 interposed therebetween. Adjacent second guard regions 32 face each other in plan view with low-concentration layer 11 interposed therebetween.

[0030] The bottom 10a of the high-concentration layer 10 is located closer to the surface 7a of the epitaxial layer 7 than the bottom 30a of the guard region 30 (strictly speaking, the bottom of the first guard region 31).

[0031] The Schottky barrier diode 1 further includes an annular field insulating film 15 formed on the surface 7a of the epitaxial layer 7. The field insulating film 15 covers a portion of the surface 7a of the epitaxial layer 7 in the inactive region 9. The field insulating film 15 has an opening 14 that exposes a portion of the surface 7a of the epitaxial layer 7.

[0032] The active size of the active area 8 is, for example, 0.1 mm 2 Over 400mm 2 The field insulating film 15 may have a single layer structure made of, for example, an SiO2 (silicon oxide) or SiN (silicon nitride) layer. The thickness of the field insulating film 15 is, for example, 0.5 μm or more and 3 μm or less.

[0033] Field insulating film 15 has an inner side surface 15a that slopes toward the epitaxial layer 7 with respect to surface 7a of epitaxial layer 7 as it extends inward of field insulating film 15, an outer side surface 15b that slopes toward the epitaxial layer 7 with respect to surface 7a of epitaxial layer 7 as it extends outward of field insulating film 15, and a first coupling surface 15c and a second coupling surface 15d that connect inner side surface 15a and outer side surface 15b and extend parallel to surface 7a of epitaxial layer 7. First coupling surface 15c is in contact with surface 7a of epitaxial layer 7. Second coupling surface 15d is located on the opposite side of first coupling surface 15c from epitaxial layer 7.

[0034] The Schottky barrier diode 1 includes a Schottky metal 16 as a Schottky electrode formed on the surface 7 a of the epitaxial layer 7 , and an anode electrode 17 formed on the Schottky metal 16 .

[0035] The Schottky junction SJ is formed near the contact interface between the Schottky metal 16 and the epitaxial layer 7. The Schottky junction SJ includes a first Schottky junction SJ1 formed between the Schottky metal 16 and the high-concentration layer 10.

[0036] The Schottky metal 16 may be, for example, Ti, Ni, Al, or Mo. The Schottky metal 16 includes a first covering portion 18 that covers the surface 7a of the epitaxial layer 7 in the active region 8, and a second covering portion 19 that covers the field insulating film 15. The second covering portion 19 covers the entire inner surface 15a of the field insulating film 15 and a portion of the second coupling surface 15d. The portion of the second coupling surface 15d that is covered by the second covering portion 19 is smaller in plan view than the portion of the second coupling surface 15d that is positioned outside the second covering portion 19.

[0037] The first guard region 31 is in contact with the Schottky metal 16 and the field insulating film 15 , and the plurality of second guard regions 32 are in contact with the field insulating film 15 .

[0038] The anode electrode 17 may include, for example, at least one of the following species: Ti, Ni, Al, Mo, and conductive polysilicon.

[0039] The Schottky barrier diode 1 further includes a passivation layer 20 formed on the anode electrode 17. The passivation layer 20 is an insulating layer. The passivation layer 20 may have a single-layer structure made of a silicon oxide layer or a silicon nitride layer, or may have a stacked structure including a silicon oxide layer and a silicon nitride layer. When the passivation layer 20 has a stacked structure, a silicon oxide layer may be formed on a silicon nitride layer, or a silicon nitride layer may be formed on a silicon oxide layer. In this embodiment, the passivation layer 20 has a single-layer structure made of a silicon nitride layer.

[0040] In a plan view, the passivation layer 20 is formed at an interval in an inner region from the side surfaces 5a to 5d of the semiconductor substrate 2. A subpad opening 21 is formed in the passivation layer 20 to expose a part of the anode electrode 17 as a pad region.

[0041] FIG. 4 is a graph showing the relationship between the n-type impurity concentration of the portion of the epitaxial layer 7 where the Schottky junction SJ is formed with the Schottky metal 16 and the threshold voltage Vth of the Schottky barrier diode 1.

[0042] The forward rise voltage (threshold voltage Vth) of the Schottky junction increases as the barrier height increases. As shown in FIG. 4, the higher the n-type impurity concentration in the epitaxial layer 7 where the Schottky junction SJ is formed with the Schottky metal 16, the smaller the threshold voltage Vth. When the n-type impurity concentration is 1.0×10 17 cm -3 If the n-type impurity concentration of the high concentration layer 10 is 1.0×10 or more, the threshold voltage Vth can be adjusted to be sufficiently small, specifically, 0.93 V or less. 17 cm -3Over 1.0 x 10 20 cm -3 Since the threshold voltage is less than 100 volts, the threshold voltage can be made sufficiently small.

[0043] On the other hand, as described above, the n-type impurity concentration of the low concentration layer 11 is, for example, 1.0×10 15 cm -3 Over 1.0 x 10 17 cm -3 Therefore, unlike this embodiment, in the configuration in which the Schottky metal 16 and the low concentration layer 11 form the Schottky junction SJ, the threshold voltage Vth is greater than 0.95V.

[0044] That is, in the configuration in which the Schottky junction SJ is formed between the high-concentration layer 10 and the Schottky metal 16 as in the first embodiment, the barrier height can be reduced compared to the configuration in which the Schottky junction SJ is formed between the Schottky metal 16 and the low-concentration layer 11.

[0045] By adjusting the degree of implantation of n-type impurities into the surface layer of the epitaxial layer 7, the barrier height can be freely adjusted. In other words, the degree of freedom in designing the Schottky barrier diode 1 is improved. For example, when the n-type impurity concentration is 1.0×10 20 cm -3 By adjusting the voltage Vth to 0.82V, the threshold voltage Vth can be adjusted to about 0.82V.

[0046] The depletion layer formed by guard region 30 when a reverse voltage is applied spreads effectively from the portion where the inner end of guard region 30 (the inner end of first guard region 31 in the example of FIG. 2) contacts low-concentration layer 11. Therefore, the depletion layer formed by guard region 30 when a reverse voltage is applied spreads more easily when the inner end of guard region 30 (the inner end of first guard region 31 in the example of FIG. 2) contacts both low-concentration layer 11 and high-concentration layer 10, compared to when the inner end of guard region 30 (the inner end of first guard region 31 in the example of FIG. 2) contacts only high-concentration layer 10.

[0047] As in the first embodiment, if the bottom 10a of the high-concentration layer 10, which has a higher n-type impurity concentration than the low-concentration layer 11, is located closer to the surface 7a of the epitaxial layer 7 than the bottom 30a of the guard region 30 (the bottom of the first guard region 31 in the example of FIG. 2), the inner end of the guard region 30 is in contact with both the low-concentration layer 11 and the high-concentration layer 10. Therefore, a depletion layer can be spread inside the guard region 30 when a reverse voltage is applied. This makes it possible to suppress a decrease in surge withstand voltage caused by the provision of the high-concentration layer 10.

[0048] Next, a description will be given of a method for manufacturing the Schottky barrier diode 1. Fig. 5 is a flowchart for explaining an example of a method for manufacturing the Schottky barrier diode 1 shown in Fig. 1.

[0049] In manufacturing the Schottky barrier diode 1, first, a semiconductor substrate 2 is prepared (step S1). Next, an n-type epitaxial layer 7 is grown on the first main surface 3 of the semiconductor substrate 2 (step S2). Next, n-type impurities are implanted into a surface portion of the surface 7a of the epitaxial layer 7, for example, via an ion implantation mask, thereby forming a high-concentration layer 10 and a low-concentration layer 11 (step S3). Next, a guard region 30 is formed by implanting p-type impurities, for example, via an ion implantation mask (step S4).

[0050] Then, for example, by CVD (Chemical Vapor Deposition), a field insulating film 15 is formed on the epitaxial layer 7 (step S5). Next, a Schottky metal 16 is formed on the field insulating film 15 by, for example, sputtering (step S6). Next, aluminum or the like is formed on the anode electrode 17 by, for example, sputtering (step S7). Next, a passivation layer 20 is formed on the anode electrode 17 by, for example, CVD (step S8). And finally, a cathode electrode 6 is formed over the entire second main surface 4 of the semiconductor substrate 2 by, for example, sputtering (step S9).

[0051] Next, first and second modified examples of the Schottky barrier diode 1 will be described with reference to FIGS. 6A to 7C.

[0052] Fig. 6A is a cross-sectional view of a Schottky barrier diode 1 according to a first modification. Fig. 6B is an enlarged view of region VIB shown in Fig. 6A. Fig. 6A is a cross-sectional view of the same portion as Fig. 2. In Figs. 6A and 6B, components equivalent to those shown in Figs. 1 to 5 described above are assigned the same reference numerals as in Fig. 1, etc., and descriptions thereof will be omitted.

[0053] In the Schottky barrier diode 1 according to the first modification, the high-concentration layer 10 is formed in the surface portion of the surface 7a of the epitaxial layer 7 not only in the active region 8 but also in the non-active region 9. The high-concentration layer 10 is exposed from the side surface of the epitaxial layer 7.

[0054] In detail, the high-concentration layer 10 includes a first region 41 located inside the inner end of the first guard region 31, a second region 42 located between the first guard region 31 and the innermost second guard region 32, a third region 43 located between adjacent second guard regions 32, and a fourth region 44 located outside the outer end of the outermost second guard region 32.

[0055] In a plan view, the first region 41 contacts the entire inner end of the first guard region 31. The second region 42 contacts the outer end of the first guard region 31 and the inner end of the innermost second guard region 32. The third region 43 contacts both the outer end of the inner second guard region 32 of adjacent second guard regions 32 and the inner end of the outermost second guard region 32 of adjacent second guard regions 32. The fourth region 44 contacts the outer end of the outermost second guard region 32. The fourth region 44 is exposed from the side surface of the epitaxial layer 7.

[0056] Fig. 7A is a plan view of a main part of a Schottky barrier diode 1 according to a second modification. Fig. 7B is a cross-sectional view taken along line VIIB-VIIB shown in Fig. 7A. Fig. 7C is an enlarged view of region VIIC shown in Fig. 7B. Fig. 7B is a cross-sectional view of the same part as in Fig. 2. In Figs. 7A and 7B, components equivalent to those shown in Figs. 1 to 7 described above are given the same reference numerals as in Fig. 1, etc., and descriptions thereof will be omitted.

[0057] In the Schottky barrier diode 1 according to the second modification, the low concentration layer 11 is located between the high concentration layer 10 and the guard region 30 in a planar view. The high concentration layer 10 is surrounded by the low concentration layer 11 in a planar view. The high concentration layer 10 faces the first guard region 31 with the low concentration layer 11 interposed therebetween in a planar view.

[0058] The low-concentration layer 11 is in contact with the Schottky metal 16 at a position between the first guard region 31 and the high-concentration layer 10. Therefore, the Schottky junction SJ is formed not only between the Schottky metal 16 and the high-concentration layer 10, but also between the Schottky metal 16 and the low-concentration layer 11. In other words, the Schottky junction SJ includes a first Schottky junction SJ1 formed between the Schottky metal 16 and the high-concentration layer 10 and a second Schottky junction SJ2 formed between the Schottky metal 16 and the low-concentration layer 11.

[0059] However, it is preferable that the first Schottky junction SJ1 is larger than the second Schottky junction SJ2 in plan view, so that the barrier height can be sufficiently reduced.

[0060] Second Embodiment Fig. 8 is a plan view of a main part of a Schottky barrier diode 1P according to a second embodiment. Fig. 9 is a cross-sectional view taken along line IX-IX shown in Fig. 8. Fig. 10 is an enlarged view of region X shown in Fig. 9.

[0061] 8 to 10, components equivalent to those shown in the above-described FIGS. 1 to 7 are given the same reference numerals as in FIG. 1 etc., and descriptions thereof will be omitted (the same applies to FIGS. 11 and 12 described later).

[0062] The Schottky barrier diode 1P further includes a p+ impurity region 50 of the second conductivity type, which is formed in a surface portion of the surface 7a of the epitaxial layer 7 so as to be in contact with the Schottky metal 16 and forms a pn junction PJ between the epitaxial layer 7 and the impurity region 50. The pn junction PJ is formed near the contact interface between the impurity region 50 and the epitaxial layer 7. The p-type impurity concentration of the impurity region 50 is, for example, 10×10 16 cm -3 Over 10x10 21 cm -3 The following is the result.

[0063] In plan view, the high concentration layers 10 and the impurity regions 50 are alternately arranged along the second direction Y.

[0064] More specifically, the heavily doped layer 10 includes a plurality of linear regions 45 arranged in a stripe pattern. The impurity region 50 includes a plurality of linear impurity regions 51 arranged in a stripe pattern.

[0065] The linear regions 45 are arranged at equal intervals in the second direction Y, and each linear region 45 extends in the first direction X. The linear regions 45 are in contact with the inner end of the guard region 30 (the inner end of the first guard region 31 in the example of FIG. 8).

[0066] The linear impurity regions 51 are arranged at equal intervals in the second direction Y, and each linear impurity region 51 extends in the first direction X. The linear impurity regions 51 are integral with the first guard region 31. More specifically, both ends of the linear impurity region 51 in the first direction X are connected to the inner ends of the first guard region 31, and there is no boundary between the linear impurity region 51 and the first guard region 31.

[0067] The bottom 50a of the impurity region 50 (the bottom of the linear impurity region 51 in the example of Figure 9) is flush with the bottom 30a of the guard region 30 and is located on the opposite side of the surface 7a of the epitaxial layer 7 than the bottom 10a of the high-concentration layer 10 (the bottom of the linear region 45).

[0068] According to the second embodiment, the same effect as that of the first embodiment can be achieved, that is, the barrier height can be reduced.

[0069] According to the second embodiment, the Schottky barrier diode 1P is provided with both a Schottky junction SJ and a pn junction PJ. Therefore, when a reverse voltage is applied, a depletion layer is formed around the pn junction PJ, and the leakage current flowing from the cathode electrode 6 toward the anode electrode 17 is suppressed. Therefore, even if the n-type impurity concentration of the high-concentration layer 10 is increased to reduce the barrier height, the leakage current can be sufficiently suppressed.

[0070] The Schottky barrier diode 1P can be manufactured by the same manufacturing method (see FIG. 5) as that of the Schottky barrier diode 1 according to the first embodiment. The impurity region 50 is formed at the same time as the guard region 30.

[0071] Next, a first modified example (see FIG. 11) and a second modified example (see FIG. 12) of the Schottky barrier diode 1P of the second embodiment will be described.

[0072] 11 , the impurity regions 50 of the Schottky barrier diode 1P may be formed in a mesh pattern so as to divide the high-concentration layer 10 into a matrix in a plan view. Specifically, the high-concentration layer 10 is composed of a plurality of unit regions 46 arranged in a matrix and surrounded by the impurity regions 50. The impurity region 50 is composed of a plurality of first extended impurity regions 52 extending in a first direction X and a plurality of second extended impurity regions 53 extending in a second direction Y.

[0073] 12, the impurity region 50 of the Schottky barrier diode 1P may include a plurality of point-like impurity regions 54 arranged in a staggered pattern in the active region 8 in a planar view. In the example shown in Fig. 12, the point-like impurity regions 54 have a circular shape in a planar view. The point-like impurity regions 54 may also have a polygonal shape in a planar view.

[0074] Third Embodiment Fig. 13 is a plan view of a main part of a Schottky barrier diode 1Q according to a third embodiment. Fig. 14 is a cross-sectional view taken along line XIV-XIV shown in Fig. 13. Fig. 15 is an enlarged view of region XV shown in Fig. 14.

[0075] 13 to 15, the same components as those shown in the above-described FIGS. 1 to 12 are denoted by the same reference numerals as in FIG. 1, etc., and the description thereof will be omitted (the same applies to FIGS. 16A to 22C described later).

[0076] The Schottky barrier diode 1Q according to the third embodiment differs from the Schottky barrier diode 1P according to the second embodiment mainly in that a lattice defect region 60 having more lattice defects than the epitaxial layer 7 is formed in the surface layer portion of the epitaxial layer 7.

[0077] The lattice defect region 60 is a region formed by implanting rare gas atoms such as argon (Ar) into the epitaxial layer 7. Therefore, the lattice defect region 60 is also called a rare gas-containing region. The impurity concentration of the lattice defect region 60 is, for example, 10×10 19 cm -3 Over 10x10 21 cm -3 The following is the result.

[0078] The lattice defect region 60 is in contact with the Schottky metal 16. When rare gas atoms are implanted into the epitaxial layer 7, the crystal lattice of SiC constituting the epitaxial layer 7 is destroyed, causing lattice defects. Therefore, although the lattice defect region 60 is in contact with the Schottky metal 16, it does not form a Schottky junction with the Schottky metal 16, and inhibits current from flowing from the Schottky metal 16 to the epitaxial layer 7. In other words, the lattice defect region 60 has more lattice defects than the epitaxial layer 7, and is therefore a high-resistance layer having a higher resistance than the epitaxial layer 7.

[0079] The lattice defect region 60 is provided around one of the plurality of linear impurity regions 51 .

[0080] More specifically, the impurity region 50 includes an inner impurity region 55 that is arranged inside the lattice defect region 60 so as to be in contact with the lattice defect region 60, and an outer impurity region 56 that is arranged outside the lattice defect region 60. Of the multiple linear impurity regions 51, the linear impurity region 51 that is located inside the lattice defect region 60 functions as the inner impurity region 55, and the linear impurity region 51 that is located outside the lattice defect region 60 functions as the outer impurity region 56. The inner impurity region 55 is sandwiched between the lattice defect regions 60 on both sides in the second direction Y.

[0081] The outer impurity region 56 includes a pair of outer contact impurity regions 57 arranged on the opposite side of the lattice defect region 60 from the inner impurity region 55 so as to be in contact with the lattice defect region 60, and a plurality of outer separating impurity regions 58 arranged on the opposite side of the lattice defect region 60 from the inner impurity region 55 so as to be spaced apart from the lattice defect region 60.

[0082] The lattice defect region 60 contacts the inner impurity region 55 on both sides in the second direction Y. In the example of FIG. 13 , both end portions of the lattice defect region 60 in the first direction X contact the inner ends of the first guard region 31. Unlike the example of FIG. 13 , both end portions of the lattice defect region 60 in the first direction X do not contact the inner ends of the first guard region 31, and may face the first guard region 31 with the low-concentration layer 11 interposed therebetween.

[0083] The lattice defect region 60 includes a first lattice defect region 61 that extends linearly in the first direction X and contacts the inner impurity region 55 from one side in the second direction Y, and a second lattice defect region 62 that extends linearly in the first direction X and contacts the inner impurity region 55 from the other side in the second direction Y.

[0084] The outer contact impurity region 57 on one side in the second direction Y is sandwiched between the first lattice defect region 61 and the linear region 45 of the high-concentration layer 10 in plan view. The outer contact impurity region 57 on the other side in the second direction Y is sandwiched between the second lattice defect region 62 and the linear region 45 of the high-concentration layer 10 in plan view.

[0085] The bottom of each linear impurity region 51 (bottom 50a of impurity region 50) is in contact with the epitaxial layer 7. The bottom of each linear impurity region 51 includes a pair of curved portions facing the back surface of the epitaxial layer 7 and a flat portion connecting the curved portions.

[0086] The bottom 60a of the lattice defect region 60 is in contact with the low-concentration layer 11. The bottom 60a of the lattice defect region 60 includes a pair of curved portions extending toward the rear surface of the epitaxial layer 7 and a flat portion connecting the curved portions. The flat portion of the bottom 60a of the lattice defect region 60 is formed flush with the flat portion of the bottom 55a of the inner impurity region 55 and the flat portion of the bottom 57a of the outer contact impurity region 57.

[0087] According to the third embodiment, the same effects as those of the first and second embodiments are achieved.

[0088] In a configuration in which the lattice defect region 60 is not provided, such as the Schottky barrier diode 1P according to the second embodiment, minority carriers are injected from the pn junction PJ into the epitaxial layer 7 when a forward overcurrent is applied. This reduces the resistance of the epitaxial layer 7, suppressing the amount of heat generated and improving surge resistance. However, if the thickness TE of the epitaxial layer 7 is large, the voltage drop across the epitaxial layer 7 increases, reducing the voltage applied to the pn junction PJ.

[0089] Therefore, by providing the lattice defect region 60 as in the third embodiment, the current I1 flowing through the lattice defect region 60 can be suppressed, and the current I1 can be made smaller than the current I2 flowing through the Schottky junction SJ1. As a result, as shown in Fig. 16A, the voltage drop V1 due to the first vicinity portion 70 located near the lattice defect region 60 in the epitaxial layer 7 is reduced to be smaller than the voltage drop V2 due to the second vicinity portion 71 located near the Schottky junction SJ1 in the epitaxial layer 7.

[0090] Therefore, the voltage drop in the portion of the epitaxial layer 7 located near the inner impurity region 55 is also small, similar to the voltage drop V1 caused by the first vicinity portion 70. Therefore, the potential difference VP across the pn junction PJ1 formed between the inner impurity region 55 and the epitaxial layer 7 can be made larger than the potential difference VS across the Schottky junction SJ1. This makes it possible to ensure a sufficient potential difference VP across the pn junction PJ1 formed between the inner impurity region 55 and the epitaxial layer 7. This in turn improves surge resistance.

[0091] As shown in FIG. 16B, if the distance L between the Schottky junction SJ1 and the inner impurity region 55 is greater than the thickness TE of the epitaxial layer 7, current can be further prevented from flowing through the portion of the epitaxial layer 7 located between the inner impurity region 55 and the semiconductor substrate 2.

[0092] The distance L between the Schottky junction SJ1 and the inner impurity region 55 corresponds to the sum of the width W1 of the outer contact impurity region 57 and the width W2 of the first lattice defect region 61 (the width of the second lattice defect region 62).

[0093] The area inside a position shifted from the boundary 73 between the Schottky junction SJ1 and the pn junction PJ2 toward the inner impurity region 55 by a distance equal to the thickness TE of the epitaxial layer 7 is referred to as the inner region IR, and the area outside the inner region IR is referred to as the outer region OR. In the inner region IR, the current flowing through the epitaxial layer 7 is effectively suppressed by the lattice defect region 60. If the distance L between the Schottky junction SJ and the inner impurity region 55 is greater than the thickness TE of the epitaxial layer 7, the inner region IR is set in the epitaxial layer 7. In other words, if the distance L between the Schottky junction SJ and the inner impurity region 55 is greater than the thickness TE of the epitaxial layer 7, the first vicinity portion 70 is located within the inner region IR.

[0094] Next, a method for manufacturing the Schottky barrier diode 1Q according to the third embodiment will be described with reference to a flowchart of FIG.

[0095] The method for manufacturing the Schottky barrier diode 1Q differs from the method for manufacturing the Schottky barrier diode 1 according to the first embodiment in that the impurity region 50 is formed simultaneously with the guard region 30 (step S4), and after the guard region 30 is formed, the lattice defect region 60 is formed (step S10). Thereafter, the field insulating film 15 is formed (step S5).

[0096] Next, a detailed description will be given of how the impurity regions 50 and the lattice defect regions 60 are formed. Figures 18A to 18C are schematic diagrams for explaining how the impurity regions 50 and the lattice defect regions 60 are formed.

[0097] 18A, after a high-concentration layer 10 is formed in the surface portion of the epitaxial layer 7, a resist mask 80 having a predetermined pattern is formed on the epitaxial layer 7. By using an ion implantation method, p-type impurities are introduced into the portions of the surface portion of the epitaxial layer 7 that are not covered by the resist mask 80, thereby forming impurity regions 50 (plurality of linear impurity regions 51) together with guard regions 30 (see FIG. 14) (step S4). Thereafter, the resist mask 80 is removed.

[0098] After resist mask 80 is removed, as shown in FIG. 18B, resist mask 81 having a pattern exposing the region where lattice defect region 60 is to be formed and covering the other regions is formed on epitaxial layer 7.

[0099] Specifically, resist mask 81 exposes both sides of linear impurity region 51, which will become the base of inner impurity region 55, in the surface portion of epitaxial layer 7. Next, as shown in Fig. 18C, rare gas atoms are introduced by ion implantation into a portion of surface portion 7a of epitaxial layer 7 that is not covered by resist mask 81, thereby forming lattice defect regions 60 on both sides of linear impurity region 51, which will become the base of inner impurity region 55 (step S10). In this way, inner impurity region 55 is formed.

[0100] Thereafter, the resist mask 81 is removed, and the field insulating film 15 is formed on the epitaxial layer 7 (step S5).

[0101] Next, first and second modified examples of the Schottky barrier diode 1Q will be described with reference to FIGS. 19 to 22C.

[0102] FIG. 19 is an enlarged cross-sectional view of a Schottky barrier diode 1Q according to a first modification. FIG. 19 is a cross-sectional view of the same portion as FIG. 14. In FIG. 19, components equivalent to those shown in FIGS. 1 to 18C described above are assigned the same reference numerals as in FIG. 1, and their description will be omitted. In the Schottky barrier diode 1Q according to the first modification, the bottom 60a of the lattice defect region 60 is located closer to the surface 7a of the epitaxial layer 7 than the bottom 50a of the impurity region 50. The bottom 60a of the lattice defect region 60 is in contact with the low-concentration layer 11. The Schottky barrier diode 1Q according to the first modification can be manufactured by a manufacturing method similar to the manufacturing method described above (see FIGS. 17 to 18C).

[0103] Fig. 20 is an enlarged cross-sectional view of a Schottky barrier diode 1Q according to a second modification. Fig. 20 is a cross-sectional view of the same portion as Fig. 14. In Fig. 20, the same components as those shown in Figs. 1 to 19 are given the same reference numerals as in Fig. 1, etc., and descriptions thereof will be omitted.

[0104] In the Schottky barrier diode 1Q according to the second modification, the bottom 60a of the lattice defect region 60 is located closer to the surface 7a of the epitaxial layer 7 than the bottom 10a of the high-concentration layer 10, and the bottom 60a of the lattice defect region 60 is in contact with the linear region 45 of the high-concentration layer 10. The Schottky barrier diode 1Q according to the second modification can be manufactured by a manufacturing method similar to the manufacturing method described above (see FIGS. 17 to 18C).

[0105] FIG. 21 is an enlarged view of a cross section of a third modified example of the Schottky barrier diode 1Q according to the third embodiment.

[0106] 21 , in the Schottky barrier diode 1Q according to the third modification, the bottom 60a of the lattice defect region 60 is located closer to the surface 7a of the epitaxial layer 7 than the bottom 50a of the impurity region 50, and the bottom 60a of the lattice defect region 60 is in contact with the impurity region 50. In other words, the impurity region 50 includes a bottomside impurity region 59 in contact with the bottom 60a of the lattice defect region 60. The bottom of the bottomside impurity region 59 is in contact with the epitaxial layer 7.

[0107] The bottomside impurity region 59 is integral with the outer contact impurity region 57 and the inner impurity region 55. More specifically, the bottomside impurity region 59 is provided on both sides of the inner impurity region 55 in the second direction Y. The bottomside impurity region 59 includes a first bottomside impurity region 59A extending between the outer contact impurity region 57 located on one side of the inner impurity region 55 and the inner impurity region 55 and in contact with the bottom of the first lattice defect region 61, and a second bottomside impurity region 59B extending between the outer contact impurity region 57 located on the other side of the inner impurity region 55 and the inner impurity region 55 and in contact with the bottom of the second lattice defect region 62.

[0108] The method for manufacturing the Schottky barrier diode 1Q according to the third modification is slightly different from the above-described manufacturing method (FIGS. 17 to 18C). FIGS. 22A to 22C are schematic views for explaining how the impurity regions 50 and the lattice defect regions 60 are formed in the method for manufacturing the Schottky barrier diode 1Q according to the second modification.

[0109] 22A, after the epitaxial layer 7 is formed on the first main surface 3 of the semiconductor substrate 2, a resist mask 82 having a predetermined pattern is formed on the epitaxial layer 7. By ion implantation, p-type impurities are introduced into portions of the surface layer of the epitaxial layer 7 that are not covered by the resist mask 82, thereby forming the guard region 30 (see FIG. 14) and the impurity region 50 (plurality of linear impurity regions 51) (step S4). More specifically, a plurality of outer separated impurity regions 58 and a first base impurity region 83 that serves as a base for the inner impurity region 55 and the pair of outer contact impurity regions 57 are formed.

[0110] Thereafter, resist mask 82 is removed. After resist mask 82 is removed, as shown in Fig. 22B, a resist mask 84 having a pattern exposing the region where lattice defect region 60 is to be formed and covering the other regions is formed on epitaxial layer 7. Specifically, resist mask 84 covers the center portion of first base impurity region 83 and both end portions of first base impurity region 83 in second direction Y.

[0111] 22C , rare gas atoms are introduced by ion implantation into a portion of the surface layer portion of the surface 7a of the epitaxial layer 7 that is not covered by the resist mask 84, thereby forming lattice defect regions 60 on both sides of a portion that becomes the base of the inner impurity region 55 in the first base impurity region 83 (step S10). As a result, the inner impurity region 55, the outer contact impurity region 57, and the bottomside impurity region 59 are formed.

[0112] Thereafter, the resist mask 84 is removed, and the field insulating film 15 is formed on the epitaxial layer 7 (step S5).

[0113] <Other embodiments> For example, the respective embodiments (first to third embodiments) can be combined as appropriate.

[0114] Specifically, in the Schottky barrier diode 1P of the second embodiment, the high-concentration layer 10 may be formed not only in the active region 8 but also in the inactive region 9, as in the first modified example of the first embodiment. Also, in the Schottky barrier diode 1P, the high-concentration layer 10 may face the first guard region 31 via the low-concentration layer 11, as in the second modified example of the first embodiment.

[0115] Similarly, in the Schottky barrier diode 1Q of the third embodiment, the high-concentration layer 10 may be formed not only in the active region 8 but also in the inactive region 9, and the high-concentration layer 10 may face the first guard region 31 via the low-concentration layer 11.

[0116] In the Schottky barrier diode 1Q of the third embodiment, the impurity regions 50 may be formed in a mesh shape so as to divide the high-concentration layer 10 into rows and columns in a plan view, as in the first modification of the second embodiment. In the Schottky barrier diode 1Q of the third embodiment, the impurity regions 50 may include a plurality of dot-like impurity regions 54 arranged in a staggered pattern in a plan view, as in the second modification of the second embodiment.

[0117] In the Schottky barrier diodes 1, 1P, and 1Q of the above-described embodiments, the semiconductor substrate 2 and the epitaxial layer 7 are made of n-type SiC, the high-concentration layer 10 is an n-type impurity region, and the high-concentration layer 10 is a p-type impurity region. However, unlike the above-described embodiments, the semiconductor substrate 2 and the epitaxial layer 7 may be made of p-type SiC, the high-concentration layer 10 is a p-type impurity region, and the impurity region 50 is an n-type impurity region.

[0118] Examples of features extracted from this specification and drawings are given below: [A1] to [A14] below provide a semiconductor device with a reduced barrier height.

[0119] [A1] A semiconductor device comprising: a semiconductor substrate having a main surface; a semiconductor layer formed on the main surface of the semiconductor substrate, the semiconductor layer including a low-concentration layer of a first conductivity type in contact with the main surface of the semiconductor substrate; and a high-concentration layer of the first conductivity type formed in a surface portion of the semiconductor layer on the side opposite to the main surface, the high-concentration layer having a higher impurity concentration than the low-concentration layer; and a Schottky electrode formed on the surface of the semiconductor layer and forming a Schottky junction with the high-concentration layer.

[0120] According to this configuration, the Schottky junction is formed in the semiconductor layer between the high-concentration layer, which has a higher impurity concentration than the low-concentration layer, and the Schottky electrode, thereby reducing the barrier height compared to a Schottky junction formed between the low-concentration layer and the Schottky electrode.

[0121] [A2] The impurity concentration of the low concentration layer is 1.0 × 10 12 cm -3 Over 1.0 x 10 17 cm -3 and the impurity concentration of the high concentration layer is less than 1.0×10 17 cm -3 Over 1.0 x 10 20 cm -3 The semiconductor device according to A1, wherein:

[0122] [A3] The semiconductor device according to A1 or A2, further comprising a second conductivity type annular guard region formed in the surface layer portion of the semiconductor layer, and the high concentration layer is formed within an active region surrounded by the guard region.

[0123] [A4] The semiconductor device according to A3, wherein the bottom of the high-concentration layer is located closer to the surface of the semiconductor layer than the bottom of the guard region.

[0124] [A5] The semiconductor device according to A3 or A4, wherein the high concentration layer is formed over the entire active region.

[0125] [A6] The semiconductor device according to any one of A3 to A5, wherein the high-concentration layer faces the guard region via the low-concentration layer.

[0126] [A7] The semiconductor device according to any one of A3 to A6, wherein the high concentration layer is set on the surface of the semiconductor layer and is formed in a non-active region surrounding the active region.

[0127] [A8] The semiconductor device according to any one of A1 to A7, further including a second conductivity type impurity region formed in the surface layer portion of the semiconductor layer so as to be in contact with the Schottky electrode and forming a pn junction between the semiconductor layer and the impurity region.

[0128] [A9] The semiconductor device according to A8, further including a lattice defect region formed in the surface layer portion of the semiconductor layer so as to be in contact with the Schottky electrode and having more lattice defects than the semiconductor layer, and the impurity region includes an inner impurity region arranged inside the lattice defect region so as to be in contact with the lattice defect region.

[0129] [A10] The semiconductor device according to A9, wherein the resistance of the lattice defect region is higher than the resistance of the semiconductor layer.

[0130] [A11] The semiconductor device according to A9 or A10, wherein the distance between the Schottky junction and the inner impurity region is greater than the thickness of the semiconductor layer.

[0131] [A12] The semiconductor device according to any one of A9 to A11, wherein the impurity region includes an outer impurity region arranged on the opposite side of the lattice defect region from the inner impurity region so as to be in contact with the lattice defect region.

[0132] [A13] The semiconductor device according to any one of A8 to A12, wherein the impurity regions are formed in a mesh shape so as to divide the high concentration layer into rows and columns in a plan view.

[0133] [A14] The semiconductor device according to any one of A8 to A13, wherein the impurity region includes a plurality of dot-like impurity regions arranged in a staggered pattern in plan view.

[0134] Although the embodiments of the invention have been described in detail, these are merely examples used to clarify the technical content of the present invention, and the present invention should not be construed as being limited to these examples, and the scope of the present invention is limited only by the appended claims.

[0135] This application corresponds to Patent Application No. 2020-160064 filed with the Japan Patent Office on September 24, 2020, the entire disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0136] 1: Schottky barrier diode, 1P: Schottky barrier diode, 1Q: Schottky barrier diode, 2: semiconductor substrate, 3: first main surface, 7: epitaxial layer, 7a: surface, 8: active region, 9: inactive region, 10: high concentration layer, 11: low concentration layer, 16: Schottky metal, 30: guard region, 30a: bottom, 40: first impurity region, 40a: bottom, 46: unit impurity region, 50: second impurity region, 54: point-like impurity region, 55: inner impurity region, 56: outer impurity region, 60: lattice defect region, L: distance, PJ: pn junction, SJ: Schottky junction, TE: thickness

Claims

1. a semiconductor substrate having a main surface; a semiconductor layer formed on the main surface of the semiconductor substrate, the semiconductor layer including: a first conductivity type low concentration layer in contact with the main surface of the semiconductor substrate; and a first conductivity type high concentration layer formed in a surface layer portion on a surface opposite to the main surface of the semiconductor layer, the high concentration layer having an impurity concentration higher than that of the low concentration layer; a Schottky electrode formed on the surface of the semiconductor layer and forming a Schottky junction with the heavily doped layer; an impurity region of a second conductivity type formed in the surface layer portion of the semiconductor layer so as to be in contact with the Schottky electrode and forming a pn junction between the semiconductor layer and the impurity region; a lattice defect region formed in the surface layer portion of the semiconductor layer so as to be in contact with the Schottky electrode, the lattice defect region having more lattice defects than the semiconductor layer; the impurity region includes an inner impurity region that is disposed inside the lattice defect region so as to be in contact with the lattice defect region, The high concentration layer includes a plurality of linear regions arranged in a stripe pattern.

2. The impurity concentration of the low concentration layer is 1.0×10 １２ cm －３ Above 1.0 x 10 １７ cm －３ is less than The impurity concentration of the high concentration layer is 1.0×10 １７ cm －３ Above 1.0 x 10 ２０ cm －３ 2. The semiconductor device according to claim 1, wherein:

3. a second conductivity type annular guard region formed in the surface layer portion of the semiconductor layer, 3. The semiconductor device according to claim 1, wherein said heavily doped layer is formed in an active region surrounded by said guard region.

4. 4. The semiconductor device according to claim 3, wherein a bottom of said heavily doped layer is located closer to said surface of said semiconductor layer than a bottom of said guard region.

5. 5. The semiconductor device according to claim 3, wherein said high concentration layer is formed over the entire active region.

6. 6. The semiconductor device according to claim 3, wherein the high concentration layer faces the guard region via the low concentration layer.

7. 7. The semiconductor device according to claim 3, wherein the high concentration layer is set on the surface of the semiconductor layer and is formed in a non-active region surrounding the active region.

8. 8. The semiconductor device according to claim 1, wherein the resistance of the lattice defect region is higher than the resistance of the semiconductor layer.

9. 9. The semiconductor device according to claim 1, wherein the distance between said Schottky junction and said inner impurity region is greater than the thickness of said semiconductor layer.

10. 10. The semiconductor device according to claim 1, wherein the impurity region includes an outer impurity region arranged on the opposite side of the lattice defect region from the inner impurity region so as to be in contact with the lattice defect region.

Images