Semiconductor wafer and method for manufacturing semiconductor wafer

Abstract

To provide a semiconductor wafer capable of accurately detecting the position of a notch part.SOLUTION: The semiconductor wafer is a semiconductor wafer on which semiconductor chips are formed, and includes: a notch part provided at an edge portion of the semiconductor wafer; and a light-shielding part having a light transmittance different from that of the semiconductor wafer, the light-shielding part being provided on a surface of the semiconductor wafer that is parallel to a surface on which the semiconductor chips are formed and also at the outer periphery of the notch part or at the edge part so as to sandwich the notch part. Accordingly, the position of the notch part can be accurately detected.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor wafers and methods for manufacturing semiconductor wafers. [Background technology]

[0002] In the prior art, a semiconductor wafer is disclosed in which dot marks are formed on the flat surface of the chamfered portion of the V-notch (for example, Patent Document 1).

[0003] In the prior art, the position of a notch formed on a semiconductor wafer is detected by irradiating a laser beam output from a licensor onto a chamfer formed on the edge of the semiconductor wafer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-93692 Summary of the Invention [Problem to be solved by the invention]

[0005] However, when the chamfer width is reduced by grinding the edge of the semiconductor wafer or when the semiconductor wafer is warped, the area of ​​the chamfer in the direction perpendicular to the light irradiated from the line sensor projector that detects the notch provided on the semiconductor wafer becomes smaller, which poses a problem that the position of the notch cannot be detected accurately.

[0006] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a semiconductor wafer in which the position of a notch can be accurately detected. [Means for solving the problem]

[0007] The semiconductor wafer according to the present disclosure is a semiconductor wafer on which semiconductor chips are formed, and includes a notch portion provided at an edge portion of the semiconductor wafer, and a light-shielding portion having a light transmittance different from that of the semiconductor wafer, the light-shielding portion being provided on the outer periphery of the notch portion or on the edge portion so as to sandwich the notch portion, on a surface included in the semiconductor wafer that is parallel to the surface on which the semiconductor chips are formed.

[0008] Furthermore, the method for manufacturing a semiconductor wafer according to the present disclosure is a method for manufacturing a semiconductor wafer on which semiconductor chips are formed, and includes a step of forming a light-shielding portion having a different light transmittance from that of the semiconductor wafer on the outer periphery of a notch portion provided on an edge portion of the semiconductor wafer, or on the edge portion so as to sandwich the notch portion, on a surface included in the semiconductor wafer that is parallel to the surface on which the semiconductor chips are formed. [Effects of the Invention]

[0009] According to the semiconductor wafer of the present disclosure, the position of the notch can be accurately detected. Furthermore, according to the semiconductor wafer manufacturing method of the present disclosure, a semiconductor wafer in which the position of the notch can be accurately detected can be obtained. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a top view of a semiconductor wafer according to a first embodiment of the present disclosure. [Figure 2] 1 is an enlarged view of the periphery of a notch portion of a semiconductor wafer according to a first embodiment of the present disclosure. [Figure 3] 1 is a top view of a semiconductor wafer according to a first embodiment of the present disclosure. [Figure 4] 1 is an enlarged view of the periphery of a notch portion of a semiconductor wafer according to a first embodiment of the present disclosure. [Figure 5] 1 is a top view of a semiconductor wafer according to a first embodiment of the present disclosure. [Figure 6] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor wafer according to a first embodiment of the present disclosure. [Figure 7] 5A to 5C are diagrams illustrating a method for detecting a notch portion of a semiconductor wafer according to the first embodiment of the present disclosure. [Figure 8] 3A to 3C are diagrams schematically illustrating detection results in the line sensor receiver according to the first embodiment of the present disclosure. [Figure 9] FIG. 10 is a top view of a semiconductor wafer according to a second embodiment of the present disclosure. [Figure 10] FIG. 10 is an enlarged view of the periphery of a notch portion of a semiconductor wafer according to a second embodiment of the present disclosure. [Figure 11] FIG. 10 is a cross-sectional view of a semiconductor wafer according to a third embodiment of the present disclosure. [Figure 12] FIG. 10 is a cross-sectional view of a semiconductor wafer according to a third embodiment of the present disclosure. [Figure 13] FIG. 10 is a cross-sectional view of a semiconductor wafer according to a third embodiment of the present disclosure. [Figure 14] FIG. 10 is a cross-sectional view of a semiconductor wafer according to a third embodiment of the present disclosure. [Figure 15] FIG. 10 is a top view of a semiconductor wafer according to a fourth embodiment of the present disclosure. [Figure 16] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor wafer according to a fourth embodiment of the present disclosure. [Figure 17] FIG. 10 is a top view of a semiconductor wafer according to a fourth embodiment of the present disclosure. [Figure 18] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor wafer according to a fourth embodiment of the present disclosure. [Figure 19] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor wafer according to a fifth embodiment of the present disclosure. [Figure 20] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor wafer according to a fifth embodiment of the present disclosure. [Figure 21] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor wafer according to a fifth embodiment of the present disclosure. [Figure 22] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor wafer according to a fifth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. Note that the drawings are schematic, and the relative sizes and positions shown in different drawings are not necessarily limited to those described and may be changed as appropriate. In the following description, similar components are denoted by the same reference numerals, and their names and functions are assumed to be the same or similar. Therefore, detailed descriptions thereof may be omitted.

[0012] Embodiment 1 A semiconductor wafer 101 according to the first embodiment will be described with reference to Fig. 1 to Fig. 8. Fig. 1 is a top view of the semiconductor wafer 101 according to the first embodiment. As shown in Fig. 1, the semiconductor wafer 101 according to the present embodiment includes an edge portion 1, a notch portion 2, and a light-shielding portion 3.

[0013] Semiconductor chips are formed on the top surface of the semiconductor wafer 101. Taking the semiconductor wafer 101 as a reference, the side on which the semiconductor chips are provided is referred to as the top surface. FIG. 1 shows the top surface of the semiconductor wafer 101. A surface different from the top surface, i.e., the surface opposite the top surface, is referred to as the bottom surface. The direction penetrating the top and bottom surfaces is referred to as the thickness direction. Surfaces other than the top and bottom surfaces are referred to as side surfaces. The same applies to the following explanations.

[0014] The semiconductor wafer 101 is made of, for example, silicon carbide (SiC). The semiconductor wafer 101 is, for example, transparent or translucent. That is, the semiconductor wafer 101 transmits, for example, light.

[0015] The edge portion 1 is the outer periphery of the semiconductor wafer 101. A chamfer is provided on the edge portion 1. The chamfer is provided as a surface that is angled with respect to the upper surface of the semiconductor wafer 101. The chamfer is provided on the edge portion 1, for example, over the entire periphery of the semiconductor wafer 101.

[0016] The notch portion 2 is a cutout provided in the edge portion 1 of the semiconductor wafer 101. The notch portion 2 is used, for example, as a reference for positioning the semiconductor wafer 101. By detecting the notch portion 2, the semiconductor wafer 101 can be placed in a desired position and a semiconductor chip can be formed on the upper surface of the semiconductor wafer 101. The notch portion 2 is also used as a mark for aligning the positions of multiple semiconductor wafers 101.

[0017] As shown in FIG. 1, the notch portion 2 has a shape that is, for example, a combination of arcs. The notch portion 2 may also have a shape that is, for example, a combination of curved lines. The notch portion 2 may also have a shape that is, for example, a combination of straight lines, such as a V-shape. The notch portion 2 may also have a shape that is, for example, a combination of straight lines and curved lines. As shown in FIG. 1, the notch portion 2 has a shape that is symmetrical with respect to the center line L that passes through the center of the semiconductor wafer 101. Note that the notch portion 2 does not have to have a shape that is symmetrical with respect to the center line L.

[0018] 2 is an enlarged view of the periphery of notch portion 2 of semiconductor wafer 101 according to embodiment 1. Light-shielding portion 3 is a portion having a different light transmittance from semiconductor wafer 101. If semiconductor wafer 101 is transparent, light-shielding portion 3 is provided, for example, as a portion having a lower light transmittance than other portions of semiconductor wafer 101. By providing light-shielding portion 3, a detection device that detects notch portion 2 can determine that an area with a large amount of light transmittance sandwiched between areas with a small amount of light transmittance is notch portion 2, and can detect the position of notch portion 2.

[0019] The light shielding portion 3 is provided near the notch portion 2. The light shielding portion 3 is also provided at a position close to the notch portion 2. The light shielding portion 3 is provided on a surface included in the semiconductor wafer 101 that is parallel to the surface on which the semiconductor chip is formed. In other words, the light shielding portion 3 is provided on a surface parallel to the top surface of the semiconductor wafer 101.

[0020] By providing the light-shielding portion 3 on a surface parallel to the surface on which the semiconductor chips are formed, even if the width of the chamfered portion in the direction perpendicular to the light emitted from the projector that detects the notch portion 2 narrows in cases such as when the semiconductor wafer 101 is warped, deformed, or when the edge portion 1 of the semiconductor wafer 101 is scraped, light can be sufficiently blocked, thereby enabling accurate detection of the position of the notch portion 2. In other words, by providing the light-shielding portion 3 on a surface parallel to the surface on which the semiconductor chips are formed, the position of the notch portion 2 can be accurately detected without being affected by warpage and deformation of the semiconductor wafer 101.

[0021] The light-shielding portion 3 is provided on the outer periphery of the notch portion 2. The light-shielding portion 3 is provided so as to surround the notch portion 2. Note that the light-shielding portion 3 does not need to completely cover the outer periphery of the notch portion 2, and the light-shielding portion 3 may surround the notch portion 2 so as to be partially interrupted, for example, as shown in FIG.

[0022] The light shielding portion 3 is provided, for example, on the upper surface of the semiconductor wafer 101. The light shielding portion 3 is provided on the surface of the semiconductor wafer 101 on which semiconductor chips are formed. The light shielding portion 3 is provided on a portion of the upper surface of the semiconductor wafer 101 on which semiconductor chips are not formed.

[0023] As shown in FIG. 2, the light-shielding portion 3 is, for example, a dot mark. The light-shielding portion 3 is formed of a plurality of dot marks. The plurality of dot marks are arranged on the outer periphery of the notch portion 2 so as to surround the notch portion 2. The plurality of dot marks are, for example, arranged symmetrically with respect to the center line L. The plurality of dot marks are, for example, arranged from the edge portion 1 of the semiconductor wafer 101 toward the center of the semiconductor wafer 101. Note that the plurality of dot marks do not need to be arranged symmetrically with respect to the center line L, as long as they are provided at positions where the position of the notch portion 2 can be detected.

[0024] The light-shielding portion 3 is preferably larger than the resolution of the line sensor receiver that receives light irradiated from the line sensor projector described below. The resolution of the line sensor receiver is, for example, about 30 mm. The dot marks are, for example, circles with a diameter of several μm to several tens of μm. The dot marks are, for example, up to about 100 μm. Multiple dot marks are arranged side by side so that the entire light-shielding portion 3 is larger than the resolution of the line sensor receiver. When the beam width of the laser light irradiated from the line sensor projector 14 is several tens of mm, the light-shielding portion 3 is arranged so that the edge portion 1 of the semiconductor wafer 101 and the light-shielding portion 3 are included in the beam width of several tens of mm.

[0025] The light-shielding portion 3 does not have to be formed in a circle. The light-shielding portion 3 may be, for example, a polygon such as a triangle or a rectangle, a continuous line, a shape surrounded by curves, or a shape combining curves and straight lines.

[0026] FIG. 3 is a top view of the semiconductor wafer 101 according to the first embodiment. FIG. 4 is an enlarged view of the periphery of the notch portion 2 of the semiconductor wafer 101 according to the first embodiment. The light-shielding portion 3 may be provided in the edge portion 1 as shown in FIGS. 3 and 4. The light-shielding portion 3 is provided in the edge portion 1 near the notch portion 2. The light-shielding portions 3 are, for example, arranged along the shape of the semiconductor wafer 101 and provided in the edge portion 1. The light-shielding portions 3 are also provided so as to sandwich the notch portion 2. The light-shielding portions 3 may be provided only on the half circumference of the edge portion 1 including the notch portion 2 as shown in FIG. 3.

[0027] Fig. 5 is a top view of the semiconductor wafer 101 according to the first embodiment. As shown in Fig. 5, the light-shielding portion 3 may be provided around the entire periphery of the edge portion 1 of the semiconductor wafer 101. Even in the case shown in Fig. 5, the light-shielding portion 3 is provided on the edge portion 1 so as to sandwich the notch portion 2 therebetween.

[0028] The semiconductor wafer 101 according to this embodiment comprises a notch portion 2 provided in an edge portion 1 of the semiconductor wafer 101, and a light-shielding portion 3 having a different light transmittance from that of the semiconductor wafer 101, which is provided on the outer periphery of the notch portion 2 or on the edge portion 1 so as to sandwich the notch portion 2 on a surface included in the semiconductor wafer 101 that is parallel to the surface on which the semiconductor chip is formed, thereby enabling the position of the notch portion to be accurately detected.

[0029] The light-shielding portion 3 may be provided on the underside of the semiconductor wafer 101, which is the surface opposite to the surface on which the semiconductor chips are provided.

[0030] Next, a description will be given of a method for manufacturing the semiconductor wafer 101. The method for manufacturing the semiconductor wafer 101 includes a step of forming a light-shielding portion 3 having a different light transmittance from that of the semiconductor wafer 101 on a surface included in the semiconductor wafer 101 that is parallel to the surface on which the semiconductor chip is formed, around the periphery of a notch portion 2 provided in an edge portion 1 of the semiconductor wafer 101, or on the edge portion 1 so as to sandwich the notch portion 2.

[0031] 6 is a diagram showing a manufacturing method of a semiconductor wafer 101. Using FIG. 6, a case where a light-shielding portion 3 is provided by a laser marking device 11 will be described in particular. The laser marking device 11 can provide the light-shielding portion 3 on the upper or lower surface of the semiconductor wafer 101. The light-shielding portion 3 provided on the semiconductor wafer 101 is, for example, a dot mark.

[0032] For example, a galvano scanning method can be used to provide the light-shielding portion 3. The laser light emitted from the laser oscillator is scanned by two orthogonal mirrors, passes through a condenser lens, and is condensed into high-energy light, which is then irradiated from the printing device 12 onto the semiconductor wafer 101, which is the target object.

[0033] By using the galvano scanning method, the laser marking device 11 can apply marks having a size of several μm to several tens of μm at any position on the semiconductor wafer 101. The laser light irradiated onto the semiconductor wafer 101 discolors or scrapes the upper surface of the semiconductor wafer 101, thereby forming a light-shielding portion 3. The light-shielding portion 3 may be provided on either the upper surface or the lower surface of the semiconductor wafer 101.

[0034] 7 is a diagram showing a method for detecting the notch portion 2 of the semiconductor wafer 101. The notch detection unit 13 detects the position of the notch portion 2 of the semiconductor wafer 101. The notch detection unit 13 includes a line sensor projector 14 and a line sensor receiver 15.

[0035] The line sensor projector 14 and the line sensor receiver 15 are disposed with the semiconductor wafer 101 sandwiched between them. The line sensor projector 14 is disposed, for example, so as to face the upper surface of the semiconductor wafer 101. The line sensor receiver 15 is disposed, for example, so as to face the lower surface of the semiconductor wafer 101.

[0036] The line sensor projector 14 emits a laser beam. In FIG. 7, the laser beam is indicated schematically by an arrow A. The line sensor projector 14 irradiates the semiconductor wafer 101 with the laser beam at a constant width. The line sensor projector 14 irradiates the notch portion 2 and the light-shielding portion 3. The width of the laser beam, i.e., the size of the laser beam in the radial direction of the semiconductor wafer 101, is, for example, several tens of mm. The line sensor projector 14 irradiates the semiconductor wafer 101 with the laser beam near the edge portion 1.

[0037] The line sensor receiver 15 detects the laser light emitted from the line sensor projector 14. The notch detection unit 13 detects the position of the notch portion 2 of the semiconductor wafer 101 from the result of the line sensor receiver 15 detecting the laser light emitted from the line sensor projector 14.

[0038] The semiconductor wafer 101 rotates in the circumferential direction of the semiconductor wafer 101, with the center of the semiconductor wafer 101 as the center of rotation. The semiconductor wafer 101 rotates, for example, in the direction of arrow B shown in FIG. 7. The line sensor projector 14 irradiates the rotating semiconductor wafer 101 with laser light. That is, the notch detection unit 13 irradiates the semiconductor wafer 101 with laser light while rotating the semiconductor wafer 101.

[0039] Fig. 8 is a diagram showing a schematic representation of the detection results of the line sensor receiver 15. The circles shown in Fig. 8 schematically show the detection areas for each resolution of the line sensor receiver 15. C to E shown in Fig. 8 show the areas where the laser light is detected by the line sensor receiver 15. Areas C to E are areas larger than the resolution of the line sensor receiver 15.

[0040] The detection results at the line sensor receiver 15 differ depending on whether a notch portion 2 exists between the line sensor projector 14 and the line sensor receiver 15 or whether a light-shielding portion 3 exists between the line sensor projector 14 and the line sensor receiver 15.

[0041] The detection result of the line sensor receiver 15 when the light-shielding portion 3 is present between the line sensor projector 14 and the line sensor receiver 15 will be described. Area D is an area facing the position where the light-shielding portion 3 is provided. When the light-shielding portion 3 is located between the line sensor projector 14 and the line sensor receiver 15, the laser light is blocked by the light-shielding portion 3, and the laser light does not reach area D, or the amount of laser light that reaches area D is smaller than the amount of laser light that reaches areas C and E.

[0042] Area C is an area facing a position of semiconductor wafer 101 where light-shielding portion 3 is not provided. When semiconductor wafer 101 is transparent, the laser light irradiated from line sensor projector 14 passes through semiconductor wafer 101 without being blocked by semiconductor wafer 101 and reaches line sensor receiver 15. When semiconductor wafer 101 is translucent, the laser light emitted from line sensor projector 14 passes through semiconductor wafer 101 and reaches line sensor receiver 15 without being blocked by semiconductor wafer 101 at all.

[0043] Area E is an area opposite to a position where the semiconductor wafer 101 is not provided. The laser light emitted from the line sensor projector 14 does not pass through the semiconductor wafer 101 and therefore reaches the line sensor receiver 15 without being blocked by the semiconductor wafer 101.

[0044] On the other hand, if a notch portion exists between the line sensor projector 14 and the line sensor receiver 15, the laser light emitted from the line sensor projector 14 does not pass through the semiconductor wafer 101, even in region D, and therefore reaches the line sensor receiver 15 without being blocked by the semiconductor wafer 101. The notch detection unit 13 identifies and detects the position of the notch portion 2 from the difference in the amount of light detected by the line sensor receiver 15 between each region.

[0045] As shown in Figure 5, when the light-shielding portion 3 is provided on the semiconductor wafer 101 around the entire circumference of the edge portion 1 except for the position where the notch portion 2 is provided, the position in region D shown in Figure 8 where the amount of light detected is greater than at other positions can be determined to be the position where the notch portion 2 is provided.

[0046] Furthermore, as shown in Figures 3 and 4, when the light-shielding portion 3 is provided in the edge portion 1 around the notch portion 2, it can be determined that the position in region D shown in Figure 8 where the intervals between the detected light amounts are narrower and larger than the positions detected immediately before and after is the position where the notch portion 2 is provided.

[0047] Furthermore, when the light-shielding portion 3 surrounds the outer periphery of the notch portion 2 as shown in Figures 1 and 2, in region D shown in Figure 8, the position where the interval between the detected light amounts is narrower than the positions detected immediately before and after can be determined to be the position where the notch portion 2 is provided.

[0048] By arranging the light-shielding portion 3 symmetrically with respect to the center line L, it becomes easier for the notch detection unit 13 to detect the position of the notch portion 2.

[0049] The semiconductor wafer 101 according to this embodiment includes a notch portion 2 provided in an edge portion 1 of the semiconductor wafer 101, and light-shielding portions 3 having a different light transmittance from that of the semiconductor wafer 101, which are provided on the outer periphery of the notch portion 2 or on the edge portion 1 so as to sandwich the notch portion 2, on a surface included in the semiconductor wafer 101 that is parallel to the surface on which the semiconductor chip is formed. Therefore, the position of the notch portion 2 can be accurately detected.

[0050] Furthermore, the method for manufacturing semiconductor wafer 101 according to this embodiment includes a step of forming a light-shielding portion 3 having a different light transmittance from that of semiconductor wafer 101 on a surface included in semiconductor wafer 101 that is parallel to the surface on which the semiconductor chip is formed, around the periphery of a notch portion 2 provided in edge portion 1 of semiconductor wafer 101, or on edge portion 1 so as to sandwich notch portion 2. Therefore, the position of notch portion 2 can be accurately detected.

[0051] Embodiment 2 A semiconductor wafer 102 according to the second embodiment will be described with reference to Figures 9 and 10. Descriptions of configurations similar to those of the first embodiment will be omitted. In Figures 9 and 10, the same reference numerals as those in Figures 1 to 8 indicate the same or corresponding parts. The semiconductor wafer 102 according to the second embodiment differs from the semiconductor wafer 101 according to the first embodiment in that the light-shielding portions 4 are grinding marks. The following description will focus on the differences from the first embodiment.

[0052] 9 is a top view of a semiconductor wafer 102 according to the second embodiment. FIG. 10 is an enlarged view of the periphery of the notch portion 2 of the semiconductor wafer 102 according to the second embodiment. The semiconductor wafer 102 includes a light-shielding portion 4. The light-shielding portion 4 is a grinding mark having unevenness. The surface condition of the light-shielding portion 4 is rough. Because the light-shielding portion 4 has unevenness, the light transmittance is lower than that of other portions of the semiconductor wafer 102.

[0053] The light shielding portion 4 is provided on a surface of the semiconductor wafer 102 that is parallel to the surface on which the semiconductor chips are formed. That is, the light shielding portion 4 is provided on a surface that is parallel to the top surface of the semiconductor wafer 102. The light shielding portion 4 is provided on, for example, the top surface of the semiconductor wafer 102. The light shielding portion 4 is provided on the surface of the semiconductor wafer 102 on which the semiconductor chips are formed. The light shielding portion 4 is provided on a portion of the top surface of the semiconductor wafer 102 on which the semiconductor chips are not formed. The light shielding portion 4 may also be provided on the bottom surface of the semiconductor wafer 102, which is the surface opposite to the surface on which the semiconductor chips are formed.

[0054] As shown in FIG. 9, the light-shielding portion 4 is provided around the entire circumference of the edge portion 1. As shown in FIG. 10, the light-shielding portion 4 is provided at least near the notch portion 2, and is provided on the edge portion 1 so as to sandwich the notch portion 2. The light-shielding portion 4 does not have to be provided on the edge portion 1 that corresponds to the outer periphery of the notch portion 2. Alternatively, the light-shielding portion 4 may be provided only on half the circumference of the edge portion 1 that includes the notch portion 2. Also, the light-shielding portion 4 does not have to be formed continuously, and may be partially interrupted.

[0055] Next, a method for manufacturing a semiconductor wafer 102 according to the second embodiment will be described. In particular, a processing method for providing grinding marks, which are light-shielding portions 4, on the semiconductor wafer 102 will be described. A grinding process is performed by applying a grindstone to the edge portion 1 of the semiconductor wafer 102 where the light-shielding portion 4 is to be provided, thereby grinding the semiconductor wafer 102. By performing the grinding process, unevenness is formed on the top surface of the semiconductor wafer 102 in the ground area. Due to the formation of unevenness, the ground area has a rougher surface condition than the unground area. Because the surface condition becomes rough, it becomes difficult for laser light to pass through.

[0056] Instead of providing grinding marks, a material having a lower optical transparency than the semiconductor wafer 102 may be applied to the semiconductor wafer 102 .

[0057] Embodiment 3 A semiconductor wafer 103 according to the third embodiment will be described with reference to FIGS. 11 to 14. Descriptions of configurations similar to those of the first embodiment will be omitted. In addition, in FIGS. 11 to 14, the same reference numerals as those in FIGS. 1 to 10 indicate the same or corresponding parts. The semiconductor wafer 103 according to the present embodiment differs from the semiconductor wafer 101 according to the first embodiment in that the light-shielding portion 5 is a light-shielding film. The following description will focus on the differences from the first embodiment.

[0058] FIG. 11 is a cross-sectional view of a semiconductor wafer 103 according to the third embodiment. FIG. 11 shows a cross section passing through the center of the semiconductor wafer 103. The semiconductor wafer 103 includes a light-shielding portion 5. The light-shielding portion 5 is a light-shielding film having an inclined portion 16. Because the light-shielding portion 5 has an inclined portion 16, the light transmittance is lower than that of other portions of the semiconductor wafer 103. The inclined portion 16 reflects laser light. Therefore, the amount of light reaching the line sensor receiver 15 is smaller in the portion where the light-shielding portion 5 is provided than in the portion where the light-shielding portion 5 is not provided. Therefore, the notch portion 2 can be detected.

[0059] The light shielding portion 5 is provided on a surface of the semiconductor wafer 103 that is parallel to the surface on which the semiconductor chips are formed. That is, the light shielding portion 5 is provided on a surface that is parallel to the top surface of the semiconductor wafer 103. The light shielding portion 5 is provided, for example, on the top surface of the semiconductor wafer 103. The light shielding portion 5 is provided on the surface of the semiconductor wafer 103 on which the semiconductor chips are formed. The light shielding portion 5 is provided on a portion of the top surface of the semiconductor wafer 103 on which the semiconductor chips are not formed. The light shielding portion 5 may also be provided on the bottom surface of the semiconductor wafer 103, which is the surface opposite to the surface on which the semiconductor chips are formed.

[0060] The light-shielding portion 5 is provided around the entire circumference of the edge portion 1, as in the second embodiment. The light-shielding portion 5 is provided at least near the notch portion 2, and is provided on the edge portion 1 so as to sandwich the notch portion 2. The light-shielding portion 5 does not have to be provided on the edge portion 1 that corresponds to the outer periphery of the notch portion 2. The light-shielding portion 5 may be provided only on half the circumference of the edge portion 1 that includes the notch portion 2. The light-shielding portion 5 does not have to be formed continuously, and may be partially interrupted.

[0061] 11, the light-shielding portion 5 has a triangular cross-sectional shape. The light-shielding portion 5 is provided, for example, so that the longest side in the cross-section faces radially outward from the semiconductor wafer 103. The light-shielding portion 5 is provided so that the sides other than the longest side in the cross-section contact the top surface of the semiconductor wafer 103. The inclined portion 16 is provided at an angle to the top surface of the semiconductor wafer 103.

[0062] Fig. 12 is a cross-sectional view of a semiconductor wafer 103 according to embodiment 3. Fig. 12 shows a cross section passing through the center of the semiconductor wafer 103. The light-shielding film serving as the light-shielding portion 5 has a triangular cross-sectional shape, and may be provided so that the longest side in the cross section faces radially inward of the semiconductor wafer 103, as shown in Fig. 12.

[0063] FIG. 13 is a cross-sectional view of a semiconductor wafer 103 according to the third embodiment. FIG. 13 shows a cross section passing through the center of the semiconductor wafer 103. As shown in FIG. 13, the light-shielding film, which is the light-shielding portion 5, may have a trapezoidal cross-sectional shape. The inclined portion 16 is provided at an angle to the upper surface of the semiconductor wafer 103. A plurality of inclined portions 16 are provided. One of the plurality of inclined portions 16 faces radially outward from the semiconductor wafer 103. Furthermore, one of the plurality of inclined portions 16 faces radially inward from the semiconductor wafer 103.

[0064] FIG. 14 is a cross-sectional view of a semiconductor wafer 103 according to the third embodiment. FIG. 14 shows a cross section passing through the center of the semiconductor wafer 103. As shown in FIG. 14, the light-shielding film, which is the light-shielding portion 5, may have a semicircular cross-sectional shape. The inclined portion 16 is provided at an angle to the upper surface of the semiconductor wafer 103. That is, the inclined portion 16 is not parallel to the upper surface of the semiconductor wafer 103. The cross-section of the inclined portion 16 is not limited to a linear shape, and may include a curved shape as shown in FIG. 14. The inclined portion 16 may be a flat surface or a curved surface. The inclined portion 16 is provided in a direction from the lower surface to the upper surface of the semiconductor wafer 103.

[0065] Embodiment 4 A semiconductor wafer 104 according to the fourth embodiment will be described with reference to Figs. 15 to 18. Descriptions of configurations similar to those of the first embodiment will be omitted. In Figs. 15 to 18, the same reference numerals as those in Figs. 1 to 14 indicate the same or corresponding parts. The semiconductor wafer 104 according to the present embodiment differs from the semiconductor wafer 101 according to the first embodiment in that the light-shielding portion 6 is an adhesive member. The following description will focus on the differences from the first embodiment.

[0066] FIG. 15 is a top view of a semiconductor wafer 104 according to the fourth embodiment. The semiconductor wafer 104 is formed by bonding two semiconductor wafers together. The semiconductor wafer 104 includes a light-shielding portion 6. The light-shielding portion 6 is an adhesive member having a lower light transmittance than a portion of the semiconductor wafer 104 where the light-shielding portion 6 is not provided. Therefore, the amount of light reaching the line sensor receiver 15 is smaller in the portion where the light-shielding portion 6 is provided than in the portion where the light-shielding portion 6 is not provided. Therefore, the notch portion 2 can be detected.

[0067] The semiconductor wafer 104 is formed by providing an adhesive member between two semiconductor wafers and bonding the two semiconductor wafers together. The adhesive member provided between the two semiconductor wafers is sandwiched between the two semiconductor wafers when the two semiconductor wafers are bonded together, and spreads over the entire space between the two semiconductor wafers. In other words, the adhesive member extends to the outer periphery of the notch portion 2. The adhesive member is provided at least on the outer periphery of the notch portion 2 of the semiconductor wafer 104. The adhesive member is also provided at least on the edge portion 1 so as to sandwich the notch portion 2. The semiconductor wafer 104 is provided with two semiconductor wafers. The adhesive member, which is the light-shielding portion 6, is provided between the two bonded semiconductor wafers.

[0068] Next, a method for manufacturing a semiconductor wafer 104 according to this embodiment will be described. FIG. 16 is a diagram showing a method for manufacturing a semiconductor wafer 104 according to a fourth embodiment. An adhesive member having a different light transmittance from that of the semiconductor wafers is placed between two semiconductor wafers, and the two semiconductor wafers are bonded together with the adhesive member. For example, the adhesive member is placed near the center of the semiconductor wafers before the two semiconductor wafers are bonded together. In the process of bonding the two semiconductor wafers together with the adhesive member, the entire surfaces of the two semiconductor wafers are bonded together with the adhesive member. In the process of bonding the two semiconductor wafers together with the adhesive member, the adhesive member spreads over the entire surfaces of the semiconductor wafers.

[0069] Fig. 17 is a top view of a semiconductor wafer 104 according to the fourth embodiment. Fig. 17 shows the semiconductor wafer 104 after being bonded. As shown in Fig. 17, an adhesive material may be applied to the edge portion 1, and two semiconductor wafers may be bonded together. The adhesive material is provided on the edge portion 1 so as to sandwich the notch portion 2.

[0070] Fig. 18 is a diagram showing a method for manufacturing a semiconductor wafer 104 according to embodiment 4. As shown in Fig. 18, an adhesive member may be provided between edge portions 1 of two semiconductor wafers to bond the two semiconductor wafers together.

[0071] The semiconductor wafer 104 according to this embodiment includes a process of placing an adhesive member having a different light transmittance than the semiconductor wafers between two semiconductor wafers and bonding the two semiconductor wafers together with the adhesive member, thereby obtaining a semiconductor wafer 104 that can accurately detect the position of the notch portion 2.

[0072] The two semiconductor wafers to be bonded together can be semiconductor wafer 101, semiconductor wafer 102, or semiconductor wafer 103 described in embodiments 1 to 3. The method for detecting notch portion 2 described in embodiment 1 can be used to bond the two semiconductor wafers together. A method for manufacturing semiconductor wafer 104 can include a step of detecting notch portion 2 of the semiconductor wafer, and a step of arranging the two semiconductor wafers so that the detected notch portions 2 overlap.

[0073] Embodiment 5 A semiconductor wafer 105 according to the fifth embodiment will be described with reference to FIGS. 19 to 22. Descriptions of configurations similar to those of the first embodiment will be omitted. In addition, in FIGS. 19 to 22, the same reference numerals as those in FIGS. 1 to 18 indicate the same or corresponding parts. The semiconductor wafer 105 according to the present embodiment is manufactured using a different method from the semiconductor wafer 101 according to the first embodiment. The following description will focus on the differences from the first embodiment.

[0074] 19 to 22 are diagrams showing a method for manufacturing a semiconductor wafer 105 according to embodiment 5. FIGS. 19 to 22 are diagrams showing a cross section passing through the center of the semiconductor wafer. A method for manufacturing a semiconductor wafer 105 according to this embodiment will be described. First, as shown in FIG. 19, a light-shielding portion 7 is provided on the upper and lower surfaces of a semiconductor wafer 111. The light-shielding portion 7 can be the light-shielding portion 3, the light-shielding portion 4, or the light-shielding portion 5 described in embodiments 1 to 3.

[0075] Next, semiconductor chips are formed on the upper surface of the semiconductor wafer 111. Next, as shown in FIG. 20, the semiconductor wafer 111, which has light-shielding portions 7 on its upper and lower surfaces, is divided into two pieces. The semiconductor wafer 111 is divided in a direction parallel to the upper surface of the semiconductor wafer 111. The semiconductor wafer 111 is divided into an upper wafer 112 and a divided wafer 113. A semiconductor chip is formed on the upper wafer 112. No semiconductor chip is formed on the divided wafer 113. Note that light-shielding portions are also formed on the upper and lower surfaces of other semiconductor wafers, and the wafer is divided into two pieces to produce another divided wafer 114 on which no semiconductor chips are formed.

[0076] Next, the position of the notch portion of divided wafer 113 is detected. The detection method described in embodiment 1 can be used to detect the notch portion. Also, the notch portion of another divided wafer 114 created by dividing another semiconductor wafer is detected. The detection method described in embodiment 1 can also be used to detect the other notch portion of the other divided wafer 114.

[0077] Next, as shown in Fig. 21, divided wafer 113 and another divided wafer 114 are arranged so that the notch portion of the detected divided wafer 113 overlaps with another notch portion of the detected other divided wafer. Next, as shown in Fig. 22, divided wafer 113 and another divided wafer 114 are bonded together to form semiconductor wafer 105, which is a reclaimed wafer.

[0078] The method for manufacturing semiconductor wafer 105 according to this embodiment includes the steps of forming light-shielding portions 7 on the upper and lower surfaces of semiconductor wafer 111, dividing semiconductor wafer 111 into two in a direction parallel to the upper surface of semiconductor wafer 111 to create divided wafers 113, detecting notch portion 2 in divided wafer 113, detecting another notch portion in another divided wafer 114 divided from another semiconductor wafer, arranging divided wafer 113 and another divided wafer 114 so that detected notch portion 2 overlaps with the detected other notch portion, and bonding divided wafer 113 and another divided wafer 114. Therefore, when creating a reclaimed wafer, the position of the notch can be accurately detected, and the position of divided wafer 113 and another divided wafer 114 can be accurately aligned.

[0079] The above describes in detail preferred embodiments, but the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0080] Furthermore, in the above-described embodiments, the materials, materials, dimensions, shapes, relative positional relationships, and implementation conditions of each component may be described, but these are merely examples in all respects and are not intended to limit the scope of each embodiment. Therefore, countless variations not exemplified are contemplated within the scope of each embodiment. For example, these include cases where any component is modified, added, or omitted, and even cases where at least one component in at least one embodiment is extracted and combined with a component in another embodiment.

[0081] Various aspects of the present disclosure are summarized below as appendices.

[0082] (Appendix 1) In a semiconductor wafer on which semiconductor chips are formed, a notch portion provided at an edge portion of the semiconductor wafer; a light-shielding portion provided on a surface of the semiconductor wafer that is parallel to the surface on which the semiconductor chip is formed, on the periphery of the notch portion or on the edge portion so as to sandwich the notch portion, and having a light transmittance different from that of the surface on which the semiconductor chip is formed; Semiconductor wafer. (Appendix 2) The light-shielding portion is provided around the entire periphery of the edge portion of the semiconductor wafer. 2. The semiconductor wafer of claim 1. (Appendix 3) The light-shielding portion is a dot mark formed on the upper surface of the semiconductor wafer. 3. The semiconductor wafer according to claim 1 or 2. (Appendix 4) The light-shielding portion is a grinding mark having unevenness. 2. The semiconductor wafer of claim 1. (Appendix 5) The light-shielding portion is a light-shielding film having an inclined portion. 2. The semiconductor wafer of claim 1. (Appendix 6) Two semiconductor wafers are provided, The light-shielding portion is provided between the two semiconductor wafers bonded together and is an adhesive member having a different light transmittance from that of the semiconductor wafers. 2. The semiconductor wafer of claim 1. (Appendix 7) The adhesive member is provided on an edge portion of the semiconductor wafer. 7. The semiconductor wafer of claim 6. (Appendix 8) The adhesive member is provided on the entire surface of the semiconductor wafer. 7. The semiconductor wafer of claim 6. (Appendix 9) A method for manufacturing a semiconductor wafer on which semiconductor chips are formed, comprising: forming a light-shielding portion having a light transmittance different from that of the semiconductor wafer on a surface of the semiconductor wafer that is parallel to the surface on which the semiconductor chip is formed, on the periphery of a notch provided in an edge portion of the semiconductor wafer, or on the edge portion so as to sandwich the notch, A method for manufacturing semiconductor wafers. (Appendix 10) A method for manufacturing a semiconductor wafer on which semiconductor chips are formed, comprising: a step of placing an adhesive member having a light transmittance different from that of the semiconductor wafers between the two semiconductor wafers and bonding the two semiconductor wafers together with the adhesive member, A method for manufacturing semiconductor wafers. (Appendix 11) In the step of bonding the two semiconductor wafers with the adhesive member, edge portions of the two semiconductor wafers are bonded with the adhesive member. 11. A method for manufacturing a semiconductor wafer according to claim 10. (Appendix 12) In the step of bonding the two semiconductor wafers with the adhesive member, the entire surfaces of the two semiconductor wafers are bonded with the adhesive member. 11. A method for manufacturing a semiconductor wafer according to claim 10. (Appendix 13) detecting the notch portion of the semiconductor wafer according to any one of Supplementary Notes 1 to 5; a step of arranging the two semiconductor wafers so that the detected notch portions overlap; a step of placing an adhesive member between two of the semiconductor wafers, the adhesive member having a light transmittance different from that of the semiconductor wafers; and bonding the two semiconductor wafers together with the adhesive member. A method for manufacturing semiconductor wafers. (Appendix 14) forming the light-shielding portion on the upper and lower surfaces of the semiconductor wafer; dividing the semiconductor wafer into two in a direction parallel to an upper surface of the semiconductor wafer to produce divided wafers; detecting the notch portion of the divided wafer; detecting another notch portion of another divided wafer separated from another semiconductor wafer; a step of arranging the divided wafer and the other divided wafer so that the detected notch portion and the other detected notch portion overlap each other; and bonding the divided wafer to the other divided wafer. 10. A method for manufacturing a semiconductor wafer according to claim 9. [Explanation of symbols]

[0083] 1 edge portion, 2 notch portion, 3, 4, 5, 6, 7 light-shielding portion, 16 inclined portion, 101, 102, 103, 104, 105, 111 semiconductor wafer, 113 divided wafer, 114 other divided wafer

Claims

1. In a semiconductor wafer on which semiconductor chips are formed, a notch portion provided at an edge portion of the semiconductor wafer; a light-shielding portion provided on a surface of the semiconductor wafer that is parallel to the surface on which the semiconductor chip is formed, on the periphery of the notch portion or on the edge portion so as to sandwich the notch portion, and having a light transmittance different from that of the surface on which the semiconductor chip is formed; Semiconductor wafer.

2. The light-shielding portion is provided around the entire periphery of the edge portion of the semiconductor wafer. The semiconductor wafer of claim 1 .

3. The light-shielding portion is a dot mark formed on the upper surface of the semiconductor wafer. The semiconductor wafer of claim 1 .

4. The light-shielding portion is a grinding mark having unevenness. The semiconductor wafer of claim 1 .

5. The light-shielding portion is a light-shielding film having an inclined portion. The semiconductor wafer of claim 1 .

6. Two semiconductor wafers are provided, the light-shielding portion is an adhesive member provided between the two semiconductor wafers bonded together and having a light transmittance different from that of the semiconductor wafers; The semiconductor wafer of claim 1 .

7. The adhesive member is provided on an edge portion of the semiconductor wafer. The semiconductor wafer according to claim 6.

8. The adhesive member is provided on the entire surface of the semiconductor wafer. The semiconductor wafer according to claim 6.

9. A method for manufacturing a semiconductor wafer on which semiconductor chips are formed, comprising: forming a light-shielding portion having a light transmittance different from that of the semiconductor wafer on a surface of the semiconductor wafer that is parallel to the surface on which the semiconductor chip is formed, on the periphery of a notch provided in an edge portion of the semiconductor wafer, or on the edge portion so as to sandwich the notch, A method for manufacturing semiconductor wafers.

10. A method for manufacturing a semiconductor wafer on which semiconductor chips are formed, comprising: a step of placing an adhesive member having a light transmittance different from that of the semiconductor wafers between the two semiconductor wafers and bonding the two semiconductor wafers together with the adhesive member, A method for manufacturing semiconductor wafers.

11. In the step of bonding the two semiconductor wafers with the adhesive member, edge portions of the two semiconductor wafers are bonded with the adhesive member. The method for manufacturing a semiconductor wafer according to claim 10.

12. In the step of bonding the two semiconductor wafers with the adhesive member, the entire surfaces of the two semiconductor wafers are bonded with the adhesive member. The method for manufacturing a semiconductor wafer according to claim 10.

13. a step of detecting the notch portion of the semiconductor wafer according to any one of claims 1 to 5; placing the two semiconductor wafers so that the detected notch portions overlap; a step of disposing an adhesive member between two of the semiconductor wafers, the adhesive member having a light transmittance different from that of the semiconductor wafers; and bonding the two semiconductor wafers together with the adhesive member. A method for manufacturing semiconductor wafers.

14. forming the light-shielding portion on the upper and lower surfaces of the semiconductor wafer; dividing the semiconductor wafer into two in a direction parallel to an upper surface of the semiconductor wafer to produce divided wafers; detecting the notch portion of the divided wafer; detecting another notch portion of another divided wafer separated from another semiconductor wafer; a step of arranging the divided wafer and the other divided wafer so that the detected notch portion and the other detected notch portion overlap each other; and bonding the divided wafer to the other divided wafer. The method for manufacturing a semiconductor wafer according to claim 9 .

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