Tin oxide and tin carbide materials for semiconductor patterning applications

Abstract

To provide a method and an apparatus for patterning a semiconductor material by using a tin-based material as a mandrel material, a hardmask material, and a liner material.SOLUTION: A method uses tin oxide and / or tin carbide material as a hard mask material, a mandrel material, and / or a liner material during a patterning application. The tin oxide or tin carbide material is easier to strip compared to other highly selective materials such as metal oxides (e.g., TiO2, ZrO2, HfO2, Al2O3) to avoid affecting critical dimensions and generating defects. Furthermore, tin oxide and tin carbide have a low refractive index (k-value) and are transparent below 663 nm for lithographic overlay.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The implementations described herein generally relate to film stacks and etching processes for etching the film stacks with high selectivity and good profile control for the patterning process. [Background technology]

[0002] The fabrication of very large-scale integrated (VLSI) and ultra-large-scale integrated (ULSI) semiconductor devices involves the reliable fabrication of sub-micron and sub-sub-micron features. However, as circuit technology continues to shrink, the size and pitch dimensions of circuit features, such as interconnects, have placed increasing demands on processing power. To further increase device and interconnect density, multi-level interconnects at the heart of this technology involve highly accurate imaging and placement of high aspect ratio features, such as vias and other interconnect structures. Furthermore, there is a demand for forming sub-micron-sized features and interconnects while reducing waste of intermediate materials, such as resist and hard mask materials.

[0003] As feature sizes have become smaller, the demand for higher aspect ratios, defined as the ratio of feature depth to feature width, has steadily increased to 10:1 and even beyond. Developing film stacks and etch processes capable of reliably forming features with such high aspect ratios poses considerable challenges. Inaccurate control or low resolution of lithographic exposure and development processes can lead to poor critical dimensions in the various layers utilized to transfer features into the film stack, resulting in unacceptable line width roughness (LWR). High line width roughness (LWR) and unwanted wiggling profiles can cause inaccurate feature transfer into the film stack, ultimately leading to device failure and yield loss.

[0004] Furthermore, during etching of such film stacks, redeposition or accumulation of by-products or other materials generated during the etching process can accumulate on the top and / or sidewalls of the features being etched, thus undesirably blocking the openings of the features being formed in the material layer. Different materials selected for the film stack can result in different amounts or profiles of redeposited by-products in the film stack. Furthermore, the openings of the etched features can be narrowed and / or sealed by the accumulated redeposition of material, preventing reactive etchants from reaching the underside of the features, thus limiting the aspect ratios that can be achieved. Furthermore, the accumulation of redeposited material or by-products can adhere randomly and / or irregularly to the top and / or sidewalls of the features being etched, and the resulting irregular profile and increased redeposited material can alter the flow path of the reactive etchants, resulting in curved or twisted profiles of the features being formed in the material layer. Inaccurate profiles or feature dimensions can cause device structure collapse, ultimately leading to device failure and low product yields. Furthermore, poor etch selectivity to the materials contained in the film stack can undesirably lead to inaccurate profiles and ultimately device failure.

[0005] Therefore, there is a need in the art for suitable film stacks and etching methods for etching features with targeted profiles and small dimensions in the film stacks. Summary of the Invention

[0006] The implementations described herein generally relate to film stacks and etching processes for etching the film stacks with high selectivity and good profile control for the patterning process.

[0007] In one aspect, a method of forming features on a substrate is provided. The method includes forming a mandrel layer on the substrate, the mandrel layer being a tin carbide layer or a tin oxide layer. The method further includes patterning the mandrel layer. The method further includes conformally forming a spacer layer on the patterned mandrel layer. The method further includes patterning the spacer layer.

[0008] Implementations may include one or more of the following: The patterned mandrel layer is selectively removed from the patterned spacer layer. Forming the mandrel layer on the substrate includes depositing the mandrel layer using a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. Patterning the mandrel layer includes supplying a first gas mixture including a halogen-containing gas and an oxygen gas and applying a first RF source power setting in the first gas mixture. The halogen-containing gas is selected from Cl2 gas, HBr gas, or a combination thereof. The first gas mixture further includes a passivation gas selected from N2, O2, COS, SO2, or a combination thereof. The spacer layer includes a material different from the material of the mandrel layer and selected from silicon oxide, silicon nitride, a metal oxide, or polysilicon. The mandrel has a hard mask layer formed thereon. The hard mask layer comprises a material selected from polysilicon, nanocrystalline silicon, amorphous silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, amorphous carbon, diamond-like carbon, titanium nitride, titanium oxide, titanium oxynitride, tantalum nitride, tantalum oxide, tantalum oxynitride, or any other suitable material, or combination thereof. The substrate comprises silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, or combinations thereof.

[0009] In another aspect, a method of forming features on a substrate is provided. The method includes forming a hard mask layer on a film stack formed over the substrate, the hard mask layer comprising tin oxide or tin carbide. The method further includes supplying a first etching gas mixture to the substrate and etching the hard mask layer to form a patterned hard mask layer.

[0010] Implementations may include one or more of the following: The method further includes supplying a second etch gas mixture to the substrate and etching the film stack exposed by the patterned hard mask layer. The film stack includes multiple dielectric layers. The film stack includes an oxide-nitride-oxide (ONO) layer. The film stack includes alternating layers of silicon and silicon germanium. The hard mask layer is selectively removed. The first etch gas mixture includes a halogen-containing gas. The halogen-containing gas is selected from Cl2 gas, HBr gas, or a combination thereof. The first etch gas mixture further includes a passivation gas selected from N2, O2, COS, SO2, or a combination thereof.

[0011] In yet another aspect, a method for forming features on a substrate is provided. The method includes forming a patterned hard mask layer on a film stack formed on the substrate, the patterned hard mask layer comprising carbon. The method further includes supplying a first etching gas mixture to the substrate. The method further includes etching the film stack exposed by the hard mask layer to form a patterned film stack. The method includes forming a liner layer over the patterned hard mask layer and the patterned film stack, the liner layer further comprising tin oxide or tin carbide.

[0012] Implementations may include one or more of the following: the liner layer is formed by an ALD process; the liner layer is exposed to wet chemistry or dry plasma to remove the liner layer; the patterned hard mask layer includes amorphous carbon, diamond-like carbon, or a combination thereof; the film stack includes multiple dielectric layers; the film stack includes an oxide-nitride-oxide (ONO) layer; the film stack includes alternating layers of silicon and silicon germanium.

[0013] In another aspect, a non-transitory computer-readable medium has stored thereon instructions that, when executed by a processor, cause the process to perform the operations of the above-described apparatus and / or method.

[0014] So that the above-mentioned features of the present disclosure may be understood in detail by reference to the implementations, a more detailed description of the implementations briefly summarized above may be had, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical implementations of the present disclosure, and therefore should not be considered as limiting the scope of the present disclosure, since the present disclosure may admit of other equally effective implementations. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 illustrates a cross-sectional view of one example of a plasma processing chamber that may be utilized to perform an etching process in accordance with one or more implementations of the present disclosure. [Figure 2] 1 shows a flowchart of a method for performing a high aspect ratio feature patterning process in accordance with one or more implementations of the present disclosure. [Figures 3A-3D] 1A-1C illustrate various stages of a high aspect ratio feature patterning process according to one or more implementations of the present disclosure. [Figure 4] FIG. 10 illustrates a flow diagram of another method for performing a high aspect ratio feature patterning process in accordance with one or more implementations of the present disclosure. [Figure 5A-5B] 1A-1C illustrate various stages of a high aspect ratio feature patterning process according to one or more implementations of the present disclosure. [Figure 5C-5D] 1A-1C illustrate various stages of a high aspect ratio feature patterning process according to one or more implementations of the present disclosure. [Figure 6] FIG. 10 illustrates a flow diagram of another method for performing a high aspect ratio feature patterning process in accordance with one or more implementations of the present disclosure. [Figures 7A-7B] 1A-1C illustrate various stages of a high aspect ratio feature patterning process according to one or more implementations of the present disclosure. [Figure 7C-7D] 1A-1C illustrate various stages of a high aspect ratio feature patterning process according to one or more implementations of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0016] For ease of understanding, where possible, like reference numerals have been used to indicate like elements that are common to the figures. It is contemplated that elements and features of one implementation may be beneficially incorporated in other implementations without further specification.

[0017] The following disclosure describes the formation of high aspect ratio features. To provide a thorough understanding of various implementations of the present disclosure, several details are set forth in the following description and in FIGS. 1-7D . To avoid unnecessarily obscuring the description of various implementations, the following disclosure does not provide other details that describe well-known structures and systems often associated with the formation of high aspect ratio features. Additionally, the apparatus descriptions described herein are exemplary and should not be construed or understood as limiting the scope of the implementations described herein.

[0018] Many of the details, operations, dimensions, angles, and other features shown in the figures are representative of particular implementations only. Thus, other implementations may have other details, components, dimensions, angles, and features without departing from the spirit or scope of the present disclosure. Moreover, further implementations of the present disclosure may be practiced without some of the details described below.

[0019] Implementations described herein generally relate to film stacks and etching processes for etching the film stacks with high selectivity and good profile control for patterning processes. One or more implementations of the present disclosure advantageously enable improved material selectivity in high aspect ratio features by using tin oxide (e.g., SnO, SnO2) or tin carbide (e.g., SnC) materials. One or more implementations of the present disclosure use tin oxide and / or tin carbide materials as hard mask materials, mandrel materials, and / or liner materials during various patterning applications. Some implementations of the present disclosure improve the poor selectivity of carbon, high-density carbon, and diamond-like carbon materials during capacitor etching of materials for memory applications, such as silicon oxide or silicon nitride, due to the high Young's modulus of tin oxide, tin carbide, and non-volatile etching by-products (e.g., SnF4). Tin oxide or tin carbide materials are easier to strip than other highly selective materials, such as metal oxides (e.g., TiO2, ZrO2, HfO2, and Al2O3), to avoid affecting critical dimensions and generating defects. Due to their potential for high selectivity over carbon, tin oxide and tin carbide materials can be used for deep etch hard masks in memory applications. Furthermore, tin oxide and tin carbide have low refractive indices (k-values) and are transparent below 663 nm for lithography overlay. Furthermore, carbon, tin, and SnOx (oxidized in air) can be easily removed by dry plasma etching or wet etchants, which helps achieve precise critical dimension control for multi-patterning. Tin and tin oxide can also be easily removed during chamber cleaning to reduce defects in the manufacturing process and increase chamber productivity.

[0020] While the particular apparatus in which the implementations described herein may be practiced is not limited, it is particularly useful to practice the implementations in a SYM3® etching system sold by Applied Materials, Inc. of Santa Clara, Calif. Additionally, other available etching systems may also benefit from the implementations described herein.

[0021] As used herein, "substrate" refers to a surface of a material, or a portion of a surface or material, on which a film processing is performed during a fabrication process. For example, substrate surfaces on which processing may be performed include, depending on the application, materials such as silicon, silicon oxide, silicon nitride, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, doped amorphous silicon, polysilicon, doped polysilicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. In addition to film processing directly on the surface of the substrate itself, in this disclosure, as disclosed in more detail below, any of the disclosed film processing steps may be performed on an underlayer formed on the substrate, and the term "substrate surface" includes such underlayers where the context indicates. Thus, for example, if a film / layer or partial film / layer is being deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0022] The substrate may be a silicon wafer, e.g., a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer, including a wafer having one or more layers of material, such as a dielectric material, a conductive material, or a semiconductive material, deposited thereon. The patterned substrate may have "features" such as vias, openings, or contact holes, which may be characterized by one or more of narrow and / or re-entrant openings, constrictions within the feature, and a high aspect ratio. The features may be formed in one or more of the layers described above. One example of a feature is a hole or via in a semiconductor substrate or a layer on the substrate. Another example is a trench in the substrate or layer. In some implementations, the feature may have an underlayer, such as a barrier layer or an adhesion layer. Non-limiting examples of underlayers include dielectric layers and conductive layers, e.g., silicon oxide, silicon nitride, silicon carbide, metal oxide, metal nitride, metal carbide, and metal layers.

[0023] In some implementations, the type of substrate produced from practicing the disclosed embodiments can depend on the aspect ratio of the features on the substrate prior to practicing the disclosed embodiments. The aspect ratio is the comparison of the depth of the feature to the critical dimension (e.g., width / diameter) of the feature. In some implementations, the features on the substrate can have an aspect ratio of at least about 2:1, at least about 3:1, at least about 4:1, at least about 6:1, at least about 10:1, at least about 20:1, or higher. The features can also have dimensions close to the opening, for example, an opening diameter or linewidth between about 5 nm and 500 nm, for example, between about 25 nm and about 300 nm.

[0024] One or more implementations of the present disclosure generally provide structures including high aspect ratio structures formed by patterning a dielectric material such that the high aspect ratio structures may be implemented in memory structures. By way of example, the high aspect ratio features formed in accordance with implementations of the present disclosure may be memory-type semiconductor devices, such as NAND-type memory devices.

[0025] 1 is a simplified cutaway view of an example plasma processing chamber 100 suitable for patterning a material layer and forming a material layer disposed on a substrate 102 therein. The plasma processing chamber 100 is suitable for performing the etching processes described herein. One example of a plasma processing chamber 100 that may be adapted to benefit from the present disclosure is the CENTRIS® SYM3® processing chamber available from Applied Materials, Inc., located in Santa Clara, California. It is contemplated that other process chambers, including process chambers from other manufacturers, may be adapted to perform implementations of the present disclosure.

[0026] The plasma processing chamber 100 includes a chamber body 105 having a process volume 101 defined therein. The chamber body 105 has sidewalls 112 and a bottom 118 coupled to ground 126. The sidewalls 112 have a liner 115 to protect the sidewalls 112 and extend the time between maintenance cycles of the plasma processing chamber 100. The dimensions of the chamber body 105 and the associated components of the plasma processing chamber 100 are not limited and can be proportionally larger than the size of the substrate 102 to be processed therein. Example substrate sizes include 200 mm diameter, 250 mm diameter, 300 mm diameter, and 450 mm diameter, among others.

[0027] The chamber body 105 supports a chamber lid assembly 110 to enclose the processing volume 101. The chamber body 105 may be made of aluminum or other suitable material. A substrate access port 113 is formed through a sidewall 112 of the chamber body 105 to facilitate transfer of a substrate 102 into and out of the plasma processing chamber 100. The substrate access port 113 may be coupled to a transfer chamber and / or other chambers of a substrate processing system (not shown).

[0028] A pumping port 145 is defined in the chamber body 105 and is connected to the processing volume 101. A pumping device (not shown) is coupled to the processing volume 101 through the pumping port 145 for evacuating the processing volume 101 and controlling the pressure of the processing volume 101. The pumping device may include one or more pumps and a throttle valve.

[0029] A gas panel 160 is coupled to the chamber body 105 by gas lines 167 to supply process gases into the processing volume 101. The gas panel 160 can include one or more process gas sources 161, 162, 163, and 164 and can further include inert, non-reactive, and reactive gases. Examples of process gases that can be provided by the gas panel 160 include, but are not limited to, oxygen-containing gases including O, HO, HO, O, NO, NO, halogen-containing gases including Cl, HCl, HF, F, Br, HCl, HBr, SF, and NF, passivation gases including nitrogen (N), carbonyl sulfide (COS), and sulfur dioxide (SO), and inert gases including argon and helium. Additionally, the process gas may include nitrogen, chlorine, fluorine, oxygen, and hydrogen-containing gases such as BCl3, C2F4, C4F8, C4F6, CHF3, CH2F2, CH3F, NF3, NH3, CO2, SO2, CO, N2, NO2, N2O, and H2, among others.

[0030] Valves 166 control the flow of process gases from sources 161, 162, 163, 164 from the gas panel 160 and are managed by a system controller 165. The flow of gases supplied to the chamber body 105 from the gas panel 160 can include combinations of gases.

[0031] The chamber lid assembly 110 may include a nozzle 114. The nozzle 114 has one or more ports for introducing process gases from sources 161, 162, 164, and 163 of a gas panel 160 into the process volume 101. After the process gases are introduced into the plasma processing chamber 100, the gases are activated to form a plasma. An antenna 148, such as one or more inductor coils, may be provided adjacent to the plasma processing chamber 100. An antenna power supply 142 may power the antenna 148 through a matching circuit 141 to inductively couple energy, such as RF energy, to the process gases to maintain a plasma formed from the process gases in the process volume 101 of the plasma processing chamber 100. Alternatively, or in addition to the antenna power supply 142, process electrodes below and / or above the substrate 102 may be used to capacitively couple RF power to the process gases to maintain a plasma in the process volume 101. The operation of the antenna power supply 142 may be controlled by a controller, such as a system controller 165 , which also controls the operation of other components in the plasma processing chamber 100 .

[0032] A substrate support pedestal 135 is disposed in the process volume 101 to support the substrate 102 during processing. The substrate support pedestal 135 can include an electrostatic chuck (ESC) 122 for holding the substrate 102 during processing. The ESC 122 uses electrostatic attraction to hold the substrate 102 against the substrate support pedestal 135. The ESC 122 is powered by an RF power supply 125 integrated with a matching circuit 124. The ESC 122 includes an electrode 121 embedded in a dielectric. The electrode 121 is coupled to the RF power supply 125 and provides a bias that attracts plasma ions formed by the process gas in the process volume 101 to the ESC 122 and the substrate 102 disposed thereon. The RF power supply 125 can be periodically turned on and off or pulsed during processing of the substrate 102. The ESC 122 includes an isolator 128 to prevent the sidewalls of the ESC 122 from being significantly attracted to the plasma to extend the maintenance lifecycle of the ESC 122. Additionally, the substrate support pedestal 135 may have a cathode liner 136 to protect the sidewalls of the substrate support pedestal 135 from plasma gases and to extend the time between maintenance of the plasma processing chamber 100 .

[0033] Additionally, the electrode 121 is coupled to a power supply 150. The power supply 150 provides a chucking voltage of about 200 volts to about 2000 volts to the electrode 121. The power supply 150 can also include a system controller, such as system controller 165, for controlling the operation of the electrode 121 by directing a DC current to the electrode 121 for chucking and dechucking the substrate 102.

[0034] The ESC 122 may include a heater disposed therein and connected to a power source (not shown) for heating the substrate, while the cooling base 129 supporting the ESC 122 may include conduits for circulating a heat transfer fluid to maintain the temperature of the ESC 122 and the substrate 102 disposed thereon. The ESC 122 is configured to operate within a temperature range defined by the thermal budget of the devices being fabricated on the substrate 102. For example, the ESC 122 may be configured to maintain the substrate 102 at a temperature of −50 degrees Celsius to about 250 degrees Celsius, e.g., from about 25 degrees Celsius to about 150 degrees Celsius.

[0035] The cooling base 129 is provided to help control the temperature of the substrate 102. To mitigate process drift and process time, the temperature of the substrate 102 may be maintained substantially constant by the cooling base 129 throughout the time the substrate 102 is in the plasma processing chamber 100. In one implementation, the temperature of the substrate 102 is maintained between −50 degrees Celsius and about 250 degrees Celsius, for example, from about 25 degrees Celsius to about 150 degrees Celsius, throughout the etching process.

[0036] A cover ring 130 is disposed over the ESC 122 and along the periphery of the substrate support pedestal 135. The cover ring 130 is configured to confine the etching gas to a targeted portion of the exposed upper surface of the substrate 102 while shielding the upper surface of the substrate support pedestal 135 from the plasma environment inside the plasma processing chamber 100. Lift pins (not shown) are selectively moved through the substrate support pedestal 135 to lift the substrate 102 above the substrate support pedestal 135 to facilitate access to the substrate 102 by a transfer robot (not shown) or other suitable transfer mechanism.

[0037] The system controller 165 may be utilized to control the process sequence, thereby regulating gas flow and other process parameters from the gas panel 160 into the plasma processing chamber 100. The software routines, when executed by the CPU, transform the CPU into a special purpose computer (controller) that controls the plasma processing chamber 100 so that processes are performed in accordance with the present disclosure. The software routines may also be stored and / or executed by a second controller (not shown) collocated with the plasma processing chamber 100.

[0038] FIG. 2 illustrates a flow diagram of a method 200 for performing a high-aspect-ratio feature patterning process utilizing a tin-based mandrel material according to one or more implementations of the present disclosure. FIGS. 3A-3D illustrate cross-sectional views of a film stack 300 at various stages of the high-aspect-ratio feature patterning process according to method 200. The mandrel material includes a tin oxide (e.g., SnO, SnO) material or a tin carbide (e.g., SnC) material. Method 200 can be utilized to form features with targeted critical dimensions and profiles, such as contact structures, gate structures, NAND structures, or interconnect structures for logic or memory devices, as needed. Alternatively, method 200 can be advantageously utilized to pattern other types of structures.

[0039] 3A, in operation 210, by providing a film stack 300 having a patterned hardmask layer 330 disposed on a patterned mandrel layer 320 disposed on a substrate 310. The patterned hardmask layer 330 is patterned using a patterned photoresist layer (not shown) having defined openings that may expose portions of the hardmask layer for etching.

[0040] During operation 220, the patterned hard mask layer 330 is then used to form a patterned mandrel layer 320. The mandrel patterning process of operation 220 can be performed in a plasma processing chamber, such as the plasma processing chamber 100 shown in FIG. 1. The mandrel patterning process is performed by supplying a first gas mixture that selectively removes material of the mandrel layer at a higher rate than material of the patterned hard mask layer 330 to form sidewalls 324 of the patterned mandrel layer 320. The first gas mixture supplied during the mandrel patterning process includes a reactive etchant utilized to etch tin carbide or tin oxide materials.

[0041] The first gas mixture may include a halogen-containing gas. The halogen-containing gas may be selected from the group consisting of HBr, chlorine gas (Cl), carbon- and fluorine-containing gases such as CF, CHF, and C4F, or combinations thereof. The first gas mixture may further include an oxygen-containing gas or H. The oxygen-containing gas may be selected from the group consisting of O, H2O, H2O2, O3, N2O, NO, CO, or combinations thereof. The first gas mixture may further include a passivation gas. The passivation gas may be selected from the group consisting of nitrogen (N), sulfur dioxide (SO2), carbonyl sulfide (COS), or combinations thereof. The first gas mixture is configured to remove material from the mandrel layer to form sidewalls 324 of the patterned mandrel layer 320. While not wishing to be bound by theory, it is believed that the inclusion of a passivation gas aids in achieving a vertical etch profile of the sidewalls 324. In one particular example, the first gas mixture includes O2 / at least one of HBr and chlorine gas (Cl2) / at least one of N2, COS, and SO2.

[0042] While the first gas mixture is supplied into a plasma processing chamber, such as the plasma processing chamber 100 shown in FIG. 1 , several process parameters are adjusted. In one implementation, the chamber pressure in the presence of the first gas mixture is adjusted. In one example, the process pressure in the etch chamber is adjusted from about 1 mTorr to about 80 mTorr, for example, from about 3 mTorr to about 60 mTorr. RF source and bias power can be applied to maintain the plasma formed from the first gas mixture. For example, to maintain the plasma inside the plasma processing chamber, RF source power of about 100 Watts to about 3000 Watts (about 200 Watts to about 1500 Watts, about 200 Watts to about 1,000 Watts, or about 500 Watts to about 3,000 Watts) can be applied to the inductively coupled antenna source. While supplying the first gas mixture, an RF bias power of less than about 1,500 Watts (about 40 Watts to 400 Watts, about 150 Watts to 400 Watts, or about 500 Watts to 1,500 Watts) may be applied. The first gas mixture may be flowed into the chamber at a flow rate of about 50 sccm to about 1,000 sccm. The temperature of the substrate may be maintained at about −50 degrees Celsius to about 250 degrees Celsius, for example, about −20 degrees Celsius to about 80 degrees Celsius.

[0043] While supplying the first gas mixture, the RF source and bias power ranges may be varied, primarily to facilitate removal of portions of the mandrel layer. For example, while supplying the first gas mixture, the RF source power may be increased, for example, from the first RF source power setting to the second RF source power setting, while the RF bias power may be decreased, for example, from the first RF bias power setting to the second RF bias power setting, as needed. In one example, after the first RF source and bias power setting is run for a time period of about 5 to about 20 seconds, the first RF source and bias power settings may be transitioned to the second RF source and bias power settings to continue the patterning process. In one example, the second RF source power setting may be about 30 to about 80% higher than the first RF source power setting. The second bias power setting may be about 30 to about 70% lower than the first bias power setting.

[0044] In one particular example, the first RF source power setting is from about 500 watts to about 600 watts, the first RF bias power setting is from about 50 watts to about 150 watts, the second RF source power setting is from about 700 watts to about 900 watts, and the second RF bias power setting is from about 20 watts to about 100 watts.

[0045] In some implementations, the patterned hard mask layer 330 may be a first type dielectric layer selected from the group of polysilicon, nanocrystalline silicon, amorphous silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, amorphous carbon, diamond-like carbon, titanium nitride, titanium oxide, titanium oxynitride, tantalum nitride, tantalum oxide, tantalum oxynitride, or any other suitable material. In one particular example, the first type of first type dielectric layer selected to form the patterned hard mask layer 330 is a carbon-containing layer, such as amorphous carbon, diamond-like carbon, SiOC, or the like. In some implementations where the mandrel material is tin oxide, the hard mask layer 330 can include a carbon-based film (e.g., a spin-on carbon film, an amorphous carbon film, a carbon-based photoresist, an extreme ultraviolet ("EUV") resist material, a dielectric material (e.g., SiO, SiN, SiON, SiOCN, or SiOC), and a silicon-containing film (e.g., a silicon or polysilicon film). In some implementations where the mandrel material is tin carbide, the hard mask layer 330 includes a patterned dielectric (e.g., SiO, SiN, SiON, SiOCN, or SiOC) or a silicon-containing film (e.g., a silicon or polysilicon film).

[0046] The patterned mandrel layer 320 comprises a different material from the patterned hard mask layer 330. The patterned mandrel layer 320 is a tin-containing material. In one example, the patterned mandrel layer 320 is a tin oxide layer (e.g., SnOx, SnO, or SnO2). In another example, the patterned mandrel layer 320 is a tin carbide layer (e.g., Sn—C, or Sn(C) containing Sn—Sn, Sn—C, and / or C—C bonds). While not being bound by theory, it is believed that the strong Sn—C bonds help maintain the vertical profile of the sidewalls 324 of the patterned mandrel layer 320. The patterned mandrel layer 320 can be formed by any suitable deposition process, such as PVD, CVD, ALD, or other suitable deposition technique. The patterned mandrel layer 320 is used to pattern a subsequently deposited spacer material. In one example, the patterned mandrel layer 320 has a thickness between about 5 nm and about 200 nm, for example, from about 40 nm to about 100 nm.

[0047] 3B, the patterned hardmask layer 330 is removed after forming the patterned mandrel layer 320. In some implementations, the patterned hardmask layer 330 may remain on the patterned mandrel layer 320 and be removed later. In some implementations, the patterned hardmask layer 330 is used up during patterning of the patterned mandrel layer 320.

[0048] In some implementations, the substrate 310 can include a dielectric layer utilized to form a contact layer, a dual damascene structure, or any suitable material. Suitable examples of the dielectric layer include carbon-containing silicon oxide (SiOC), tetraethyl orthosilicate (TEOS), thermal silicon oxide, polymeric materials such as polyamide, SOG, USG, silicon oxide, silicon nitride (e.g., SiNx), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbon-nitride (SiCN), silicon oxycarbide, boron nitride (BN), high-k dielectrics including, for example, hafnium oxide (e.g., HfOx, HfO2), aluminum oxide (e.g., AlxOy, Al2O3), zirconium oxide (ZrO2), titanium oxide, or a combination thereof. In one example, the substrate 310 includes silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, or a combination thereof.

[0049] 3B, a spacer layer 340 is formed over the substrate 310 and the patterned mandrel layer 320. The spacer layer 340 is formed from a material different from the material of the patterned mandrel layer 320 and the substrate 310. In some implementations, the spacer layer 340 comprises a material different from the material of the patterned mandrel layer 320 and selected from silicon oxide, silicon nitride, a metal oxide, or polysilicon. In one example, the spacer layer 340 is a doped silicon-containing layer, such as a boron-doped silicon material, phosphorus-doped silicon, or other suitable group III, IV, or V doped silicon material. In one example, the spacer layer 340 is a boron-doped silicon layer.

[0050] In some implementations, the spacer layer 340 is formed by a CVD process. Note that the spacer layer 340 can be formed by any suitable deposition process, such as PECVD (plasma-enhanced chemical vapor deposition), ALD, SACVD, HDPCVD, spin-on coating, or other suitable deposition technique. In one example, the spacer layer 340 has a thickness of from about 5 nm to about 25 nm.

[0051] In one example, the spacer layer 340 is conformally formed on the patterned mandrel layer 320 and conformally lines the top surface 322 and sidewalls 324 of the patterned mandrel layer 320. It is believed that the spacer layer 340 can provide good etch selectivity during subsequent patterning processes so that a good profile of the spacer layer 340 after the patterning process can be obtained, as needed.

[0052] In operation 240, the spacer layer 340 is patterned as shown in FIG. 3C. The spacer patterning process of operation 240 can be performed in a plasma processing chamber, such as the plasma processing chamber 100 shown in FIG. 1. The patterning process is performed by supplying a second gas mixture capable of selectively removing portions of the spacer layer 340 with targeted directionality, such that some portions of the spacer layer 340 (e.g., sidewalls 342) can remain on the substrate 310 with the targeted profile to form the spacer structure 350. In one example, the second gas mixture supplied during the spacer patterning process can include a reactive etchant utilized for anisotropic etching of silicon-containing materials from the spacer layer 340, particularly for anisotropically etching doped silicon-containing materials.

[0053] In some implementations, the second gas mixture includes a halogen-containing gas selected from the group, such as HBr, chlorine gas (Cl), boron trichloride (BCl), nitrogen trifluoride (NF), sulfur hexafluoride gas (SF), carbon- and fluorine-containing gases, such as CF, CHF, and CF, or combinations thereof. In one example, the second gas mixture includes HBr and chlorine gas (Cl) utilized to etch the spacer layer 340. The second gas mixture is configured to remove top and bottom portions of the spacer layer 340 without significantly corroding the sidewalls 342 of the spacer layer 340. In one example, etching the spacer layer 340 results in a substantially square top surface of the spacer structure 350.

[0054] While the second gas mixture is being supplied into the plasma processing chamber, several process parameters are adjusted. In one implementation, the chamber pressure in the presence of the second gas mixture is adjusted. In one example, the process pressure in the plasma processing chamber is adjusted from about 1 mTorr to about 80 mTorr, for example, from about 3 mTorr to about 60 mTorr. RF source and bias power can be applied to maintain the plasma formed from the second gas mixture. For example, to maintain the plasma inside the plasma processing chamber, RF source power of about 100 Watts to about 3000 Watts (about 200 Watts to about 1500 Watts, about 200 Watts to about 1,000 Watts, or about 500 Watts to about 3000 Watts) can be applied to the inductively coupled antenna source. While supplying the second gas mixture, RF bias power of less than about 1500 Watts (about 40 Watts to 400 Watts, about 150 Watts to about 400 Watts, or about 500 Watts to about 1,500 Watts) can be applied. The second gas mixture may be flowed into the chamber at a flow rate of about 50 sccm to about 1,000 sccm. The temperature of the substrate may be maintained at about −50 degrees Celsius to about 250 degrees Celsius, for example, about −20 degrees Celsius to about 80 degrees Celsius.

[0055] While supplying the second gas mixture, the RF source and bias power ranges may be varied, primarily to facilitate removal of portions of the spacer layer 340. For example, while supplying the second gas mixture, the RF source power may be increased, e.g., from a first RF source power setting to a second RF source power setting, while the RF bias power may be decreased (e.g., from the first RF bias power setting to the second RF bias power setting), as needed. In one example, after the first RF source and bias power setting is run for a time period between about 5 seconds and about 20 seconds, the first RF source and bias power settings may be transitioned to the second RF source and bias power settings to continue the spacer patterning process. In one example, the second RF source power setting is about 30% to about 80% higher than the first RF source power setting. The second bias power setting is about 30 percent to about 70 percent lower than the first bias power setting.

[0056] In one example, the first RF source power setting is from about 500 watts to about 600 watts, the first RF bias power setting is from about 50 watts to about 150 watts, the second RF source power setting is from about 700 watts to about 900 watts, and the second RF bias power setting is from about 20 watts to about 100 watts.

[0057] In operation 250, the patterned mandrel layer 320 is removed to form spacer structures 350, as shown in Figure 3D. The etch chemistry selected for removal of the patterned mandrel layer 320 may be selected based on the materials used to form the patterned mandrel layer 320 and the spacer layer 340.

[0058] In one example, the spacer patterning process can include one or more processing stages. For example, after a second gas mixture is provided to primarily remove the top and bottom portions of the spacer layer 340, a third gas mixture is provided to primarily remove the patterned mandrel layer 320. The third gas mixture can include O, H, H / N, Cl, HBr, HO, HO, or a combination thereof, and / or a carrier gas such as N, He, or Ar. The third gas mixture can include an oxygen-containing gas mixture and / or a carrier gas such as N, He, or Ar. In one example, carbon- and fluorine-containing gases such as CHF and CF can also be utilized as needed. In one example, the second gas mixture includes O and N, or O, N, and CHF.

[0059] While the third gas mixture is being supplied into the plasma processing chamber, several process parameters may be adjusted. In one implementation, the chamber pressure in the presence of the third gas mixture is adjusted. In one example, the process pressure in the plasma processing chamber is adjusted from about 1 mTorr to about 80 mTorr, for example, from about 3 mTorr to about 60 mTorr. RF source and bias power may be applied to maintain the plasma formed from the third gas mixture. For example, to maintain the plasma inside the plasma processing chamber, RF source power of about 100 Watts to about 3,000 Watts (about 200 Watts to about 1,500 Watts, about 200 Watts to about 1,000 Watts, or about 500 Watts to about 3,000 Watts) may be applied to the inductively coupled antenna source. While supplying the third gas mixture, RF bias power of less than about 1,500 Watts (about 40 Watts to 400 Watts, about 150 Watts to about 400 Watts, or about 500 Watts to about 1,500 Watts) may be applied. The third gas mixture may be flowed into the chamber at a flow rate of about 50 sccm to about 1,000 sccm. The temperature of the substrate may be maintained at about −50 degrees Celsius to about 250 degrees Celsius, for example, about −20 degrees Celsius to about 80 degrees Celsius. The spacer structure 350 may be subjected to further processing.

[0060] Implementations using tin-based mandrels may include one or more of the following potential advantages: Due to the strong Sn-C bond, the Sn-C mandrels maintain a vertical profile even at small dimensions (e.g., <10 nm). Carbon, Sn, or SnOx (oxidation in air) can be easily removed by dry plasma etching or wet etchants, which provides precise critical dimension control for multi-patterning.

[0061] FIG. 4 shows a flow diagram of another method 400 for etching a film stack 500 having a tin-based hard mask layer 530. FIGS. 5A-5D show cross-sectional views of the film stack 500 at various stages of a high-aspect-ratio feature patterning process according to the method 400. The method 400 may be utilized to form features with targeted critical dimensions and profiles, such as contact structures, gate structures, NAND structures, or interconnect structures for logic or memory devices, as desired. Alternatively, the method 400 may be advantageously utilized to etch other types of structures.

[0062] The method 400 begins in operation 410 by providing a film stack 500 having a hard mask layer 530 disposed on a plurality of layers 520 over a substrate 510, as shown in FIG. 5A.

[0063] The hard mask layer 530 includes tin oxide (SnO, SnO2) or tin carbide (SnC) as described herein. In some implementations, the plurality of layers 520 includes multiple dielectric layers. In one example, the multiple dielectric layers include alternating oxide-nitride-oxide (ONO) layers. In another implementation, the plurality of layers 520 includes alternating silicon and silicon-germanium layers.

[0064] In some implementations, as shown in FIG. 5A , the hard mask layer 530 has a patterned photoresist layer 540 disposed thereon. The patterned photoresist layer 540 can be a positive-tone photoresist and / or a negative-tone photoresist capable of undergoing a chemically amplified reaction. In one example, the patterned photoresist layer 540 is a polymer-organic material suitable for EUV lithography processes. In one or more examples, the patterned photoresist layer 540 includes at least one metal element selected from at least one of Sn, Ta, In, Ga, Zr, Zn, any alloy thereof, or any combination thereof. The metal element included in the patterned photoresist layer 540 can modify light absorption efficiency during the lithography exposure process as needed.

[0065] A patterned photoresist layer 540 is disposed on the hard mask layer 530. In some implementations, the hard mask layer 530 is disposed on additional layers, such as a bottom antireflective coating (BARC) layer and / or an organic layer (not shown). The organic layer can include either an organic material or a mixture of organic and inorganic materials.

[0066] The hard mask layer 530 to be formed in the film stack 500 includes a tin oxide or tin carbide material. The hard mask layer 530 can include a single layer or multiple layers. In the example shown in FIG. 5A , the hard mask layer 530 is a single layer containing or formed from tin oxide, tin carbide, or a combination thereof. In one or more examples, the hard mask layer 530 has a thickness of from about 10 Å to about 500 Å, e.g., from about 20 Å to about 200 Å, e.g., from about 50 Å to about 100 Å.

[0067] The hard mask layer 530 may be formed by any suitable deposition technique, hi some implementations, the hard mask layer 530 is formed by CVD, ALD, PVD, or other suitable deposition process.

[0068] In some implementations, the hard mask layer 530 is formed by a CVD or PVD process, and a carrier gas and / or an inert gas with a relatively high atomic weight, such as Xe or Kr, may be used during the plasma deposition process of the hard mask layer 530. The substrate temperature controlled during the formation of the hard mask layer 530 may be controlled to be between about −50 degrees Celsius and about 250 degrees Celsius. Without being bound by theory, it is believed that controlling the substrate temperature at a relatively low temperature, for example, less than 250 degrees Celsius, during the formation of the hard mask layer 530 can help form the hard mask layer 530 at a relatively slow deposition rate and provide a film surface with a relatively smooth surface.

[0069] The substrate 510 can be any one of a semiconductor substrate, a silicon wafer, a glass substrate, etc. The substrate 510 can be made of crystalline silicon (e.g., Si <100> or Si <111> The substrate 510 may be made of a material such as silicon dioxide, strained silicon, silicon germanium, germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon-on-insulator (SOI), carbon-doped silicon dioxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire. The substrate 510 may have various dimensions, such as 200 mm, 300 mm, 450 mm, or other diameters, and may be a rectangular or square panel. Unless otherwise noted, examples described herein are given with respect to substrates having a 200 mm diameter, a 300 mm diameter, or a 450 mm diameter.

[0070] During operation 420, an etching process is performed to pattern the hard mask layer 530 to form a patterned hard mask layer 550, as shown in FIG. 5B . The hard mask layer 530 is patterned using a patterned photoresist layer 540 having defined openings 542, which may expose portions of the surface of the hard mask layer 530 for etching. The patterned hard mask layer 550 has defined openings or features 552, exposing portions of the surfaces of the plurality of layers 520. Because the dimensions of the openings 542 defined by the patterned photoresist layer 540 are small, e.g., less than 100 nm, the gas mixture and process parameters for etching the hard mask layer 530 are carefully selected to etch the hard mask layer 530 with good profile control without damaging the underlying plurality of layers 520.

[0071] In one or more examples, the etching process of operation 420 is performed by supplying a first etching gas mixture into the plasma processing chamber while maintaining the temperature of the substrate support pedestal 135 at room temperature (e.g., about 23 degrees Celsius) to about 150 degrees Celsius.

[0072] In some implementations, the first etching gas mixture includes at least one halogen-containing gas. The halogen-containing gas may include a fluorine-containing gas, a chlorine-containing gas, a bromine-containing gas, or a combination thereof. Suitable examples of halogen-containing gases include SF, SiCl, SiCl, NF, HBr, Br, CHF, CHF, CF, CF, CF, CF, HCl, CF, Cl, HF, CCl, CHCl, CHCl, and CHCl. ​​In some examples, a silicon-containing gas may also be provided in the first etching gas mixture. Suitable examples of silicon-containing gases include SiCl, SiCl, SiH, and SiH. In particular, examples of chlorine-containing gases include HCl, Cl, CCl, CHCl, CHCl, CHCl, SiCl, and SiCl, and examples of bromine-containing gases include HBr and Br. Reactive gases, such as oxygen-containing or nitrogen-containing gases, for example, O 2 , N 2 , N 2 O, NO 2 , O 3 , H 2 O, etc., may also be provided in the first etching gas mixture as needed.

[0073] In some implementations, the halogen-containing gas used to etch the hard mask layer 530 includes a chlorine-containing gas or a bromine-containing gas. While supplying the first etching gas mixture into the plasma processing chamber, an inert gas can be supplied to the etching gas mixture, if necessary, to aid in profile control. Examples of inert gases supplied to the gas mixture include Ar, He, Ne, Kr, and Xe.

[0074] In one example, the first etch gas mixture utilized to etch the hard mask layer 530, such as tin oxide or tin carbide, includes HBr, Cl2, Ar, He, or a combination thereof.

[0075] During operation 420, the chamber pressure of the first etching gas mixture is also adjusted. In some implementations, the process pressure in the plasma processing chamber is adjusted from about 2 mTorr to about 100 mTorr, such as about 6 mTorr, for example, from about 3 mTorr to about 20 Torr. In the presence of the first etching gas mixture, RF source or bias power can be applied to maintain the plasma formed from a continuous or pulsed mode, as needed. For example, to maintain the plasma inside the plasma processing chamber, RF source power having a frequency of about 13.56 MHz can be applied to the inductively coupled antenna source at an energy level from about 200 Watts to about 1,000 Watts, such as from about 500 Watts. Additionally, RF bias power having a frequency from about 2 MHz to about 13.56 MHz can be applied at less than 500 Watts, such as from about 0 Watts to about 450 Watts, such as about 150 Watts.

[0076] In some implementations, during etching in operation 420, the RF bias power and the RF source power may be pulsed into the plasma processing chamber. The RF bias power and the RF source power may be synchronously or asynchronously pulsed into the plasma processing chamber. In some examples, the RF bias power and the RF source power are asynchronously pulsed into the plasma processing chamber. For example, the RF source power may be pulsed into the processing chamber before pulsing the RF bias power. For example, the RF bias power may be in a pulse mode synchronous with the RF source power or with a time delay relative to the RF source power. In some examples, the RF source power and the RF bias power are pulsed between about 5% and about 75% of each duty cycle. For example, each duty cycle between each time unit is about 0.1 milliseconds (ms) to about 10 ms.

[0077] In one example, the first etch gas mixture supplied in operation 220 includes O gas supplied into the chamber at a flow rate of about 0 sccm to about 50 sccm. The first etch gas mixture further includes a halogen-containing gas, such as HBr, supplied at a flow rate of about 25 sccm to about 250 sccm, such as about 100 sccm. In one example, the halogen-containing gas includes a fluorine-containing gas. The fluorine-based etch chemistry forms SnF, which is non-volatile to improve selectivity during dielectric etching. SnF or SnO can be removed by a hydrogen plasma to form a SnH-based plasma or a halogen-based plasma (e.g., Cl / HBr).

[0078] After the features 552 are formed in the hard mask layer 530 , a de-scum or strip process may be performed to remove the remaining patterned photoresist layer 540 .

[0079] In operation 430, further etching or patterning may be performed to continue transferring the features 552 into the plurality of layers 520 to form a patterned plurality of layers 560 having features 562 formed therein, as shown in FIG. 5C . In some implementations, the etching or patterning of operation 430 is performed using the first gas mixture of operation 420. In other implementations, the etching or patterning of operation 430 is performed using a second gas mixture that is different from the first gas mixture used during operation 420. The second gas mixture may be selected based on the type of material used to form the patterned hard mask 550 and the type of material used to form the plurality of layers 520.

[0080] In operation 440, a hardmask removal process may be performed to remove the patterned hardmask 550 from the patterned plurality of layers 560, as shown in FIG. 5D. The strip process of operation 440 may be highly selective to silicon oxide and silicon nitride, which may result in the critical dimensions of the patterned plurality of layers 520 remaining unchanged.

[0081] Implementations using a tin-based hard mask may include one or more of the following potential advantages: Fluorine-based etch chemistries form SnF4, which is non-volatile to improve selectivity during dielectric etching. SnF4 or SnO2 can be removed by H2 plasma to form SnH4-based plasma or halogen-based plasma (e.g., Cl2 / HBr). The strip process of tin-based hard mask films can be highly selective to silicon oxide and silicon nitride (ONO structure post-etch, no critical dimension change). Tin oxide can also be selectively removed by wet chemistries (e.g., HCl, HNO3, or H2SO4).

[0082] 6 shows a flow diagram of a method 600 for performing a high-aspect-ratio feature patterning process utilizing a tin-based liner material according to one or more implementations of the present disclosure. FIGS. 7A-7D show cross-sectional views of a film stack 700 at various stages of the high-aspect-ratio feature patterning process according to method 600. Method 600 may be utilized to form features with targeted critical dimensions and profiles, such as contact structures, gate structures, NAND structures, or interconnect structures for logic or memory devices, as needed. Alternatively, method 600 may be advantageously utilized to etch other types of structures.

[0083] 7A , by providing a film stack 700 having a patterned hardmask layer 730 disposed on a plurality of layers 720 disposed on a substrate 710. The patterned hardmask layer 730 may be patterned using a patterned photoresist layer (not shown) having defined openings, thereby exposing portions of the hardmask layer for etching. The patterned hardmask layer 730 has defined openings or features 732, exposing portions of the surfaces of the plurality of layers 720.

[0084] In one example, the patterned hard mask layer 730 may be a first type dielectric layer selected from the group of polysilicon, nanocrystalline silicon, amorphous silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, amorphous carbon, diamond-like carbon, titanium nitride, titanium oxide, titanium oxynitride, tantalum nitride, tantalum oxide, tantalum oxynitride, or any other suitable material. In one particular example, the first type dielectric layer selected to form the patterned hard mask layer 730 is a carbon-containing layer, such as amorphous carbon, diamond-like carbon, SiOC, or the like.

[0085] The patterned hard mask layer 730 may be formed using any suitable patterning process.

[0086] In operation 620, further etching or patterning may be performed to continue transferring feature 732 to layers 720 to form patterned layers 740 having feature 742 formed therein, as shown in FIG. 7B. Feature 742 extends the depth of the feature from a top surface 744 of patterned layers 740 to a bottom surface 746 of feature 742. Feature 742 has a width defined by at least one sidewall 748.

[0087] Any suitable etching or patterning process may be performed to form patterned plurality of layers 740. The etching or patterning of operation 620 may be performed using a gas mixture selected based on the type of material used to form patterned hard mask layer 730 and the type of material used to form plurality of layers 720. In some implementations, the etching or patterning of operation 620 is performed using a gas mixture and etching conditions similar to the first gas mixture and etching conditions of operation 420. In other implementations, the etching or patterning of operation 620 is performed using a gas mixture and process conditions different from the first gas mixture and etching conditions used during operation 420.

[0088] In operation 630, as shown in FIG. 7C , a liner layer 760 is formed over the patterned hard mask layer 730 (if present) and the patterned plurality of layers 740. The liner layer 760 is a tin-based liner layer. The liner layer 760 includes tin oxide, tin carbide, or a combination thereof. The liner layer 760 can be viewed as another spacer layer that helps reduce the dimensions of the opening 742 defined therebetween, if desired, at reduced dimensions (e.g., a spacer-on-spacer approach). The liner layer 760 can be formed by CVD, ALD, or any other suitable deposition technique. In one example, the liner layer 760 is a tin oxide or tin carbide layer formed by an ALD process. 7C is conformally formed over the patterned hard mask layer 730 and the patterned layers 740, thereby conformally lining the top surface 734 of the patterned hard mask layer 730 and the sidewalls 748 of the patterned layers 740. The liner layer 760 further reduces the dimensions of the features 742 defined between the sidewalls 748, which may further be utilized as a mask layer to transfer the features, if desired, at reduced dimensions, to underlying or unpatterned portions of the patterned layers 740. In one example, the liner layer 760 has a thickness of from about 1 nm to about 10 nm, e.g., from about 2 nm to about 5 nm.

[0089] In operation 640, another patterning process is performed to transfer feature 742 to an underlying or unpatterned portion of patterned layers 740, as needed, to form feature 752 with reduced small dimensions, as shown in FIG. 7D . During operation 640, a portion of liner layer 760 may be removed, for example, liner layer 760 formed on top surface 734 of patterned hard mask layer 730. Liner layer 760 and the unpatterned portions of patterned layers 740 are subjected to anisotropic etching or patterning until feature 752 is formed. The patterning process of operation 640 may be similar to the patterning process performed in operation 240. In some implementations, operation 640 exposes the top surface of substrate 710.

[0090] Implementations that use tin-based liners may include one or more of the following potential advantages: Tin-based liners can reduce or prevent dielectric via hole warping in critical dimensions Tin-based liners can be easily removed in wet or dry plasma without compromising the critical dimensions of the features.

[0091] The implementations and all functional operations described herein may be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structural means disclosed herein and structural equivalents thereof, or in combinations thereof. The implementations described herein may be implemented as one or more non-transitory computer program products, such as one or more computer programs tangibly embodied in a machine-readable storage device for execution by or to control the operation of a data processing apparatus, e.g., a programmable processor, a computer, or multiple processors or computers.

[0092] The processes and logic flows described herein may be performed by one or more programmable processors executing one or more computer programs to perform functions by manipulating input data and generating output. The processes and logic flows may also be performed by, and an apparatus may be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

[0093] The term "data processing apparatus" encompasses all apparatus, devices, and machines for processing data, including, by way of example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, an apparatus may include code that creates an execution environment for a given computer program, such as code comprising processor firmware, a protocol stack, a database management system, an operating system, or one or more combinations thereof. Processors suitable for the execution of computer programs include, by way of example, both general-purpose and special-purpose microprocessors, and any one or more processors of any kind of digital computer.

[0094] Suitable computer-readable media for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, by way of example, semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices, magnetic disks, e.g., internal hard disks or removable disks, magneto-optical disks, and CD-ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0095] When introducing elements of the present disclosure or example aspects or implementations thereof, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the element.

[0096] The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements.

[0097] While the foregoing is directed to implementations of the present disclosure, other and further implementations of the present disclosure may be devised without departing from the basic scope thereof, the scope of which is determined by the following claims.

Claims

1. 1. A method of forming a feature on a substrate, comprising: forming a mandrel layer on a substrate, the mandrel layer being a tin carbide layer or a tin oxide layer; patterning the mandrel layer; conformally forming a spacer layer on the patterned mandrel layer; patterning the spacer layer; 1. A method for forming a feature on a substrate, comprising:

2. Selectively removing the patterned mandrel layer from the patterned spacer layer. The method of claim 1 further comprising:

3. patterning the mandrel layer supplying a first mixed gas containing a halogen-containing gas and an oxygen gas; applying a first RF source power setting into the first gas mixture; The method of claim 1 , comprising:

4. The method of claim 1 , wherein the spacer layer comprises a material different from that of the mandrel layer and is selected from silicon oxide, silicon nitride, metal oxide, or polysilicon.

5. The method of claim 1 , wherein the mandrel layer has a hard mask layer formed thereon.

6. 6. The method of claim 5, wherein the hard mask layer comprises a material selected from polysilicon, nanocrystalline silicon, amorphous silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, amorphous carbon, diamond-like carbon, titanium nitride, titanium oxide, titanium oxynitride, tantalum nitride, tantalum oxide, tantalum oxynitride, or any other suitable material, or combination thereof.

7. The method of claim 1 , wherein the substrate comprises silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, or a combination thereof.

8. 1. A method of forming a feature on a substrate, comprising: forming a hard mask layer comprising tin oxide or tin carbide on a film stack formed on a substrate; applying a first etching gas mixture to the substrate; etching the hard mask layer to form a patterned hard mask layer; A method comprising:

9. applying a second etching gas mixture to the substrate; Etching the film stack exposed by the patterned hard mask layer; The method of claim 8 further comprising:

10. 10. The method of claim 9, further comprising selectively removing the hard mask layer.

11. 9. The method of claim 8, wherein the first etching gas mixture comprises a halogen-containing gas.

12. The halogen-containing gas is Cl ２ 12. The method of claim 3 or claim 11, wherein the gas is selected from HBr gas, HBr gas, or a combination thereof.

13. The first etching gas mixture comprises N ２ , O ２ , COS, SO ２ 10. The method of claim 9, further comprising a passivation gas selected from:

14. 1. A method of forming a feature on a substrate, comprising: forming a patterned hard mask layer comprising carbon on a film stack formed on a substrate; applying a first etching gas mixture to the substrate; etching the film stack exposed by the hard mask layer to form a patterned film stack; forming a liner layer comprising tin oxide or tin carbide over the patterned hard mask layer and the patterned film stack; 1. A method for forming a feature on a substrate, comprising:

15. The method of claim 14 , wherein the liner layer is formed by an ALD process.

16. The method of claim 14, further comprising exposing the liner layer to wet chemistry or dry plasma to remove the liner layer.

17. 15. The method of claim 14, wherein the patterned hard mask layer comprises amorphous carbon, diamond-like carbon, or a combination thereof.

18. The method of claim 9 or claim 14, wherein the film stack comprises multiple dielectric layers.

19. 20. The method of claim 18, wherein the film stack comprises an oxide nitride oxide (ONO) layer.

20. 20. The method of claim 18, wherein the film stack comprises alternating layers of silicon and silicon germanium.

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