Semiconductor device

Abstract

To provide, for example, a semiconductor device with a new structure.SOLUTION: A semiconductor device includes: a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided over a substrate containing a semiconductor material. The second transistor includes an oxide semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a manufacturing method thereof. do. [Background technology]

[0002] Memory devices that use semiconductor elements are volatile memory devices that lose their contents when the power supply is cut off. and non-volatile memory devices, which retain their contents even when the power supply is cut off. can be.

[0003] A typical example of a volatile memory device is a DRAM (Dynamic Random Access Memory). DRAM is a memory element that can be selected from transistors. By storing charge in the capacitor, information is stored.

[0004] Based on the above principle, in DRAM, when information is read, the charge in the capacitor is lost. Therefore, every time data is read, a write operation is required again. The transistors that make up the transistors have leakage current, and when the transistors are not selected, Therefore, the data retention period is short. A write operation (refresh operation) is required, and power consumption must be reduced sufficiently. Furthermore, if the power supply is cut off, the memory contents are lost, making it difficult to store long-term memories. To store the data, a separate storage device using magnetic or optical materials is required.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM uses circuits such as flip-flops to store the memory contents. In order to retain data, no refresh operation is required, which is an advantage over DRAM. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. In addition, there is a problem that the memory contents are lost when the power supply is cut off. In this regard, it is no different from DRAM.

[0006] A typical example of a nonvolatile memory device is flash memory. A floating gate is provided between the gate electrode of the transistor and the channel forming region, Since memory is stored by holding an electric charge in the floating gate, the data retention period is extremely long. The advantage is that it lasts for a very long time (semi-permanent) and does not require the refresh operations required for volatile storage devices. The point is as follows (see, for example, Patent Document 1).

[0007] However, the gate insulating layer that constitutes the memory element is damaged by the tunnel current that occurs during writing. This causes a problem in that the memory element will stop functioning after a certain number of writes. To mitigate the effect of this problem, for example, the number of writes to each memory element is made uniform. However, to achieve this, complex peripheral circuits are required. However, even if such a method is adopted, the fundamental problem of lifespan will not be resolved. Therefore, flash memory is not suitable for applications where information needs to be rewritten frequently.

[0008] Also, to hold charge on the floating gate or to remove that charge. High voltages are required for this. Furthermore, it takes a relatively long time for the charge to be retained or removed. There is also the problem that it takes time to write and erase data, and it is not easy to speed up the writing and erasing. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 57-105889 Summary of the Invention [Problem to be solved by the invention]

[0010] In view of the above-mentioned problems, one embodiment of the disclosed invention provides a method for storing stored contents even when power is not supplied. To provide a semiconductor device having a new structure that can retain data and has no limit on the number of times it can be written. This is one of the purposes of the organization. [Means for solving the problem]

[0011] One embodiment of the present invention is a transistor formed using an oxide semiconductor and a transistor formed using other materials. The semiconductor device has a stacked structure with a transistor formed using the above-mentioned method. Such a configuration can be adopted.

[0012] One aspect of the present invention is a semiconductor memory device including a source line, a bit line, a first signal line, a plurality of second signal lines, and a plurality of A plurality of memory cells connected in series between the word line, the source line and the bit line, and an input a plurality of second signals to select memory cells designated by the input address signals; a second signal line and word line driver circuit for driving the signal line and the plurality of word lines; a write circuit that outputs a potential to a first signal line and a bit line that is connected to a specified memory cell; a read circuit that compares the potential of the bit line input from the bit line with a plurality of read potentials; and one of a plurality of correction voltages based on the comparison result between the potential of the bit line and a plurality of read potentials. a control circuit for selecting a write potential and a plurality of read potentials; and a potential generating circuit for supplying a potential to the read circuit, and one of the plurality of memory cells is a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; a second gate electrode, a second source electrode, and a second drain electrode; a first transistor and a capacitor element, the first transistor being formed on a substrate including a semiconductor material; the second transistor includes an oxide semiconductor layer, and the first gate electrode and one of the second source electrode and the second drain electrode and one of the electrodes of the capacitor element is The source line and the first source electrode are electrically connected to each other, and the bit line and the first source electrode are electrically connected to each other. The first drain electrode is electrically connected to the first signal line and the second source electrode or The other of the second drain electrodes is electrically connected to one of the plurality of second signal lines and the second gate electrode. The word line is electrically connected to the other electrode of the capacitor element. It is a semiconductor device electrically connected.

[0013] One aspect of the present invention is a semiconductor memory device including a source line, a bit line, a first signal line, a plurality of second signal lines, and a plurality of A plurality of memory cells connected in series between the word line, the source line and the bit line, and an input a plurality of second signals to select memory cells designated by the input address signals; a second signal line and word line driver circuit for driving a first signal line and a plurality of word lines; In the write operation, a first write potential is output to the first signal line, and in the second write operation, a write circuit that outputs one of a plurality of second write potentials to a first signal line; In the first read operation, the signal input from the bit line connected to the specified memory cell is The potential of the first bit line is compared with a plurality of first read potentials, and a second read operation is performed. In the second bit line input from the bit line connected to the specified memory cell, and comparing the potential with a plurality of second read potentials to read data from the memory cell. a read circuit, based on a comparison result between the potential of the first bit line and the plurality of first read potentials; A control for selecting one of a plurality of correction voltages and one of a plurality of second write potentials. a control circuit for controlling a first write potential, a plurality of second write potentials, and a plurality of first read potentials; and generating a plurality of second read potentials and supplying them to the write circuit and the read circuit. and a potential generating circuit configured to generate a potential, and one of the plurality of memory cells has a first gate electrode, a first source a first transistor having a first gate electrode and a first drain electrode; a second transistor having a second source electrode and a second drain electrode; and a capacitance element. , wherein the first transistor is provided on a substrate including a semiconductor material, and the second transistor The gate electrode is configured to include an oxide semiconductor layer, and has a first gate electrode and a second source electrode or a first One of the drain electrodes of the capacitor element is electrically connected to the source line. The first source electrode is electrically connected to the bit line, and the first drain electrode is electrically connected to the bit line. The first signal line and the other of the second source electrode and the second drain electrode are electrically connected to each other. , and one of the plurality of second signal lines and the second gate electrode are electrically connected. In this semiconductor device, one of the plurality of word lines is electrically connected to the other electrode of the capacitor element. be.

[0014] In the above, the semiconductor device includes a first selection line, a second selection line, a gate a third transistor electrically connected at its gate electrode, a second select line, and a gate electrode; and a fourth transistor electrically connected at the bit line. The source line is electrically connected to the first drain electrode through a fourth transistor. The first source electrode is electrically connected to the second source electrode via a transistor.

[0015] In the above, the first transistor is a channel transistor provided in a substrate including a semiconductor material. impurity regions provided so as to sandwich the channel forming region; a first gate insulating layer on the impurity region; a first gate electrode on the first gate insulating layer; and and a first source electrode and a first drain electrode electrically connected to the first transistor.

[0016] In the above, the second transistor has a second gate electrode on a substrate including a semiconductor material. a second gate insulating layer on the second gate electrode; and an oxide semiconductor layer on the second gate insulating layer. a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer; and,

[0017] In the above, the substrate containing a semiconductor material may be a single crystal semiconductor substrate or an SOI substrate. It is preferable to use a plate, and it is particularly preferable that the semiconductor material is silicon.

[0018] In the above, the oxide semiconductor layer is made of an In-Ga-Zn-O based oxide semiconductor material. In particular, the oxide semiconductor layer preferably contains In2Ga2ZnO7 crystals. Furthermore, the hydrogen concentration of the oxide semiconductor layer is preferably 5×10 19 ato ms / cm 3The off-state current of the second transistor is preferably 1× or less. 10 -13 It is preferable to set it to A or less.

[0019] In the above, the second transistor is provided in a region overlapping with the first transistor. The configuration can be as follows.

[0020] In this specification, the terms "above" and "below" refer to the positional relationship of the components "directly above" and "below." For example, the term "the first layer on the gate insulating layer" is not limited to "directly under" the first layer. The expression "gate electrode" means that other components are included between the gate insulating layer and the gate electrode. In addition, the terms "upper" and "lower" are merely expressions used for the convenience of explanation. Unless otherwise specified, the terms "top" and "bottom" are interchangeable.

[0021] In addition, in this specification, the terms "electrode" and "wiring" are used to refer to these components functionally. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wire" are used interchangeably to refer to the plural "electrodes." This also includes cases where "wires" and "circuits" are formed integrally.

[0022] Also, the functions of "source" and "drain" may differ depending on whether transistors with different polarities are used or not. However, they may be swapped when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" are used interchangeably. It is assumed that this is possible.

[0023] In this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects.

[0024] For example, "something that has some kind of electrical effect" includes not only electrodes and wiring, but also transistors. Switching elements such as transistors, resistors, inductors, capacitors, and other various devices This includes elements that have functions such as:

[0025] Generally, an "SOI substrate" is a substrate with a silicon semiconductor layer on an insulating surface. However, in this specification and the like, a semiconductor layer made of a material other than silicon is provided on an insulating surface. In other words, the semiconductor that "SOI substrate" has is also used as a concept that includes the substrate with a structure in which The layer is not limited to a silicon semiconductor layer. Also, the substrate in the "SOI substrate" is a silicon Not only semiconductor substrates such as silicon wafers, but also glass substrates, quartz substrates, sapphire substrates, and metal substrates In other words, it includes a conductive substrate with an insulating surface and a semiconductor substrate on an insulator substrate. The term "SOI substrate" broadly includes those having a layer made of a silicon material. In this document, "semiconductor substrate" does not only refer to a substrate made of semiconductor material, but also to a substrate made of semiconductor material. In other words, in this specification, the term "SOI substrate" is also used broadly. "Semiconductor substrate" is included in the category.

[0026] In this specification and the like, a material other than an oxide semiconductor refers to a semiconductor material other than an oxide semiconductor. Any semiconductor material may be used. For example, silicon, germanium, silicon Silicon germanium, silicon carbide, gallium arsenide, etc. Other semiconductor materials include organic semiconductor materials. It should be noted that the materials constituting the semiconductor device etc. are not particularly specified. In this case, either an oxide semiconductor material or a semiconductor material other than an oxide semiconductor may be used. . [Effects of the Invention]

[0027] In one embodiment of the present invention, a transistor including a material other than an oxide semiconductor is provided in a lower portion, and A semiconductor device including a transistor including an oxide semiconductor is provided.

[0028] Since a transistor using an oxide semiconductor has an extremely small off-state current, It is possible to retain the memory contents for a much longer period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, power consumption can be reduced sufficiently. , it is possible to retain the stored contents for a long period of time.

[0029] Furthermore, high voltage is not required to write information, and there is no problem of element degradation. Unlike nonvolatile memory, there is no need to inject and extract electrons from the floating gate. There is absolutely no deterioration, such as deterioration of the gate insulating layer. The semiconductor device does not have the limitation on the number of times it can be rewritten, which is a problem with conventional nonvolatile memory. Furthermore, depending on the on / off state of the transistor, Since information is written, high-speed operation can be easily achieved. Another advantage is that no action is required to

[0030] In addition, transistors using materials other than oxide semiconductors are called transistors using oxide semiconductors. Compared to conventional memory controllers, it is possible to operate at higher speeds, so by using this, it is possible to read and write the stored contents. It is possible to perform reading at high speed.

[0031] In this way, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor, a semiconductor device with unprecedented features can be realized. It is possible. [Brief explanation of the drawings]

[0032] [Figure 1] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Figure 2] 1A and 1B are a cross-sectional view and a plan view illustrating a semiconductor device. [Figure 3] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 4] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 5] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 6] FIG. 10 is a cross-sectional view of a transistor including an oxide semiconductor. [Figure 7] Energy band diagram (schematic diagram) at the A-A' cross section in Figure 6. [Figure 8] (A) shows the state when a positive voltage (VG>0) is applied to the gate (GE1), and (B) shows the state when a negative voltage (VG<0) is applied to the gate (GE1). [Figure 9] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). [Figure 10] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 11] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 12] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 13] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 14]FIG. 1 is a diagram illustrating a memory cell. [Figure 15] FIG. 10 is a diagram for explaining a writing circuit. [Figure 16] FIG. 2 is a diagram for explaining a read circuit. [Figure 17] FIG. [Figure 18] FIG. [Figure 19] FIG. 10 is a flowchart illustrating the operation. [Figure 20] 10A and 10B are diagrams showing an example of a state after data is written when no correction is performed and an example of a state after data is written when correction is performed. [Figure 21] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 22] FIG. [Figure 23] A graph showing the relationship between Vg and (1 / C)2. [Figure 24] 1A and 1B are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0033] An example of an embodiment of the present invention will be described below with reference to the drawings. and the present invention is not limited to the above description, and may be modified in various forms and forms without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention is not to be construed as being limited to the description of the embodiment shown in the accompanying drawings.

[0034] In addition, the position, size, range, etc. of each component shown in the drawings etc. are for ease of understanding. Therefore, the actual position, size, range, etc. may not necessarily be represented in the drawings, etc. The present invention is not limited to the position, size, range, etc. disclosed in the above.

[0035] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid confusion and are not intended to limit the number.

[0036] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described. This will be described with reference to FIGS. 1 to 13, 22 and 23.

[0037] <Circuit configuration of semiconductor device> In the semiconductor device shown in FIG. 1A, the gate electrode of the transistor 160 and the The first electrode 62 is electrically connected to either the source electrode or the drain electrode of the first The wiring (1st Line: also called source line) and the source electrode of transistor 160 , electrically connected to the second wiring (also called the bit line) and the transistor. The drain electrode of the capacitor 160 is electrically connected to the third wiring (3rd Line (also called the first signal line) and the source electrode or drain electrode of the transistor 162 The other of the four lines is electrically connected to the fourth line (also called the second signal line). and the gate electrode of the transistor 162 are electrically connected to each other.

[0038] The transistor 160 using a material other than an oxide semiconductor is a transistor using an oxide semiconductor. Compared to conventional memory controllers, it is possible to operate at higher speeds, so by using this, it is possible to read and write the stored contents. Furthermore, the transistor 1 using an oxide semiconductor can be The transistor 62 has a feature that the off-state current is extremely small. By turning off the transistor 2, the potential of the gate electrode of the transistor 160 is kept low for an extremely long time. It is possible to hold it upright.

[0039] The source or drain electrode of transistor 162 is connected to the gate electrode of transistor 160. By electrically connecting the floating gate electrode to the electrode, a nonvolatile memory element can be formed. The floating gate of a gate-type transistor functions in the same way as the floating gate of a gate-type transistor. , the source electrode or drain electrode of the transistor 162 and the gate electrode of the transistor 160 The part where the electrodes are electrically connected is called the floating gate part FG. The gate part FG is buried in an insulating material and can therefore hold a charge. That is, transistor 162 is made of a silicon semiconductor, as compared to transistor 160. , because the off-current is less than 1 / 100,000, the charge stored in the floating gate FG The loss due to leakage of transistor 162 can be ignored.

[0040] Such a configuration has been pointed out in the conventional floating gate type transistor. This avoids the problem of deterioration of the gate insulating film (tunnel insulating film). The gate insulating film is deteriorated by the tunnel current generated when electrons are injected into the floating gate. Therefore, in the semiconductor device shown in FIG. This effectively ignores the limit on the number of writes.

[0041] In the semiconductor device shown in FIG. 1B, the gate electrode of the transistor 160 and the One of the source electrode or the drain electrode of the capacitor 62 and one of the electrodes of the capacitor 164 are electrically connected. The first wiring and the source electrode of the transistor 160 are electrically connected. The second wiring and the drain electrode of the transistor 160 are electrically connected to each other. The third wiring and the other wirings, such as the source electrode or the drain electrode of the transistor 162, are connected to each other. The fourth wiring and the gate electrode of the transistor 162 are electrically connected to each other. The fifth wiring and the other electrode of the capacitor 164 are electrically connected to each other. is connected.

[0042] That is, the semiconductor device shown in FIG. 1B is the same as the semiconductor device shown in FIG. 1A except that a capacitor element 16 4 is added. As a result, in the semiconductor device shown in FIG. 1(B), In addition to the effects obtained in the semiconductor device shown in FIG. 1, the effect of improving the charge retention characteristics can be obtained. do.

[0043] Furthermore, if the capacitance value of the capacitive element 164 is C1 and the gate capacitance of the transistor 160 is C2, It is preferable that C1>C2. By making C1>C2, the fifth wiring can be used. When controlling the potential of the gate electrode of the transistor 160, the potential applied to the fifth wiring is large. Therefore, depending on the read method, the read voltage can be reduced. The following effect is obtained.

[0044] In the semiconductor device shown in FIG. 1C, the gate electrode of the transistor 160 and the One of the source electrode or the drain electrode of the capacitor 66 and one of the electrodes of the capacitor 164 are electrically connected. The first wiring and the source electrode of the transistor 160 are electrically connected. The second wiring and the drain electrode of the transistor 160 are electrically connected to each other. The third wiring and the other of the source electrode and the drain electrode of the transistor 166 are connected to each other. are electrically connected to the fourth wiring and the first gate electrode of the transistor 166. The fifth wiring and the other electrode of the capacitor 164 are electrically connected to each other. The sixth wiring and the second gate electrode of the transistor 166 are electrically connected. The sixth wiring is connected to the fourth wiring by applying a different potential to the sixth wiring. It may be configured to control it.

[0045] That is, the semiconductor device shown in FIG. 1C has a structure similar to that of the semiconductor device shown in FIG. 62 is replaced with a transistor 166 having a second gate electrode. Therefore, in the semiconductor device shown in FIG. 1C, the same characteristics as those obtained in the semiconductor device shown in FIG. In addition to this effect, the electrical characteristics (e.g., threshold voltage) of the transistor 166 can be easily adjusted. For example, applying a negative potential to the sixth wiring 166 can be easily made normally off.

[0046] In the semiconductor device shown in FIG. 1D, the gate electrode of the transistor 160 and the One of the source electrode or the drain electrode of the capacitor 66 and one of the electrodes of the capacitor 164 are electrically connected. The first wiring and the source electrode of the transistor 160 are electrically connected. The second wiring and the drain electrode of the transistor 160 are electrically connected to each other. The third wiring and the other of the source electrode and the drain electrode of the transistor 166 are connected to each other. are electrically connected to the fourth wiring and the first gate electrode of the transistor 166. The fifth wiring and the other electrode of the capacitor 164 are electrically connected to each other. The first gate electrode of the transistor 166 and the second gate electrode of the transistor 166 are electrically connected to each other. It is electrically connected to the gate electrode.

[0047] That is, the semiconductor device shown in FIG. 1D has the same structure as the semiconductor device shown in FIG. 1C except for the sixth wiring. The potential of the first wiring is equal to the potential of the fourth wiring. In addition to the effects obtained in the semiconductor device shown in FIG. The effect is an increase in the amount of current 66.

[0048] In the semiconductor device shown in FIG. 1, the potential of the gate electrode of the transistor 160 can be maintained. By taking advantage of this feature, it is possible to write, store, and read information as follows: The following description will be based on the configuration shown in FIG. 1(A), but the same applies to other configurations. do.

[0049] First, writing and holding of information will be explained. First, the potential of the fourth wiring is set to The potential is set to turn on the transistor 162, thereby turning on the transistor 162. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 160 (write After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off. By turning off the transistor 162, the gate electrode of the transistor 160 The potential is maintained (retention).

[0050] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 For example, if the potential of the gate electrode of transistor 160 is If the potential is such that the transistor 160 is turned on, the transistor 160 will remain on for a long time. The potential of the gate electrode of the transistor 160 is maintained for a certain period of time. If the potential is such that the transistor 160 is turned off, the transistor 160 will remain in the off state for a long time. is maintained over time.

[0051] Next, the reading of information will be described. As described above, when the transistor 160 is in the ON state, Alternatively, when the off state is maintained, a predetermined potential (low potential) is applied to the first wiring. When the transistor 160 is turned on, the potential of the second wiring changes depending on whether the transistor 160 is turned on or off. For example, when the transistor 160 is on, the potential of the first wiring is In response to this, the potential of the second wiring is reduced. In this case, the potential of the second wiring does not change.

[0052] In this way, in the state where the information is held, the potential of the second wiring is compared with a predetermined potential. This allows the information to be read out.

[0053] Next, the rewriting of information will be described. That is, the potential of the fourth wiring is held when the transistor 162 is turned on. This turns on the transistor 162. (the potential related to the new information) is applied to the gate electrode of the transistor 160. The potential of the fourth wiring is set to a potential at which the transistor 162 is turned off. By turning off 62, the new information is held.

[0054] In this way, the semiconductor device according to the disclosed invention can directly write information again. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need for an erase operation, and can suppress a decrease in operation speed due to the erase operation. That is, high-speed operation of the semiconductor device is realized.

[0055] The above explanation is for n-type transistors (n-channel transistors) in which electrons are the majority carriers. This is about using a large number of hole-capacitors instead of n-type transistors. It goes without saying that a p-type transistor can be used as a carrier.

[0056] <Plane and cross-sectional configurations of semiconductor device> 2 shows an example of the configuration of the semiconductor device shown in FIG. 2(A) shows a cross section of the semiconductor device, and FIG. 2(B) shows a plan view of the semiconductor device. These correspond to the cross sections taken along lines A1-A2 and B1-B2 in FIG. 2(B). The semiconductor device shown in FIG. 2B has a transistor using a material other than an oxide semiconductor in the lower part. The semiconductor device has a transistor 160 and a transistor 162 using an oxide semiconductor thereon. The transistor 160 and the transistor 162 are both n-type transistors. However, a p-type transistor may also be used. In particular, transistor 160 is In addition, the semiconductor device shown in FIGS. A similar configuration can be adopted.

[0057] The transistor 160 includes a channel forming region 11 provided in a substrate 100 including a semiconductor material. 6, and the impurity region 114 and the high concentration impurity region 115 provided so as to sandwich the channel forming region 116. The pure region 120 (collectively referred to as the impurity region) and the channel forming region 11 6, and a gate electrode provided on the gate insulating layer 108. 110 and a source or drain electrode 130a electrically connected to the impurity region 114. , and a source electrode or a drain electrode 130b.

[0058] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110. In addition, in the region of the substrate 100 that does not overlap with the sidewall insulating layer 118 in a cross-sectional view, a high A high concentration impurity region 120 is provided, and a metal compound region 124 is provided on the high concentration impurity region 120. In addition, an element isolation insulating layer 106 is formed on the substrate 100 so as to surround the transistor 160. The transistor 160 is covered with an interlayer insulating layer 126 and an interlayer insulating film. A source or drain electrode 130a, a source or drain electrode 130b, a The drain electrode 130b is formed through an opening formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. That is, the source electrode or the drain electrode is electrically connected to the metal compound region 124. The source or drain electrode 130a and the source or drain electrode 130b are formed in the metal compound region 124. The high concentration impurity region 120 and the impurity region 114 are electrically connected via the The gate electrode 110 is provided with a source or drain electrode 130a and a source or drain electrode 130b. An electrode 130c provided similarly to the drain electrode 130b is electrically connected to the drain electrode 130b.

[0059] The transistor 162 includes a gate electrode 136d provided on the interlayer insulating layer 128 and a gate A gate insulating layer 138 is provided on the electrode 136d, and a gate insulating layer 138 is provided on the gate insulating layer 138. an oxide semiconductor layer 140; and a metal oxide film provided on the oxide semiconductor layer 140. The source or drain electrode 142a is electrically connected to the source or drain electrode 142b. and an inner electrode 142b.

[0060] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136d, the source electrode or The electrode 136a is in contact with the drain electrode 130a, and the source or drain electrode 130b Electrode 136b is formed in contact with electrode 130c, and electrode 136c is formed in contact with electrode 130c. do.

[0061] In addition, a protective film is formed on the transistor 162 so as to be in contact with part of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode or a drain electrode. An opening is provided that reaches the source electrode 142a and the source or drain electrode 142b. Through the openings, the electrodes 150d and 150e are connected to the source and drain electrodes. The electrode 142a is formed in contact with the source electrode or the drain electrode 142b. As well as electrodes 150d and 150e, gate insulating layer 138, protective insulating layer 144, interlayer insulating layer The electrodes 136a, 136b, and 136c are in contact with each other through openings provided in the layer 146. Electrodes 150a, 150b, and 150c are formed.

[0062] Here, the oxide semiconductor layer 140 is highly purified by sufficiently removing impurities such as hydrogen. Specifically, the hydrogen concentration of the oxide semiconductor layer 140 is preferably 5×10 19 atoms / cm 3Below 5×10 18 atoms / cm 3 Below, more hope Preferably 5 x 10 17 atoms / cm 3 In addition, it must contain sufficient oxygen. It is desirable that defects caused by oxygen deficiency are reduced by the hydrogen concentration. The oxide semiconductor layer 14 is highly purified by reducing the amount of oxygen to 0.5% and reducing defects caused by oxygen deficiency. 0, the carrier concentration is 1×10 12 / cm 3 Less than 1×10 11 / cm 3 In this way, the use of an i-type or substantially i-type oxide semiconductor Therefore, the transistor 162 can have excellent off-state current characteristics. When the input voltage Vd is +1V or +10V, the gate voltage Vg is -5V to -2 In the 0V range, the off-state current is 1×10 -13 A or less. In this way, the hydrogen concentration is sufficient. The oxide semiconductor layer 140 is highly purified by reducing the amount of oxygen to 0.5% and has fewer defects due to oxygen deficiency. By applying the above, the off-state current of the transistor 162 can be reduced. The hydrogen concentration in the oxide semiconductor layer 140 can be determined by the secondary electron Secondary Ion Mass Spectros (SIMS) The measurements were taken using a computer copy.

[0063] An insulating layer 152 is provided on the interlayer insulating layer 146, and a buried insulating layer 152 is provided on the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so that the electrodes are embedded in the Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150a. b, electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 54d is in contact with electrode 150e.

[0064] That is, in the semiconductor device shown in FIG. 2, the gate electrode 110 of the transistor 160 and the The source electrode or drain electrode 142a of the transistor 162 is connected to the electrode 130c, the electrode 1 36c, electrode 150c, electrode 154c and electrode 150d. do.

[0065] <Method for manufacturing semiconductor device> Next, an example of a method for manufacturing the semiconductor device will be described. The method for fabricating the transistor 160 will be explained with reference to FIG. A method for manufacturing the capacitor 162 will be described with reference to FIGS.

[0066] <Method for manufacturing the lower transistor> First, a substrate 100 containing a semiconductor material is prepared (see FIG. 3(A)). The plate 100 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be used. Here, the substrate 100 containing a semiconductor material is a single crystal silicon substrate. An example will be shown below. Generally, an "SOI substrate" is a substrate in which silicon semiconductor is formed on an insulating surface. It refers to a substrate having a structure in which a conductor layer is provided, but in this specification, it refers to a substrate having a silicon layer on an insulating surface. The concept also includes substrates having semiconductor layers made of materials other than those mentioned above. The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The substrate is configured such that a semiconductor layer is provided on an insulating substrate such as a glass substrate via an insulating layer. This includes:

[0067] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 3(A)). The protective layer 102 may be made of, for example, silicon oxide or silicon nitride. An insulating layer made of silicon nitride oxide or the like can be used. In order to control the threshold voltage of the transistor, impurities that give n-type conductivity are used. The substrate 100 may be doped with an impurity element that imparts p-type conductivity or a metal element that imparts p-type conductivity. In the case of silicon, impurities that give n-type conductivity include phosphorus and arsenic. In addition, impurities that impart p-type conductivity include, for example, boron and aluminum. Sodium, gallium, etc. can be used.

[0068] Next, etching is performed using the protective layer 102 as a mask, and the The part of the substrate 100 in the area where the semiconductor substrate 100 is not exposed is removed. The conductive region 104 is formed (see FIG. 3(B)). It is preferable to use an etching gas or an etchant, but wet etching may also be used. The etching liquid can be appropriately selected depending on the material to be etched.

[0069] Next, an insulating layer is formed so as to cover the semiconductor region 104, and the region overlapping the semiconductor region 104 is The insulating layer is selectively removed to form an element isolation insulating layer 106 (see FIG. 3(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, etc. The insulating layer can be removed by polishing such as CMP or etching. After the semiconductor region 104 is formed or after the element isolation insulating film is formed, After the layer 106 is formed, the protective layer 102 is removed.

[0070] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0071] The insulating layer will later become the gate insulating layer and is obtained using a CVD method, sputtering method, etc. Silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide It is preferable to use a single layer or multilayer structure of a film containing aluminum, tantalum oxide, etc. The surface of the semiconductor region 104 is oxidized or nitrided by plasma treatment or thermal oxidation treatment. The insulating layer may be formed by the high density plasma treatment. Using a mixture of rare gases such as Xe and oxygen, nitrogen oxide, ammonia, nitrogen, and hydrogen The thickness of the insulating layer is not particularly limited, but may be, for example, 1 nm or more and 10 nm or less. It can be 0 nm or less.

[0072] The layer containing the conductive material is made of a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Also, the insulating film can be formed using a semiconductor material such as polycrystalline silicon containing a conductive material. The method for forming the conductive material is not particularly limited, and examples thereof include vapor deposition, C Various film formation methods such as VD method, sputtering method, and spin coating method can be used. In this embodiment mode, the layer containing a conductive material is formed using a metal material. The following information will be provided.

[0073] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108. Then, the gate electrode 110 is formed (see FIG. 3(C)).

[0074] Next, an insulating layer 112 is formed to cover the gate electrode 110 (see FIG. 3(C)). Phosphorus (P) or arsenic (As) is added to the conductive region 104 to form a shallow junction with the substrate 100. In this case, an n-type transistor is formed. However, when forming a p-type transistor, Impurity elements such as boron (B) and aluminum (Al) can be added. By forming the region 114, a channel-forming region is formed below the gate insulating layer 108 in the semiconductor region 104. A region 116 is formed (see FIG. 3C). Here, the concentration of the added impurity is set appropriately. By doing so, the short channel effect can be suppressed. In this case, it is desirable to increase the concentration of impurities after forming the insulating layer 112. The process of forming the region 114 is adopted, but after forming the impurity region 114, the insulating layer 1 This may be a process for forming 12.

[0075] Next, a sidewall insulating layer 118 is formed (see FIG. 3(D)). The layer 118 is formed by forming an insulating layer to cover the insulating layer 112 and then applying a highly anisotropic By applying a simple etching process, it can be formed in a self-aligned manner. Then, the insulating layer 112 is partially etched to expose the upper surface of the gate electrode 110 and the impurity region 1 It is advisable to expose the top surface of 14.

[0076] Next, a layer is formed so as to cover the gate electrode 110, the impurity region 114, the sidewall insulating layer 118, etc. An insulating layer is formed on the impurity region 114. Then, phosphorus ( By adding ions such as P and arsenic (As), a high concentration impurity region 120 is formed (see FIG. 3(E)). After that, the insulating layer is removed, and the gate electrode 110, the sidewall insulating layer 118, A metal layer 122 is formed so as to cover the high concentration impurity region 120 and the like (see FIG. 3(E)). The metal layer 122 can be formed by various film forming methods such as vacuum deposition, sputtering, and spin coating. The metal layer 122 can be formed using the semiconductor material that constitutes the semiconductor region 104. It is desirable to form the electrode using a metal material that reacts with the electrode to form a low-resistance metal compound. Such metal materials include, for example, titanium, tantalum, tungsten, nickel, and cobalt. Examples include platinum and platinum.

[0077] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A metal compound region 124 is formed in contact with the high concentration impurity region 120 (see FIG. 3(F)). When polycrystalline silicon or the like is used as the gate electrode 110, the gate electrode 110 A metal compound region is also formed in the portion in contact with the metal layer 122.

[0078] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize a very short time of heat treatment. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in a region where the conductivity is sufficiently increased. This can sufficiently reduce the electrical resistance and improve the device characteristics. After forming region 124, metal layer 122 is removed.

[0079] Next, an interlayer insulating layer 126 and an interlayer insulating layer 127 are formed to cover the respective components formed by the above-described steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by oxidation. Silicon, silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, titanium oxide The insulating layer can be formed using a material containing an inorganic insulating material such as palladium. It is also possible to form the insulating layer using an organic insulating material such as acrylic. Although the structure is a two-layer structure of an edge layer 126 and an interlayer insulating layer 128, the structure of the interlayer insulating layer is not limited to this. After the interlayer insulating layer 128 is formed, the surface is not subjected to a CMP or etching process. Therefore, it is desirable to flatten it.

[0080] Thereafter, an opening is formed in the interlayer insulating layer so as to reach the metal compound region 124. The source or drain electrode 130a and the source or drain electrode 130b are The source or drain electrode 130a and the source or drain electrode 130b are formed (see FIG. 3(H)). The drain electrode 130b is formed by, for example, using a PVD method or a CVD method in the region including the opening. After forming the conductive layer, a part of the conductive layer is removed by etching or CMP. It can be formed by removing the

[0081] In addition, a part of the conductive layer is removed to form the source electrode or drain electrode 130a and the source electrode Alternatively, when forming the drain electrode 130b, the surface thereof is processed to be flat. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When a tungsten film is formed to fill the opening, the inclusions are removed by the subsequent CMP. It removes the necessary tungsten film, titanium film, titanium nitride film, etc., and also improves the flatness of the surface. In this way, the source electrode or drain electrode 130a, By planarizing the surface including the source or drain electrode 130b, it is possible to This makes it possible to form good electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0082] Here, the source electrode or drain electrode 130 in contact with the metal compound region 124 Although only the gate electrode 130a and the source electrode or the drain electrode 130b are shown, The electrode in contact with the port electrode 110 (for example, the electrode 130c in FIG. 2) is also formed. The source or drain electrode 130a, the source or drain electrode There are no particular limitations on the material that can be used for the electrode 130b, and various conductive materials can be used. For example, molybdenum, titanium, chromium, tantalum, tungsten, Conductive materials such as aluminum, copper, neodymium, and scandium can be used.

[0083] In this manner, the transistor 160 is formed using the substrate 100 containing a semiconductor material. After the above steps, electrodes, wiring, insulating layers, etc. may be further formed. In addition, by adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, Therefore, a highly integrated semiconductor device can be provided.

[0084] <How to make the upper transistor> Next, referring to FIGS. 4 and 5, a process for forming a transistor 162 on the interlayer insulating layer 128 will be described. 4 and 5 show various electrodes and transistors on the interlayer insulating layer 128. Since the figure shows the manufacturing process of the transistor 162, the The transistor 160 and other components that correspond to it are omitted.

[0085] First, an interlayer insulating layer 128, a source electrode or drain electrode 130a, and a source electrode or drain electrode 130b are formed. An insulating layer 132 is formed on the drain electrode 130b and the electrode 130c (see FIG. 4(A)). The edge layer 132 can be formed by using a PVD method, a CVD method, or the like. silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The insulating film 10 can be formed using a material containing an inorganic insulating material such as silica.

[0086] Next, the source or drain electrode 130a, the source or drain electrode 130b, and the insulating layer 132 are Openings are formed that reach the drain electrode 130b and the electrode 130c. An opening is also formed in the region where the gate electrode 136d is to be formed. A conductive layer 134 is formed to fill the opening (see FIG. 4B). The mask can be formed by a method such as etching using a photomask. It can be formed by exposure or other methods. Wet etching is also used. Either etching or dry etching may be used, but from the viewpoint of fine processing, dry etching is preferred. The conductive layer 134 is preferably formed by a deposition method such as PVD or CVD. The conductive layer 134 can be formed by a film method. , molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium Conductive materials such as ZnO, ZnS, and scandium, as well as alloys and compounds thereof (e.g., nitrides), are examples of such materials. can be done.

[0087] More specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method is The outer electrode (here, the source electrode or the drain electrode 130a, the source electrode or the drain electrode The oxide film at the interface with the lower electrode (electrode 130b, electrode 130c, etc.) is reduced to reduce the contact resistance with the lower electrode. The titanium nitride film formed afterwards also serves to reduce the diffusion of conductive materials. It also has a barrier function that suppresses the formation of a barrier film made of titanium or titanium nitride. Afterwards, a copper film may be formed by plating.

[0088] After the conductive layer 134 is formed, the conductive layer 13 is removed by etching, CMP, or other methods. 4 is removed to expose the insulating layer 132, and the electrodes 136a, 136b, and 13 6c, a gate electrode 136d is formed (see FIG. 4(C)). The electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d are formed by removing the portions. When forming the insulating layer 132, it is desirable to process it so that the surface is flat. , the surfaces of the electrodes 136a, 136b, 136c, and gate electrode 136d are planarized. This allows for the formation of good electrodes, wiring, insulating layers, semiconductor layers, etc. in subsequent processes. This makes it possible to:

[0089] Next, the insulating layer 132, the electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d The gate insulating layer 138 is formed to cover the gate insulating layer 138 (see FIG. 4(D)). The gate insulating layer can be formed by using a CVD method, a sputtering method, or the like. 138 is silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, oxide It is preferable to form the gate insulating film so as to contain hafnium, tantalum oxide, etc. The layer 138 may have a single layer structure or a multilayer structure. Silicon oxynitride was produced by plasma CVD using silane (SiH4), oxygen, and nitrogen. The thickness of the gate insulating layer 138 is not particularly limited. However, it can be, for example, 10 nm or more and 500 nm or less. For example, a first gate insulating layer having a film thickness of 50 nm or more and 200 nm or less and a first gate insulating layer It is preferable to laminate a second gate insulating layer having a thickness of 5 nm to 300 nm on the layer.

[0090] Note that an oxide semiconductor (high-temperature oxide semiconductor) that has been made i-type or substantially i-type by removing impurities is Since the purified oxide semiconductor is extremely sensitive to the interface states and the interface charges, When such an oxide semiconductor is used for the oxide semiconductor layer, the interface with the gate insulating layer is important. That is, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer has a high-quality oxide semiconductor layer. Quality will be required.

[0091] For example, the high density plasma CVD method using microwaves (2.45GHz) produces dense and high dielectric strength materials. This is advantageous in that a high quality gate insulating layer 138 can be formed. The close contact between the conductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. Because it can be made into a good one.

[0092] Of course, if it can form a good insulating layer as a gate insulating layer, highly purified Even when an oxide semiconductor layer is used, other methods such as sputtering and plasma CVD are used. In addition, the film quality and the oxide semiconductor layer can be improved by heat treatment after the formation. Alternatively, an insulating layer may be applied to modify the interface properties of the gate insulating layer 138. The film quality as a gate insulating film is good, and the interface state density with the oxide semiconductor layer is reduced, resulting in a good interface. All that is required is to form something that can form a surface.

[0093] Furthermore, at 85°C, 2 × 10 6 V / cm, 12-hour gate bias thermal stress test (B In the T test, when impurities are added to an oxide semiconductor, the impurities and the oxide semiconductor The bond with the main component of is broken by a strong electric field (B: bias) and high temperature (T: temperature), and The dangling bonds induce a drift in the threshold voltage (Vth).

[0094] In response to this, impurities in the oxide semiconductor, especially hydrogen and water, are eliminated as much as possible, and the gate electrode is By improving the interface characteristics with the base insulating layer, a stable transistor is produced even during BT tests. It is possible to obtain data.

[0095] Next, an oxide semiconductor layer is formed over the gate insulating layer 138 and etched using a mask. The oxide semiconductor layer is processed by the above method to form an island-shaped oxide semiconductor layer 140. (See FIG. 4(E)).

[0096] The oxide semiconductor layer includes In-Ga-Zn-O, In-Sn-Zn-O, and In-A l-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn -O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn- It is preferable to use an O-based or Zn—O-based oxide semiconductor layer, especially an amorphous oxide semiconductor layer. In this embodiment, an In—Ga—Zn—O-based oxide semiconductor is formed as the oxide semiconductor layer. An amorphous oxide semiconductor layer is formed by a sputtering method using a target for sputtering. Note that adding silicon to an amorphous oxide semiconductor layer can suppress crystallization. Therefore, for example, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used. An oxide semiconductor layer may be formed using the above-mentioned method.

[0097] Examples of targets for forming an oxide semiconductor layer by sputtering include oxide A target of a metal oxide containing zinc as the main component can be used. and Zn-containing oxide semiconductor film deposition target (composition ratio: In2O3:Ga2O 3:ZnO=1:1:1[mol number ratio], In:Ga:Zn=1:1:0.5[mol number In addition, an oxide semiconductor material containing In, Ga, and Zn can be used. The film target was In2O3:Ga2O3:ZnO=1:1:2 [molar ratio]. Or a tantalum having a composition ratio of In2O3:Ga2O3:ZnO=1:1:4 [molar ratio] The filling rate of the oxide semiconductor film forming target is 90% or more. 0% or less, preferably 95% or more (for example, 99.9%). By using a target for bulk film formation, a dense oxide semiconductor layer is formed.

[0098] The oxide semiconductor layer is formed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or Alternatively, it is preferable to use a mixed atmosphere of rare gas (typically argon) and oxygen. In practice, the concentration of impurities such as hydrogen, water, hydroxyl groups, or hydrides is approximately several ppm. It is preferable to use a high purity gas in which the concentration has been reduced to a level of preferably about several ppb.

[0099] When forming the oxide semiconductor layer, the substrate is held in a treatment chamber kept in a reduced pressure state. The temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating, the impurity concentration in the oxide semiconductor layer can be reduced. Damage caused by sputtering can also be reduced. The residual moisture in the metal oxide layer is removed, and a sputtering gas from which hydrogen and water have been removed is introduced. The oxide semiconductor layer is formed using a target of It is preferable to use an adsorption type vacuum pump. For example, a cryopump or an ion pump A titanium sublimation pump can be used. A cryopump with a cold trap may be used. The deposition chamber is filled with, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (preferably Since the oxide semiconductor formed in the film formation chamber is exhausted, The concentration of impurities contained in the layer can be reduced.

[0100] The formation conditions are, for example, a distance of 100 mm between the substrate and the target, a pressure of 0.6 Pa, DC power 0.5kW, oxygen atmosphere (oxygen flow rate 100%), The following conditions can be applied. When a pulsed direct current (DC) power supply is used, film formation can be performed. This reduces the amount of powdery material (also called particles or dust) that is generated at times, and the film thickness distribution is uniform. The thickness of the oxide semiconductor layer is preferably 2 nm or more and 200 nm or less, more preferably 5 nm or less. The thickness is from 100 nm to 30 nm. The appropriate thickness varies depending on the oxide semiconductor material used. Therefore, the thickness may be appropriately selected depending on the material used.

[0101] Before forming the oxide semiconductor layer by sputtering, argon gas was introduced to Reverse sputtering is performed to generate a smear, and dust adhering to the surface of the gate insulating layer 138 is removed. Here, the reverse sputtering is a method of removing the sputtering Instead of bombarding the target with ions, the treatment surface is bombarded with ions. The method of bombarding the treated surface with ions is as follows: A high frequency voltage is applied to the surface to be treated in an argon atmosphere to generate plasma near the substrate. In addition, nitrogen atmosphere, helium atmosphere, oxygen atmosphere, etc. can be used instead of argon atmosphere. An atmosphere or the like may also be used.

[0102] The oxide semiconductor layer can be etched by either dry etching or wet etching. Of course, both can be used in combination. To enable matching, etching conditions (etching gas, etching solution, etc.) are set according to the material. The etching time, temperature, etc. are set appropriately.

[0103] The etching gas used in dry etching is, for example, a gas containing chlorine (chlorine-based gas, For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride ( CCl4) and other gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride). Fluorine (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (C HF3), hydrogen bromide (HBr), oxygen (O2), and helium (He) in these gases Alternatively, a gas containing a rare gas such as argon (Ar) may be used.

[0104] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A plasma-coupled plasma etching method can be used. As shown in the figure, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) The amount of power, the temperature of the electrode on the substrate, etc. are set appropriately.

[0105] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide (31% by weight hydrogen peroxide: 28% by weight ammonia water: water = 5:2:2) In addition, etching solutions such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. It's fine.

[0106] Next, the oxide semiconductor layer is preferably subjected to first heat treatment. The temperature of the first heat treatment is The temperature is set to 300°C or higher and 750°C or lower, preferably 400°C or higher and lower than the strain point of the substrate. For example, The substrate is placed in an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heated in a nitrogen atmosphere. Heat treatment is performed at 450° C. in air for 1 hour. Avoid contact to prevent recontamination with water or hydrogen.

[0107] The heat treatment device is not limited to an electric furnace, and may be any device that uses heat conduction from a medium such as heated gas, or It may also be a device that heats the object to be treated by thermal radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure water A device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. A gas is used.

[0108] For example, in the first heat treatment, the substrate is immersed in an inert gas heated to a high temperature of 650°C to 700°C. After heating for several minutes, the substrate is taken out of the inert gas (GRTA) treatment. GRTA treatment allows high-temperature heat treatment in a short time. Because it is a heat treatment, it can be applied even at temperatures exceeding the distortion point of the substrate.

[0109] The first heat treatment is performed in a gas atmosphere containing nitrogen or a rare gas (helium, neon, argon, etc.) as the main component. It is desirable to carry out the process in an atmosphere that does not contain water, hydrogen, etc. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. The impurity concentration is 1 ppm or less, preferably 0.1 ppm or less.

[0110] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized. For example, the crystallinity may be 90% or more, or 80% or more. % or more of a microcrystalline oxide semiconductor layer. Depending on the material of the oxide semiconductor layer, it may become an amorphous oxide semiconductor layer that does not contain crystalline components. There are also cases where this is the case.

[0111] In addition, crystals (grain size 1 nm or more) are formed on the amorphous oxide semiconductor (for example, on the surface of the oxide semiconductor layer). In the case where an oxide semiconductor layer having a thickness of 20 nm or less (typically 2 nm or more and 4 nm or less) is formed, There are also cases where this is the case.

[0112] In addition, by providing a crystalline layer on the amorphous surface, the electrical characteristics of the oxide semiconductor layer can be changed. For example, an In-Ga-Zn-O oxide semiconductor film formation target can be used. When forming an oxide semiconductor layer using In2Ga2ZnO7 The electrical characteristics of the oxide semiconductor layer are changed by forming a crystal part in which the crystal grains are oriented. It is possible.

[0113] More specifically, for example, the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer. By orienting the oxide semiconductor layer in this direction, the conductivity in the direction parallel to the surface of the oxide semiconductor layer is improved. This can improve the insulating properties in the direction perpendicular to the surface of the oxide semiconductor layer. Such a crystalline portion has the function of preventing impurities such as water and hydrogen from penetrating into the oxide semiconductor layer. Has.

[0114] The oxide semiconductor layer having the above-described crystal portion is formed by GRTA treatment. It can be formed by surface heating. In addition, the Zn content is higher than the In or Ga content. By using a smaller sputtering target, it is possible to form the film more suitably.

[0115] The first heat treatment on the oxide semiconductor layer 140 is performed to process the oxide semiconductor layer 140 into an island-shaped oxide semiconductor layer 140. In this case, the first heat treatment is performed on the oxide semiconductor layer. The substrate is then removed and subjected to a photolithography process.

[0116] The first heat treatment has the effect of dehydrating and dehydrogenating the oxide semiconductor layer 140. Therefore, it can also be called dehydration treatment, dehydrogenation treatment, etc. The hydrogenation treatment is carried out after forming the oxide semiconductor layer, by forming a source electrode or a drain electrode on the oxide semiconductor layer 140. After laminating the source electrode and drain electrode, a protective insulating layer is formed on the source electrode or drain electrode. In addition, such dehydration treatment, dehydration The oxidation treatment may be carried out not only once but also multiple times.

[0117] Next, a source electrode or drain electrode 142a, The source or drain electrode 142b is formed (see FIG. 4(F)). The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1 After forming a conductive layer to cover 40, the conductive layer is selectively etched. It can be formed.

[0118] The conductive layer is formed using PVD methods such as sputtering, or CVD methods such as plasma CVD. The conductive layer can be formed using a material such as aluminum, chromium, copper, Elements selected from tantalum, titanium, molybdenum, and tungsten, or the above elements Alloys containing manganese, magnesium, zirconium, beryllium, etc. can be used. Alternatively, one or more materials selected from the group consisting of aluminum and thorium may be used. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Alternatively, a material containing a single element selected from the group consisting of aluminum and a combination of multiple elements may be used. It may have a single layer structure or a laminated structure of two or more layers. Single-layer aluminum film structure, two-layer aluminum film with titanium film laminated on top, titanium Examples of such a structure include a three-layer structure in which a film, an aluminum film, and a titanium film are laminated.

[0119] The conductive layer may be formed using a conductive metal oxide. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), Indium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), oxide Indium-zinc oxide alloy (In2O3-ZnO), or these metal oxide materials It is possible to use a material containing silicon or silicon oxide.

[0120] Here, the exposure to light when forming the mask used for etching is ultraviolet light, KrF laser light, or ArF Preferably, a laser beam is used.

[0121] The channel length (L) of the transistor is the distance from the bottom end of the source or drain electrode 142a to the , is determined by the distance between the lower end of the source electrode or drain electrode 142b. When exposure is performed with a channel length (L) of less than 25 nm, the channel length is extremely small, ranging from several nm to several tens of nm. Extreme ultraviolet light with extremely short wavelengths is used to create a mask-shaped Extreme ultraviolet light exposure provides high resolution and a large depth of focus. The channel length (L) of the formed transistor is set to 10 nm or more and 1000 nm or less. Furthermore, the off-state current is extremely small, This avoids a large power consumption.

[0122] When etching the conductive layer, the oxide semiconductor layer 140 is not removed. The materials and etching conditions are adjusted appropriately. In this step, a part of the oxide semiconductor layer 140 is etched to form a groove (a recess ) may be formed as an oxide semiconductor layer.

[0123] In addition, between the oxide semiconductor layer 140 and the source electrode or the drain electrode 142a, An oxide conductive layer is formed between the conductive layer 140 and the source or drain electrode 142b. The oxide conductive layer and the source or drain electrode 142a or the source or drain electrode 142b may be The metal layer for forming the drain electrode 142b is formed continuously (continuous film formation). The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, it is possible to reduce the resistance of the source region or the drain region. This allows the transistor to operate at high speed.

[0124] In order to reduce the number of masks used and the number of processes, an exposure method is used in which the transmitted light has multiple intensities. A resist mask is formed using a multi-tone mask, which is a mask, and an etching process is performed using this. The resist mask formed using the multi-tone mask has a plurality of thicknesses. The shape becomes stepped, and the shape can be further deformed by ashing. It can be used for multiple etching processes to process different patterns. A multi-tone mask allows for resist masks that correspond to at least two different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding photomasks can be formed. The lithography process can also be eliminated, simplifying the process.

[0125] After the above process, plasma treatment using gas such as N2O, N2, or Ar may be performed. It is preferable that the plasma treatment is performed on the exposed surface of the oxide semiconductor layer. Adhered water and other substances are removed. In addition, gases containing oxygen, such as a mixture of oxygen and argon, In this case, oxygen is supplied to the oxide semiconductor layer, and plasma treatment using a gas is performed. It is possible to reduce defects caused by oxygen deficiency.

[0126] Next, the protective insulating layer 14 in contact with a part of the oxide semiconductor layer 140 is removed without being exposed to the air. 4 is formed (see Figure 4(G)).

[0127] The protective insulating layer 144 is formed by a method such as sputtering, which does not mix impurities such as water or hydrogen into the protective insulating layer 144. The thickness of the film should be at least 1 nm. The protective insulating layer 144 can be formed of a material such as silicon oxide, silicon nitride, or the like. Silicon oxynitride, silicon nitride oxide, etc. The structure may be a single layer structure, The substrate temperature when the protective insulating layer 144 is formed is equal to or higher than room temperature and equal to or higher than 300° C. The atmosphere is preferably a rare gas (typically argon) atmosphere or an oxygen atmosphere. Alternatively, a mixed atmosphere of a rare gas (typically argon) and oxygen is preferably used.

[0128] If hydrogen is contained in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer or the oxide semiconductor layer may be damaged by the hydrogen. Oxygen is extracted from the oxide semiconductor layer by the oxide semiconductor layer. Therefore, the protective insulating layer 1 may have a low resistance and a parasitic channel may be formed. It is important to avoid using hydrogen in the formation method so that 44 does not contain as much hydrogen as possible. is.

[0129] In addition, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. The compound semiconductor layer 140 and the protective insulating layer 144 are formed so as not to contain hydrogen, hydroxyl groups, or water. This is because.

[0130] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O) and other compounds containing hydrogen atoms are removed, The concentration of impurities contained in the layer 144 can be reduced.

[0131] The sputtering gas used when forming the protective insulating layer 144 is hydrogen, water, a hydroxyl group, or The concentration of impurities such as hydrides is reduced to a few ppm (preferably a few ppb). It is preferable to use high purity gases that have been removed.

[0132] Then, a second heat treatment (preferably 20 It is desirable to carry out the heating at a temperature of 0°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. The second heat treatment can reduce the variation in the electrical characteristics of the transistor. In this case, oxygen can be supplied to the oxide semiconductor layer.

[0133] In addition, a third heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be carried out by maintaining a constant heating temperature, or by heating from room temperature to 10 Repeat the heating process from 0°C to 200°C and then cooling it down to room temperature several times. This heat treatment may be carried out under reduced pressure before the formation of the protective insulating layer. Heat treatment under reduced pressure can shorten the heating time. This may be carried out instead of the second heat treatment, or may be carried out before or after the second heat treatment.

[0134] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 5(A)). The edge layer 146 can be formed by using a PVD method, a CVD method, or the like. silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The interlayer insulating layer 146 can be formed using a material containing an inorganic insulating material such as silica. After that, it is desirable to flatten the surface by a method such as CMP or etching. It's nice.

[0135] Next, the electrode 1 is formed on the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. 36a, electrode 136b, electrode 136c, source or drain electrode 142a, source An opening is formed so as to reach the electrode or drain electrode 142b, and a conductive layer is formed so as to be embedded in the opening. A conductive layer 148 is formed (see FIG. 5B). The opening is formed by etching using a mask or the like. The mask can be formed by a method such as exposure using a photomask. The etching can be wet etching or dry etching. However, from the viewpoint of fine processing, it is recommended to use dry etching. The conductive layer 148 is preferably formed by a film forming method such as a PVD method or a CVD method. Materials that can be used to form the conductive layer 148 include molybdenum, titanium, and the like. Tantalum, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. Examples include any conductive material, their alloys, and compounds (e.g., nitrides).

[0136] Specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then a CVD method is applied. After forming a thin titanium nitride film by this method, a tungsten film is formed so as to fill the opening. Here, the titanium film formed by the PVD method is Electrodes (here, electrode 136a, electrode 136b, electrode 136c, source electrode or drain electrode) The oxide film at the interface with the electrode 142a, the source electrode or the drain electrode 142b is reduced. It also functions to reduce the contact resistance with the external electrode. It has a barrier function that suppresses the diffusion of conductive materials. After forming the barrier film, a copper film may be formed by plating.

[0137] After the conductive layer 148 is formed, the conductive layer 148 is removed by etching, CMP, or other methods. A portion of the interlayer insulating layer 146 is removed to expose the electrodes 150a, 150b, and 150c. Electrode 150c, electrode 150d, and electrode 150e are formed (see FIG. 5(C)). 48 is removed to form electrodes 150a, 150b, 150c, 150d, and When forming 150e, it is desirable to process it so that the surface is flat. Next, an interlayer insulating layer 146, an electrode 150a, an electrode 150b, an electrode 150c, an electrode 150d, an electrode By flattening the surface of the electrode 150e, it is possible to obtain good electrodes, wiring, and insulation in the subsequent processes. It is possible to form a layer, a semiconductor layer, etc.

[0138] Furthermore, an insulating layer 152 is formed, and the electrodes 150a, 150b, and 150c are attached to the insulating layer 152. 50c, the electrode 150d, and the electrode 150e are formed, and the insulating layer 150 is embedded in the opening. After forming the conductive layer as shown above, a part of the conductive layer is removed by a method such as etching or CMP. , the insulating layer 152 is exposed, and the electrodes 154a, 154b, 154c, and 154 This step is the same as that for forming the electrodes 150a and the like. Therefore, I will omit the details.

[0139] When the transistor 162 is manufactured by the above method, the hydrogen concentration in the oxide semiconductor layer 140 is Degrees are 5 x 10 19 atoms / cm 3 and the off-current of the transistor 162 is is 1 x 10 -13 A or less. In this way, the hydrogen concentration is sufficiently reduced and the resulting product is highly purified. By using the oxide semiconductor layer 140 in which defects due to oxygen deficiency are reduced, excellent In addition, a transistor 162 having the above characteristics can be obtained. The transistor 160 includes a transistor using an oxide semiconductor, and the transistor 162 includes a transistor using an oxide semiconductor thereon. Therefore, a semiconductor device having excellent characteristics can be manufactured.

[0140] Below, we will explain the significance of purifying oxide semiconductors and making them intrinsic (i-type), The advantages of configuring a semiconductor device using this method will be briefly described below.

[0141] <Intrinsic oxide semiconductor> Many studies have been conducted on the physical properties of oxide semiconductors, but these studies have focused on the energy The present invention does not include the idea of ​​sufficiently reducing the localized level itself in the gap. In this case, water and hydrogen, which can cause localized levels, are removed from the oxide semiconductor to produce a highly pure This is because the oxide semiconductor is made intrinsic (i-type) by This is based on the idea of ​​sufficiently reducing the localized level itself. This makes it possible to manufacture extremely excellent industrial products.

[0142] When removing hydrogen and water, oxygen may also be removed at the same time. Therefore, oxygen is supplied to the dangling bonds of the metal that are generated due to oxygen deficiency, and the localization caused by oxygen vacancies By reducing the intrinsic level, oxide semiconductors can be further purified and made intrinsic (i-type). For example, an oxide film containing excess oxygen is formed in close proximity to the channel forming region, and By heat treatment at a temperature of 00 to 400°C, typically around 250°C, the acid By supplying oxygen from the oxide film, it is possible to reduce the localized level due to oxygen defects. During the first to third heat treatments, the inert gas may be replaced with a gas containing oxygen. The third heat treatment is followed by precipitation in an oxygen atmosphere or an atmosphere from which hydrogen and water have been sufficiently removed. Oxygen can also be supplied to the oxide semiconductor through a heating process.

[0143] The cause of deterioration in the characteristics of oxide semiconductors is the 0.1 eV to 0.2 eV below the conduction band caused by excess hydrogen. This is thought to be due to shallow levels of 100 eV and deep levels due to oxygen deficiency. The technical idea is to thoroughly remove hydrogen and provide sufficient oxygen to eliminate the defects. would be the correct one.

[0144] Note that oxide semiconductors are generally n-type. However, in one embodiment of the disclosed invention, By removing impurities such as i and supplying oxygen, which is a constituent element of oxide semiconductors, In this respect, it is possible to achieve i-type by adding impurity elements, as in silicon. Therefore, it can be said to include a technological concept that has never been seen before.

[0145] <Process advantages compared to other semiconductor materials> Semiconductor materials that can be compared to oxide semiconductors include silicon carbide (e.g., 4H-Si C). Oxide semiconductors and 4H-SiC have several things in common. The intrinsic carrier density of oxide semiconductors at room temperature is 10 -7 / cm 3 This is estimated to be about 6.7 × 10 in 4H-SiC. -11 / cm 3 Same as The intrinsic carrier density of silicon (1.4×10 10 / cm 3 degree ) and you can see how extraordinary the degree of this is.

[0146] The energy band gap of oxide semiconductors is 3.0 to 3.5 eV, and 4H-S The energy band gap of iC is 3.26 eV, so it is called a wide-gap semiconductor. Oxide semiconductors and silicon carbide have in common this point as well.

[0147] On the other hand, there is a significant difference between oxide semiconductors and silicon carbide. The semiconductor process using silicon carbide requires, for example, 1000 s to activate the dopant. Since heat treatment at 500℃ to 2000℃ is required, it is different from semiconductor elements using other semiconductor materials. At such high temperatures, semiconductor substrates and semiconductor elements may be destroyed. On the other hand, oxide semiconductors are heated to temperatures between 300°C and 500°C (glass transition temperature It can be produced by heat treatment at a maximum temperature of about 700°C, and is comparable to other semiconductor materials. It is possible to form an integrated circuit using the oxide semiconductor and then form a semiconductor element using the oxide semiconductor. become.

[0148] In addition, unlike silicon carbide, it is possible to use a substrate with low heat resistance, such as a glass substrate. Furthermore, compared to silicon carbide, it has the advantage that it does not require high-temperature heat treatment. This has the advantage that the energy cost can be sufficiently reduced.

[0149] <Conduction mechanism of transistors using oxide semiconductors> Here, the conduction mechanism of a transistor using an oxide semiconductor will be explained with reference to FIGS. 6 to 9. In the following explanation, an ideal situation is assumed for ease of understanding. Not all of the information provided reflects the actual situation. It is noted that this is merely an inventive step and does not affect the validity of the invention.

[0150] FIG. 6 is a cross-sectional view of a transistor (thin film transistor) using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on the gate electrode (GE1) via a gate insulating layer (GI). A source electrode (S) and a drain electrode (D) are provided thereon. An insulating layer is provided to cover the drain electrode (D).

[0151] FIG. 7 shows an energy band diagram (schematic diagram) in the cross section A-A' of FIG. The black circles (●) in 7 represent electrons, and the white circles (○) represent holes, each with a charge (-q, +q ) and a positive voltage (V D >0), the dashed line indicates the gate voltage When no voltage is applied to the electrode (V G =0), the solid line indicates a positive voltage (V G >0) When no voltage is applied to the gate electrode, the high potential barrier This indicates an off state in which no carriers (electrons) are injected from the electrode to the oxide semiconductor, and no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, and the on-state in which current flows is established. Indicates attitude.

[0152] FIG. 8 shows an energy band diagram (schematic diagram) in the cross section taken along line BB' in FIG. FIG. 8(A) shows the gate electrode (GE1) with a positive voltage (V G >0) is a given state, This shows the on-state where carriers (electrons) flow between the source electrode and the drain electrode. FIG. 8B shows a case where a negative voltage (V G <0) is applied. This shows the case where the transistor is in the off state (a state in which minority carriers do not flow).

[0153] Figure 9 shows the relationship between the vacuum level and the work function (φ M ) and the electron affinity (χ) of the oxide semiconductor. show.

[0154] At room temperature, electrons in metals are degenerate, and the Fermi level is located within the conduction band. Conventional oxide semiconductors are n-type, and their Fermi level (E F ) is located in the center of the band gap The intrinsic Fermi level (E i ) and is located closer to the conduction band. It is known that some hydrogen atoms act as donors in semiconductors, which is one of the factors that cause them to become n-type. There are.

[0155] In contrast, an oxide semiconductor according to one embodiment of the disclosed invention can convert hydrogen, which is a factor in making the oxide semiconductor n-type, into an oxide. The oxide semiconductor is made of a material that contains as few impurity elements as possible, other than the main components of the oxide semiconductor. By purifying it to such a high level, it becomes genuine (type i) or is intended to become genuine. In other words, instead of adding impurity elements to make it i-type, impurities such as hydrogen and water are removed as much as possible. By doing so, it is possible to obtain a highly purified i-type (intrinsic semiconductor) or something close to it. This results in the Fermi level (E F ) is the intrinsic Fermi level (E i ) It is possible.

[0156] The band gap (E g ) is 3.15 eV, and the electron affinity (χ) is 4.3 V It is said that the work function of titanium (Ti) that constitutes the source and drain electrodes is is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, In this case, no Schottky barrier is formed for electrons.

[0157] At this time, the electrons are transported between the gate insulating layer and the highly purified oxide semiconductor layer as shown in FIG. The electrons move near the interface with the oxide semiconductor (the lowest energetically stable part of the oxide semiconductor).

[0158] Also, as shown in FIG. 8B, when a negative potential is applied to the gate electrode (GE1), Since the number of holes, which are carriers, is substantially zero, the current is a value that is infinitely close to zero.

[0159] In this way, high purity oxide semiconductors are used to minimize the inclusion of elements (impurity elements) other than the main components of the oxide semiconductor. By this, the gate insulating layer becomes intrinsic (i-type) or substantially intrinsic. Therefore, the gate insulating layer must have a good interface with the oxide semiconductor. Specifically, for example, power frequencies from the VHF band to the microwave band are required. Insulating layers are produced by CVD using high-density plasma generated by a large number of processes, and by sputtering. It is preferable to use an insulating layer manufactured by a method such as the above.

[0160] The oxide semiconductor is highly purified while the interface between the oxide semiconductor and the gate insulating layer is improved. For example, the channel width (W) of a transistor can be reduced to 1×10 4 μm, channel length When (L) is 3 μm, 10 -13 Off-state current of less than A, sub- A threshold swing value (S value) (gate insulating layer thickness: 100 nm) can be achieved.

[0161] In this way, the oxide semiconductor is highly oxidized so that elements other than the main components (impurity elements) are not included as much as possible. Purification can improve the operation of the transistor.

[0162] <Carrier concentration in oxide semiconductor> One of the technical ideas of the disclosed invention is to make the carrier concentration in the oxide semiconductor layer sufficiently small. The aim is to obtain the intrinsic (i-type) state as close as possible. The method of measurement and the carrier concentration measured in the oxide semiconductor layer are shown in FIGS. This will be explained with reference to 3.

[0163] The carrier concentration in the oxide semiconductor layer was measured by fabricating a MOS capacitor using the oxide semiconductor layer. This can be determined by evaluating the CV measurement results (CV characteristics) of the MOS capacitor. It is Noh.

[0164] The carrier concentration is measured by the following steps (1)-(3): (1) MOS capacitor gate (2) Obtain the CV characteristics by plotting the relationship between the gate voltage Vg and the capacitance C. From the V characteristics, the gate voltage Vg and (1 / C) 2 and obtain a graph that shows the relationship between In the weak inversion region, (1 / C) 2 (3) The obtained differential value is Rear Density N d In equation (1), e is the elementary charge. , ε0 is the dielectric constant of a vacuum, and ε is the dielectric constant of an oxide semiconductor.

[0165]

number

[0166] The sample used for the measurement was a MOS capacitor with the following structure: a titanium layer having a thickness of 100 nm, a titanium nitride layer having a thickness of 100 nm on the titanium layer, and A 2 μm In-Ga-Zn-O oxide semiconductor (a-IGZO) was used on a titanium layer. a silicon oxynitride layer having a thickness of 300 nm on the oxide semiconductor layer; The silicon oxynitride layer has a 300 nm silver layer on it.

[0167] The oxide semiconductor layer was formed using a target for forming an oxide semiconductor film containing In, Ga, and Zn. (In:Ga:Zn=1:1:0.5 [molar ratio]) by sputtering method The oxide semiconductor layer was formed in a mixed atmosphere of argon and oxygen (flow ratio: The gas flow rate was Ar:O2=30(sccm):15(sccm).

[0168] Figure 22 shows the CV characteristics, and Figure 23 shows the relationship between Vg and (1 / C) 2 The relationship between these is shown in the figure. (1 / C) in the weak inversion region of 23 2 The carrier obtained from the differential value of The concentration is 6.0 x 10 10 / cm 3 It was.

[0169] In this way, an oxide semiconductor that has been made i-type or substantially i-type (for example, a semiconductor having a carrier concentration of 1×10 12 / cm 3 Less than 1×10 11 / cm 3 By using It is possible to obtain a transistor with extremely excellent off-state current characteristics.

[0170] As described above, by using an oxide semiconductor, in particular, a highly purified and intrinsic oxide semiconductor, It is understood that various effects can be obtained. A transistor using an oxide semiconductor and a transistor using a material other than an oxide semiconductor are combined. By using them in combination, a semiconductor device with excellent characteristics can be realized.

[0171] <Modification> 10 to 13 show modified examples of the configuration of the semiconductor device. Therefore, a case where the configuration of the transistor 162 is different from that described above will be described. The configuration of register 160 is the same as above.

[0172] In FIG. 10, a gate electrode 136d is provided under the oxide semiconductor layer 140, and a source electrode or The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1. The transistor 162 is configured to be in contact with the oxide semiconductor layer 140 on the lower surface of the transistor 162. The planar structure can be changed as needed to correspond to the cross section. Here, only the cross section will be shown.

[0173] The major difference between the configuration shown in FIG. 10 and the configuration shown in FIG. 2 is that the source electrode or drain electrode The electrode 142a and the source or drain electrode 142b are connected to the oxide semiconductor layer 140. That is, in the configuration shown in FIG. The source electrode or drain electrode 142a and the source electrode or drain electrode 142b 10, the lower surface of the oxide semiconductor layer 140 is in contact with the , the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, Due to this difference in contact, the arrangement of other electrodes, insulating layers, etc. may differ. The details of each component are the same as in Figure 2.

[0174] Specifically, the semiconductor device includes a gate electrode 136d provided on the interlayer insulating layer 128, and a gate a gate insulating layer 138 provided on the gate electrode 136d; In addition, the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, , on the source or drain electrode 142a, the source or drain electrode 142b and an oxide semiconductor layer 140 in contact with the side surface.

[0175] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136d, the source electrode or The electrode 136a is in contact with the drain electrode 130a, and the source or drain electrode 130b Electrode 136b is formed in contact with electrode 130c, and electrode 136c is formed in contact with electrode 130c. do.

[0176] In addition, a protective film is formed on the transistor 162 so as to be in contact with part of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode or a drain electrode. An opening is provided that reaches the source electrode 142a and the source or drain electrode 142b. Through the openings, the electrodes 150d and 150e are connected to the source and drain electrodes. The electrode 142a is formed in contact with the source electrode or the drain electrode 142b. As well as electrodes 150d and 150e, gate insulating layer 138, protective insulating layer 144, interlayer insulating layer The electrodes 136a, 136b, and 136c are in contact with each other through openings provided in the layer 146. Electrodes 150a, 150b, and 150c are formed.

[0177] Here, the oxide semiconductor layer 140 is highly purified by sufficiently removing impurities such as hydrogen. Specifically, the hydrogen concentration of the oxide semiconductor layer 140 is preferably 5×10 19 atoms / cm 3 Below 5×10 18 atoms / cm 3 Below, more hope Preferably 5 x 10 17 atoms / cm 3 In addition, it must contain sufficient oxygen. It is desirable that defects caused by oxygen deficiency are reduced by the hydrogen concentration. The oxide semiconductor layer 14 is highly purified by reducing the amount of oxygen to 0.5% and reducing defects caused by oxygen deficiency. 0, the carrier concentration is 1×10 12 / cm 3 Less than 1×10 11 / cm 3 In this way, the use of an i-type or substantially i-type oxide semiconductor Therefore, the transistor 162 can have excellent off-state current characteristics. When the input voltage Vd is +1V or +10V, the gate voltage Vg is -5V to -2 In the 0V range, the off-state current is 1×10 -13 A or less. In this way, the hydrogen concentration is sufficient. The oxide semiconductor layer 140 is highly purified by reducing the amount of oxygen to 0.5% and has fewer defects due to oxygen deficiency. By applying the above, the off-state current of the transistor 162 can be reduced. The hydrogen concentration in the oxide semiconductor layer 140 can be determined by the secondary electron Secondary Ion Mass Spectros (SIMS) The measurements were taken using a computer copy.

[0178] An insulating layer 152 is provided on the interlayer insulating layer 146, and a buried insulating layer 152 is provided on the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so that the electrodes are embedded in the Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150a. b, electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 54d is in contact with electrode 150e.

[0179] FIG. 11 shows the structure of a semiconductor device having a gate electrode 136d on an oxide semiconductor layer 140. Here, FIG. 11(A) shows the source electrode or drain electrode 142a and the source The drain electrode 142b is formed on the lower surface of the oxide semiconductor layer 140. 11B is an example of a configuration in which the source electrode or the drain electrode is in contact with the conductor layer 140. The source electrode 142a and the drain electrode 142b are disposed on the upper surface of the oxide semiconductor layer 140. 10B is an example of a structure in which the oxide semiconductor layer 140 is in contact with the oxide semiconductor layer 140 on the other surface.

[0180] 11. The major difference between the configurations shown in FIGS. 2 and 10 and the configuration shown in FIG. 11 is that the oxide semiconductor layer 140 11(A) and 11(B). ) is that the source electrode or drain electrode 142a and the source electrode Alternatively, the drain electrode 142b may be formed on either the lower surface or the upper surface of the oxide semiconductor layer 140. And due to these differences, other electrical The arrangement of the electrodes, insulating layers, etc. is different. The details of each component are the same as in Figure 2. is.

[0181] Specifically, the semiconductor device shown in FIG. 11A has a source a source or drain electrode 142a, a source or drain electrode 142b, and a source electrode The upper surfaces of the source or drain electrodes 142a and 142b are connected to the electrodes. and a gate insulating layer 138 provided on the oxide semiconductor layer 140. and a gate electrode 136d on the gate insulating layer 138 in a region overlapping with the oxide semiconductor layer 140. and,

[0182] 11B, the semiconductor device shown in FIG. 11B is a semiconductor device including an oxide semiconductor layer formed over an interlayer insulating layer 128. a source electrode or a gate electrode provided in contact with the upper surface of the oxide semiconductor layer 140; The drain electrode 142a, the source or drain electrode 142b, and the oxide semiconductor layer 1 40, source electrode or drain electrode 142a, and source electrode or drain electrode The gate insulating layer 138 provided on the gate insulating layer 142b and the oxide semiconductor layer on the gate insulating layer 138 and a gate electrode 136d in an area overlapping with 140.

[0183] In the configuration shown in FIG. 11, compared to the configuration shown in FIG. 2, some components can be omitted. In this case, the manufacturing process can be simplified. Of course, this is not essential in the configuration shown in Figure 2, etc. It goes without saying that some components can be omitted.

[0184] FIG. 12 shows a case where the size of the element is relatively large, and a gate electrode is provided under the oxide semiconductor layer 140. In this case, the flatness of the surface and the coverage are important. Since the requirements are relatively mild, wiring and electrodes are formed by embedding them in the insulating layer. For example, the gate electrode 13 can be formed by patterning the conductive layer after it is formed. Although not shown here, it is possible to form the transistor 16 0 can also be produced in the same way.

[0185] The major difference between the configuration shown in FIG. 12(A) and the configuration shown in FIG. 12(B) is that the source electrode or The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1. 40. Due to these differences, the arrangement of other electrodes, insulating layers, etc. also differs. The details of each component are the same as those in FIG. 2 and the like.

[0186] Specifically, the semiconductor device shown in FIG. 12A has a gate insulating film formed on an interlayer insulating layer 128. an electrode 136d, a gate insulating layer 138 provided on the gate electrode 136d, and a gate insulating layer A source or drain electrode 142a, a source or drain electrode, is provided on the layer 138. A drain electrode 142b and a source or drain electrode 142a and a source or drain electrode and an oxide semiconductor layer 140 in contact with the upper surface of the inner electrode 142b.

[0187] 12B, the semiconductor device shown in FIG. 12B has a gate electrode 1 provided on an interlayer insulating layer 128. 36d, a gate insulating layer 138 provided on the gate electrode 136d, and a gate insulating layer 13 an oxide semiconductor layer 140 provided in a region overlapping with the gate electrode 136d on the oxide semiconductor layer 140; A source electrode or drain electrode 14 is provided in contact with the upper surface of the semiconductor layer 140. 2a and a source or drain electrode 142b.

[0188] In addition, in the configuration shown in FIG. 12, compared to the configuration shown in FIG. 2, some components can be omitted. In this case, too, the effect of simplifying the manufacturing process can be obtained.

[0189] FIG. 13 shows a case where the size of the element is relatively large, in which a gate electrode is formed on the oxide semiconductor layer 140. In this case, too, the flatness of the surface and the coverage are important. Since the requirements for this are relatively low, it is possible to embed wiring and electrodes in the insulating layer. For example, by performing patterning after forming the conductive layer, the gate electrode Although not shown here, it is possible to form a transistor 136d. 160 can also be produced in the same manner.

[0190] The major difference between the configuration shown in FIG. 13(A) and the configuration shown in FIG. 13(B) is that the source electrode or The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1. 40. Due to these differences, the arrangement of other electrodes, insulating layers, etc. also differs. The details of each component are the same as those in FIG. 2 and the like.

[0191] Specifically, the semiconductor device shown in FIG. 13A has a source a source or drain electrode 142a, a source or drain electrode 142b, and a source electrode The upper surfaces of the source or drain electrodes 142a and 142b are connected to the electrodes. The oxide semiconductor layer 140, the source electrode or drain electrode 142a, and the a drain electrode 142b, a gate insulating layer 138 provided on the oxide semiconductor layer 140, A gate electrode 1 is provided on the gate insulating layer 138 in a region overlapping with the oxide semiconductor layer 140. 36d and has.

[0192] 13B, the semiconductor device shown in FIG. 13B is an oxide semiconductor film formed on an interlayer insulating layer 128. a source electrode or a gate electrode provided in contact with the upper surface of the oxide semiconductor layer 140; The drain electrode 142a, the source or drain electrode 142b, and the source or The drain electrode 142a, the source or drain electrode 142b, and the oxide semiconductor layer 140 a gate insulating layer 138 provided thereon; and an oxide semiconductor layer 140 on the gate insulating layer 138. and a gate electrode 136d provided in the overlapping region.

[0193] In addition, in the configuration shown in FIG. 13, compared to the configuration shown in FIG. 2, some components can be omitted. In this case, too, the effect of simplifying the manufacturing process can be obtained.

[0194] As described above, one embodiment of the disclosed invention realizes a semiconductor device with a novel structure. In this embodiment, the transistor 160 and the transistor 162 are stacked. However, the configuration of the semiconductor device is not limited to this example. In this configuration, the channel lengths of the transistors 160 and 162 are perpendicular to each other. The positional relationship between the transistor 160 and the transistor 162 is the same as in the above example. Furthermore, the transistor 160 and the transistor 162 may be overlapped. It may be provided.

[0195] For ease of understanding, the present embodiment will be described with reference to a semiconductor device with a minimum storage unit (1 bit). However, the configuration of the semiconductor device is not limited to this. By appropriately connecting the components, it is possible to construct a more advanced semiconductor device. By using multiple devices, it is possible to configure a NAND or NOR type semiconductor device. The configuration is not limited to that shown in FIG. 1 and can be modified as appropriate.

[0196] The semiconductor device according to this embodiment has a very low off-state current due to the low off-state current of the transistor 162. It is possible to retain information for a long time. No refresh operation is required, which reduces power consumption. It can be used as a non-volatile memory device.

[0197] In addition, since information is written by the switching operation of the transistor 162, It does not require high voltage and does not have the problem of element degradation. Therefore, since information can be written and erased, high-speed operation can be easily realized. This means that there is no need to erase the information required in flash memory, etc. There are also benefits to this.

[0198] In addition, transistors using materials other than oxide semiconductors are called transistors using oxide semiconductors. Compared to conventional memory controllers, it is possible to operate at higher speeds, so by using this, it is possible to read and write the stored contents. It is possible to perform reading at high speed.

[0199] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0200] (Embodiment 2) In this embodiment, a circuit configuration and operation of a semiconductor device according to one embodiment of the present invention will be described. do.

[0201] FIG. 14 shows an example of a circuit diagram of a semiconductor device (hereinafter also referred to as a NAND memory cell). As an example, a NAND memory cell 200 in which memory cells 220 are connected in series is shown. .

[0202] The NAND memory cell 200 includes a plurality of memory cells 220(1) to 220(2) connected in series. (km), km word lines WL(1) to WL(km) and second signal lines S2(1) to S 2 (km), a bit line BL, a source line SL, a first signal line S1, and two selection lines SE L1, SEL2, and the select line SEL1, along with the bit line BL and the memory cell 220(1). The transistor 255(1) is arranged between the source line SL and the select line SEL2. A transistor 255(2) arranged between the memory cells 220(km) are.

[0203] A memory cell 220(i) (i is an integer greater than or equal to 1 and less than or equal to 1) is one of the plurality of memory cells 220. The number of the first signal line S1, the second signal line S2(i), the word line WL(i), and the transistor 201(i), transistor 202(i), and capacitance element 203(i). The transistor 201(i) is formed using a material other than an oxide semiconductor. The transistor 202(i) is formed using an oxide semiconductor.

[0204] Here, the gate electrode of the transistor 201(i) and the source of the transistor 202(i) One of the drain and drain electrodes is electrically connected to one of the electrodes of the capacitor 203(i). In addition to the source electrode or drain electrode of the transistor 202(i), On the other hand, the first signal line S1 is electrically connected to the second signal line S2(i) and the transistor The gate electrode of 202(i) is electrically connected to the word line WL(i) and the capacitance element 2 The other electrode of 03(i) is electrically connected.

[0205] Furthermore, the transistor 20 included in the memory cell 220(i1) (i1 is an integer between 2 and 1000) The drain electrode of the transistor 201 (i1) in the memory cell 220 (i1-1) is connected to the drain electrode of the transistor 202 (i1-1). 1 (i1-1), and the source electrode of memory cell 220 (i2) (i2 is 1 to 1 m- The source electrode of the transistor 201(i2) in the memory cell 220(i The drain electrode of the transistor 201(i2+1) in the memory The drain electrode of the transistor 201(1) in the cell 220(1) is connected to the transistor 2 55(1) and the transistor 220(km) The source electrode of O1(km) is connected to the drain electrode of transistor 255(2). The drain electrode of the transistor 255(1) is connected to the bit line BL, and the transistor 25 The source electrode of the transistor 5(2) is connected to the source line SL. The source electrode of the transistor 201(i) is a transistor (including those constituting other memory cells). Also, the bit line BL and the gate of the transistor 201(i) are connected via a The drain electrode is connected via a transistor (including those that constitute other memory cells). It has been done.

[0206] FIG. 15 shows an example of the write circuit 211. The first signal line S1 is connected to the write The switch is electrically connected to the write potential Vwrite or Vs1_0. It is controlled by signals Fw1 and Fw2.

[0207] FIG. 16 shows an example of the read circuit 212. The read circuit 212 includes a sense amplifier circuit. The read circuit 212 is electrically connected to the bit line BL. The sense amplifier circuit is connected to one of the input terminals via a switch. The potential Vin input to one of the input terminals is also called the potential of the bit line BL. The other input terminal of the line is connected to a read potential Vread. is also connected to the potential VBL_0 and the potential Vpc via a switch. is controlled by signals Fr1, Fr2, and Fpc.

[0208] Next, the write and read operations of the NAND memory cell 200 shown in FIG. 14 will be described. Here, the memory cells 220 (i ) operation will be explained.

[0209] The memory cell 220(i) operates in various ways depending on the charge or potential stored at node A(i). In addition, the off-state current of the transistor 202(i) is extremely small. Since the charge or potential of node A(i) is small or essentially zero, In the following description, writing refers to writing data to memory cell 220(i). By charging or discharging the charge to the memory cell A(i), the memory cell 220(i) is brought into a predetermined state. Reading refers to setting a potential determined according to the state of the memory cell 220(i) to a predetermined value. It is to compare the potential with a fixed potential. It can also refer to a series of operations to write specific data to a memory card. Data reading can also refer to a series of operations to read data stored in a memory cell. .

[0210] When writing to the memory cell 220(i), for example, the potential of the word line WL(i) is set to V The potential of one electrode of the capacitor is fixed as WL_0 (for example, 0 V). The potential of the second signal line S2(i) is set to VS2_1 (for example, Vdd), and the transistor 202(i) ) is turned on. In addition, in the read circuit 212 electrically connected to the bit line BL, Then, signal Fr2 is asserted (enabled) and signals Fr1 and Fpc are deasserted ( As a result, the potential VBL_0 is applied to the bit line. In the write circuit 211 electrically connected to the line S1, the signal Fw1 is asserted. The signal Fw2 is deasserted to enter the write state. As a result, the first signal line S1 is in the write state. A write potential Vwrite corresponding to the data to be written is applied. That is, before the potential of the first signal line S1 changes, the potential of the second signal line S2(i) is set to VS2_ 0 (for example, 0V) to turn off the transistor 202(i).

[0211] When writing, the source electrode and the drain electrode of the transistor 201(i) A predetermined potential may be applied to either one or both of the potentials. For example, the word line WL( j) (j=i+1 to km integer) potential is VWL_1 (for example, Vdd) The selector 201(j) (j=i+1 to km) is turned on, and the potential of the select line SEL2 is set to V SEL_1 (for example, Vdd) to turn on the transistor 255(2), and the source line The potential of SL is set to VSL_0 (for example, 0 V), and the source electrode of the transistor 201(i) The potential may be VSL_0.

[0212] As a result, a charge corresponding to the potential Vwrite of the first signal line S1 is accumulated at the node A(i). The off-state current of the transistor 202(i) is extremely small. , or is substantially 0, the potential of the gate electrode of the transistor 201(i) remains constant for a long time. It is maintained for a period of time.

[0213] When reading from memory cell 220(i), the bit line is precharged in advance. During the precharge period, for example, the signal Fpc is asserted in the read circuit 212. Then, the signals Fr1 and Fr2 are deasserted to apply the precharge potential Vpc to the bit lines. Then, the potential of the selection line SEL1 is set to VSEL_1 (for example, Vdd). The transistor 255(1) is turned on, and the potential of the word lines WL(1) to WL(km) is set to VWL Turn on transistors 201(1) to 201(km) as read_0 (for example, Vdd) In this state, the potential of the selection line SEL2 is set to VSEL_0 (for example, 0 V) ​​and the transistor 255 ( 2) is turned off, and the source electrodes and drain electrodes of the transistors 201(1) to 201(km) are turned off. A precharge potential Vpc is applied to the gate electrode.

[0214] After the precharge, the read circuit 212 asserts the signal Fr1 and Deassert Fpc and signal Fr2 to connect the bit line BL to the input terminal of the sense amplifier circuit. One of the input terminals of the sense amplifier circuit is connected to the potential of the bit line BL. Also, the potential of the selected word line WL(j) is set to VWLread_1 (for example, 0V). Also, the potential of the source line SL is raised to VSLread (for example, Vdd). As a result, a current flows from the source line SL to the bit line BL, and the potential of the bit line BL rises. The potential of the node A(j) is VA(j), and the threshold voltage of the transistor 201(j) is Vt h(j), the potential Vin of the bit line is charged to approximately VA(j)-Vth(j). Then, the read circuit 212 compares Vin with the read potential Vread. Read out.

[0215] The write circuit 211 connected to the first signal line S1 asserts the signal Fw2. Then, the signal Fw1 is deasserted, and the potential of the first signal line S1 is set to VS1_0 (for example, 0V). Give.

[0216] The potential charged to the bit line will be described. The bit line is connected to the transistors 201(1) to When at least one of 201(km) is turned off, the current stops flowing and charging ends. When the potential of the source electrode is VSLread, the transistor 201(i) (i= The drain electrode potential at which the transistor (an integer between 1 and 1000) is exactly in the off state is VA(i) - Vth (i) In other words, the bit line is charged to the lowest potential of these potentials. become.

[0217] Considering the above, to perform the above read operation, VA(j) - Vth(j) must be less than VA(i )-Vth(i) (i = integer between 1 and 1 km) The charge potential is set to be lower than VA(j) - Vth(j). The potential Vin is charged to approximately VA(j) - Vth(j). VA(i) (i is 1 except j) ~km) is increased by increasing the word line potential VWLread_0. It is advisable to determine VWLread_0 and Vpc so that these are satisfied.

[0218] The relationship between the capacitance value C1 of the capacitor 203 and the gate capacitance C2 of the transistor 201 is It is preferable that C1>C2. By doing so, the noise when the word line potential is changed is Since the change in the potential of word line A becomes large, the potential of the word line VWLread_0 can be kept low.

[0219] The bit line potential Vin (potential Vin) to be compared during reading includes the This includes the potential of the node at the input terminal of the sense amplifier circuit connected to the bit line via a switch or the like. This shall be the case.

[0220] Next, a write operation according to one embodiment of the present invention will be described. As shown in FIG. 17, the first write (write for obtaining variation information) (reading to obtain variation information), the second write (reading to obtain the data to be stored) Each step is explained below.

[0221] The first write is performed to initialize the memory cell and to set the memory cell to a predetermined state. Specifically, Vwi (potential for initialization) is used as the write potential Vwrite. This is used to perform the write operation described above.

[0222] The first read is intended to obtain variation information of the memory cell. The threshold voltage Vth of the memory cell 201 varies from memory cell to memory cell. The distribution is as shown in A).

[0223] Due to such variations, the first read after the first write operation For example, the threshold voltage Vth of the transistor 201 varies. When the variation is as shown in FIG. 18(A), the potential Vin The variation in the potential of the bit line BL (or the potential of the bit line BL) is distributed as shown in FIG.

[0224] Therefore, in the first read, in order to obtain the variation information of the memory cell, The potential Vin of the bit line is read in detail. As the read potential Vread applied to the sense amplifier circuit, a plurality of potentials Vri_0 ~Vri_m (m is an integer greater than 0) are selected, and Vin is compared with Vri_j (j is an integer between 0 and m). This comparison is performed multiple times by changing j in Vri_j. As a result, it is determined which interval (the interval delimited by Vri_j and Vri_(j + 1)) the potential Vin of the bit line related to the read belongs to. The plurality of potentials Vri_j (j is an integer between 0 and m) can be determined, for example, corresponding to the threshold distribution of the transistor 201. For the threshold distribution of the transistor 201, a voltage range including this is determined and divided into m intervals. Let the lowest voltage of the interval be V0 and the interval width be ΔVth. The interval delimited by V0 + i×ΔVth and V0 + (i + 1)×ΔVth is called interval i (i is an integer between 0 and m - 1). The plurality of potentials Vri_j (j is an integer between 0 and m) can be determined such that when the threshold voltage Vth of the transistor 201 satisfies V0 + j×ΔVth < Vth < V0 + (j + 1)×ΔVth, the potential Vin of the bit line satisfies Vri_j < Vin < Vri_(j + 1). As described above, since Vin is approximately VA - Vth, Vri_j can be determined as approximately VA - (V0 + (m - j)×ΔVth). Of course, it is also possible to determine this from simulations and experiments.

[0225] Note that the distribution width of (VA - Vth) representing the state of the memory cell after writing depends on ΔVth. ​​​​​​​​​​​​​​​​​​​​​​​​​It is determined. When ΔVth is small, the distribution of the states of the memory cells after writing (writing the data to be stored) becomes narrow, and when ΔVth is large, the distribution of the states of the memory cells after writing becomes wide. ΔVth may be determined in consideration of the degree of multi-valuedness "n" of the data written to the memory cells, the power supply potential, etc. Next, in the first reading, a method of multiple comparisons using a plurality of potentials Vri_0 to Vri_m (m is an integer greater than 0) will be described. As a representative method, by performing m - 1 comparisons in order with a plurality of potentials Vri_0 to Vri_(m - 1), there is a method of determining which interval the threshold voltage Vth of the transistor 201 of the memory cell belongs to. Also, as shown in FIG. 19, it is also possible to take a method of feeding back the comparison result and performing repeated comparisons. Hereinafter, using FIG. 19, a method of determining which interval the threshold voltage Vth of the transistor 201 of the memory cell belongs to will be described for the case of m = 8. Note that, in the method shown in FIG. 19, three comparisons are performed.

[0228] First, as the read potential Vread, a potential Vri_4, which is near the center of the plurality of potentials Vri_0 to Vri_8, is used to perform the first comparison with the potential Vin. As a result of the first comparison, if the output of the sense amplifier circuit is "0" (SA_OUT = "0"), that is, when Vin < Vri_4, a potential Vri_2, which is near the center of the plurality of potentials Vri_1 to Vri_4, is used as the read potential Vread to perform the second comparison with the potential Vin.

[0229]

[0230]

[0231] ​​​​​​​​​​​​​Also, when the output of the sense amplifier circuit is "1" (SA_OUT = "1"), that is, Vin > V in the case of ri_4, the potential near the center of the plurality of potentials Vri_4 to Vri_7, the potential Vri_6 is used as the read potential Vread, and the second comparison with the potential Vin is performed.

[0232] As a result of the comparison using the potential Vri_2 as the read potential Vread, SA_OUT = "0", that is, when Vin < Vri_2, the potential Vri_1 is used as the read potential Vread, and the third comparison with the potential Vin is performed. Similarly, when SA_OUT = "1", that is, Vin > Vri_2, the potential Vri_3 is used as the read potential Vread, and the third comparison with the potential Vin is performed. Similarly, as a result of the comparison using the potential Vri_6 as the read potential Vread, SA_OUT = "0", that is, when Vin < Vri_6, the potential Vri_5 is read as the potential Vread, and the third comparison with the potential Vin is performed. Similarly, when SA_OU T = "1", that is, when Vin > Vri_6, the potential Vri_7 is read as the read potential Vre ad, and the third comparison with the potential Vin is performed.

[0233] As a result of the third comparison, when Vin < Vri_1, the threshold voltage Vth of the transistor 201 of the memory cell is determined to belong to interval 0. Similarly, if Vin > Vri_ 1, it belongs to interval 1, if Vin < Vri_3, it belongs to interval 2, if Vin > Vri_3, it belongs to interval 3,​​​​​​​​In this case, the number of comparisons can be reduced to M and the first read can be performed.

[0234] When multiple comparisons are performed in the first read, the bit Since no charging or discharging of the lines is involved, high-speed readout is possible.

[0235] In the first readout, a plurality of potentials Vri_0 to Vri_m (m is greater than 0) As a comparison method using integers, we have explained an example of multiple comparisons, but we have also explained how to perform a single comparison. Specifically, m-1 sense amplifier circuits are provided in the read circuit. That's fine.

[0236] Next, in the second write (writing of data to be stored), the desired data is written to the memory cell. The data is written as n values ​​from "0" to "n-1". The data "i" is stored in a memory cell whose transistor 201 has a threshold voltage of a typical value Vth_typ. The write potential when writing (i=an integer from 0 to n) is defined as Vw_i.

[0237] In the second write, when writing data “i” to a memory cell, it is determined which division the memory cell is in. Write is performed using a write potential that is corrected based on whether the write potential falls within the range. The section including the representative value Vth_typ of the threshold voltage of the resistor 201 is defined as section i0. Then, the correction voltage in the section i0+k (k is an integer between -i0 and m-1-i0) is k×ΔVth. Table 1 shows the threshold voltage ranges of the transistor 201. The relationship between the voltage and the correction voltage is shown.

[0238] [Table 1]

[0239] For example, in section i0, the correction voltage is 0, and in the adjacent section which is larger than section i0 by ΔVth, the correction voltage is The voltage is ΔVth, and in the adjacent section that is ΔVth smaller than section i0, the correction voltage is -ΔV If the memory cell belongs to the section (i0+k), the corrected write voltage is Write is performed using Vw_i+k×ΔVth, which is the value.

[0240] By performing such writing, it is possible to narrow the distribution of states after writing. As a result, it is possible to improve the degree of multi-value. In the verify operation, the data is written and read once at the first time, so it is different from the conventional verify write. This allows for faster writes compared to repeating write and read operations multiple times. It is possible.

[0241] Figure 20 shows the data when no correction is performed (i.e., when all correction voltages are set to 0V). An example of the data after writing (Fig. 20(A)) and an example of the data after writing when correction is performed (Fig. 20(B)) In FIG. 20(A), the write potential is independent of the memory cell. The state after writing is constant, and the distribution of the threshold voltage of the transistor 201 is similar to that of the transistor 201. As a result, for example, a memory cell can only store four or fewer states. On the other hand, in FIG. 20B, the write potential is corrected for each memory cell, so The latter state has a narrow distribution of about ΔVth. As a result, for example, the memory cell has 16 values The state can be stored.

[0242] Next, regarding a read operation (a read operation of stored data) according to one embodiment of the present invention, explain.

[0243] To read out the n-values ​​"0" to "n-1" as data, the read potential Vread A potential selected from multiple potentials Vr_0 to Vr_n-2 (n-2 is an integer greater than 0) is used as the The read potential Vr_j (j=an integer from 0 to n-2) is used to make multiple comparisons. _j is the value of the potential Vin when the memory cell of data "j" is read, and the value of the potential Vin when the memory cell of data "j+ The potential is determined to be between the values ​​of the potential Vin when a 1" memory cell is read.

[0244] Multiple comparisons using multiple potentials Vr_0 to Vr_n-2 (n-2 is an integer greater than 0) For example, a plurality of potentials Vr_0 to Vr_n-2 are sequentially set to n-1 By making this comparison, the state of the memory cell can be determined from data "0" to "n-1". In addition, it can be determined whether the first read operation is performed in the same manner as the method described with reference to FIG. A similar method can also be used. As a result, it is possible to read the data with fewer comparisons. Furthermore, it is possible to provide n-1 sense amplifier circuits and perform reading with one comparison. It is Noh.

[0245] An example of a specific operating voltage (potential) is shown in Table 2. For example, if the degree of multi-value is n=16 and the power supply voltage is The voltage level is Vdd=2.1V, and the typical value of the threshold voltage of the transistor 201 is Vth_typ= 0.3V, the width of the threshold voltage of the transistor 201 is ΔVth=0.04V, The number of sections of the threshold voltage of the register 201 and the number of sections of Vin for the first readout are m=8, An example in which the threshold voltage of the transistor 202 is 0.1 V and the capacitance ratio is C1 / C2=1. The write potential for the first write is Vwi=0.98V, and the word line potential for the read is Vwi=0.98V. VWLread_1=0V, VWLread_0=4V, precharge potential Vpc= 0V, and the source line potential can be VSLread=2.1V. The potential VWLread_0 is higher than Vdd, but the capacitance ratio is C1 / C2>1. By increasing the value, the potential VWLread_0 of the unselected word lines can be lowered, which is preferable. stomach.

[0246] [Table 2]

[0247] The correction voltages corresponding to the ranges of the threshold voltage of the transistor 201 are shown in Table 3. The read potential Vri_i (i=an integer from 0 to 8) for the first read is shown in Table 4. The pre-correction write potential Vw_i (i = integer from 0 to 15) for the second write is shown in Table 5. The value indicated by the arrow is used as a read potential Vr_i (i=0 to 14) for reading the stored data. The values ​​shown in Table 6 can be used for the voltages. Except for the word line potential VWLread_0, the write operation and It is possible to perform read and write operations.

[0248] [Table 3]

[0249] [Table 4]

[0250] [Table 5]

[0251] [Table 6]

[0252] Another example of specific operating voltages (potentials) is shown in Table 7. Here, the driving voltages during readout and For example, if the degree of multi-value is n=16 and the power supply potential is Vdd, = 2.1V, the typical value of the threshold voltage of the transistor 201 is Vth_typ = 0.3V, The interval width of the threshold voltage of the transistor 201 is ΔVth=0.04V, and the interval width of the threshold voltage of the transistor 20 The number of sections of the threshold voltage of the first readout Vin is m=8, and the number of sections of the transistor Vin is m=1. An example in which the threshold voltage of the capacitor 202 is 0.1 V and the capacitance ratio is C1 / C2=3 is shown.

[0253] The write potential for the first write is Vwi=1.73V, and the word line potential for the read is V WLread_1=-1V, VWLread_0=2.1V, precharge potential is Vpc = -1V, and the source line potential can be VSLread = 2.1V. Instead of setting the word line potential VWLread_0 to Vdd, the potential VWLr This is a driving method in which ead_1 is at a negative potential.

[0254] The write potential for the first write was set to Vwi=1.73V. In the read operation, the read word line potential is lowered by 1V, VWLread When C1=-1V, the capacitance ratio is C1 / C2=3, so node A is 0.75V. As a result, the potential of node A becomes 0.98V. In other words, Vwi=1.73V is the voltage corresponding to Vwi=0.98V in the specific operating voltage shown in Table 2. It is ranked 1st.

[0255] When the word line is set to a negative potential during reading, the second signal line S2 is also set to a negative potential. In other words, the second signal line S2 of the row selected for reading is applied with the same negative potential. In addition, in the peripheral circuitry that handles negative potential signals, the ground potential is also set to a negative potential. In particular, the ground potential of the read circuit must also be set to a negative potential.

[0256] Even when using a negative potential, the capacitance ratio C1 / C2 can be increased to C1 / C2>1. This is preferable because it can reduce the absolute value of the word line potential VWLread_1.

[0257] [Table 7]

[0258] The correction voltages corresponding to the ranges of the threshold voltage of the transistor 201 are shown in Table 3. The read potential Vri_i (i=an integer from 0 to 8) for the first read is shown in Table 4. The pre-correction write potential Vw_i (i = integer from 0 to 15) for the second write is shown in Table 5. The value indicated by the arrow is used as a read potential Vr_i (i=0 to 14) for reading the stored data. The values ​​shown in Table 8 can be used for the numbers.

[0259] [Table 8]

[0260] The read potential Vr_i (i=an integer from 0 to 14) for reading the stored data is The read potential Vr_j can be determined in the same manner as the specific potential Vr_i described above. is the value of the potential Vin when reading out the memory cell of data "j" and the value of the potential Vin when reading out the memory cell of data "j+1" The potential Vin is determined to be between the values ​​of Vin and Vin when the memory cell is read. In comparison with the specific example, when the written potential is high, the word line potential VW Since Lread_1 is 1V lower and the capacitance ratio is C1 / C2=3, the potential Vin is 0. The potential Vr_i is also reduced by 0.75V. If the potential of the word line is low, the transistor 201 is turned off as a result of lowering the potential of the word line. In this case, the capacitance ratio becomes large enough (C1>>C2) and the voltage Vin decreases. It varies depending on the input potential.

[0261] As described above, the writing in one aspect of the present invention is the first writing (for obtaining variation information). write), first read (read to obtain variation information), second write (Writing data to be stored) By performing the second write, the variation information of the memory cell is obtained. The specified data is written to the memory using a write voltage corrected based on the variation information of the memory cells. As a result, the distribution of states after writing is narrowed. In one aspect of the present invention, the write operation is performed by applying a charge to the node A of the memory cell. The write drive method, which is the charging and discharging of the memory cell, and the potential determined according to the state of the memory cell are The read driving method is not limited to the method of comparing with the potential. For example, As an example of the method, a method of raising the source line potential and charging the bit line has been explained. By controlling the word line potential, the transistor 201 of the selected memory cell is turned on or off. The potential Vin, which is determined by the conductance of the NAND memory cell, is controlled to be in the off state. It is also possible to compare with Vread.

[0262] FIG. 21 shows an embodiment of the present invention having a kr×(kc×kw) NAND memory cell array. An example of a block circuit diagram of such a semiconductor device is shown below. For example, if the degree of multi-level is n=4, , the memory capacity is 2 × km × kr × (kc × kw) bits. If n = 16, the memory capacity is 4 ×km×kr×(kc×kw) bits. Generally, n=2 k (k is an integer greater than or equal to 1) If this is the case, the memory capacity will be k times larger than in the binary case.

[0263] The semiconductor device shown in FIG. 21 has km×kr word lines WL(1_1) to WL(kr_km ) and second signal lines S2(1_1) to S2(kr_km), and kc×kw bit lines BL (1_1) to BL(kw_kc) and the first signal lines S1(1_1) to S1(kw_kc), A plurality of NAND memory cells 200(1, 1) to 200(kr, kw_kc) are arranged vertically in kr rows. Arranged in a matrix of (rows) x (kc x kw) (columns) (kr, kc, kw are natural numbers) A memory cell array 210, a read circuit 212, a write circuit 211, and a plurality of memory cells a multiplexer 219, a driver circuit 213 for the second signal line and the word line, a column decoder 214, and an Address buffer 215, data buffer 218, potential generating circuit 217, control circuit 216, etc. It is composed of peripheral circuits such as refresh circuits. Here, kc is the number of columns that can be independently selected by the column decoder 214, and kw is The number of columns selected simultaneously, kr is the number of rows of NAND memory cells, and km is the number of NAND memory cells. is the number of rows of memory cells that make up the

[0264] The NAND memory cell 200 can use the circuit shown in FIG. As a representative example of a memory cell, consider NAND memory cell 200(i, j). D memory cell 200(i, j) (i is an integer between 1 and kr, and j is an integer between 1 and kc × kw) The integers are the bit lines BL(j), the first signal lines S1(j), and the word lines WL(i_1) to W L(i_km), second signal lines S2(i_1) to S2(i_km), and source line SL(j) Also, the bit lines BL(1_1) to BL(kw_kc) and The signal lines S1(1_1) to S1(kw_kc) are connected to a multiplexer 219. The word lines WL(1_1) to WL(kr_km), the second signal lines S2(1_1) to S2( kr_km) and selection lines SEL1(1) to SEL1(kr), SEL2(1) to SEL2 (kr) is connected to the word line and second signal line driver circuit 213, respectively.

[0265] Next, each circuit will be explained. The write circuit 211 and the read circuit 212 are respectively The circuits shown in Figures 15 and 16 can be used.

[0266] The multiplexer 219 receives the output signal of the column decoder 214 as a control signal and outputs the kc A bit line selected from the bit lines kc is connected to the read circuit 212. One of the control signals is asserted, and the bit controlled by the asserted control signal is The multiplexer 219 also connects the kc first signal lines S1 to BL_S. The first signal line selected from the kc control lines is connected to the write circuit 211. When one of the signals is asserted, the first signal line controlled by the asserted control signal is Connect to the S1_S line.

[0267] In the case of a semiconductor device with a configuration of kc=1, the column decoder 214 and the multiplexer In this case, the write circuit 211 and the first signal line S1 are directly connected. Then, the read circuit 212 and the bit line BL can be directly connected.

[0268] The column decoder 214 receives the column address output from the address buffer 215 and the control circuit 2 The control signal output from 16 is used as an input signal, and the output signal specified by the address is asserted. and deasserts other output signals.

[0269] The second signal line and word line driver circuit 213 receives the row address output from the address buffer 215. The address and the control signal output from the control circuit 216 are used as input signals. The word line and the second signal line connected to the NAND memory cells in the same row are connected to the other word lines and the second signal line. and a second signal line, and a word line and a second signal line connected to NAND memory cells in different rows. A predetermined potential is applied to each of the signal lines.

[0270] The potential generating circuit 217 generates a write potential in accordance with the control signal output from the control circuit 216. Vwrite, read potential Vread, precharge potential Vpc, etc. are output. The write potential Vwrite is Vwi in the first write operation and Vwi in the second write operation. Vw_ j (j=an integer from 0 to n-1) is output. The read potential Vread is In the data read operation, one of the potentials Vr_j (j=an integer from 0 to n-2) is set to the first potential Vr_j. In a read operation, one of the potentials Vri_j (j=0 to m+1) is output. The potential is specified by the output signal of the control circuit. For example, the voltage output from the control circuit It has a digital-to-analog converter (DAC) that uses a digital signal representing the level as the input signal. It may be possible.

[0271] The potential generating circuit 217 generates a plurality of write potentials Vwrite and a plurality of read potentials Vwrite. For example, if there are multiple write circuits 211, If different potentials need to be written to each, multiple write potentials Vwrite can be used. Therefore, an appropriate potential can be supplied to each of the write circuits 211. For example, in the case where there are a plurality of read circuits 212, the comparison results are fed as shown in FIG. When the method of repeatedly comparing the read potential Vread is used, Thus, an appropriate potential can be supplied to each read circuit 212.

[0272] The address buffer 215 receives address signals input to the semiconductor device and signals output from the control signal circuit. The control signal is used as an input signal, and a predetermined column address is selected at a predetermined timing according to the control signal. The address register may be included.

[0273] The data buffer 218 receives the Din signal input to the semiconductor device and the data from the read circuit 212. and a control signal output from the control circuit 216 as input signals. 1, the Dout signal output from the semiconductor device, and the signal input to the control circuit 216 The data buffer 218 has a data register and outputs a signal according to the control signal. The control circuit 216 stores various input signals in the data register at a predetermined timing. The input output signal is used to select the write potential Vwrite or the read potential Vread. These signals are necessary for writing data to memory cells and reading data from memory cells. be.

[0274] The control circuit 216 controls signals such as WE, RE, CLK, etc. input to the semiconductor device and data buffers. The output signal from the address buffer 215 is used as an input signal. , a data buffer 218, a column decoder 214, a second signal line and word line driver circuit 213 The control signals are used to control data write and read operations. It is a control signal that contains information such as timing control signals for execution and potentials to be used. In the second write operation, the write potential is corrected based on the information on the write potential and the information on the correction voltage. The control circuit 216 generates and outputs information on the write potential. It may have a ROM for generating corrected write potential information from voltage information. For example, the write potential information is 4 bits, the correction voltage information is 3 bits, and the corrected write If the write potential is expressed in 6 bits, an 8 kbit ROM may be provided. A calculation is performed to generate corrected write potential information from the write potential information and the correction voltage information. The control circuit may include a calculation circuit.

[0275] In this embodiment, the read potential Vread is generated by the potential generating circuit 217. However, the read potential Vread can be generated by other configurations. For example, there is a method of providing a reference memory cell. By providing the same circuit configuration as that for generating Vin, Vread can be generated. The value of Vread can be controlled by controlling the potential of node A of the reference memory cell. It can be controlled.

[0276] The semiconductor device according to this embodiment has an extremely low off-state current due to the low off-state current of the transistor 202. It is possible to retain information for a long time. No refresh operation is required, which reduces power consumption. It can be used as a non-volatile memory device.

[0277] In addition, since information is written by the switching operation of the transistor 202, It does not require high voltage and does not have the problem of element degradation. Therefore, since information can be written and erased, high-speed operation can be easily realized. By controlling the potential input to the transistor, data can be directly rewritten. This eliminates the need for the erase operation required in flash memories and the like. This can suppress the decrease in operating speed caused by the operation.

[0278] In addition, transistors using materials other than oxide semiconductors are called transistors using oxide semiconductors. Compared to conventional memory controllers, it is possible to operate at higher speeds, so by using this, it is possible to read and write the stored contents. It is possible to perform reading at high speed.

[0279] In addition, since the semiconductor device according to this embodiment is a multi-value type, it is possible to increase the storage capacity per area. Therefore, it is possible to achieve miniaturization and high integration of the semiconductor device.

[0280] As described above, the variation information of the memory cells is acquired, and the write voltage is set according to the variation information. By writing a value to the memory cell, the distribution of the memory cell state after writing is narrowed. As a result, it is possible to improve the degree of multi-value. In the write operation, the potential of the floating node can be directly controlled. Therefore, the three-step write process is: first write, first read, and second write. This operation allows for highly accurate threshold voltage control. A write operation is faster than multiple writes and reads. This makes it possible to achieve this.

[0281] (Embodiment 3) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the above embodiment will be described. The semiconductor device obtained in the above embodiment is a semiconductor device that does not require power supply. Even if the data is written or erased, it is possible to retain the data. Furthermore, the operation is also fast. Therefore, it is possible to use this semiconductor device to develop new electrical circuits. It is possible to provide a sub-device. The semiconductor device is then mounted on a circuit board or the like and installed inside various electronic devices.

[0282] FIG. 24A shows a notebook personal computer including the semiconductor device according to the above embodiment. The computer is composed of a main body 301, a housing 302, a display unit 303, a keyboard 304, etc. The semiconductor device according to one embodiment of the present invention is implemented in a notebook personal computer. By applying this technology, it is possible to retain information even when there is no power supply. There is no deterioration due to writing and erasing. Furthermore, the operation is fast. The semiconductor device according to the present invention is preferably applied to a notebook personal computer. is.

[0283] FIG. 24B shows a personal digital assistant (PDA) including the semiconductor device according to the above embodiment. The main body 311 includes a display unit 313, an external interface 315, an operation button 314, etc. The stylus 312 is also provided as an accessory for operation. By applying the semiconductor device according to the present invention to a PDA, information can be retained even when there is no power supply. In addition, there is no deterioration due to writing and erasing. Therefore, it is preferable to apply the semiconductor device according to one aspect of the present invention to a PDA. is.

[0284] FIG. 24C shows an example of electronic paper including the semiconductor device according to the above embodiment. The electronic book 320 is shown. The electronic book 320 is made up of two housings, housing 321 and housing 323. The housing 321 and the housing 323 are integrated by a shaft portion 337. The opening and closing operation can be performed around the axis 337. The semiconductor device 320 can be used like a paper book. By applying this technology to electronic paper, it is possible to retain information even when there is no power supply. In addition, there is no deterioration due to writing and erasing. Furthermore, the operation is fast. For this reason, it is preferable to apply a semiconductor device according to one embodiment of the present invention to electronic paper. do.

[0285] The housing 321 incorporates a display unit 325, and the housing 323 incorporates a display unit 327. The display unit 325 and the display unit 327 may be configured to display a continuous screen, or may be configured to display different screens. By configuring to display different screens, for example, The text is displayed on the right display section (display section 325 in FIG. 24(C)) and the text is displayed on the left display section (display section 325 in FIG. 24(C)). In (C), an image can be displayed on the display unit 327).

[0286] FIG. 24C shows an example in which an operation unit and the like are provided on the housing 321. The body 321 includes a power supply 331, operation keys 333, a speaker 335, etc. You can turn the page by pressing the arrow 333. In addition, there is a keyboard and a pointer on the same surface as the display unit of the housing. The back and sides of the housing may be provided with an external Connection terminals (earphone jack, USB terminal, AC adapter and USB cable, etc.) terminals that can be connected to various cables, a recording medium insertion section, etc. Furthermore, the electronic book 320 may be configured to have the function of an electronic dictionary.

[0287] The electronic book 320 may also be configured to be able to send and receive information wirelessly. It is also possible to purchase and download desired book data from the child book server. It is possible.

[0288] Electronic paper can be applied to any field that displays information. For example, in addition to e-books, posters, advertisements on trains and other vehicles, credit cards, etc. The present invention can be applied to displays on various cards such as gift cards.

[0289] FIG. 24D shows a mobile phone including the semiconductor device according to the above embodiment. The phone is made up of two housings, housing 340 and housing 341. Housing 341 has a front display panel 342, speaker 343, microphone 344, pointing device 3 46, a camera lens 347, an external connection terminal 348, etc. The mobile phone includes a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. The antenna is built into the housing 341. By applying the body device to a mobile phone, information can be retained even when there is no power supply. In addition, there is no deterioration due to writing and erasing. Therefore, it is preferable to apply the semiconductor device according to one embodiment of the present invention to a mobile phone. be.

[0290] The display panel 342 has a touch panel function, and in FIG. 24(D) an image is displayed. The multiple operation keys 345 are shown by dotted lines. A boost circuit is implemented to boost the voltage output by 9 to the voltage required for each circuit. In addition to the above configuration, it may be configured to incorporate a contactless IC chip, a small recording device, etc. It is also possible.

[0291] The display direction of the display panel 342 changes appropriately depending on the usage mode. The camera lens 347 is located on the same surface as the camera 42, making it possible to make video calls. The speaker 343 and microphone 344 are not limited to voice calls, but also video calls, recording, playback Furthermore, the housing 340 and the housing 341 can be slid, and as shown in FIG. It can be folded from the unfolded state to the overlapping state, making it possible to make it compact and portable. It is Noh.

[0292] The external connection terminal 348 can be connected to various cables such as an AC adapter or a USB cable. The external memory slot 350 can store a recording medium. It can insert and store and move larger amounts of data. In addition to the above functions, It may also be equipped with infrared communication functions, television reception functions, etc.

[0293] FIG. 24(E) shows a digital camera including the semiconductor device according to the previous embodiment. The digital camera comprises a main body 361, a display unit (A) 367, an eyepiece 363, and an operation switch 364. , a display unit (B) 365, a battery 366, etc. By applying the semiconductor device according to the present invention to a digital camera, information can be stored even when there is no power supply. In addition, there is no deterioration due to writing and erasing. Therefore, the semiconductor device according to one embodiment of the present invention is suitable for a digital camera. It is preferable to use

[0294] FIG. 24F shows a television set including the semiconductor device according to the above embodiment. In the vision device 370, a display unit 373 is built into a housing 371. In this case, the stand 375 is used to hold the case in place. 371 is shown in the supporting configuration.

[0295] The television device 370 can be operated using an operation switch provided on the housing 371 or a separate remote control. This can be done by operating the operating device 380. The remote control operating device 380 has an operating key 379. This allows you to control the channel and volume, and to operate the image displayed on the display unit 373. In addition, the remote control operation device 380 can receive the output from the remote control operation device 380. A display unit 377 for displaying information may be provided. By applying the body device to a television device, information can be retained even when there is no power supply. In addition, there is no deterioration due to writing and erasing. Therefore, the semiconductor device according to one embodiment of the present invention is applied to a television set. This is preferable.

[0296] It is preferable that the television device 370 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts. By connecting to a wired or wireless communication network, The purpose of this communication is to communicate information between two parties (one party) or two-way (between a sender and a receiver, or between receivers). It is possible to do this.

[0297] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. Can be used in combination [Explanation of symbols]

[0298] 100 boards 102 Protective layer 104 Semiconductor Area 106 Element isolation insulating layer 108 Gate insulating layer 110 gate electrode 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer insulation layer 128 Interlayer Insulation Layer 130a Source electrode or drain electrode 130b Source electrode or drain electrode 130c electrode 132 Insulating layer 134 Conductive Layer 136a electrode 136b Electrode 136c electrode 136d Gate electrode 138 Gate insulating layer 140 Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 144 Protective Insulation Layer 146 Interlayer insulation layer 148 Conductive Layer 150a electrode 150b electrode 150c electrode 150d electrode 150e electrode 152 Insulating layer 154a electrode 154b electrode 154c electrode 154d electrode 160 transistors 162 transistors 164 Capacitor 166 transistors 200 memory cells 201 Transistor 202 Transistor 203 Capacitor 210 memory cell array 211 Write circuit 212 readout circuit 213 Drive Circuit 214 Column Decoder 215 Address Buffer 216 Control circuit 217 Potential generation circuit 218 Data Buffer 219 Multiplexer 220 memory cells 255 transistors 301 Main Unit 302 Case 303 Display section 304 keyboard 311 Main Unit 312 Stylus 313 Display section 314 Operation Button 315 External Interface 320 e-books 321 Case 323 Case 325 Display section 327 Display section 331 Power supply 333 Operation Key 335 Speaker 337 Shaft 340 Case 341 Case 342 Display Panel 343 Speaker 344 Microphone 345 Operation Key 346 Pointing Device 347 Camera Lenses 348 External connection terminal 349 Solar Cells 350 external memory slot 361 Main Unit 363 Eyepiece 364 Operation Switch 365 Display section (B) 366 Battery 367 Display section (A) 370 Television Equipment 371 Case 373 Display section 375 Stand 377 Display section 379 Operation Key 380 Remote Controlled Device

Claims

1. a first transistor to a third transistor and a capacitor; one of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; one of a source or a drain of the second transistor is electrically connected to one of a source or a drain of the third transistor; a semiconductor device in which one electrode of the capacitance element is electrically connected to a gate of the second transistor, the first transistor includes an oxide semiconductor in a channel formation region; the second transistor includes silicon in a channel formation region; a first conductive film having a region located above a channel formation region of the second transistor and functioning as a gate of the second transistor; a first insulating film having a region disposed above the first conductive film; a second conductive film having a region disposed above the first insulating film and functioning as a gate of the first transistor; a semiconductor film having a region disposed above the second conductive film and having a channel formation region of the first transistor; a second insulating film having a region disposed above the first insulating film and a region disposed above the semiconductor film; a third conductive film having a region disposed above the second insulating film, electrically connected to one of the source and drain of the first transistor, and electrically connected to the gate of the second transistor; a fourth conductive film having a region disposed above the second insulating film and electrically connected to the other of the source and the drain of the second transistor; the semiconductor film does not overlap with the first conductive film; Semiconductor device.

2. a first transistor to a third transistor and a capacitor; one of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; one of a source or a drain of the second transistor is electrically connected to one of a source or a drain of the third transistor; a semiconductor device in which one electrode of the capacitance element is electrically connected to a gate of the second transistor, the first transistor includes an oxide semiconductor in a channel formation region; the second transistor includes silicon in a channel formation region; a first conductive film having a region located above a channel formation region of the second transistor and functioning as a gate of the second transistor; a first insulating film having a region disposed above the first conductive film; a second conductive film having a region disposed above the first insulating film and functioning as a gate of the first transistor; a semiconductor film having a region disposed above the second conductive film and having a channel formation region of the first transistor; a second insulating film having a region disposed above the first insulating film and a region disposed above the semiconductor film; a third conductive film having a region in contact with an upper surface of the second insulating film, electrically connected to one of the source and drain of the first transistor, and electrically connected to the gate of the second transistor; a fourth conductive film having a region in contact with an upper surface of the second insulating film and electrically connected to the other of the source and the drain of the second transistor; the semiconductor film does not overlap with the first conductive film; Semiconductor device.

3. In claim 1 or claim 2, each of the third conductive film to the fourth conductive film contains one or more of aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten; Semiconductor device.

Images