Wiring board and manufacturing method of them
The wiring board incorporates recesses on the plane portion of the conductive layer filled with insulating material to level the surface, addressing height differences and preventing defects in the outer layer.
Patent Information
- Application Number
- JP2024095042
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-06-12
- Publication Date
- 2025-12-24
AI Technical Summary
The conventional wiring boards exhibit a height difference between the upper surface of the insulating layer covering the center of the solid pattern and the upper surface of the insulating layer covering the outer edge, which needs to be addressed.
A wiring board design featuring a recess formed on the upper surface of the plane portion of the conductive layer, filled with a portion of the upper insulating layer, to level the surface and reduce height differences.
The design effectively suppresses the protrusion of the upper surface of the insulating layer, ensuring a uniform surface profile and preventing defects such as excessive recessing in the outermost insulating layer.
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Figure 2025186739000001_ABST
Abstract
Description
[Technical Field]
[0001] The present disclosure relates to a wiring board and a manufacturing method thereof. [Background technology]
[0002] BACKGROUND ART A known wiring board has an insulating layer laminated on a conductive layer including a solid pattern (see, for example, Patent Document 1). [Prior art documents] [Patent documents]
[0003] [Patent Document 1] JP 2017-212380 A (paragraph
[0022] , Figure 1) Summary of the Invention [Problem to be solved by the invention]
[0004] In the wiring board having the above-described conventional structure, the upper surface of the insulating layer covering the center of the solid pattern may be higher than the upper surface of the insulating layer covering the outer edge of the solid pattern. This application discloses a technique for reducing such a height difference. [Means for solving the problem]
[0005] One aspect of the presently disclosed invention is a wiring board having a lower insulating layer, a conductive layer including a plane portion formed on the lower insulating layer, and an upper insulating layer stacked on the lower insulating layer and the conductive layer, wherein a recess having an inner surface which is a laser-processed surface, a grinding-processed surface, or a cutting-processed surface is formed on the upper surface of the plane portion, and a portion of the upper insulating layer is filled in the recess. [Brief explanation of the drawings]
[0006] [Figure 1] FIG. 1 is an enlarged cross-sectional view of a wiring board according to a first embodiment. [Figure 2] Figure 2 is a cross-sectional view of Figure 1 taken along the line A-A. [Figure 3] FIG. 3A is a cross-sectional view of a core substrate on which an insulating layer is laminated, FIG. 3B is a cross-sectional view of a core substrate on which a via hole is formed, and FIG. 3C is a cross-sectional view of a core substrate on which a via conductor and a conductive layer are formed. [Figure 4] FIG. 4A is an enlarged cross-sectional view of a core substrate in which a recess is formed in a plane portion, FIG. 4B is an enlarged cross-sectional view of a core substrate in which an insulating layer is laminated, and FIG. 4C is an enlarged cross-sectional view of a wiring board. DETAILED DESCRIPTION OF THE INVENTION
[0007] [First embodiment] 1 to 4, wiring board 10 of the present embodiment will be described. Wiring board 10 of the present embodiment is, for example, a multilayer laminated board in which conductive layers 20 and insulating layers 21 are alternately laminated on both the front and back surfaces of core substrate 11. Furthermore, the outermost layer of wiring board 10 is solder resist layer 12, which is an insulating layer.
[0008] Core substrate 11 has a structure in which, for example, multiple prepregs (B-stage sheets made by impregnating a core material such as woven glass cloth with resin) are laminated. Insulating layer 21 does not have a core material and is a film containing, for example, a thermosetting resin such as epoxy resin and an inorganic filler. Solder resist layer 12 is, for example, an ultraviolet-curable photosensitive film made of epoxy resin or the like.
[0009] The insulating layer 21 may be a prepreg, and the core substrate 11 may be formed of multiple resin films. The solder resist layer 12 may be formed by curing a liquid. Furthermore, the core substrate 11 is provided with multiple through-hole conductors 13 that connect the conductive layers 20 together, the insulating layer 21 is provided with multiple via conductors 23 that connect the conductive layers 20 together, and the solder resist layer 12 is formed with multiple connection openings (not shown) for exposing pads included in the outermost conductive layer 20, but the formation of these through-hole conductors 13 etc. is optional.
[0010] Conductive patterns are formed on the conductive layer 20 to form an electric circuit. Therefore, the conductive layer 20 includes conductive portions 24 where conductors are arranged and gap portions 25 where no conductors are arranged and the underlying insulating layer 21 is exposed. The conductive portions 24 of the conductive layer 20 of this embodiment include plain portions 28.
[0011] The plane portion 28 is included in the conductive portion 24 of the conductive layer 20 one layer below the outermost conductive layer 20, and has a rectangular planar shape, for example, as shown in Fig. 2. In the conductive portion 24 of the conductive layer 20, wiring 27, lands 26, etc. are arranged near the plane portion 28. The plane portion 28 is also used as a power supply layer, a ground layer, a heat sink, etc., and is also called a plain layer or a solid layer because the conductors are concentrated and occupy a wider area than the lands 26 and wiring 27.
[0012] Generally, there is no clear definition of what constitutes a plane portion 28, but at least a part of the conductive portion 24 of the conductive layer 20 that is used as a power supply layer, ground layer, or heat sink is considered a plane portion.
[0013] A recess 29 is formed on the upper surface of the plane portion 28, recessing the entire surface in a stepped manner except for the outer edge portion. Furthermore, an outer edge protrusion 28A of the plane portion 28 that remains around the recess 29 is in the shape of a closed frame. Specifically, the recess 29 occupies 60 to 95% of the entire area of the upper surface of the plane portion 28. Furthermore, the thickness of the outer edge protrusion 28A is approximately the same as that of the other conductive portions 24, such as the wiring 27 and the lands 26. Furthermore, the depth of the recess 29 is approximately 1 / 4 to 3 / 4 of the thickness of the outer edge protrusion 28A. Furthermore, the recess 29 is filled with a portion of the resin that constitutes the insulating layer 21 that is laminated on the conductive layer 20.
[0014] Incidentally, the recess 29 in this embodiment has a shape and size in which substantially the entire plain portion 28 except for the outer edge portion is recessed in a stepped shape, but is not limited to this, and one or more circular or elliptical recesses 29 may be formed in a rectangular plain portion 28, or one or more rectangular or polygonal recesses 29 may be formed in a circular or rectangular plain portion 28. Furthermore, the outer edge protrusion 28A surrounding the recess 29 in this embodiment is entirely closed, but may be partially open.
[0015] This completes the description of the configuration of wiring board 10 of this embodiment. Next, a method for manufacturing wiring board 10 will be described below with reference to Figures 3 and 4. In the following description, the conductive layers 20 and insulating layers 21 will be distinguished by being prefixed with "first," "second," etc., in order from the core substrate 11 side. (1) As shown in FIG. 3A, core substrate 11 is prepared. Core substrate 11 has a structure in which copper foil is laminated on both sides of insulating base material 11K, which is made by laminating a plurality of prepregs. The copper foil on both sides of core substrate 11 is etched to form a predetermined wiring structure, and through-holes are formed in predetermined locations of core substrate 11. Subsequently, core substrate 11 is subjected to electroless plating, plating resist formation, and electrolytic plating, so that through-hole conductors 13 are filled in the through-holes, and first conductive layers 20, each including conductive portions 24 and gap portions 25, are formed on both the front and back surfaces of insulating base material 11K. Note that through-hole conductors 13 may be a conductive paste or the like.
[0016] (2) Next, a resin film serving as first insulating layer 21 is placed on first conductive layer 20 and hot-pressed. As a result, the molten resin of first insulating layer 21 penetrates gaps 25 of first conductive layer 20, and the top surface of first insulating layer 21 is flattened.
[0017] (3) After the first insulating layer 21 has cooled, via holes 23H are formed by a laser at predetermined locations in the first insulating layer 21. In this embodiment, a carbon dioxide laser, a UV-YAG laser, or the like is used to form the via holes 23H (see FIG. 3B).
[0018] (4) Electroless plating, plating resist formation, and electrolytic plating are performed on first insulating layer 21 and inside via hole 23H. As a result, conductive portion 24 of second conductive layer 20 is formed in the portion of first insulating layer 21 not covered by the plating resist, via conductor 23 is formed inside via hole 23H, and the portion covered by the plating resist is exposed as gap portion 25 (see FIG. 3C). Furthermore, this conductive portion 24 includes land 26, wiring 27, and plain portion 28.
[0019] (5) As shown in FIG. 4A, a laser is applied to the plain portion 28 of the conductive portion 24, excluding the outer edge, to form a recess 29. The portion not irradiated with the laser remains as an outer edge protrusion 28A. In this embodiment, a green laser is used to form the recess 29. Note that only one side of the wiring substrate 10 is shown in FIGS. 4A to 4C.
[0020] The recessed portion 29 may be formed by a green laser or a router, or by removing the top surface of the plain portion 28 by half etching.
[0021] (6) As shown in Fig. 4B, a resin film is superimposed as second insulating layer 21 on first insulating layer 21 and second conductive layer 20. When the resin film is heat-pressed, part of the melted second insulating layer enters gap 25 on the upper surfaces of lands 26 and wiring 27 of conductive portion 24. Meanwhile, part of the melted second insulating layer enters recess 29 on the upper surface of plain portion 28.
[0022] (7) Next, similarly to steps (2) to (4), via conductors 23 and third conductive layer 20 are formed. Then, a dry film made of photosensitive resin is superimposed on the upper surface of third conductive layer 20, and a vacuum lamination process is performed to form solder resist layer 12 (see FIG. 4C).
[0023] The solder resist layer 12 may be a dry film as in this embodiment, or may be a liquid resist made of a thermosetting resin or a photosensitive resin.
[0024] This completes the description of the manufacturing method for wiring board 10 of this embodiment. As described above, in wiring board 10 of this embodiment, recesses 29 are formed over the entire surface of first insulating layer 21 except for the outer edge of plain portion 28. This allows resin that cannot flow to gap 25 adjacent to plain portion 28 to be received in recesses 29, thereby suppressing protrusion of the upper surface of first insulating layer 21 above plain portion 28. In other words, the entire surface of plain portion 28 except for the outer edge is thinner than conductive portion 24 outside plain portion 28, suppressing protrusion of the upper surface of first insulating layer 21 above plain portion 28. This makes it possible to suppress height differences in the upper surface of solder resist layer 12, which is the outermost insulating layer, in wiring board 10 of this embodiment.
[0025] Furthermore, in the wiring board 10 of this embodiment, the inner surface of the recess 29 is a laser-processed surface and is formed by laser processing, so it can be made to a suitable depth compared to one formed by plating, and defects such as the recess being too deep and causing a recess in the upper surface of the outermost insulating layer of the wiring board are prevented.
[0026] Furthermore, by configuring the recesses 29 so as not to open to the sides of the plain portion 28 as in this embodiment, the resin of the insulating layer 21 can remain in the recesses 29 without flowing out, thereby preventing the insulating layer 21 from protruding while leaving a necessary amount of resin on the plain portion 28. Furthermore, by leaving the outer edge protrusions 28A, the risk of the tip of the laser or router being misaligned when forming the recesses 29 can be reduced, which will damage the insulating layer around the periphery of the plain portion.
[0027] Furthermore, the insulating layer 21 laminated on the plain portion 28 may be a film-like resin or a liquid resin. If the resin is a film-like resin as in this embodiment, it is thought that the resin is less likely to flow than a liquid resin, and excess resin is more likely to remain on the plain portion. Therefore, the effect of forming the recesses can be more effectively enjoyed.
[0028] Furthermore, in this embodiment, the plain portion 28 in which the recesses 29 are formed is included in the conductive layer 20 that is one layer inner than the outermost conductive layer 20, but it may also be the outermost conductive layer 20. Furthermore, the plain portion 28 in which the recesses 29 are formed may also be included in the conductive portion 24 formed on the upper surface of the core substrate 11. Even with this configuration, it is possible to suppress the protrusion of the solder resist layer 12. Furthermore, the core substrate 11 does not have to be a double-sided substrate in which a plurality of conductive layers 20 and insulating layers 21 are laminated on both the front and back sides thereof, and may be a single-sided substrate in which a plurality of conductive layers 20 and insulating layers 21 are laminated on only one of the front and back sides thereof.
[0029] Although the present specification and drawings disclose specific examples of the technology included in the scope of the claims, the technology described in the claims is not limited to these specific examples, but also includes various modifications and variations of the specific examples, as well as parts taken out independently from the specific examples.
[0030] [Explanation of symbols] 10. Wiring board 12 Solder resist layer 20 Conductive layer 21 Insulating layer 24 Conductive part 25 Gap 28 Plain section 29 Recess
Claims
1. A wiring board having a lower insulating layer, a conductive layer including a plane portion formed on the lower insulating layer, and an upper insulating layer stacked on the lower insulating layer and the conductive layer, A recess having an inner surface that is a laser-processed surface, a ground surface, or a machined surface is formed on the upper surface of the plain portion, and a portion of the upper insulating layer is filled into the recess.
2. 2. The wiring board according to claim 1, The recessed portion does not have any openings on the sides.
3. (Newly added claims) 2. The wiring board according to claim 1, The recessed portion occupies 60% to 95% of the entire area of the plain portion.
4. 2. The wiring board according to claim 1, The conductive layer is the conductive layer immediately below the outermost conductive layer.
5. 5. The wiring board according to claim 4, The height difference of the upper insulating layer in the region directly above the plane portion is 5 μm or less.
6. 5. The wiring board according to claim 4, The maximum depth of the irregularities on the upper surface of the outermost layer is 1 / 4 to 3 / 4 of the thickness of the plain portion.
7. A method for manufacturing a wiring substrate having a lower insulating layer, a conductive layer including a plane portion formed on the lower insulating layer, and an upper insulating layer stacked on the lower insulating layer and the conductive layer, comprising: The method includes forming a recess in the upper surface of the plane portion by a laser or a router, and filling the recess with a portion of the upper insulating layer.
8. 8. The method for manufacturing a wiring board according to claim 7, The method includes a step of laminating a resin film as the insulating layer on the conductive layer.
Citation Information
Patent Citations
Wiring board
JP2017212380A