Cadmium selenide-based photovoltaic devices and methods for forming same

Abstract

A photovoltaic device is provided that includes a polycrystalline II-VI semiconductor absorber material that includes an n-type absorber composition and has a p-type hole contact layer. Methods for treating the semiconductor absorber layer and for forming the hole contact layer are described.

Description

[Technical field]

[0001]

[0001] Photovoltaic devices generate power by converting light into direct current electricity using semiconductor materials that exhibit the photovoltaic effect. When exposed to light, the photovoltaic effect generates electricity when photons are absorbed in the semiconductor material, exciting electrons to a higher energy state. These excited electrons can move within the material, thereby generating an electric current. [Background technology]

[0002]

[0002] Thin film photovoltaic devices are typically made from various layers of different materials formed on a substrate, each layer performing a different function. Thin film photovoltaic devices include a front electrode and a back electrode to provide electrical access to the photoactive semiconductor layer or other layers sandwiched between them. Summary of the Invention

[0003]

[0003] Although many improvements have been developed to constantly increase conversion efficiency, there remains a continuing need for improved thin-film PV devices that capture or recover the maximum amount of solar radiation practicable while minimizing absorption losses.

[0004]

[0004] The embodiments set forth in the drawings are exemplary and illustrative in nature and are not intended to limit the subject matter defined by the claims. The following detailed description of exemplary embodiments can be understood when read in conjunction with the following drawings, in which like reference numerals indicate the same or corresponding parts throughout the views. The patent or application file may contain at least one drawing executed in color and / or one or more photographs. Copies of this patent or patent application publication with color drawing(s) will be provided by the U.S. Patent and Trademark Office upon request and payment of the necessary fee. [Brief description of the drawings]

[0005] [Figure 1]

[0005] FIG. 1 is a schematic diagram illustrating a cross-sectional view of a tandem photovoltaic device according to one or more embodiments shown and described herein. [Diagram 2]

[0006] 2A-2C are schematic diagrams illustrating example sub-modules of the photovoltaic device of FIG. 1 according to one or more embodiments shown and described herein. [Figure 3A]

[0007] 3A, 3B, and 3C are schematic diagrams illustrating cross-sectional views of the photovoltaic sub-module of FIG. 2 along line 3-3, according to one or more embodiments described herein. [Figure 3B] 3A, 3B, and 3C are schematic diagrams illustrating cross-sectional views of the photovoltaic sub-module of FIG. 2 along line 3-3, according to one or more embodiments described herein. [Figure 3C] 3A, 3B, and 3C are schematic diagrams illustrating cross-sectional views of the photovoltaic sub-module of FIG. 2 along line 3-3, according to one or more embodiments described herein. [Figure 4]

[0008] 1A and 1B are schematic diagrams illustrating a substrate according to one or more embodiments shown and described herein. [Diagram 5]

[0009] FIG. 2 is a schematic diagram illustrating a cross-sectional view of the tandem photovoltaic device of FIG. 1 according to one or more embodiments shown and described herein. [Figure 6]

[0010] FIG. 2A is a schematic diagram illustrating a cross-sectional view of a layer stack according to one or more embodiments shown and described herein. [Figure 7]

[0011] FIG. 1 illustrates an exemplary method, according to one or more embodiments shown and described herein. [Figure 8]

[0012] 1 is a graph showing the time resolved photoluminescence intensity (TRPL) transient curves of a CdSe layer fabricated according to the described method. [Figure 9A]

[0013] 9A, 9B, and 9C show images of the treatment layers. [Figure 9B] 9A, 9B, and 9C are images of the treatment layers. [Figure 9C] 9A, 9B, and 9C are images of the treatment layers. [Figure 10]

[0014] FIG. 1 shows the logarithm of the fractional fraction of grain orientation evaluated from electron backscatter diffraction (EBSD), a contour plot illustrating the crystallographic orientations produced from selected deposition and processing conditions. [Figure 11]

[0015] 1 is a graph showing measurements of O − and O 2 − normalized to Se − measured by time-of-flight secondary ion mass spectrometry (TOF-SIMS). [Figure 12]

[0016] FIG. 13 shows an image of Cl − measured by TOF-SIMS in a sample of the treated film. [Figure 13]

[0017] FIG. 13 is a diagram showing an image of O − measured by TOF-SIMS in a sample of the treated film. [Figure 14]

[0018] 1 is a graph showing a comparison of the emission spectra of films treated with and without Se. [Figure 15]

[0019] 1 is a graph showing the time resolved photoluminescence intensity (TRPL) transient curves of CdSe layers fabricated with and without Se treatment. [Figure 16]

[0020] 1 is a graph showing carrier density versus depletion width obtained from capacitance-voltage measurements of CdSe layers fabricated with and without Se treatment. [Figure 17]

[0021] 13 is a graph showing the change in X-ray fluorescence spectroscopy counts before and after CHT treatment of CdSe layers fabricated with and without Se treatment. [Figure 18]

[0022] 1 is a graph showing the change in apparent charge carrier density concentration in a film in response to a treatment process. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006]

[0023] SUMMARY OF THE DISCLOSURE Provided are structures and compositions for use in photovoltaic (PV) devices. Embodiments provide an absorber layer that includes or consists essentially of cadmium selenide.

[0007]

[0024] Cadmium selenide (CdSe) layers can be formed by physical vapor deposition techniques. These deposition techniques can produce as-deposited polycrystalline films that have smaller grain sizes than desired. Annealing can be used to increase the grain size, but some existing annealing techniques can result in an undesirable number of selenium vacancies (V vacancies) in the crystal lattice of the resulting polycrystalline film because selenium evaporates at a lower temperature than cadmium and selenium can react or combine with other gases that may be present during the annealing process. Se By controlling aspects of the deposition process, post-deposition treatments, and device fabrication, improved layers and photovoltaic devices can be produced.

[0008]

[0025] CdSe-based absorber layers can be used in the top submodule of a tandem module. Various embodiments and material choices for making high performance devices are provided herein. The embodiments provided herein relate to aspects of high quality CdSe-based solar cells, including the impact of material quality on performance, the formation of p-n junctions, and the architecture of n-type CdSe absorbers. Tuning the quality of the polycrystalline grains of cadmium selenide can be achieved by controlling a combination of factors. These factors include deposition conditions and post-deposition treatments. The CdSe layer can be n-type. The absorber layer including n-type CdSe can form a p-n junction with a hole contact including a p-type layer with a high band gap and large work function.

[0009]

[0026] When conditions are controlled according to the described method, the properties of the resulting polycrystalline film are improved. Using the exemplary method, average grain size of about 1.3 μm to 3.0 μm, incorporation of oxygen dopants, improved uniformity of grain size and orientation, and selenium vacancies (V Se It has been possible to fabricate polycrystalline cadmium selenide films in which the lattice orientation of (103) is reduced and the proportion of grains with a (002) lattice orientation is shifted. Devices incorporating such films have shown improved efficiency, approximately 1×10 13 ~1×10 17 in the range, average minority p-type charge carrier lifetimes of greater than 1 nanosecond (ns), and reduced propensity to delaminate.

[0010]

[0027] According to embodiments provided herein, a photovoltaic device can include an absorber layer and a hole contact. The absorber layer can include CdSe. The absorber layer can be n-type. The hole contact can form a pn junction with the absorber layer.

[0011]

[0028] According to embodiments provided herein, a tandem photovoltaic device can include an upper submodule above a lower submodule. The upper submodule can include an absorber layer and a hole contact. The absorber layer of the upper submodule can include CdSe. The absorber layer can be n-type. The hole contact can form a pn junction with the absorber layer.

[0012]

[0029] According to embodiments provided herein, a method of forming a photovoltaic device can include heating an absorber layer consisting essentially of CdSe in the presence of a halogen compound. The grain size of the absorber layer can increase and the halogen can diffuse into the absorber layer. After the halogen has diffused, the absorber layer can be heated in air to reduce the amount of halogen from the absorber layer. After the amount of halogen is present or removed, the absorber layer can be heated in a Se environment to fill vacancies in the absorber layer.

[0013]

[0030] According to embodiments provided herein, a method of forming a photovoltaic device can include depositing a CdSe layer on a layer stack by vapor transport deposition and treating the layer to modify its properties. Treating the layer can include contacting the CdSe layer with a halogen compound and, optionally, an accelerator, and heating the CdSe layer on the layer stack in a controlled environment. The controlled environment can include selenium, oxygen, and nitrogen. The method can include forming a CdSe layer in contact over a buffer layer of the layer stack. The method can include forming a hole transport layer (HTL) in contact over the CdSe layer.

[0014]

[0031] Although embodiments of the present technology relate to tandem photovoltaic devices including a first submodule and a second submodule; it should be appreciated that such tandem photovoltaic devices can include additional submodules and additional submodule features. Submodules in a tandem photovoltaic device can be stacked and separated by intermediate layers. Incident electromagnetic radiation, or light, enters the device from the front or top surface and enters the top submodule. Light that is not absorbed in the top submodule can be transmitted to the back cell or bottom submodule. Multijunction solar cells can achieve higher total conversion efficiencies than single junction cells by capturing a larger portion of the solar spectrum. These devices can be formed of materials with different bandgap characteristics that respond to different ranges of the spectrum. For devices where the primary light source comes from above, the light incident on the top cell can have a large bandgap to capture the energetic short wavelengths, while the bottom cell can have a smaller bandgap to capture the longer wavelengths and reflected photons.

[0015]

[0032] Tandem photovoltaic devices can include bifacial devices configured to receive incident radiation from both the front and back sides. A bifacial tandem device can be configured to receive direct solar radiation on a top or front side and radiation reflected from an external surface, including visible and infrared light, on a back or back side.

[0016]

[0033] Tandem photovoltaic devices can generate electrical power by converting light into direct current electricity using semiconductor materials that exhibit the photovoltaic effect. When exposed to light, the photovoltaic effect generates electrical power when photons are absorbed in the semiconductor material, exciting electrons to a higher energy state. These excited electrons can move within the material, thereby generating an electrical current. Each submodule of a tandem device may include one or more semiconductor materials. Semiconductor materials suitable for use in photovoltaic devices can include, for example, Type II-VI materials, including cadmium selenide and cadmium telluride alloys; Type III-V materials, including GaAs and InGaN; Type I-III-VI materials, including CIGS and CIS materials; and perovskites, including amorphous silicon a-Si, and organic-inorganic ABX3 materials.

[0017]

[0034] The term "light" can refer to various wavelengths in the electromagnetic spectrum, such as, but not limited to, wavelengths in the ultraviolet (UV), infrared (IR), and visible portions of the electromagnetic spectrum. As used herein, "sunlight" refers to light emitted from the sun.

[0018]

[0035] The term "layer" can refer to a thickness of material provided on a surface. A layer can cover all or part of a surface. A layer can include sublayers and can have a compositional gradient within the layer. A layer can include one or more functional material layers.

[0019]

[0036] Unless otherwise indicated, values ​​of material properties correspond to conditions at normal temperature and pressure, i.e., 20° C. and 1 atmosphere pressure.

[0037] Unless otherwise indicated, values ​​in the ranges provided are inclusive of the endpoints and include all distinct values ​​and further divided ranges throughout the range.

[0020]

[0038] In this specification, terms such as first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or sections, but these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer, or section from another region, layer, or section. As used herein, terms such as "first", "second", and other numerical terms do not imply any order or sequence unless clearly indicated by the context. Thus, a first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section without departing from the teachings of the exemplary embodiments.

[0021]

[0039] With respect to the disclosed methods, the order of steps presented is exemplary in nature and, thus, unless expressly stated otherwise, the order of steps may vary in different embodiments, including instances where certain steps may be performed simultaneously.

[0022]

[0040] When an element or layer is referred to as being "on" or "engaged", "connected" or "coupled" to another element or layer, the element or layer may be directly on, engaged, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element or layer is referred to as being "directly on" or "directly engaged", "directly connected" or "directly coupled" to another element or layer, there may not be an intervening element or layer. Other words used to describe the relationship between elements should be interpreted similarly (e.g., "between" vs. "directly between", "adjacent" vs. "directly adjacent", etc.). As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used herein, "a" and "an" indicate that "at least one" of an item is present; where possible, more than one of such items may be present.

[0023]

[0041] Spatially relative terms such as "inner," "outer," "beneath," "below," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature, for example, as shown in the figures. Spatially relative terms may be intended to encompass different orientations of the device during manufacture, or during use or operation, in addition to the orientation shown in the figures. For example, if a device in the figures is turned over, elements described as "below" or "down" other elements or features would be oriented "above" the other elements or features. The device may be oriented differently (rotated 90 degrees or at another orientation) and the spatially relative descriptors used herein would be interpreted accordingly.

[0024]

[0042] As used herein, the term "absorber layer" refers to a semiconductor layer in which the absorption of electromagnetic radiation excites electrons in the absorber layer from a lower energy "ground state" or "valence band," where they are bound to specific atoms in the solid, to a higher energy "excited state" or "conduction band" where they can move around within the solid.

[0025]

[0043] As used herein, an "n-type layer" refers to a semiconductor layer having electron donors that provide excess electrons as majority carriers in the conduction band, while a "p-type layer" refers to a semiconductor layer having electron acceptors that cause a deficiency of electrons (also called an excess of "holes") in the valence band to function as majority carriers. In each case, the excess carriers (electrons or holes) may be provided by chemically doping the semiconductor with a suitable dopant, or may be generated by intrinsic properties and defects present in the material. In the case of junction partners in a PV device, n-type and p-type layers or materials interface with each other to form a pn junction.

[0026]

[0044] Doped semiconductors that are p-type or n-type may be further characterized based on the density of their respective majority charge carriers. Although the boundary is not strict, it is generally believed that the electron acceptor carriers (i.e., "holes") are approximately 1×10 11 cm -3 ~Approx. 1×10 17 cm -3 in the range, the material is generally considered p-type, with an acceptor carrier density of approximately 1 × 10 17 cm -3 If the electron donor carriers exceed 1×10, the material is considered to be p+ type. 11 cm -3 ~Approx. 1×10 17 cm -3 in the range, the material is considered n-type, with a donor carrier density of approximately 1 × 10 17 cm -3, it is considered n+ type. The boundary is not strict and may overlap. This is because a layer can be p+ for a p-type layer (or n+ for an n-type layer) if the carrier concentration is at least two orders of magnitude (i.e., 100 times) higher, regardless of the absolute carrier density. Furthermore, at about 1×10 19 cm -3 A charge density greater than is sometimes considered to be of "++" type, and thus a layer of either n-type or p-type can be "++" relative to a layer of the same type that is itself "+" relative to a third layer if the carrier density of the same type in the ++ layer is more than 100 times that of the + layer.

[0027]

[0045] Turning now to the figures and with reference to Figures 1 and 5, an embodiment of a tandem photovoltaic device 300 is shown. As photons are absorbed from light and converted to electrical current by the photovoltaic effect, the tandem photovoltaic device 300 can be configured to receive light and convert the light into electrical energy. For discussion and clarity, the tandem photovoltaic device 300 can define a front side 302 configured to face a primary light source, such as the sun. Additionally, the tandem photovoltaic device 300 can also define a back side 304 offset from the front side 302, for example, by multiple layers of functional material.

[0028]

[0046] The tandem photovoltaic device 300 may have an upper submodule 100, a lower submodule 500, and an intermediate layer 400 therebetween. The upper submodule 100 may also be referred to as a top cell, a front cell, or a first submodule. The lower submodule 500 may also be referred to as a bottom cell, a back cell, or a second submodule. The intermediate layer 400 may also be referred to as an intermediate layer stack, a dielectric stack, or a transparent bonding layer. The upper submodule 100, the lower submodule 500, and the intermediate layer 400 may each include multiple layers. Each of the upper submodule 100 and the lower submodule 500 of the tandem photovoltaic device 300 may include one or more absorber layers for converting light into charge carriers and conductive layers for collecting the charge carriers.

[0029]

[0047] The top sub-module 100 can have a first surface 102 that substantially faces the front side 302 of the tandem photovoltaic device 300 and a second surface 104 that substantially faces the back side 304 of the photovoltaic device 300. The intermediate layer 400 can have a first surface 402 that substantially faces the front side 302 of the photovoltaic device 300 and a second surface 404 that substantially faces the back side 304 of the photovoltaic device 300. The bottom sub-module 500 can have a first surface 502 that substantially faces the front side 302 of the photovoltaic device 300 and a second surface 504 that substantially faces the back side 304 of the photovoltaic device 300.

[0030]

[0048] As shown in FIG. 1 , incident light (hv) 10 enters the front side 302 of the tandem photovoltaic device 300 through the top submodule 100, where a first portion 11 of the light energy can be absorbed by the top submodule 100 and the remaining portion 12 of the light energy can pass through the top submodule 100 to the middle layer 400. In the middle layer 400, the reflected light 13 can return toward the absorbing region of the top submodule 100 and the transmitted light 14 can reach the bottom submodule 500. Optionally, in a bifacial tandem device, the backside light energy 16 can enter the backside 304 of the tandem photovoltaic device 300 toward the bottom submodule 500. In many implementations, the backside light energy 16 can include external reflected visible and near infrared light. The top submodule can absorb the first portion 11 of the light energy, which can include an absorbed combination of the incident light 10 and the reflected light 13. The bottom sub-module can absorb a second portion 15 of the light energy, including transmitted light 14 and, optionally, backside light energy 16 .

[0031]

[0049] 2, an exemplary embodiment of a top submodule 100 of a tandem photovoltaic device 300 is shown. The top submodule 100 can include multiple layers disposed between a front side 102 and a back side 104. In some embodiments, the layers of the top submodule 100 can be divided into an array of photovoltaic cells 200. For example, the top submodule 100 can be scribed according to multiple series scribes 202 and multiple parallel scribes 204. The series scribes 202 can extend along the length Y of the top submodule 100 and separate the photovoltaic cells 200 along the length Y of the top submodule 100. Adjacent cells of the photovoltaic cells 200 can be connected in series along the width X of the top submodule 100. In other words, monolithic interconnects of adjacent cells 200 can be formed, for example, adjacent to the series scribes 202. The parallel scribes 204 extend along the width X of the top submodule 100 and can separate the photovoltaic cells 200 along the width X of the top submodule 100. In operation, current 205 flows primarily along the width X through the photovoltaic cells 200 connected in series by the series scribes 202. In operation, the parallel scribes 204 can limit the ability of the current 205 to flow along the length Y. The parallel scribes 204 are optional and can be configured to separate the series connected photovoltaic cells 200 into groups 206 arranged along the length Y.

[0032]

[0050] 2, the parallel scribes 204 can electrically isolate groups 206 of photovoltaic cells 200 connected in series. In some embodiments, the groups 206 of photovoltaic cells 200 can be connected in parallel, for example, via electrical bussing. Optionally, the number of parallel scribes 204 can be configured to limit the maximum current generated by each group 206 of photovoltaic cells 200. In some embodiments, the maximum current generated by each group 206 can be about 200 milliamps (mA) or less, such as about 100 mA or less in one embodiment, about 75 mA or less in another embodiment, or about 50 mA or less in a further embodiment.

[0033]

[0051] 3A-3C, the layers of the upper submodule 100 may include a thin film stack including multiple layers. These layers may be provided on a substrate 110. The substrate 110 may be configured to facilitate the transmission of light to the upper submodule 100. The substrate 110 may be disposed on a front side 102 of the upper submodule 100. The substrate 110 may have a first surface 112 that substantially faces the front side 102 of the upper submodule 100 and a second surface 114 that substantially faces the rear side 104 of the upper submodule 100. One or more layers of material may be disposed between the first surface 112 and the second surface 114 of the substrate 110.

[0034]

[0052] 4, the substrate 110 may include a transparent layer 120 having a first surface 122 substantially facing the front side 102 of the upper submodule 100 and a second surface 124 substantially facing the rear side 104 of the upper submodule 100. In some embodiments, the second surface 124 of the transparent layer 120 may form the second surface 114 of the substrate 110.

[0035]

[0053] The transparent layer 120 can include a substantially transparent material, such as, for example, glass. Suitable glasses can include soda-lime glass or any glass with reduced iron content. The transparent layer 120 can have any suitable transmittance range, including, in some embodiments, from about 250 nm to about 1,300 nm. The transparent layer 120 can also have a transmittance percentage, including, for example, in one embodiment, about 50% or more, in another embodiment, about 60% or more, in yet another embodiment, about 70% or more, in a further embodiment, about 80% or more, or in a further embodiment, about 85% or more. In one embodiment, the transparent layer 120 can be formed from a glass having a transmittance of about 90% or more. Optionally, the substrate 110 can include a coating 126 applied to the first surface 122 of the transparent layer 120. The coating 126 can be configured to interact with light or improve the durability of the substrate 110, including, but not limited to, an anti-reflective coating, an anti-soiling coating, or a combination thereof.

[0036]

[0054] 3A-3C, the upper submodule 100 may include a barrier layer 130 configured to mitigate diffusion of contaminants from the substrate 110 that may lead to degradation or delamination of other layers of the photovoltaic stack. The barrier layer 130 may have a first surface 132 that substantially faces the front side 102 of the upper submodule 100 and a second surface 134 that substantially faces the back side 104 of the upper submodule 100. In some embodiments, the barrier layer 130 may be provided adjacent to the substrate 110. For example, the first surface 132 of the barrier layer 130 may be provided on the second surface 114 of the substrate 110.

[0037]

[0055] In general, the barrier layer 130 may be substantially transparent, thermally stable, have a low number of pinholes, have the ability to block sodium, and have good adhesion. The barrier layer 130 may include one or more layers of material. Exemplary materials include, but are not limited to, tin oxide, silicon dioxide, aluminum doped silicon oxide, silicon oxide, silicon nitride, or aluminum oxide. The barrier layer 130 may have a thickness bounded by a first surface 132 and a second surface 134. In one example, the barrier layer thickness may be greater than 5 nanometers (nm), greater than or equal to 10 nm, or greater than or equal to 15 nm. In one example, the barrier layer thickness may be less than or equal to 50 nm, less than 40 nm, or less than or equal to about 20 nm.

[0038]

[0056] The top submodule 100 can include an n-type contact layer 150. The n-type contact layer 150 may also be referred to as a negative charge transport layer, n-type contact, e-selective contact, electron transport layer (ETL), or electron selective layer. As a selective contact to the absorber, this layer helps direct electrons from the absorber to the highly conductive electron contact while minimizing holes that may recombine at that contact. Additionally, this layer includes a highly conductive region that can direct electrons without significant series resistance. The n-type contact layer 150 can have a first surface 152 that substantially faces the front side 102 of the top submodule 100 and a second surface 154 that substantially faces the back side 104 of the top submodule. The n-type contact layer 150 has a thickness defined by the distance between the first surface 152 and the second surface 154. In some embodiments, the thickness of the n-type contact layer 150 is greater than 2 nm, in the range between 10 nm and 180 nm, or in one exemplary embodiment, in the range between 15 nm and 80 nm.

[0039]

[0057] The n-type contact layer 150 can include n++ or n+ materials, or a combination thereof. The n-type contact layer 150 can include a conductive oxide. In one example, the n-type contact layer 150 can include materials including, but not limited to, tin dioxide, doped tin dioxide (e.g., F-SnO2), indium tin oxide, or cadmium tin oxide (Cd2SnO4).

[0040]

[0058] The upper submodule 100 includes an absorber layer 160 that includes a material configured to cooperate with adjacent layers to form a p-n junction in a photovoltaic device. Thus, absorbed photons of light can release electron-hole pairs, generating carrier flow to generate electrical power. The absorber layer 160 can have a first surface 162 that substantially faces the front side 102 of the upper submodule 100 and a second surface 164 that substantially faces the back side 104 of the upper submodule. A thickness of the absorber layer 160 can be defined between the first surface 162 and the second surface 164. In an exemplary device, the thickness of the absorber layer 160 can be between about 200 nm and about 10,000 nm. In some examples, the thickness of absorber layer 160 is 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1100 nm, 1200 nm, 1300 nm, 1500 nm, 1600 nm, 1800 nm, 2000 nm, 2200 nm or more, or 2400 nm or more. In some examples, the thickness of absorber layer 160 is 10000 nm, 5000 nm, 4000 nm, 3500 nm, 3000 nm, 2800 nm, 2500 nm, 2000 nm, 1800 nm, 1600 nm, 1500 nm, 1300 nm or less, or 1200 nm or less. In one example, the absorber layer has a thickness in the range of 700 nm to 1500 nm, and in another example, the absorber layer has a thickness in the range of 1200 nm to 2500 nm.

[0041]

[0059] The absorber layer 160 can include a polycrystalline II-VI thin film semiconductor in which electrons are excited to produce a photovoltaic effect. The absorber layer 160 can include an n-type material. The absorber layer can be n-type throughout its thickness. The absorber layer can include CdSe. The absorber layer can consist essentially of CdSe. The absorber layer can include cadmium, selenium, and one or more dopants. In some embodiments, the absorber layer 160 includes a dopant selected from oxygen, chlorine, rubidium, sulfur, bromine, fluorine, iodine, cesium, potassium, sodium, lithium, or a combination thereof.

[0042]

[0060] In some embodiments, the absorber layer has compositional and structural properties that reduce the recombination rate of charge carriers, increase the carrier diffusion length, and extend the carrier lifetime. These properties can include, for example, layer thickness, stoichiometry, dopant concentration, vacancy concentration, grain size, and polycrystalline structure and orientation. In some embodiments, the average carrier diffusion length is greater than 10 nm, 20 nm, 50 nm, 70 nm, 100 nm, 200 nm, 700 nm, 800 nm, 1000 nm, 1200 nm, or is in the range of 20 nm to 1500 nm. In some embodiments, the average carrier lifetime is greater than 1 ns, 2 ns, 5 ns, 10 ns, 15 ns or more, greater than 20 ns, or is in the range of 1 ns to 100 ns.

[0043]

[0061] In some embodiments, the atomic concentration of oxygen in the central region 166 of the absorber layer 160 is about 1×10 16 cm -3 For example, in one embodiment, about 1×10 17 cm -3 ~Approx. 5×10 20 cm -3 and in another embodiment, about 3×10 17 cm -3 ~Approx. 1×10 19 cm -3 , or in a further embodiment, about 5×10 17 cm -3 ~Approx. 5×10 18 cm -3In some embodiments, the absorber layer may have a 1×10 17 cm -3 ~1×10 19 cm -3 The central region 166 is the central 50% of the absorber layer 160 and is offset from each of the first surface 162 and second surface 164 of the absorber layer 160 by 25% of the thickness of the absorber layer 160. Alternatively or additionally, the concentration profile of oxygen can be varied across the thickness of the absorber layer 160.

[0044]

[0062] In some embodiments, the atomic concentration of chlorine in the central region 166 of the absorber layer 160 is about 1×10 21 cm -3 For example, in one embodiment, less than about 1×10 17 cm -3 ~Approx. 1×10 21 cm -3 and in another embodiment, about 5×10 17 cm -3 ~Approx. 1×10 20 cm -3 , or in a further embodiment, about 5×10 17 cm -3 ~Approx. 5×10 19 cm -3 It could be.

[0045]

[0063] The top submodule 100 includes a hole contact 180. The hole contact 180 may also be referred to as a positive charge transport layer, a p-type contact, a hole transport material, a hole transport layer (HTL), an h+selective contact, or a hole selective layer. The hole contact 180 provides an electrical contact to the absorber layer 160. The hole contact 180 may have a first surface 182 that substantially faces the frontside 102 of the top submodule 100 and a second surface 184 that substantially faces the backside 104 of the top submodule.

[0046]

[0064] The thickness of the hole contact 180 can be defined between the first surface 182 and the second surface 184. In some embodiments, the thickness of the hole contact 180 can be between about 2 nm and about 200 nm, or between about 2 nm and about 100 nm.

[0047]

[0065] In some embodiments, the hole contact 180 is a polymer, a small molecule, or an inorganic compound. In some embodiments, the hole contact 180 comprises a metal oxide or a metal oxynitride. In some embodiments, the hole contact 180 comprises a transition metal oxide.

[0048]

[0066] The hole contact 180 can include an organic hole transport material (HTM). In one example, the hole contact includes at least one of poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine (PTAA); perylenediimide (PDI); 4,4'-bis(N-carbazolyl)-1,1'-biphenyl (CBP); tris(4-carbazoyl-9-ylphenyl)amine (TCTA); 1,3,5-tris(carbazol-9-yl)benzene (TCP); poly(9,9-dioctylfluorene-alt-benzothiadiazole) (F8BT). In another example, the hole contact consists essentially of an organic HTM selected from PTAA, PDI, CBP, TCTA, TCP, or F8BT.

[0049]

[0067] The hole contact 180 can include inorganic materials with good valence band alignment and wide band gaps. In one example, the hole contact can be made of copper aluminum sulfide (CuAlS2); copper aluminum selenide (CuAlSe2); copper gallium oxide (CuGaO2); magnesium germanium phosphide (GeMgP2); boron phosphide (BP); gallium phosphide (GaP), zinc selenide (ZnSe); or tantalum oxynitride (TaO x N (1-x) ) includes at least one of the following.

[0050]

[0068] In some embodiments, the hole contact 180 comprises a p-type transparent conductive oxide. In some embodiments, the p-type transparent conductive oxide is nickel oxide (NiO x ) or tin oxide (SnO x In some embodiments, the p-type transparent conductive oxide is doped with at least one of boron (B), magnesium (Mg), nitrogen (N), antimony (Sb), or a combination thereof.

[0051]

[0069] In some embodiments, the hole contact 180 comprises a p-type alloy including at least one of zinc (Zn), sulfur (S), selenium (Se); and tellurium (Te).

[0070] In some embodiments, the hole contact 180 comprises an inorganic compound selected from nickel oxide (NiOx), cuprous thiocyanate (CuSCN), copper iodide (CuI), or copper oxide (Cu2O).

[0052]

[0071] The hole contact 180 can combine materials with wide bandgaps and high work functions. In some embodiments, the hole contact 180 includes a buffer sub-layer and a contact sub-layer. In one example, the buffer sub-layer is made of molybdenum sulfide (MoS x ) or tungsten sulfide (WS x In one example, the contact sub-layer may include niobium disulfide (NbS2), vanadium sulfide (V x S x ), vanadium(II) sulfide (VS), tantalum sulfide (TaS x ), Tantalum(IV) sulfide (TaS2), Titanium sulfide (Ti x S x ), titanium(IV) sulfide (TiS2), or a combination thereof.

[0053]

[0072] The composition of the hole contact 180, or the composition of a sublayer of the hole contact 180, can be selected to provide a buffer and an ohmic contact, or to have good work function and band gap alignment to adjacent layers. In some embodiments, the material of the hole contact 180 has a work function greater than 5 eV. The hole contact 180 can be p-type or p+ type.

[0054]

[0073] The hole contact 180 may form a pn junction 176 with the absorber layer 160. The hole contact 180 may include a p-type layer of the pn junction 176, and the absorber layer may include an n-type layer of the pn junction.

[0055]

[0074] The top submodule 100 may include a transparent conductive layer 140 configured to provide electrical contacts for transporting charge carriers generated by the first submodule 100. The transparent conductive layer 140 may have a first surface 142 that substantially faces the front side 102 of the first submodule 100 and a second surface 144 that substantially faces the back side 104 of the first submodule 100. The transparent conductive layer 140 may be disposed between the absorber layer and the front side 102 of the first submodule 100. A p-type hole contact 180 may be disposed between the n-type absorber layer 160 and the transparent conductive layer 140. In some embodiments, for example in FIG. 3B, the transparent conductive layer 140 may be p+ type. In some embodiments, for example in FIGS. 3A and 3C, the transparent conductive layer 140 may be n-type or n+ type.

[0056]

[0075] The top submodule 100 may optionally include a conductive layer 190. The conductive layer 190 may have a first surface 192 that substantially faces the energy side 102 of the photovoltaic device and a second surface 194 that substantially faces the back side 104 of the photovoltaic device.

[0057]

[0076] In some embodiments, the top sub-module 100 may include a p+ / n+ tunnel or recombination junction 175. In some embodiments, the hole contact 180 may form the p+ layer of the p+ / n+ junction 175. In some embodiments, the n+ layer 170 may form the n+ layer of the p+ / n+ junction 175.

[0058]

[0077] The function of the p+ / n+ junction is twofold. First, significant band bending occurs, creating a narrow depletion width across the p+ / n+ junction, allowing electrons and holes to tunnel or recombine. This process converts holes, which were majority carriers in the p contact, into electrons, which are majority carriers in the n+ region. The second function of the electron collecting side of the p+ / n+ junction is to provide sufficiently low resistance to the lateral transport of current, which can be achieved through the n+ or n++ portion of the TCO-like layer. These functions can be provided through the use of single layers, layers with sublayers, or multiple n-type layers, including one or more n+ and / or n++ layers.

[0059]

[0078] In some embodiments, the n+ side of the n+ / p+ junction 175 includes a layer 170 of n+ doped metal oxide, the metal oxide layer including at least one of the following materials: fluorine doped tin oxide (SnO2:F); indium tin oxide (ITO), cadmium tin oxide (Cd2SnO4), tungsten (VI) oxide (WO3), molybdenum (VI) oxide (MoO3), chromium (VI) oxide (CrO3), vanadium (V) oxide (VO5), or combinations thereof. In some embodiments, the n+ side of the n+ / p+ tunnel junction includes at least one of the following materials: gallium phosphide (GaP); boron phosphide (BP); zinc selenide (ZnSe), or combinations thereof.

[0060]

[0079] The photovoltaic device 100 may optionally include one or more intermediate layers, a diffusion barrier layer, and / or one or more secondary buffer layers. The addition of one or more barrier or buffer layers may be used to inhibit diffusion of dopants or contaminants between layers. The buffer layer may be utilized to reduce the number of irregularities that arise during the formation of the semiconductor. The buffer layer may be configured to provide an insulating layer between adjacent layers. The buffer layer may include a material having a higher resistivity than the adjacent layers, including, but not limited to, intrinsic tin dioxide, zinc magnesium oxide (e.g., Zn 1-x Mg x The buffer layer may include a material selected from the group consisting of tin oxide (Si02), tin dioxide (SnO2), silicon dioxide (SiO2), aluminum oxide (Al2O3), aluminum nitride (AlN), zinc tin oxide, zinc oxide, tin silicon oxide, or combinations thereof. In some embodiments, the material of the buffer layer may be configured to substantially match the band gap of the adjacent semiconductor layer. The buffer layer may have a thickness including, for example, about 10 nm or more in one embodiment, between about 10 nm and about 80 nm in another embodiment, or a range of 15 nm to 60 nm in further embodiments.

[0061]

[0080] The sub-module may further include additional layers and structural components including, but not limited to, one or more of a buffer layer, a barrier layer, an interface layer, a dielectric layer, a conductive layer, a support layer, an anti-reflective layer, scribing, encapsulation, a bus, and combinations thereof.

[0062]

[0081] In a substrate structured device, the device can be formed from the back surface to the front surface of the substrate. In a superstrate structured device, the device can be formed from the front surface to the back surface of the substrate.

[0063]

[0082] 3A shows an example of a submodule that can be prepared as a substrate structure device. In the example shown, an n-type CdSe absorber layer 160 is between and adjacent to a p-type hole contact layer 180 and an n-type contact 150.

[0064]

[0083] 3B and 3C show an example of a submodule that can be prepared as a superstrate structured device. An n-type CdSe absorber layer 160 is between a p-type hole contact layer 180 and an n-type contact 150. In the example shown, the n+ or n++ layer is provided by a transparent conductive layer 140.

[0065]

[0084] An example of a submodule is shown in FIG. 3C. In this example, a p-type hole contact layer 180 is between the n-type CdSe absorber layer 160 and the transparent conductive layer 140. This configuration can be facilitated by using an n+ / p+ junction 175. In some embodiments, the hole contact also serves as the p+ layer of the p+ / n+ junction. Alternatively, in some embodiments, an additional p+ layer is between the hole contact 180 and the absorber layer 160. The use of n++ type TCOs can be chosen as a practical option due to the greater number of composition options for good transparent conductive oxides of n-type rather than p-type. Therefore, when using n-type photovoltaic absorbers in a superstrate configuration, it can be advantageous to use an n+ / p+ junction to convert the carrier type and create a pn junction on the front side of the absorber on the light incident side. For devices with good p++ layers containing one or more materials, the structure can be simplified to a submodule architecture of p++ / p+ / HTL / CdSe-n / ETL / n+ / n++ from front to back.

[0066]

[0085] FIG. 6 shows a layer stack of a partially formed device. The absorber stack 600 includes a substrate stack 610 and a semiconductor film 660. The absorber stack 600 can have a first surface 602 and a second or exposed surface 604. The substrate stack 610 includes a substrate layer and a number of layers formed on the substrate layer. The semiconductor film 660 includes an as-deposited absorber material. The semiconductor film 660 is provided as a layer on the surface of the absorber stack 600, and the as-deposited absorber precursor material can be treated to form an absorber layer. The semiconductor film 660 can have a first surface 662 or stack-contact surface and a second surface or exposed surface 664. Treatment of the as-deposited semiconductor layer 660 can be applied to an exposed surface 664 of the film that corresponds to the exposed surface 604 of the absorber stack 600.

[0067]

[0086] In embodiments formed in a superstrate configuration, the absorber stack 600 may have a first surface 602 that substantially faces the front side 102 of the first submodule 100 and a second surface 604 that substantially faces the back side 104 of the first submodule 100. The substrate stack 610 may have a first surface 612 that substantially faces the front side 102 of the first submodule 100 and a second surface or exposed surface 614 that substantially faces the back side 104 of the first submodule 100. A semiconductor film 660 including CdSe may be deposited adjacent the substrate stack with the first surface 662 in direct contact with the second surface 614 of the substrate stack to form the absorber stack 600.

[0068]

[0087] A photovoltaic device can contain multiple layers of material deposited sequentially on a substrate. The steps for fabricating a photovoltaic device may include sequentially arranging functional layers or layer precursors in a "stack" of layers through one or more deposition processes, including, but not limited to, spin coating, spray coating, slot coating, blade coating, dip coating, sputtering, evaporation, molecular beam deposition, pyrolysis, closed space sublimation (CSS), pulsed laser deposition (PLD), chemical vapor deposition (CVD), electrochemical deposition (ECD), atomic layer deposition (ALD), or vapor transport deposition (VTD). The as-deposited layer or layer stack may be treated to modify properties using one or more methods, for example, by annealing, passivation, heating, vapor contact, or chemical treatment. Fabrication of a photovoltaic device may further include selectively removing portions of certain layers of the stack of layers, such as by scribing, to divide the photovoltaic device into multiple photovoltaic cells.

[0069]

[0088] An exemplary method is shown in Figure 7. The method includes providing a substrate layer stack 710; depositing a semiconductor film to form an absorber stack 720; contacting the film with a halogen composition 730; and heating the absorber layer stack in a controlled environment 740.

[0070]

[0089] The step 710 of providing a substrate layer stack can include preparing an exposed surface 614 of the substrate stack 610. In some embodiments, the exposed surface 614 can be substantially smooth. In an exemplary method of preparing a submodule in a substrate orientation, the substrate layer stack 610 has an n-type top layer that can include a buffer material and an electron transport layer having a smooth top surface 614. In an exemplary method of preparing a submodule in a superstrate orientation, the substrate layer stack 610 can include a p-type hole transport material. Optionally, the p-type hole transport material can be the p+ layer of a p+ / n+ junction on which a semiconductor film is deposited to form an absorber layer.

[0071]

[0090] The step of depositing the semiconductor film 720 can include depositing cadmium selenide by vapor transport deposition (VTD). It has been found that using VTD can produce higher quality films compared to other physical deposition methods. The quality of the resulting film can also be adjusted by controlling the deposition temperature. In one example, the layer is deposited at a temperature of about 520° C., in the range of 480-560° C., or in the range of 500-540° C. using N2 or N2 with a low oxygen percentage as the carrier gas.

[0072]

[0091] The step 730 of contacting the film with the halogen composition can include contacting the film with an alkali metal halide. The step 730 of contacting the film with the halogen composition can include contacting the film with an alkali metal chloride. This step may further include contacting the film with a promoter. The contacting step may include providing the composition as a liquid, gel, or vapor. In some embodiments, the halogen compound includes at least one of CdCl2, NH4Cl, CdBr2, CdI2, MgCl2, or Ba(ClO3)2. In some embodiments, the promoter includes at least one of Li, Na, K, Rb, or Cs. In one example, the contacting step can include contacting the film with cadmium chloride and rubidium chloride.

[0073]

[0092] The step 740 of heating the absorber layer stack in a controlled environment can include providing an oxygenated environment. In some embodiments, the environment includes Se. The step 740 of heating the absorber layer stack in a controlled environment can be performed after or simultaneously with the step of contacting the absorber layer stack with a halogen composition. The halogen composition may include cadmium chloride or other chloride compounds. The step 740 of heating the absorber layer stack in a controlled environment can also be referred to as a chloride heat treatment (CHT) or annealing step. Heating in the presence of oxygen and optionally selenium after or while applying the halogen composition and optionally an accelerator can promote grain growth and diffusion of chloride and oxygen to grain boundaries and the bulk or central region of the absorber, reducing selenium vacancies in the film. The use of selenium in a controlled environment further reduces selenium vacancies.

[0074]

[0093] In some embodiments, the environment includes O2 in an amount of 2%, 5%, 10%, 12%, 15%, 18% or more, or in an amount up to 25% range, or in an amount up to 20% range. In some embodiments, the environment includes Se in an amount of 0.001%, 0.01%, 0.05%, 0.1%, 0.5%, 1.0% or more, up to 5.0% range, up to 2.5% range, or up to 2.0% range. In some embodiments, the controlled environment includes selenium vapor at a partial pressure in the range of 0.01 Torr to 60 Torr, or in the range of 0.1 Torr to 30 Torr. In some embodiments, the temperature of the controlled environment is 300° C., 320° C., 340° C., 350° C., 360° C., 370° C., 380° C., 390° C., or 400° C. or more. In some embodiments, the temperature of the controlled environment is equal to or less than 520° C., 500° C., 490° C., 480° C., 470° C., 460° C., or 450° C. In some embodiments, the temperature of the controlled environment is in the range of 380° C. to 500° C. In some embodiments, the temperature of the controlled environment is in the range of 380° C. to 475° C. In some embodiments, the temperature of the controlled environment is in the range of 400° C. to 440° C. In some embodiments, the pressure of the controlled environment is equal to or less than about 760 Torr (1 atmosphere). In some embodiments, the pressure of the controlled environment is in the range of 250 Torr to about 760 Torr. In some embodiments, the pressure of the environment is in the range of 250 Torr to about 500 Torr. In some embodiments, the pressure of the environment is in the range of 1.0 Torr to about 500 Torr. In some embodiments, the pressure of the environment is in the range of 50 Torr to 500 Torr, the partial pressure of oxygen is in the range of 1.0 Torr to 125 Torr, and the partial pressure of selenium is in the range of 0.1 Torr to 30 Torr. In some embodiments, heating the absorber layer stack in the controlled environment is performed for a period of at least 20 minutes, at least 40 minutes, at least 60 minutes, at least 90 minutes, at least 120 minutes, or at least 180 minutes. In some embodiments, heating the absorber layer stack in the controlled environment is performed for a period of less than 24 hours, less than 18 hours, less than 12 hours, less than 10 hours, less than 8 hours, less than 6 hours, less than 5 hours, less than 4 hours, or less than or equal to 3 hours.In some embodiments, the step of heating the absorber layer stack in the controlled environment is performed for a period of 1 to 6 hours. In some embodiments, the step of heating the absorber layer stack in the controlled environment is performed for a period of 1 to 3 hours.

[0075]

[0094] Selected deposition methods and different post-deposition treatments were used to prepare and process example absorber layers, and the resulting absorber layers were characterized.

[0095] FIG. 8 shows the time resolved photoluminescence intensity (TRPL) transient curves of the as-deposited and post-CHT CdSe films. The slower TRPL transient decay indicates improved minority carrier lifetime. Line 810 shows the results for the as-deposited film without treatment, line 820 shows the results after 1 hour of treatment, and line 830 shows the results after 3 hours of treatment. The as-deposited sample has a short lifetime. The CHT treatment process improves the lifetime, and longer treatment times further increase the lifetime. Average lifetime: as-deposited = 0.04 ns (40 ps); 1 hour = 1 ns; 2 hours = 2 ns. Grain size also increases with CHT time.

[0076]

[0096] 9A, 9B, and 9C show optical microscope images at 100x magnification, illustrating grain growth with increasing CHT time. In some embodiments, the absorber layer is a polycrystalline film with a thickness in the range of 0.25 μm to 2.0 μm and an average grain size in the range of 1.3 μm to 3.0 μm. In some embodiments, the average grain size is equal to or greater than the thickness of the absorber layer.

[0077]

[0097] FIG. 10 shows orientation contours after CHT with (hkl) Miller indices indicating the orientation of the crystal planes. FIG. 10 shows the logarithm of the ratio of (002) to (103) orientations. For example, contour 1040 labeled 2-3 indicates that the area fraction of grains with (002) orientation is 100 to 1000 times that of (103) grains. The graph shows contours 1040, 1030, 1020, and 1010, indicating the shift in the area fraction of grains with (002) orientation relative to (103) grains. The data correspond to samples deposited at 480°C, 520°C, or 460°C, with no CHT treatment, or treated at 400°C or 440°C. In particular, the film deposited at 520°C starts out as (002) and changes increasingly to (103) with CHT temperature and time. The sample deposited at 560C shown on the right is predominantly (002). Without wishing to be bound by theory, it has been found that films with a higher percentage of (103) orientation may also improve optoelectronic properties. During growth, the film tends to nucleate as (002) and at low temperature deposition, the film is more random with respect to the (002)(103) orientation. During recrystallization, the orientation shifts to (103) and the surface energy decreases.

[0078]

[0098] In one example, the film has a first crystal structure as deposited, a first predominant crystal orientation, and a first average grain size. After processing, the film has a second processed crystal structure, a second predominant crystal orientation, and a second average grain size. In some embodiments, the absorber layer is a polycrystalline film, and the ratio of grains having a (103) orientation to a (002) orientation is 1:1 or greater.

[0079]

[0099] The concentrations of dopants and constituent elements in the absorber layer can be measured by secondary ion mass spectrometry (SIM). Figure 11 shows an example of a comparative absorber layer characterized by time-of-flight secondary ion mass spectrometry (ToF-SIMS).

[0080]

[0100] As shown in Figure 11, post-deposition treatments can produce semiconductor films with altered oxygen levels in the bulk region of the layer. Post-deposition treatments can alter the total oxygen and the ratio of O2 to Se and O2 with depth. - Adjust the ratio of O to Se detected by the absorber. - A large difference indicates the extent to which oxygen is incorporated into the film.

[0081]

[0101] Figure 11 shows the Se concentration at each depth in the comparative absorber layer sample measured by time-of-flight secondary ion mass spectrometry (TOF-SIMS). - Normalized to O - and O2 counts are shown. Oxygen levels in the bulk region or central portion of the absorber thickness can best show changes due to processing, while oxygen levels near the exposed surface (depth=0) can be affected by accidental air exposure. The four lines show results for an as-deposited layer 1110, a layer 1120 heat treated with cadmium chloride in a nitrogen environment, a layer 1130 heat treated with cadmium chloride in an air environment 1130, and a layer 1140 heat treated with cadmium chloride followed by a vacuum annealing step. The chart shows that heat treatments that promote grain growth reduce oxygen content, which can be remedied by including oxygen in a post-deposition treatment.

[0082]

[0102] Figure 12 shows Cl at grain boundaries in a CdSe layer after post-deposition cadmium chloride heat treatment in environments containing oxygen ranging from 5% to 20%. The left panel shows the captured image, and the right panel shows the same image color-inverted and converted to grayscale.

[0083]

[0103] Figure 13 shows oxygen at the grain boundaries. The left panel shows the image as it was captured, and the right panel shows the same image color inverted and converted to grayscale. Figures 12 and 13 show the same sample area at the same scale. Figures 12 and 13 show the presence of both chlorine and oxygen in the film after CHT, with higher concentrations of both along the grain boundaries.

[0084]

[0104] 14 shows measurements of CdSe semiconductor films produced with halogen and selenium vapor treatments, or with halogen but no selenium vapor treatment. Data line 1410 shows the results with the Se treatment, and data line 1420 shows the results without the Se treatment. The data show that adding a Se vapor treatment reduces the sub-bandgap intensity and improves the optoelectronic properties.

[0085]

[0105] 15 shows the time resolved photoluminescence intensity (TRPL) transient curves of CdSe layers fabricated with and without post-deposition Se treatment. Data corresponding to Se treatment is shown by line 1510. Data corresponding to the control without Se treatment is shown by line 1520. As shown, Se treatment improves the TRPL, indicating improved minority carrier lifetime.

[0086]

[0106] Figure 16 shows capacitance-voltage (CV) measurements plotting charge carrier concentration per cubic centimeter versus depth for CdSe absorbers after thermal treatment. The data set on the right shows results after treatment in a Se-containing environment, while the left shows treatment without Se. The top data set shows results after thermal treatment at about 280 C, while the bottom data set shows results after thermal treatment at about 380 C. Se reduces the apparent doping at both Se temperatures. The results show that thermal treatment in a Se-containing environment reduces Se vacancies in the polycrystalline lattice.

[0087]

[0107] FIG. 17 shows a comparison of selenium levels in the bulk region of the absorber layer for samples of CdSe layers after cadmium chloride heat treatment at either 440° C. or 460° C., either with selenium vapor (right data bar) or without selenium vapor (left data bar). The increase in Se can be detected by X-ray fluorescence. The data shows that the layer treated with selenium vapor treatment has an increase in selenium in the CdSe layer.

[0088]

[0108] Figure 18 shows the change in apparent charge carrier concentration associated with the treatment process. Annealing with cadmium chloride in a nitrogen environment can obtain the desired grain growth, but has the detrimental effect of introducing a large number of selenium vacancies. The increase in apparent charge carrier concentration associated with the nitrogen environment is not primarily due to a change in dopant concentration, but rather to an increase in selenium vacancies, approximately 1 × 10 18 cm -3 This corresponds to a high apparent n-type charge carrier concentration of approximately 1 × 10. Increased selenium vacancies can lead to decreased carrier lifetimes, increased recombination rates, and decreased carrier diffusion lengths, resulting in lower overall efficiency. Halogen heat treatment with oxygen, or oxygen and selenium, improves the defects and reduces selenium vacancies; this post-deposition treatment reduces the apparent charge carrier concentration level in CdSe films to approximately 1 × 10. 16 cm -3 This relates to varying levels of

[0089]

[0109] The results show that n-type CdSe absorber layers deposited by vapor transport deposition at temperatures ranging from about 400 °C to about 490 °C, followed by post-deposition treatment in an oxygenated and / or selenium-enriched environment, produce devices with fewer defects, less recombination, and longer lifetimes of mobile charge carriers. Measurements show that heat treatment of the doped devices generally results in increased efficiency and V OC increased, short circuit current density increased, fill factor improved, resistance decreased, shunt decreased, and performance improved.

[0090]

[0110] It should now be appreciated that embodiments of the present disclosure provide n-type CdSe absorber layers and methods of making and processing the absorber layers.

[0111] According to embodiments provided herein, a photovoltaic device can include an absorber layer and a back contact. The absorber layer can include cadmium and selenium.

[0091]

[0112] The tandem photovoltaic device can include an upper submodule over a lower submodule. The upper submodule can include an absorber layer including cadmium and selenium or consisting essentially of CdSe, and a hole contact forming a p-n junction with the absorber layer. In an embodiment, the absorber layer is n-type, and the absorber layer has an n-type carrier concentration of 1×10 17 cm -3 In some embodiments, the absorber layer has less than 1×10 at the grain boundaries as measured by secondary ion mass spectrometry. 13 cm -3 Contains chlorine in grain boundaries at levels equal to or higher.

[0092]

[0113] A method of forming an absorber layer for a photovoltaic device includes providing a layer stack including a p-type layer; depositing a polycrystalline film on the p-type layer, where the polycrystalline film includes cadmium and selenium or consists essentially of CdSe. The method can include contacting an exposed surface of the polycrystalline film with a halogen compound and optionally an accelerator. The method can include heating the polycrystalline film in a controlled environment to form the absorber layer, where the controlled environment includes oxygen, whereby the absorber layer has an n-type carrier concentration of 1×10 17 cm -3 In some embodiments, the controlled environment includes selenium. In some embodiments, the method includes providing grain boundary chlorine of less than 1×10 at the grain boundaries as measured by secondary ion mass spectrometry. 13 In some embodiments, the method produces an absorber layer in which the average grain size of the polycrystalline film is greater than the thickness of the film.

[0093]

[0114] While particular embodiments have been illustrated and described herein, it should be understood that various other changes and modifications can be made without departing from the spirit and scope of the claimed subject matter. Moreover, although various aspects of the claimed subject matter have been described herein, such aspects need not be utilized in combination. It is therefore intended that the appended claims cover all such changes and modifications that are within the scope of the claimed subject matter.

Claims

1. 1. A tandem photovoltaic device comprising an upper sub-module on a lower sub-module, the upper sub-module comprising: an absorber layer consisting essentially of CdSe, and a hole contact; the absorber layer is n-type; The absorber layer is 1×10 １７ cm －３ and having an n-type carrier concentration of less than The absorber layer has a grain boundary with a lattice constant of 1×10 １３ cm －３ containing chlorine in grain boundaries at levels equal to or greater than 100 nm; and the hole contact forms a pn junction with the absorber layer; Tandem photovoltaic devices.

2. The tandem photovoltaic device of claim 1 , wherein the absorber layer has a carrier diffusion length of 50 nm or greater.

3. The tandem photovoltaic device of claim 1 or 2, wherein the absorber layer has a carrier lifetime of 1 ns or greater.

4. The absorber layer is 1×10 １６ cm －３ 4. The tandem photovoltaic device of claim 1 or any of claims 2-3, having an n-type carrier concentration of:

5. The tandem photovoltaic device of claim 1 or any of claims 2-4, wherein the absorber layer comprises oxygen in the grain boundaries.

6. The absorbent layer has a central region of the absorbent layer having a thickness of 1×10 １７ cm －３ ~1×10 １９ cm －３ 6. The tandem photovoltaic device of claim 1 or any of claims 2 to 5, comprising an average concentration of oxygen in the range of

7. The tandem photovoltaic device of claim 1 or any of claims 2-6, wherein the absorber layer comprises a dopant comprising rubidium (Rb).

8. The tandem photovoltaic device of claim 1 or any of claims 2-7, wherein the absorber layer is a polycrystalline film with a thickness in the range of 0.25 μm to 2.0 μm and an average grain size in the range of 1.3 μm to 3.0 μm.

9. The tandem photovoltaic device of claim 1 or any one of claims 2 to 8, wherein the absorber layer is a polycrystalline film and the ratio of grains having a (103) orientation to a (002) orientation is 1:1000 or more.

10. The tandem photovoltaic device of claim 1 or any of claims 2 to 9, wherein the hole contact comprises a high work function layer having a work function of 5 eV or greater.

11. The tandem photovoltaic device of claim 1 or any of claims 2 to 10, wherein the hole contact comprises a layer having a p-to-n-mobility ratio of less than 2.

12. the hole contact comprises a p+ layer of an n+ / p+ tunnel junction; the n+ / p+ tunnel junction has an n+ side and a p+ side; the absorber layer forms a pn junction with the p+ side of an n+ / p+ tunnel junction; A tandem photovoltaic device according to claim 1 or any one of claims 2 to 11.

13. 13. The tandem photovoltaic device of claim 12, wherein the n+ side of the n+ / p+ tunnel junction comprises a layer of n+ doped metal oxide.

14. The metal oxide layer is SnO ２ 14. The tandem photovoltaic device of claim 13, comprising: F.

15. The tandem photovoltaic device of claim 13 , wherein the metal oxide layer comprises ITO.

16. The metal oxide layer is Cd ２ SnO ４ The tandem photovoltaic device of claim 13 comprising:

17. The metal oxide layer is WO ３ The tandem photovoltaic device of claim 13 comprising:

18. The metal oxide layer is MoO ３ The tandem photovoltaic device of claim 13 comprising:

19. The metal oxide layer is CrO ３ The tandem photovoltaic device of claim 13 comprising:

20. The metal oxide layer is V ２ O ５ The tandem photovoltaic device of claim 13 comprising:

21. The tandem photovoltaic device of claim 12 , wherein the n+ side of the n+ / p+ tunnel junction is on an n-type transparent conductive oxide.

22. The tandem photovoltaic device of claim 12 , wherein the n+ side of the n+ / p+ tunnel junction comprises GaP.

23. The tandem photovoltaic device of claim 12 , wherein the n+ side of the n+ / p+ tunnel junction comprises BP.

24. The tandem photovoltaic device of claim 12 , wherein the n+ side of the n+ / p+ tunnel junction comprises ZnSe.

25. 25. The tandem photovoltaic device of claim 1 or any of claims 2-24, wherein the hole contact comprises a p-type transparent conducting oxide.

26. 26. The tandem photovoltaic device of claim 25, wherein the p-type transparent conductive oxide comprises nickel oxide.

27. 26. The tandem photovoltaic device of claim 25, wherein the p-type transparent conductive oxide comprises tin oxide.

28. 26. The tandem photovoltaic device of claim 25, wherein the p-type transparent conductive oxide is doped with B, Mg, N, Sb, or any combination thereof.

29. 25. The tandem photovoltaic device of claim 1 or any of claims 2-24, wherein the hole contact comprises a p-type alloy of Zn, S, Se, and Te.

30. The tandem photovoltaic device of claim 1 or any of claims 2-24, wherein the hole contact comprises PTAA.

31. The tandem photovoltaic device of claim 1 or any of claims 2-24, wherein the hole contact comprises PDI.

32. The tandem photovoltaic device of claim 1 or any of claims 2-24, wherein the hole contact comprises CBP.

33. The tandem photovoltaic device of claim 1 or any of claims 2-24, wherein the hole contact comprises a TCTA.

34. The tandem photovoltaic device of claim 1 or any of claims 2-24, wherein the hole contact comprises a TCP.

35. 25. The tandem photovoltaic device of claim 1 or any of claims 2-24, wherein the hole contact comprises F8BT.

36. The hole contact is CuAlS ２ 25. The tandem photovoltaic device of claim 1 or any of claims 2 to 24, comprising:

37. The hole contact is CuAlSe ２ 25. The tandem photovoltaic device of claim 1 or any of claims 2 to 24, comprising:

38. The hole contact is CuGaO ２ 25. The tandem photovoltaic device of claim 1 or any of claims 2 to 24, comprising:

39. The hole contact is GeMgP ２ 25. The tandem photovoltaic device of claim 1 or any of claims 2 to 24, comprising:

40. The tandem photovoltaic device of claim 1 or any of claims 2-24, wherein the hole contact comprises BP.

41. The tandem photovoltaic device of claim 1 or any of claims 2-24, wherein the hole contact comprises GaP.

42. 25. The tandem photovoltaic device of claim 1 or any of claims 2-24, wherein the hole contact comprises ZnSe.

43. The hole contact is TaO ｘ N （１－ｘ） 25. The tandem photovoltaic device of claim 1 or any of claims 2 to 24, comprising:

44. The hole contact is MoS ２ 25. The tandem photovoltaic device of claim 1 or any of claims 2 to 24, comprising a buffer layer comprising:

41. The hole contact is WS ２ 25. The tandem photovoltaic device of claim 1 or any of claims 2 to 24, comprising a buffer layer comprising:

42. The hole contact is NbS ２ 25. The tandem photovoltaic device of claim 1 or any of claims 2 to 24, comprising:

43. 25. The tandem photovoltaic device of claim 1 or any of claims 2-24, wherein the hole contact comprises VS.

44. The hole contact is TaS ２ 25. The tandem photovoltaic device of claim 1 or any of claims 2 to 24, comprising:

45. The hole contact is TiS ２ 25. The tandem photovoltaic device of claim 1 or any of claims 2 to 24, comprising:

46. 1. A method of forming an absorber layer of a photovoltaic device, comprising the steps of: providing a layer stack including a p-type layer; depositing a polycrystalline film over the p-type layer, said polycrystalline film consisting essentially of CdSe; contacting an exposed surface of the polycrystalline film with a halogen compound and a promoter; heating the polycrystalline film in a controlled environment to form the absorber layer, wherein the controlled environment comprises oxygen; , whereby The n-type carrier concentration of the absorber layer is 1×10 １７ cm －３ is less than The absorber layer has a grain boundary with a lattice constant of 1×10 １３ cm －３ contains grain boundary chlorine at levels equal to or greater than 100%; and the average grain size of the polycrystalline film is greater than the thickness of the film; method.

47. 47. The method of claim 46, wherein the p-type layer is a hole contact and forms a pn junction with the absorber layer.

48. 48. The method of claim 46 or 47, wherein the controlled environment comprises selenium (Se), and heating in the Se-containing controlled environment reduces Se vacancies in the polycrystalline film.

49. The halogen compound is CdCl ２ , N.H. ４ Cl, CdBr ２ , CdI ２ , MgCl ２ , or Ba(ClO ３ ) ２ 49. The method of claim 46 or any of claims 47 to 48, comprising at least one of:

50. 50. The method of claim 46 or any of claims 47-49, wherein the promoter comprises at least one of Li, Na, K, Rb, or Cs.

51. 51. The method of claim 46 or any of claims 47-50, wherein the promoter comprises rubidium chloride.

52. 52. The method of claim 46 or any of claims 47-51, wherein the step of depositing a polycrystalline film comprises depositing a film by vapor transport deposition (VTD).

53. 53. The method of claim 46 or any of claims 47-52, wherein the layer stack comprises an n+ / p+ tunnel junction and the hole contact comprises a p+ layer of the n+ / p+ tunnel junction.

54. 54. The method of claim 46 or any of claims 47-53, wherein the average grain size of the polycrystalline film is greater than 1.2 μm.

55. 1. A method of forming a photovoltaic device, comprising: annealing an absorber layer consisting essentially of CdSe in the presence of a halogen compound, whereby the grain size of the absorber layer grows and halogen diffuses into the absorber layer; and treating the absorber layer by heating in a controlled environment containing Se and O2, whereby the treatment reduces Se vacancies in the absorber layer; A method comprising:

56. 56. The method of claim 55, wherein the annealing step and the treatment step are performed sequentially, the annealing step preceding the treatment step.

57. 56. The method of claim 55, wherein the annealing step and the treating step are performed simultaneously.

58. A method according to claim 55 or any of claims 56-57, wherein the hole contact forms a pn junction with the absorber layer.

59. 1. A photovoltaic device comprising: an absorber layer comprising CdSe and being n-type; a hole contact forming a pn junction with said absorber layer; 1. A photovoltaic device comprising:

60. 60. The method or photovoltaic device of any of claims 46 to 59, wherein the absorber layer is provided in a top sub-module of a tandem photovoltaic device.

61. 61. The method or photovoltaic device of any of claims 46 to 60, wherein the absorber layer has a carrier diffusion length of 50 nm or greater.

62. 62. The method or photovoltaic device of any one of claims 46 to 61, wherein the absorber layer has a carrier lifetime of 1 ns or greater.

63. The absorber layer is 1×10 １６ cm －３ 63. The method or photovoltaic device of any of claims 46 to 62, having a p-type dopant concentration of:

64. 64. The method or photovoltaic device of any of claims 47-54 or 58-63, wherein the hole contact comprises a layer having a valence band offset greater than 0 eV with respect to the absorber layer.

65. 65. The method or photovoltaic device of any of claims 47-54 or 58-64, wherein the hole contact comprises a high work function layer having a work function of 5 eV or greater.

66. 66. The method or photovoltaic device of any of claims 47-54 or 58-65, wherein the hole contact comprises a layer having a p-to-n-mobility ratio of less than 2.

67. the hole contact comprises a p+ layer of an n+ / p+ tunnel junction; the n+ / p+ tunnel junction has an n+ side and a p+ side; the absorber layer forms a pn junction with the p+ side of an n+ / p+ tunnel junction; 67. A method or photovoltaic device according to any of claims 47 to 54 or 58 to 66.

68. 68. The method or photovoltaic device of claim 67, wherein the n+ side of the n+ / p+ tunnel junction comprises a layer of n+ doped metal oxide.

69. The metal oxide layer is SnO ２ : F, ITO, Cd ２ SnO ４ , W.O. ３ , MoO ３ , CrO ３ , or V ２ O ５ 69. The method or photovoltaic device of claim 68, comprising at least one of:

70. 70. The method or photovoltaic device of any one of claims 67 to 69, wherein the n+ side of the n+ / p+ tunnel junction is on an n-type transparent conducting oxide.

71. 71. The method or photovoltaic device of any of claims 67 to 70, wherein the n+ / p+ tunnel junction comprises at least one of GaP, BP, or ZnSe.

72. 72. The method or photovoltaic device of any of claims 47-54 or 58-71, wherein the hole contact comprises a p-type transparent conducting oxide.

73. 73. The method or photovoltaic device of claim 72, wherein the p-type transparent conductive oxide comprises nickel oxide.

74. 73. The method or photovoltaic device of claim 72, wherein the p-type transparent conductive oxide comprises tin oxide.

75. 75. The method or photovoltaic device of any of claims 72 to 74, wherein the p-type transparent conductive oxide is doped with B, Mg, N, Sb, or any combination thereof.

76. 72. The method or photovoltaic device of any of claims 47-54 or 58-71, wherein the hole contact comprises a p-type alloy of Zn, S, Se, and Te.

77. The hole contact is selected from the group consisting of PTAA, PDI, CBP, TCTA, TCP, F8BT, and CuAlS. ２ , CuAlSe ２ ,CuGaO ２ , GeMgP ２ , BP, GaP, ZnSe, TaO ｘ N （１－ｘ） , MoS ２ , W.S. ２ , NbS ２ , V.S., TaS. ２ , or TiS ２ 72. The method or photovoltaic device of any of claims 47-54 or 58-71, comprising at least one of:

78. The hole contact is MoS ２ Or W.S. ２ 78. The method or photovoltaic device of claim 77, comprising a buffer layer comprising:

79. The hole contact is CuAlS ２ 79. The method or photovoltaic device of claim 77 or 78, comprising:

80. The hole contact is CuAlSe ２ 79. The method or photovoltaic device of claim 77 or 78, comprising:

81. The hole contact is CuGaO ２ 79. The method or photovoltaic device of claim 77 or 78, comprising:

82. 79. The method or photovoltaic device of claim 77 or 78, wherein the hole contact comprises PTAA.

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