Surface Mount Multilayer Ceramic Capacitors

Abstract

The present invention is directed to a surface mount coupled capacitor. The coupled capacitor comprises a body including at least two sets of alternating dielectric layers and internal electrode layers, each set of alternating dielectric layers and internal electrode layers including a first internal electrode layer and a second internal electrode layer. Each internal electrode layer includes a top edge, a bottom edge opposite the top edge, and two side edges extending between the top edge and the bottom edge, which define the body of the internal electrode layer. The coupled capacitor includes external terminals electrically connected to the internal electrode layers, the external terminals being formed on a top surface of the coupled capacitor and on a bottom surface of the coupled capacitor opposite the top surface of the coupled capacitor. The capacitor comprises one or more dielectric regions including one or more air gaps.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 63 / 295,070, having a filing date of December 30, 2021, which is incorporated by reference herein in its entirety. [Background technology]

[0002] Multilayer coupling capacitors are typically constructed with multiple dielectric and internal electrode layers arranged in a stack. During fabrication, the stacked dielectric and internal electrode layers are pressed and sintered to obtain a substantially unitary capacitor body. In an attempt to improve the performance of these capacitors, various configurations and designs have been used for the dielectric and internal electrode layers.

[0003] However, these configurations are commonly modified as rapid changes occur in the electronics industry that require new performance standards. Specifically, various application design considerations have created the need to redefine capacitor parameters and their performance in high speed environments, especially in light of faster and higher density integrated circuits. For example, higher currents, higher density circuit boards, and rising costs have all served to focus the need for better and more efficient capacitors. Additionally, the design of various electronic components has been driven by general industry trends toward miniaturization as well as increased functionality. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 7,177,137 [Patent Document 2] U.S. Patent No. 7,463,474 Summary of the Invention [Problem to be solved by the invention]

[0005] In view of such, there is a need to provide a ceramic capacitor having improved operating characteristics. Additionally, some applications would also benefit from providing a coupling capacitor that could have a smaller footprint on a circuit board. [Means for solving the problem]

[0006] According to one embodiment of the present invention, a surface mount coupling capacitor is disclosed. The coupling capacitor comprises a body including a first set of alternating dielectric layers and internal electrode layers and a second set of alternating dielectric layers and internal electrode layers. Each set of alternating dielectric layers and internal electrode layers includes a first internal electrode layer and a second internal electrode layer. Each internal electrode layer includes a top edge, a bottom edge opposite the top edge, and two side edges extending between the top edge and the bottom edge, which define the body of the internal electrode layer. The coupling capacitor includes external terminals electrically connected to the internal electrode layers, the external terminals being formed on a top surface of the coupling capacitor and a bottom surface of the coupling capacitor opposite the top surface of the coupling capacitor. The capacitor comprises one or more dielectric regions including one or more air voids.

[0007] Other features and aspects of the invention are described in greater detail below.

[0008] A full and enabling disclosure of the present invention, including the best mode thereof, to one of ordinary skill in the art, is set forth more particularly in remaining portions of the specification, including reference to the accompanying figures. [Brief description of the drawings]

[0009] [Figure 1A] FIG. 2 is a generalized top and side exterior perspective view of one embodiment of a 1 by 2 package coupling capacitor in accordance with the present invention. [Figure 1B] FIG. 1B is a side exterior perspective view of the coupling capacitor of FIG. [Figure 1C]FIG. 2 is a front external perspective view of the coupling capacitor of FIGS. 1A and 1B. [Diagram 2] FIG. 2 is a side view of a circuit board and integrated circuit package including the package coupling capacitor of the present invention. [Diagram 3] FIG. 1 is a side view of a circuit board and integrated circuit package including a prior art coupling capacitor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Those skilled in the art should appreciate that this discussion is merely a description of exemplary embodiments and is not intended as a limitation of the broader aspects of the invention.

[0011] In general, the present invention is directed to a surface mount multilayer coupling capacitor, for example for mounting on a circuit board. The surface mount multilayer coupling capacitor includes multiple capacitive elements within a body. That is, the multilayer coupling capacitor includes multiple capacitive elements within a single integral package. In this regard, the multilayer coupling capacitor includes a first set of alternating dielectric layers and internal electrode layers and a second set of alternating dielectric layers and internal electrode layers. Each set of alternating dielectric layers and internal electrode layers defines a capacitive element. The capacitor also includes a dielectric region that includes an air gap.

[0012] The particular arrangement of the capacitive elements within a single integral package (i.e., a single body) and the inclusion of the air gap can provide several advantages. For example, by utilizing the air gaps disclosed herein, crosstalk and interference between external terminals can be specifically minimized and / or eliminated, particularly when the capacitors are utilized in various electronic devices. Additionally, as discussed further below, the coupling capacitors of the present invention can be mounted on a circuit board as surface mount capacitors and can provide a smaller footprint on the circuit board, which can also allow for a reduction in the size of the circuit board.

[0013] 2, the coupling capacitor 408 may be mounted (e.g., surface mounted) on a circuit board 406 that includes a substrate (e.g., an insulating layer) having an upper surface and a lower surface. The circuit board 406 has a plurality of current paths (not shown) defined therein. The external terminals of the coupling capacitor 408 are in electrical communication with respective predetermined current paths of the circuit board 406. Furthermore, the external terminals of the coupling capacitor 408 may be physically connected to the circuit board 406 using any method commonly known in the art, such as general-purpose soldering techniques.

[0014] 2, an integrated circuit package 402 may also be provided on a circuit board 406. The integrated circuit package 402 may be connected to the circuit board 406 using a ball grid array 404. The circuit board may further include a processor 400. The processor 400 may also be connected to the integrated circuit package 402 using a ball grid array 412.

[0015] In general, ball grid array 404 may be configured to have a certain pitch. As is generally known in the art, pitch refers to the nominal distance between centers (also referred to as center-to-center spacing). The pitch of the external terminals of ball grid array 404 and coupling capacitor 408 may be determined by the individual circuit configuration. The pitch between the external terminals in one direction (i.e., the x-direction or the y-direction) may be the same as the pitch between adjacent external terminals in the other direction (i.e., the y-direction or the x-direction, respectively). That is, the pitch between any two adjacent external terminals may be substantially the same as the pitch between any other two adjacent external terminals.

[0016] The pitch can be about 0.1 mm or more, e.g., about 0.2 mm or more, about 0.3 mm or more, about 0.4 mm or more, about 0.5 mm or more, about 0.6 mm or more, about 0.7 mm or more, about 0.8 mm or more, about 0.9 mm or more, about 1.0 mm or more, etc. The pitch can be about 2.0 mm or less, e.g., about 1.5 mm or less, about 1.4 mm or less, about 1.3 mm or less, about 1.2 mm or less, about 1.1 mm or less, about 1.0 mm or less, etc. For example, the pitch can be about 0.2 mm, about 0.4 mm, about 0.6 mm, about 0.8 mm, about 1.0 mm, about 1.2 mm, etc. Specifically, the pitch can be 0.6 mm, 0.8 mm, or 1.0 mm. In one embodiment, the pitch may be about 0.6 mm, e.g., + / -10%, + / -5%, + / -2%, + / -1% of 0.6 mm, etc. In another embodiment, the pitch may be about 0.8 mm, e.g., + / -10%, + / -5%, + / -2%, + / -1% of 0.8 mm, etc. In a further embodiment, the pitch may be about 1 mm, e.g., + / -10%, + / -5%, + / -2%, + / -1% of 1 mm, etc.

[0017] In a similar embodiment, the pitch of the external terminals of coupling capacitor 408 may also be the same as the pitch of ball grid array 404. For example, the external terminals may be provided to make contacts typically used by a ball grid array, specifically a peripheral ball grid array. In this regard, the pitch of the external terminals may be the same as the pitch of the peripheral ball grid array. That is, the pitch may be within 10%, e.g., within 5%, within 2%, within 1%, within 0.5%, within 0.1%, etc., of the pitch of the peripheral ball grid array.

[0018] Furthermore, like a ball grid array, the external terminals may be provided in rows and / or columns. That is, the external terminals may be provided such that they are present in at least one row and at least two columns. For example, the external terminals may be provided in at least two rows, e.g., at least three rows, at least four rows, etc. Furthermore, the external terminals may be provided in at least two columns, e.g., at least three columns, at least four columns, etc. The number of rows and columns may be determined by the number of different sets of alternating dielectric layers and internal electrode layers.

[0019] Additionally, ball grid array 412 has a pitch as described above with respect to ball grid array 404. In one embodiment, the pitch of ball grid array 412 can be less than the pitch of the external terminals of ball grid array 404 and coupling capacitor 408. Some common pitches for ball grid array 412 include 0.1 mm and 0.2 mm.

[0020] Furthermore, the integrated circuit package 402 may also be connected to the circuit board 406 using a coupling capacitor 408 as defined herein. In this regard, the internal electrode layers of the coupling capacitor 408 may be positioned such that they are perpendicular to the horizontal plane of the circuit board 406 and the integrated circuit package 402. In other words, the internal electrode layers of the coupling capacitor 408 may be positioned such that they are substantially non-parallel to the circuit board 406. For example, the coupling capacitor 408 may be positioned between the integrated circuit package 402 and the circuit board 406 such that the coupling capacitor 408 is "sandwiched" between the two components. In this regard, the coupling capacitor 408 is directly connected to the integrated circuit package 402 and the circuit board 406. For example, the coupling capacitor 408 may be physically connected to the circuit board 406 and / or the circuit package 402 using any method commonly known in the art, such as general-purpose soldering techniques.

[0021] By using a coupling capacitor in the above arrangement, coupling capacitor 408 may allow for the removal of a portion of the original ball grid array 404. However, coupling capacitor 408 may still be surrounded by ball grid array 404 as shown in FIG.

[0022] Meanwhile, a prior art circuit board 506 is shown in Figure 3. Circuit board 506 includes a processor 500, an integrated circuit package 502, and ball grid arrays 504 and 512. However, rather than using a single integral capacitor package like coupling capacitor 408 in Figure 2, circuit board 506 of Figure 3 uses individual multi-layer ceramic capacitors 508. Furthermore, multi-layer ceramic capacitors 508 are positioned elsewhere on circuit board 506 and are connected to processor 500 and integrated circuit package 502 through vias 514.

[0023] However, for reasons discussed herein, the present configuration using a single integral capacitor may enable various advantages and benefits as compared to circuit boards using discrete multi-layer ceramic capacitors.

[0024] In general, a coupling capacitor may be used to generally block DC signals while allowing AC signals to pass or be transmitted. That is, a coupling capacitor may be used to block low frequency signals and transmit high frequency signals. In general, a coupling capacitor may have a generally high impedance / resistance at low frequencies that allows for blocking of DC signals. In contrast, a coupling capacitor may have a generally low impedance / resistance at high frequencies that allows for transmission of AC signals.

[0025] One distinct advantage of the coupling capacitors and configurations of the present invention is that the electrical length from the processor to the coupling capacitor is substantially reduced when used in a circuit board as described herein. For example, as shown in FIG. 2, the distance from the processor 400 to the coupling capacitor 408 is substantially less than the distance between the processor 500 and the capacitor 508 in FIG. 3. Placing the coupling capacitor in this manner also allows for the elimination of the via 514 as shown in FIG. 3. Furthermore, placing the capacitor in this manner allows the capacitor to be located within the equalizer window, which is preferably as low as possible. In this regard, allowing the capacitor to be located within the window can allow for noise filtering of the signal for transmission.

[0026] Moreover, another distinct advantage of the coupling capacitors and configurations of the present invention is the ability to tune the capacitors to obtain an impedance difference as close to 100Ω as possible. In this regard, the impedance difference may be ±25% of 100Ω, such as ±15%, ±10%, ±5%, ±2%, ±1%, ±0.5%, etc. It should be understood that the 100Ω impedance difference discussed above is merely one embodiment of the present invention, and that the coupling capacitors may be configured to obtain any desired impedance difference. Such impedance difference may be calculated using any method commonly known in the art.

[0027] Moreover, another distinct advantage of the coupling capacitors and configurations of the present invention is the ability to minimize insertion loss. Such minimal insertion loss may result from the ability to minimize impedance differences. In this regard, the insertion loss may be 0.5 dB or less, e.g., 0.25 dB or less, 0.15 dB or less, 0.1 dB or less, 0.05 dB or less, etc. Such insertion loss may be calculated using any method commonly known in the art.

[0028] Furthermore, the capacitance value may not necessarily be limited. For example, the capacitance of the coupling capacitor may be in the picofarad or nanofarad range. Specifically, the capacitance may be 1,000 μF or less, such as 750 μF or less, 500 μF or less, 250 μF or less, 100 μF or less, 50 μF or less, 25 μF or less, 10 μF or less, 5 μF or less, 2.5 μF or less, 1 μF or less, 750 nanofarads or less, 500 nanofarads or less, 250 nanofarads or less, 100 nanofarads or less, etc. The capacitance can be 1 picofarad or greater, e.g., 10 picofarads or greater, 25 picofarads or greater, 50 picofarads or greater, 100 picofarads or greater, 250 picofarads or greater, 500 picofarads or greater, 750 picofarads or greater, 1 nanofarad or greater, 10 nanofarads or greater, etc. Capacitance can be measured using common techniques known in the art.

[0029] Furthermore, the resistance of the capacitor may not necessarily be limited. For example, the resistance of the coupling capacitor may be 100mOhms or less, such as 75mOhms or less, 50mOhms or less, 40mOhms or less, 30mOhms or less, 25mOhms or less, 20mOhms or less, 15mOhms or less, 10mOhms or less, 5mOhms or less, etc. The resistance may be 0.01mOhms or more, such as 0.1mOhms or more, 0.25mOhms or more, 0.5mOhms or more, 1mOhms or more, 1.5mOhms or more, 2mOhms or more, 5mOhms or more, 10mOhms or more, etc. The resistance may be measured using common techniques known in the art.

[0030] Furthermore, the inductance of the capacitor may not necessarily be limited. For example, the inductance of the coupling capacitor may be less than 1 nanohenry. Specifically, the inductance may be 900 picohenry or less, for example, 750 picohenry or less, 500 picohenry or less, 400 picohenry or less, 250 picohenry or less, 100 picohenry or less, 50 picohenry or less, 25 picohenry or less, 15 picohenry or less, 10 picohenry or less, etc. The inductance may be 1 femtohenry or more, for example, 25 femtohenry or more, 50 femtohenry or more, 100 femtohenry or more, 250 femtohenry or more, 500 femtohenry or more, 750 femtohenry or more, etc.

[0031] The inventors have discovered that the above-mentioned advantages can be obtained by controlling the width of the internal electrode layers. Such control also allows for control of the spacing between the internal electrode layers in the first set and the internal electrode layers in the second set. In this regard, the shape of the internal electrode layers is not necessarily limited by the present invention, so long as certain operating characteristics and properties can be achieved. In one embodiment, the coupling capacitor may have a certain ratio of internal electrode layer width to spacing. In general, the spacing is considered to be the spacing "s" between the lateral edges of the first and second sets of internal electrode layers, as shown in FIG. 1C.

[0032] As described above, the present invention includes a multi-layer coupling capacitor that houses multiple capacitive elements in a single integral package. The capacitor includes a top surface and a bottom surface opposite the top surface. The capacitor also includes at least one side surface extending between the top and bottom surfaces. The capacitor may include at least three side surfaces, such as at least four side surfaces. In one embodiment, the capacitor includes a total of at least six surfaces (e.g., one top, one bottom, four sides). For example, the capacitor may have a parallelepiped shape, such as a rectangular parallelepiped shape.

[0033] Additionally, the capacitor can have a desired height. For example, the height can be 10 microns or more, e.g., 25 microns or more, 50 microns or more, 100 microns or more, 200 microns or more, 250 microns or more, 300 microns or more, 350 microns or more, 500 microns or more, 1,000 microns or more, 2,000 microns or more, etc. The height can be 5,000 microns or less, e.g., 4,000 microns or less, 2,500 microns or less, 2,000 microns or less, 1,000 microns or less, 750 microns or less, 500 microns or less, 450 microns or less, etc. When surrounded by a ball grid array, the height of the capacitor can be within 10%, e.g., within 7%, within 5%, within 3%, within 2%, within 1%, etc., of the height (or diameter) of the balls of the ball grid array. For example, such height can be the initial height prior to any reflow.

[0034] In one embodiment, the height of the capacitor can be 10% or more of the pitch, such as 20% or more, 30% or more, 40% or more, 45% or more, etc. The height can be less than 100% of the pitch, such as 90% or less, 80% or less, 70% or less, 60% or less, 55% or less, etc.

[0035] Generally, a multilayer coupling capacitor includes a first set of alternating dielectric layers and internal electrode layers and a second set of alternating dielectric layers and internal electrode layers, and the capacitor also includes external terminals electrically connected to the internal electrode layers and formed on a top surface of the capacitor and a bottom surface of the capacitor opposite the top surface of the capacitor.

[0036] Generally, a capacitor includes at least two sets of alternating dielectric layers and internal electrode layers. However, it should be understood that the present invention can include any number of sets of alternating dielectric layers and internal electrode layers and is not necessarily limited to this. For example, a capacitor can include at least three sets of alternating dielectric layers and internal electrode layers, such as at least four sets.

[0037] The first set of alternating dielectric layers and internal electrode layers and the second set of alternating dielectric layers and internal electrode layers may form at least a portion of the body of the capacitor. By arranging the dielectric layers and internal electrode layers in a stacked or laminated configuration, the capacitor may be considered a multilayer coupled capacitor, and may be considered a multilayer ceramic capacitor, particularly if, for example, the dielectric layers comprise ceramic.

[0038] Each set of alternating dielectric layers and internal electrode layers comprises a dielectric layer that is interleaved with the internal electrode layers. Specifically, the internal electrode layers include a first internal electrode layer and a second internal electrode layer that are interleaved in a facing relationship and separated by a dielectric layer disposed between each internal electrode layer. In this regard, each internal electrode layer is a separate and distinct internal electrode layer. However, in one embodiment, the dielectric layer that separates the internal electrode layers may not be separate. For example, the dielectric layer that separates the first set of internal electrode layers and the second set of internal electrode layers may be the same such that it extends along the width of the combined capacitor. For example, two internal electrodes may be provided within a single dielectric layer such that one internal electrode is present in the first set described above while one internal electrode is present in the second set described above. Such layers may then be stacked to form the capacitor disclosed herein.

[0039] In general, the thickness of the dielectric layers and the internal electrode layers is not limited and may be any thickness desired depending on the performance characteristics. For example, the thickness of the internal electrode layers may be, but is not limited to, about 500 nm or more, such as about 1 μm or more, about 2 μm or more, to about 10 μm or less, such as about 5 μm or less, about 4 μm or less, about 3 μm or less, about 2 μm or less, etc. For example, the internal electrode layers may have a thickness of about 1 μm to about 2 μm.

[0040] Furthermore, the present invention is not necessarily limited by the number of internal electrode layers per set of alternating dielectric layers and internal electrode layers, or the number of internal electrode layers in the entire capacitor. For example, each set may include 5 or more internal electrode layers, such as 10 or more, 25 or more, 50 or more, 100 or more, 200 or more, 300 or more, 500 or more, 600 or more, 750 or more, 1,000 or more, etc. Each set may have 5,000 or less internal electrode layers, such as 4,000 or less, 3,000 or less, 2,000 or less, 1,500 or less, 1,000 or less, 750 or less, 500 or less, 400 or less, 300 or less, 250 or less, 200 or less, 175 or less, 150 or less, etc. The entire capacitor may also include the above-mentioned number of electrode layers.

[0041] The internal electrode layer has a top edge and a bottom edge opposite the top edge. The internal electrode layer also has two side edges or lateral edges extending between the top and bottom edges. In one embodiment, the side edges, top edge, and bottom edge define a body of the internal electrode layer.

[0042] In general, in one embodiment, the top and bottom edges may have the same dimension (e.g., length). In another embodiment, the top and bottom edges may have different dimensions (e.g., length). The side edges may have the same dimension (e.g., height). Furthermore, the height of the side edges of the internal electrode layers when extending between the top and bottom surfaces of the capacitor may be less than the height of the capacitor. In other words, in one embodiment, the internal electrode layers may form electrical connections, such as direct electrical connections in which the internal electrode layers contact the external terminals only through the external terminals on the top surface of the capacitor or the external terminals on the bottom surface of the capacitor.

[0043] For example, each set of alternating dielectric layers and internal electrode layers comprises a dielectric layer interleaved with the internal electrode layers. Specifically, the internal electrode layers include first and second internal electrode layers interleaved in facing relationship and separated by a dielectric layer disposed between each internal electrode layer. In one embodiment, the first internal electrode layer electrically contacts a first external terminal, while the second internal electrode layer electrically contacts a second external terminal. For example, the first internal electrode layer of each set may electrically contact an external terminal on a top surface of the capacitor, while the second internal electrode layer of each set electrically contacts an external terminal on a bottom surface of the capacitor.

[0044] Each internal electrode of each set may be substantially aligned. For example, in one embodiment, at least one side edge of a first internal electrode layer may be substantially aligned with at least one side edge of a second internal electrode layer. In another embodiment, an electrical contact point of at least one side edge of a first internal electrode layer with a respective external terminal may be substantially aligned with an electrical contact point of at least one side edge of a second internal electrode layer with an opposite external terminal. In one embodiment, an electrical contact point of both side edges of a first internal electrode layer with a respective external terminal may be substantially aligned with an electrical contact point of both side edges of a second internal electrode layer with an opposite external terminal.

[0045] By substantially aligned it is meant that the side edges or contact points of the first internal electrode layer are within + / - 10%, e.g., within + / - 5%, within + / - 4%, within + / - 3%, within + / - 2%, within + / - 1%, within + / - 0.5%, etc., of the side edges or contact points of the second internal electrode layer based on the distance from the side edges of the coupled capacitor.

[0046] In general, the internal electrode layers of one set cannot overlap with the internal electrode layers of another set. In general, however, the internal electrode layers within a given set may overlap. For example, such internal electrode layers may at least partially overlap. In one embodiment, the internal electrode layers only partially overlap. As an example, the first and second internal electrode layers in each set may at least partially overlap. Specifically, the top edge of one internal electrode layer overlaps the bottom edge of another internal electrode layer. In the case where the first internal electrode layer includes a top edge that contacts an external terminal on the top surface of the capacitor and the second internal electrode layer includes a bottom edge that contacts an external terminal on the bottom surface of the capacitor, the bottom edge of the first internal electrode layer and the top edge of the second internal electrode layer overlap. Additionally, the overlap of the first and second internal electrode layers can be at least 10% or more, e.g., 25% or more, 35% or more, 50% or more, 60% or more, 70% or more, 80% or more, etc. based on the area defined by the lateral edges of the internal electrode layers and the top and bottom surfaces of the capacitor. Alternatively, such percentages can be based on the area of ​​the internal electrode layers.

[0047] Furthermore, in one embodiment, before the first internal electrode layer in each set, one or more dielectric layers may be provided such that such one or more dielectric layers are between such internal electrode layer and the adjacent side surface. Similarly, after the last internal electrode layer in each set, one or more dielectric layers may be provided such that such one or more dielectric layers are between such internal electrode layer and the adjacent side surface. In this regard, such dielectric layers may include at least two, e.g., at least three, at least five, at least ten, etc., dielectric layers. Thus, such regions may have a thickness greater than the thickness of the individual dielectric layers in the respective set. In particular, the distance may be at least twice, e.g., at least three, at least five, at least ten, etc., the thickness of the dielectric layers in the set.

[0048] Similarly, the at least two sets of alternating dielectric and internal electrode layers are spaced apart longitudinally (i.e., in a direction spanning the length of the capacitor and the major surfaces of the internal electrode and dielectric layers). For clarity, the lateral direction (i.e., spanning the thickness of the internal electrode and dielectric layers) is defined as the width of the capacitor, as determined by the number of layers in the capacitor.

[0049] The distance and spacing between the internal electrode layers in a given set or row may be specifically designed to ensure induced formation of terminations. Such distance between the internal electrode layers in a given row may be about 10 microns or less, such as about 8 microns or less, from about 2 microns to about 8 microns, etc. However, it should be understood that such distance may not necessarily be limited.

[0050] Additionally, the distance between adjacent columnar stacks of electrodes may be, but is not limited to, at least twice as large as the distance between adjacent internal electrode layers in a given column to ensure that separate terminations do not extend together. In some embodiments, the distance between adjacent columnar stacks of exposed metallization is about four times the distance between adjacent exposed electrode tabs in a particular stack. However, such distances may be highly dependent on the desired capacitance performance and circuit board configuration.

[0051] Furthermore, as described herein, the external terminals have a certain pitch. In this regard, the bottom edges and top edges of each of the first and second sets of internal electrode layers may have the same or similar pitch. Furthermore, the width of the internal electrode layers, particularly at the electrical contact points, may be the same as the width of the external terminals. In another embodiment, the width of the internal electrode layers, for example at the electrical contact points or elsewhere along the lateral dimension, may be less than the width of the external terminals.

[0052] Furthermore, the internal electrode layers may be symmetrical and / or symmetrically positioned within the capacitor in a given direction. For example, the internal electrode layers may be symmetrical about a vertical line passing through the center of the body of the internal electrode layers (i.e., a line extending from the center of the top edge to the center of the bottom edge of the internal electrode layers). Furthermore, the first set and the second set of internal electrode layers may be symmetrically positioned within the capacitor such that they are symmetrical about a vertical line passing through the center of the body of the capacitor (i.e., a line extending from the top surface to the bottom surface).

[0053] As shown herein, the capacitor comprises a dielectric region that includes one or more voids. In this regard, the dielectric region may be a region that includes a dielectric material but does not include internal electrode material. In this regard, the dielectric region may constitute a region that does not include alternating dielectric layers and internal electrode layers. Thus, the dielectric region may include dielectric material between each set of alternating dielectric layers and internal electrode layers. Furthermore, the dielectric region may include dielectric material between the lateral edges and adjacent longitudinal side surfaces of the electrodes in a given set of alternating dielectric layers and internal electrode layers. It should be understood that such dielectric regions may be formed from ceramic green sheets of alternating dielectric layers and internal electrode layers, but such regions do not include any internal electrode material or corresponding layers. As a result, voids may be provided within such regions. Furthermore, the dielectric region may include dielectric material present between the first internal electrode layer of each set and adjacent side surfaces of the capacitor. The dielectric region may also include dielectric material present between the last internal electrode layer of each set and adjacent side surfaces of the capacitor. In one particular embodiment, the dielectric region may include the region within the capacitor that exists between the two external terminals. It should be further understood that the dielectric region may include any combination of the above-mentioned regions.

[0054] As mentioned above, the dielectric region includes a region that includes dielectric material but does not include internal electrode material. Thus, excluding voids, the dielectric region may include 90 vol.% or more of dielectric material, such as 93 vol.% or more, 95 vol.% or more, 97 vol.% or more, 98 vol.% or more, 99 vol.% or more, 100 vol.% etc.

[0055] In general, such voids may not include any material, and in particular may not include any dielectric material or internal electrode material. In one embodiment, the voids may be closed, for example partially or completely, by an enclosure material. In one embodiment, the voids may be partially closed by an enclosure material. By partially closed, the enclosure material is present only partially around the interior of the void such that the void is partially separated from the dielectric material. In this regard, at least a certain perimeter of the void may be in direct contact with the dielectric material of the dielectric region. In another embodiment, the voids may be completely or entirely closed by an enclosure material. By entirely closed, the enclosure material is present around the interior of the void such that the void is entirely separated from the dielectric material. Nevertheless, the enclosure material may be utilized to function as a barrier between the interior of the void and the dielectric material of the dielectric region. In one embodiment, the enclosure material may be a non-conductive material. However, it should be understood that in one embodiment, the voids may not even be partially closed by the enclosure material.

[0056] In this regard, in one embodiment, the void may be provided without any barrier between the void and the dielectric material of the dielectric region. The void may have any shape, and is not necessarily limited. For example, the shape may be a sphere, a cylinder, etc. In one embodiment, the shape may be a sphere. The void may have a maximum dimension (e.g., length, width, diameter, etc.). The maximum dimension may be 5 microns or more, e.g., 10 microns or more, 20 microns or more, 30 microns or more, 40 microns or more, 50 microns or more, 80 microns or more, 100 microns or more, 200 microns or more, 300 microns or more, 400 microns or more, 500 microns or more, 600 microns or more, 800 microns or more, 1,000 microns or more, etc. The maximum dimension can be 5,000 microns or less, e.g., 4,000 microns or less, 3,000 microns or less, 2,000 microns or less, 1,800 microns or less, 1,600 microns or less, 1,400 microns or less, 1,200 microns or less, 1,000 microns or less, 800 microns or less, 600 microns or less, 500 microns or less, 400 microns or less, 300 microns or less, 250 microns or less, 200 microns or less, 180 microns or less, 160 microns or less, 140 microns or less, 120 microns or less, 100 microns or less, 80 microns or less, 60 microns or less, 50 microns or less, 40 microns or less, etc.

[0057] These voids may be provided using any means that can provide such voids in the capacitor. For example, these voids may be formed by printing specific patterns on ceramic green sheets, followed by lamination and firing the stacked laminates. Alternatively, these voids may be formed using various drilling techniques to provide any desired shape in the dielectric material of the dielectric region.

[0058] As another example, the air gap may be provided using one or more vias (e.g., through-hole vias). The vias may not be filled with any material, such as any conductive or non-conductive material, such that air is present inside. Additionally, in one embodiment, the vias may be provided such that they are only within the dielectric region. In this regard, the vias may be provided such that they do not contact any of the internal electrode layers.

[0059] In one embodiment, the vias may extend from the top surface of the capacitor to the bottom surface of the capacitor. In this regard, the vias may be cylindrical extending through the thickness of the capacitor. Thus, the vias may be through-hole conductive vias. In another embodiment, the vias may extend only partially through the thickness of the capacitor. For example, the vias may extend 10% or more of the thickness of the capacitor, such as 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, etc. The vias may extend 100% or less of the thickness of the capacitor, such as 90% or less, 80% or less, 70% or less, 60% or less, 50% or less, 40% or less, 30% or less, 20% or less, 10% or less, etc. In one embodiment, such an extension through the above-mentioned thickness may refer to the average extension of the vias through the thickness of the capacitor.

[0060] In embodiments including two or more vias, all of the vias may have the same length. For example, two or more of the vias may have the same length. However, it should be understood that two or more of the vias may have different lengths.

[0061] The cross-sectional area of ​​the via hole is 0.00005 mm 2 More than, for example, 0.0001 mm 2 More than 0.0005mm 2 Above 0.001mm 2 More than 0.005mm 2 Above 0.01mm 2 The cross-sectional area of ​​the via hole can be 1 mm 2 For example, 0.5 mm or less 2 Below, 0.1mm2 Below, 0.09mm 2 Below, 0.07mm 2 Below, 0.05mm 2 Below, 0.01mm 2 Below, 0.005mm 2 Below, 0.001mm 2 It could be the following etc.

[0062] The distance between the vias is not necessarily limited by the present invention. As described herein, the external terminals may have a certain pitch. In this regard, the vias may also have the same or similar pitch. Furthermore, the average pitch between a first via and an adjacent second via may be less than the average pitch between the first via and another adjacent third via.

[0063] Furthermore, the average length of the first and second vias may be a certain length compared to the average pitch between the first via and the adjacent second via. In one embodiment, the average length may be equal to or greater than the average pitch between the first via and the adjacent second via. In a further embodiment, the average length may be equal to or less than the average pitch between the first via and the adjacent second via. For example, the average length may be 10 times or less, such as 8 times or less, 6 times or less, 5 times or less, 4 times or less, 3 times or less, 2 times or less, 1 time or less, etc., of the average pitch between the first via and the adjacent second via. The average length may be 0.001 times or more, such as 0.01 times or more, 0.1 times or more, 0.2 times or more, 0.3 times or more, 0.5 times or more, 0.7 times or more, 0.9 times or more, 1 time or more, etc.

[0064] In one embodiment, the vias may be provided between adjacent external terminals in the "L" direction of the capacitor. In one embodiment, the vias may be provided between adjacent external terminals in the "W" direction of the capacitor. In yet a further embodiment, the vias are provided between adjacent external terminals in both the "L" and "W" directions of the capacitor.

[0065] The method may also include forming vias. In one embodiment, the vias may be formed by forming holes or notches in the ceramic green sheets before the ceramic green sheets are laminated together. Alternatively, the vias may be formed by forming holes in the stacked body after lamination. For example, this may be done after laminating the layers and the ceramic green sheets. Furthermore, in one embodiment, this may be done before firing the stacked body. In another embodiment, this may be done after firing the stacked body. Nevertheless, the vias may be capped, such as to cover any holes on the top and / or bottom surfaces of the capacitor. For example, the vias may be capped using a non-conductive material, such as a ceramic or a polymer. In particular, the ceramic may be a ceramic utilized to form a dielectric layer of the capacitor.

[0066] In another embodiment, the dielectric region may include hollow filler materials. For example, these hollow filler materials may allow for the presence of air within the interior of the material. These hollow filler materials may be entirely closed or at least partially open. By entirely closed, there is a barrier around the interior of the hollow filler material such that the hollow filler material is entirely separated from the dielectric material. On the other hand, in the case of an open hollow filler material, at least some of the perimeter is open and exposed such that there is no barrier between the interior of the hollow filler material and the dielectric material.

[0067] The hollow filler material may be any filler material that can contain a hollow interior. For example, they may include, but are not limited to, spheres, fibers, tubes, rods, and the like. In one embodiment, the filler material may include spheres, such as microspheres or nanospheres. For example, in one embodiment, the filler material may include microspheres. In another embodiment, the filler material may include nanospheres. In another embodiment, the filler material may include tubes.

[0068] In one embodiment, the hollow filler material may be non-conductive. For example, the hollow filler material may not be made of metal. Furthermore, in one embodiment, the hollow filler material may not be made of a material that includes metal additives. In this regard, in one embodiment, the hollow filler material may be made of a polymer or a ceramic. For example, the ceramic may include glass, silicate, and the like. In one embodiment, the ceramic may include glass. In another embodiment, the ceramic may include silicate, such as aluminosilicate. Meanwhile, the polymer may be a thermoplastic polymer or a thermosetting polymer. In one embodiment, the polymer may be a thermoplastic polymer. In another embodiment, the polymer may be a thermosetting polymer.

[0069] The hollow filler material may have a certain density. For example, the density may be 0.2 g / cc or more, such as 0.25 g / cc or more, 0.3 g / cc or more, 0.35 g / cc or more, 0.4 g / cc or more, 0.5 g / cc or more, 0.6 g / cc or more, 0.7 g / cc or more, etc. The density may be 1.5 g / cc or less, such as 1.3 g / cc or less, 1.1 g / cc or less, 1 g / cc or less, 0.9 g / cc or less, 0.8 g / cc or less, 0.7 g / cc or less, 0.6 g / cc or less, 0.5 g / cc or less, 0.4 g / cc or less, etc. In one embodiment, the density mentioned above may refer to bulk density.

[0070] The hollow filler material can have a maximum dimension (e.g., length, width, diameter, etc.) that can be 5 microns or more, e.g., 10 microns or more, 20 microns or more, 30 microns or more, 40 microns or more, 50 microns or more, 80 microns or more, 100 microns or more, 200 microns or more, 300 microns or more, 400 microns or more, 500 microns or more, 600 microns or more, 800 microns or more, 1,000 microns or more, etc. The maximum dimension can be 5,000 microns or less, e.g., 4,000 microns or less, 3,000 microns or less, 2,000 microns or less, 1,800 microns or less, 1,600 microns or less, 1,400 microns or less, 1,200 microns or less, 1,000 microns or less, 800 microns or less, 600 microns or less, 500 microns or less, 400 microns or less, 300 microns or less, 250 microns or less, 200 microns or less, 180 microns or less, 160 microns or less, 140 microns or less, 120 microns or less, 100 microns or less, 80 microns or less, 60 microns or less, 50 microns or less, 40 microns or less, etc.

[0071] The hollow filler material may be present in the dielectric region at a particular weight percentage, for example, the hollow filler material may be present in an amount of 0.1 wt.% or more, such as 0.5 wt.% or more, 1 wt.% or more, 2 wt.% or more, 3 wt.% or more, 5 wt.% or more, 8 wt.% or more, 10 wt.% or more, 15 wt.% or more, 20 wt.% or more, 25 wt.% or more, 30 wt.% or more, etc., of the weight of the dielectric region. The hollow filler material may be present in an amount of 50 wt.% or less, e.g., 40 wt.% or less, 35 wt.% or less, 30 wt.% or less, 25 wt.% or less, 20 wt.% or less, 18 wt.% or less, 16 wt.% or less, 14 wt.% or less, 12 wt.% or less, 10 wt.% or less, 9 wt.% or less, 8 wt.% or less, 7 wt.% or less, 6 wt.% or less, 5 wt.% or less, etc.

[0072] The hollow filler material may be present in the dielectric region at a particular volume percentage. For example, the hollow filler material may be present in an amount of 0.1 vol.% or more, such as 0.5 vol.% or more, 1 vol.% or more, 2 vol.% or more, 3 vol.% or more, 5 vol.% or more, 8 vol.% or more, 10 vol.% or more, 15 vol.% or more, 20 vol.% or more, 25 vol.% or more, 30 vol.% or more, etc., of the weight of the dielectric region. The hollow filler material may be present in an amount of 50 vol.% or less, such as 40 vol.% or less, 35 vol.% or less, 30 vol.% or less, 25 vol.% or less, 20 vol.% or less, 18 vol.% or less, 16 vol.% or less, 14 vol.% or less, 12 vol.% or less, 10 vol.% or less, 9 vol.% or less, 8 vol.% or less, 7 vol.% or less, 6 vol.% or less, 5 vol.% or less, etc.

[0073] The above provides various options for providing voids in the dielectric region, but it should be understood that these options can be used individually or in combination. For example, voids formed in the body (e.g., without a barrier / enclosure material) can be combined with voids formed as vias. Similarly, the voids can include voids formed by vias and hollow filler materials. Alternatively, the voids can include a combination of voids formed in the body without a barrier / enclosure material and hollow filler materials. In this regard, it should be understood that the present invention is not necessarily limited in this respect.

[0074] The voids may constitute a certain volume of the capacitor. For example, the voids may constitute 1 vol.% or more, such as 2 vol.% or more, 3 vol.% or more, 5 vol.% or more, 10 vol.% or more, 15 vol.% or more, 20 vol.% or more of the capacitor, specifically the stacked laminate of the dielectric layers and the internal electrode layers. The voids may constitute 30 vol.% or less, such as 25 vol.% or less, 20 vol.% or less, 18 vol.% or less, 15 vol.% or less, 13 vol.% or less, 11 vol.% or less, 10 vol.% or less, 9 vol.% or less, 8 vol.% or less, 7 vol.% or less, 6 vol.% or less, 5 vol.% or less, etc., of the capacitor, specifically the stacked laminate of the dielectric layers and the internal electrode layers.

[0075] The voids may constitute a certain volume of the dielectric region of the capacitor. For example, the voids may constitute 1 vol.% or more of the dielectric region of the capacitor, such as 2 vol.% or more, 3 vol.% or more, 5 vol.% or more, 10 vol.% or more, 15 vol.% or more, 20 vol.% or more, 25 vol.% or more, 30 vol.% or more, etc. The voids may constitute 40 vol.% or less of the dielectric region of the capacitor, such as 30 vol.% or less, 25 vol.% or less, 20 vol.% or less, 18 vol.% or less, 15 vol.% or less, 13 vol.% or less, 11 vol.% or less, 10 vol.% or less, 9 vol.% or less, 8 vol.% or less, 7 vol.% or less, 6 vol.% or less, 5 vol.% or less, etc.

[0076] Although not intended to be limiting, by providing the above-mentioned voids, the dielectric region can have a relatively low relative dielectric constant. For example, the relative dielectric constant can be 3 or more, for example, 3.5 or more, 4 or more, 4.5 or more, 5 or more, 7 or more, 10 or more, 15 or more, 20 or more, 25 or more, 30 or more, 40 or more, 50 or more, 60 or more, 70 or more, 80 or more, 90 or more, 100 or more, 200 or more, 300 or more, 400 or more, 500 or more, 1,000 or more, etc. The relative dielectric constant can be 10,000 or less, for example, 5,000 or less, 2,000 or less, 1,000 or less, 800 or less, 600 or less, 400 or less, 200 or less, 150 or less, 100 or less, 90 or less, 80 or less, 70 or less, 60 or less, 50 or less, 40 or less, 30 or less, 25 or less, 20 or less, 15 or less, 10 or less, etc. In one embodiment, such aforementioned relative dielectric constant is measured at 1 MHz.

[0077] The capacitor of the present invention also includes external terminals on the top and bottom surfaces. In one particular embodiment, the external terminals may not be present on the side surfaces of the capacitor.

[0078] The external terminals include at least one terminal of a first polarity and at least one terminal of a second opposite polarity. The capacitor may include at least one, e.g., at least two, at least four, at least six, at least eight, etc., terminal of the first polarity and / or the second opposite polarity on a top surface of the capacitor. Additionally, the capacitor may include the above-mentioned amount of terminals on a bottom surface of the capacitor.

[0079] The capacitor may include an equal number of terminals of a first polarity and / or terminals of a second polarity on the top surface of the capacitor and on the bottom surface of the capacitor. The number of terminals of a first polarity may be equal to the number of terminals of a second opposite polarity on the top surface of the capacitor. The number of terminals of a first polarity may be equal to the number of terminals of a second opposite polarity on the bottom surface of the capacitor. The total number of terminals present on the top surface of the capacitor may be equal to the total number of terminals present on the bottom surface of the capacitor. The total number of terminals of a first polarity present on the top and bottom surfaces of the capacitor may be equal to the total number of terminals of a second opposite polarity present on the top and bottom surfaces of the capacitor.

[0080] In general, the terminals of polarities located on the top and bottom surfaces of the capacitor may not be interdigitated. In this regard, the terminals of corresponding polarities on the top and bottom surfaces may not be offset by terminal location, but may instead be positioned directly above or below a terminal of another polarity on the opposite top or bottom surface. In other words, the terminals of corresponding polarities corresponding to a particular set of alternating dielectric layers and internal electrode layers may be substantially aligned. By substantially aligned, it is meant that the offset of one side edge of a polarity terminal on the top surface from a side surface of the capacitor is within + / -10%, e.g., within + / -5%, within + / -4%, within + / -3%, within + / -2%, within + / -1%, within + / -0.5%, etc., of the offset from a side edge of the corresponding polarity terminal on the bottom surface. However, in one embodiment, the external terminals may be interdigitated.

[0081] The capacitor of the present invention may be further described in light of the embodiments illustrated in FIGS. 1A-1C.

[0082] 1A shows the capacitor 10 in a 2 by 1 configuration, i.e., the capacitor includes two terminals along one dimension, a top surface and a bottom surface. In this regard, the capacitor 10 includes a total of two external terminals 12, 14 on the top surface and two corresponding external terminals (not shown) on the bottom surface, where the external terminals on the top surface correspond to the external terminals on the bottom surface.

[0083] The capacitor 10 of Figure 1A includes external terminals 12, 14 and, as shown in Figure 1C, two sets 110 of alternating dielectric and internal electrode layers. As shown in Figures 1B and 1C, each set 110 of alternating dielectric and internal electrode layers includes internal electrode layers 105, 115 and a dielectric layer (not shown) in an alternating arrangement.

[0084] Typically, the internal electrode layer 105 extends to the top surface of the capacitor, and the internal electrode layer 115 extends to the bottom surface of the capacitor. The extensions aid in the formation of external terminals. In this regard, the internal electrode layers may be exposed on the top and bottom surfaces of the capacitor to allow for connection between the body of the internal electrode layer and the external terminals. For example, the internal electrode layers 105, 115 extend to the edge of the dielectric layer and allow for the formation of external terminals.

[0085] The lateral or side edges of the internal electrode layers 105, 115 may be aligned in the vertical direction. That is, the lateral edge of the first internal electrode layer 105 may be aligned with the lateral edge of the second internal electrode layer 115. In one embodiment, both lateral edges may be aligned. In another embodiment, the contact point of the first internal electrode layer 105 with the external terminal may be aligned with the contact point of the second internal electrode layer 115 with the external terminal.

[0086] In addition, as shown in Figures 1B and 1C, the capacitor 10 also includes dielectric regions 125. As shown herein, such dielectric regions include regions that may simply include dielectric material but do not include internal electrode material. As shown in Figure 1B, such dielectric regions 125 include the region before the first internal electrode layer of each set and between such layer and the adjacent side surface. The dielectric regions 125 also include the region after the last internal electrode layer of each set and between such layer and the adjacent side surface. As shown in Figure 1C, the dielectric regions 125 include the material between each set of alternating dielectric and internal electrode layers, as well as the material between the nearest side or side edge of the internal electrode layer and the adjacent side surface.

[0087] According to such dielectric region 125, one or more air voids may be provided as disclosed herein. As one example, a via 135 is provided as shown in FIG. 1C. However, it should be understood that more than one via may be provided. Furthermore, such a via extends through the thickness from the top surface to the bottom surface of the capacitor. However, it should be understood that the via may not extend through the entire thickness of the capacitor. As also shown herein, the air void may be provided in another manner as also disclosed herein.

[0088] 1A includes at least one terminal of a first polarity and at least one terminal of a second opposite polarity on the top surface, and, although not shown, the bottom surface includes at least a terminal of a first polarity and a terminal of a second opposite polarity.

[0089] As shown in Figures 1A-1C, the capacitor includes two external terminals and two sets of alternating dielectric and internal electrode layers on each surface. However, as noted above, the invention is not limited by the number of external terminals and / or the number of sets of alternating dielectric and internal electrode layers. Also, Figure 1B uses only eleven internal electrode layers per set of alternating dielectric and internal electrode layers. However, it should be understood that the invention can include any number of internal electrode layers per set and is not necessarily limited thereto.

[0090] In general, the present invention provides a capacitor having a unique construction that provides various benefits and advantages. In this regard, it should be understood that the materials used to construct the capacitor are not limited and may be any commonly used in the art and may be formed using any method commonly used in the art.

[0091] In general, the dielectric layer is typically formed from a dielectric material. The dielectric material may have a relatively high relative dielectric constant in one embodiment. In another embodiment, the dielectric material may have a relatively low relative dielectric constant. For example, the relative dielectric constant may be 3 or more, such as 3.5 or more, 4 or more, 4.5 or more, 5 or more, 7 or more, 10 or more, 15 or more, 20 or more, 25 or more, 30 or more, 40 or more, 50 or more, 60 or more, 70 or more, 80 or more, 90 or more, 100 or more, 200 or more, 300 or more, 400 or more, 500 or more, 1,000 or more, 2,000 or more, 5,000 or more, 10,000 or more, etc. The dielectric constant can be 40,000 or less, for example, 30,000 or less, 20,000 or less, 10,000 or less, 5,000 or less, 2,000 or less, 1,000 or less, 800 or less, 600 or less, 400 or less, 200 or less, 150 or less, 100 or less, 90 or less, 80 or less, 70 or less, 60 or less, 50 or less, 40 or less, 30 or less, 25 or less, 20 or less, 15 or less, 10 or less, etc.

[0092] In this regard, the dielectric material may be a ceramic, which may be provided in a variety of forms, such as a wafer (e.g., pre-fired) or as a dielectric material that is co-fired within the device itself.

[0093] Specific examples of this type of high dielectric constant material include, for example, NPO (COG) materials (up to about 100), X7R materials (from about 3,000 to about 7,000), X7S materials, Z5U materials, and / or Y5V materials. It should be recognized that the above-mentioned materials are described by their industry-accepted definitions, some of which are standard classifications established by the Electronic Industries Association (EIA) and thus should be recognized by those skilled in the art. For example, such materials may include ceramics. Such materials may include perovskites, such as barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), sodium bismuthate titanate, etc. For example, in one specific embodiment, a material having the chemical formula Ba x Sr 1-x Barium strontium titanate ("BSTO") of TiO3 may be used, where x is from 0 to 1, in some embodiments from about 0.15 to about 0.65, and in some embodiments from about 0.25 to about 0.6. Other suitable perovskites include, for example, Ba x Ca 1-x TiO3, where x is from about 0.2 to about 0.8, and in some embodiments from about 0.4 to about 0.6; and Pb x Zr 1-xTiO3 ("PZT"), where x ranges from about 0.05 to about 0.4, and may include lead lanthanum zirconium titanate ("PLZT"), lead titanate (PbTiO3), barium calcium zirconium titanate (BaCaZrTiO3), sodium nitrate (NaNO3), KNbO3, LiNbO3, LiTaO3, PbNb2O6, PbTa2O6, KSr(NbO3), and NaBa2(NbO3)5KHb2PO4. Still further complex perovskites are known to be represented by the general formula A[B1 1 / 3 B2 2 / 3 ]O3 materials, where A is Ba x Sr 1-x (x can be a value from 0 to 1), and B1 is Mg y Zinc 1-y (y can range from 0 to 1), and B2 is Ta z Nb 1-z where z can be a value from 0 to 1. In one specific embodiment, the dielectric layer can include a titanate.

[0094] The internal electrode layers may be formed from any of a variety of different materials, as known in the art. The internal electrode layers may be made from metals, such as conductive metals. The materials may include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and the like, as well as various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloys, as well as respective sputtered layers of chromium, nickel, and gold, may also be suitable. In one particular embodiment, the internal electrode layers may include nickel or an alloy thereof.

[0095] The external terminals may be formed from any of a variety of different metals as known in the art. The external terminals may be made from a metal, such as a conductive metal. Materials may include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), etc., as well as various combinations thereof. In one particular embodiment, the external terminals may include copper or an alloy thereof.

[0096] The external terminals may be formed using any method commonly known in the art. The external terminals may be formed using techniques such as sputtering, painting, printing, electroless plating or fine copper termination (FCT), electroplating, plasma deposition, jet spray / airbrush, etc.

[0097] The external terminals may be formed such that they are thin film platings of metal. Such thin film platings may be formed by depositing a conductive material, such as a conductive metal, on exposed portions of the internal electrode layers. For example, leading edges of the internal electrode layers may be exposed to allow for the formation of plated terminations.

[0098] The external terminals may have an average thickness of about 50 μm or less, e.g., about 40 μm or less, about 30 μm or less, about 25 μm or less, about 20 μm or less, etc., to about 5 μm or more, e.g., about 10 μm or more, about 15 μm or more, etc. For example, the external terminals may have an average thickness of about 5 μm to about 50 μm, e.g., about 10 μm to about 40 μm, about 15 μm to about 30 μm, about 15 μm to about 25 μm, etc.

[0099] In general, the external terminals may include plated terminals. For example, the external terminals may include electroplated terminals, electroless plated terminals, or a combination thereof. For example, the electroplated terminals may be formed via electrolytic plating. The electroless plated terminals may be formed via electroless plating.

[0100] When multiple layers make up the external terminals, the external terminals may include electroplated terminals and electroless plated terminals. For example, electroless plating may be used first to deposit an initial layer of material. The plating technique may then be switched to electrochemical plating, which may allow for faster build-up of the material.

[0101] When forming a plating terminal using any plating method, the leading edge of the internal electrode layer exposed from the body of the capacitor is exposed to a plating solution. In one embodiment, exposing can refer to immersing the capacitor in the plating solution.

[0102] The plating solution includes a conductive material, such as a conductive metal, that is used to form the plated terminations. Such conductive material may be any of the materials described above or any that are generally known in the art. For example, the plating solution may be a nickel sulfamate bath solution or other nickel solution, such that the plating layer and external terminals include nickel. Alternatively, the plating solution may be a cuprate bath solution or other suitable copper solution, such that the plating layer and external terminals include copper.

[0103] Additionally, it should be understood that the plating solution may contain other additives as is commonly known in the art. For example, the additives may include other organic additives and media that can aid in the plating process. Additionally, additives may be used to provide a plating solution at a desired pH. In one embodiment, a resistance reducing additive may be used in the solution to aid in complete plating coverage and bonding of plating material to the exposed leading edges of the capacitor and internal electrode layers.

[0104] The capacitor may be exposed, submerged, or immersed in the plating solution for a predetermined time. Such exposure time may be for a time sufficient to allow sufficient plating material to deposit to form a plating termination, but is not necessarily limited. In this regard, the time should be sufficient to allow for the formation of continuous connections between desired exposed adjacent leading edges of the internal electrode layers of a given polarity of each internal electrode layer in a set of alternating dielectric and internal electrode layers.

[0105] In general, the difference between electrolytic and electroless plating is that electrolytic plating uses an electrical bias, such as by using an external power source. Electrolytic plating solutions typically use a high current density range, e.g., 10-15 amp / ft 2 (rated at 9.4 volts). A connection can be made with a negative connection to the capacitor which requires the formation of a plating terminal, and a positive connection to a solid material in the same plating solution (e.g., Cu in a Cu plating solution). That is, the capacitor is biased with a polarity opposite to that of the plating solution. Using such a method, the conductive material of the plating solution is attracted to the exposed leading edge metal of the internal electrode layer.

[0106] Various pretreatment steps may be used prior to submerging or exposing the capacitor to the plating solution. Such steps may be performed for a variety of purposes, including catalyzing, accelerating, and / or improving adhesion of plating material to the leading edges of the internal electrode layers.

[0107] Additionally, an initial cleaning step may be used prior to plating or any other pretreatment step. Such a step may be used to remove any oxide buildup that forms on the exposed edges of the internal electrode layers. This cleaning step may be particularly useful to help remove any buildup of nickel oxide when the internal electrodes or other conductive elements are formed of nickel. Component cleaning may be accomplished by complete immersion in a pre-cleaning solution layer, such as one that includes an acid cleaner. In one embodiment, the exposure may be for a predetermined period of time, such as on the order of about 10 minutes. Cleaning may alternatively be accomplished by a chemical polishing or harperizing step.

[0108] Additionally, a step may be performed to activate the exposed metallic leading edges of the internal electrode layers to facilitate deposition of conductive material. Activation may be accomplished by palladium salt immersion, photopatterned (via mask or laser) palladium organometallic precursors, screen printed or inkjet deposited palladium compounds, or electrophoretic palladium deposition. It should be recognized that palladium-based activators are currently disclosed merely as examples of activation solutions that often work well with activation of exposed tab portions formed of nickel or its alloys. However, it should be understood that other activation solutions may also be utilized.

[0109] Also, instead of or in addition to the activation step described above, an activation dopant can be introduced into the conductive material when forming the internal electrode layers of the capacitor. For example, if the internal electrode layers include nickel and the activation dopant includes palladium, a palladium dopant can be introduced into the nickel ink or composition forming the internal electrode layers. In this way, the palladium activation step can be eliminated. It should be further recognized that some of the above activation methods, such as organometallic precursors, also lend themselves to the co-deposition of glass formers to enhance adhesion to the generally ceramic body of the capacitor. When the activation step is performed as described above, it often leaves traces of the active body material on the exposed conductive parts before and after termination plating.

[0110] Additionally, post-plating steps may also be used. Such steps may be performed for a variety of purposes, including strengthening and / or improving adhesion of the material. For example, a heating (or annealing) step may be used after performing the plating step. Such heating may be performed via baking, laser subjection, UV irradiation, microwave irradiation, arc welding, etc.

[0111] As shown herein, the external terminal comprises at least one plating layer. In one embodiment, the external terminal may comprise only one plating layer. However, it should be understood that the external terminal may comprise multiple plating layers. For example, the external terminal may comprise a first plating layer and a second plating layer. In addition, the external terminal may also comprise a third plating layer. The materials of these plating layers may be any of those described above and those generally known in the art.

[0112] For example, one plating layer, such as the first plating layer, may include copper or an alloy thereof. Another plating layer, such as the second plating layer, may include nickel or an alloy thereof. Another plating layer, such as the third plating layer, may include a combination, such as tin, lead, gold, or an alloy. Alternatively, an initial plating layer may include nickel, followed by a plating layer of tin or gold. In another embodiment, an initial plating layer of copper may be formed, followed by a layer of nickel.

[0113] In one embodiment, the initial or first plating layer can be a conductive metal (e.g., copper). This area can then be covered with a second layer comprising a resistive-polymeric material for sealing. This area can then be polished to selectively remove the resistive-polymeric material, and then plated again with a third layer comprising a conductive metallic material (e.g., copper).

[0114] The second layer above the initial plating layer may correspond to a solder barrier layer, for example a nickel solder barrier layer. In some embodiments, the layer may be formed by electroplating an additional layer of metal (e.g., nickel) over an initial electroless or electrolytic plated layer (e.g., plated copper). Other exemplary materials for the solder barrier layer include nickel-phosphorus, gold, and silver. The third layer above the solder barrier layer may correspond to a conductive layer, such as plated Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or other suitable plated solder, in some embodiments.

[0115] Additionally, a layer of metal plating may be formed, followed by an electroplating step to provide a resistive or more resistive metal alloy coating, such as an electroless Ni-P alloy, over such metal plating, although it should be understood that any metal coating may be included, as would be understood by one of ordinary skill in the art from the full disclosure of this application.

[0116] It should be appreciated that any of the above steps may occur as a bulk process, such as a barrel plating termination process, a fluidized bed plating termination process, and / or a flow-through plating termination process, all of which are commonly known in the art. Such bulk processes allow multiple components to be processed at once, providing an efficient and rapid termination process. This is particularly advantageous compared to traditional termination methods, such as printing thick film terminations, which require individual component processing.

[0117] As described herein, the formation of the external terminals is generally guided by the location of the exposed leading edges of the internal electrode layers. Such a phenomenon may be referred to as "self-determining" because the formation of the external plated terminals is determined by the configuration of exposed conductive metal of the internal electrode layers at selected peripheral locations on the capacitor.

[0118] Further aspects of the above techniques for forming thin film plated terminations are described in U.S. Patent No. 7,177,137 to Ritter et al. and U.S. Patent No. 7,463,474 to Ritter et al., which are incorporated herein by reference for all purposes. It should be recognized that additional techniques for forming capacitor terminals may also fall within the scope of this technology. Exemplary alternatives include, but are not limited to, forming terminations by plating, magnetic, masking, electrophoretic / electrostatic, sputtering, vacuum deposition, printing, or other techniques for forming both thick and thin film conductive layers.

[0119] The coupling capacitor of the present invention may be used in many applications. For example, the coupling capacitor may be used in various applications requiring high speed interfaces (e.g., high speed differential interfaces). The applications may include applications using SerDes (i.e., serializer / deserializer) functions or architectures. The applications may also include applications using PCIE (i.e., PCI Express) and / or QPI (i.e., QuickPath Interconnect) functions or architectures. The applications may include various communication devices. For example, the applications may include Ethernet systems such as Gigabit Ethernet systems, wireless network routers, fiber optic communication systems, and storage devices.

[0120] These and other modifications and variations of the present invention may be practiced by those skilled in the art without departing from the spirit and scope of the present invention. Moreover, it should be understood that aspects of the various embodiments may be interchanged both in whole or in part. Moreover, the above description is by way of example only and is not intended to limit the invention, which is further described in the appended claims. [Explanation of symbols]

[0121] 10 Capacitor 12 External terminal 14 External terminal 105 First internal electrode layer 110 A set of alternating dielectric layers and internal electrode layers 115 Second internal electrode layer 125 Dielectric Region 135 Beer 400 processors 402 Integrated Circuit Package 404 Ball Grid Array 406 Circuit board 408 Coupling Capacitor 412 Ball Grid Array 500 processors 502 Integrated Circuit Package 504 Ball Grid Array 506 circuit board 508 Multilayer Ceramic Capacitor 512 Ball Grid Array 514 Beer

Claims

1. A body including a first set of alternating dielectric layers and internal electrode layers and a second set of alternating dielectric layers and internal electrode layers, each set of alternating dielectric layers and internal electrode layers includes a first internal electrode layer and a second internal electrode layer; a body, each internal electrode layer including a top edge, a bottom edge opposite said top edge, and two side edges extending between said top edge and said bottom edge, which define the body of said internal electrode layer; an external terminal electrically connected to the internal electrode layer; A multi-layer coupling capacitor comprising: the external terminals are formed on a top surface of the coupling capacitor and on a bottom surface of the coupling capacitor opposite the top surface of the coupling capacitor; The capacitor is a multi-layer coupled capacitor comprising one or more dielectric regions containing one or more voids.

2. 2. The multilayer coupled capacitor of claim 1 , wherein at least one of the first internal electrode layer or the second internal electrode layer electrically contacts the external terminal on the top surface of the coupled capacitor and the other internal electrode layer electrically contacts the external terminal on the bottom surface of the coupled capacitor opposite the top surface of the coupled capacitor.

3. 2. The multi-layer coupling capacitor of claim 1, wherein at least one lateral edge of the first internal electrode layer is substantially aligned with at least one lateral edge of the second internal electrode layer.

4. 2. The multi-layer coupling capacitor of claim 1, wherein both lateral edges of said first internal electrode layer are substantially aligned with both lateral edges of said second internal electrode layer.

5. 2. The multi-layer coupling capacitor of claim 1, wherein the one or more dielectric regions are present between each set of alternating dielectric layers and internal electrode layers including first and second internal electrode layers.

6. 2. The multi-layer coupling capacitor of claim 1, wherein the one or more dielectric regions are between a first or last internal electrode layer in a set and an adjacent side surface.

7. 2. The multi-layer coupled capacitor of claim 1, wherein the one or more dielectric regions are between a lateral edge of an internal electrode layer and an adjacent side surface.

8. The multi-layer coupled capacitor of claim 1 , wherein the one or more voids comprise a via.

9. The multi-layer coupled capacitor of claim 8 , wherein the vias extend through a thickness of the capacitor.

10. 2. The multi-layer coupling capacitor of claim 1, wherein said dielectric region is the region that exists between two external terminals.

11. 10. The multi-layer coupled capacitor of claim 1, wherein the one or more voids comprise from 1 vol. % to 15 vol. % of the capacitor.

12. The multi-layer coupled capacitor of claim 1 , wherein the dielectric layers comprise a ceramic.

13. The multi-layer coupled capacitor of claim 12 , wherein the ceramic comprises a titanate.

14. The multi-layer coupled capacitor of claim 1 , wherein the internal electrode layers comprise a conductive metal.

15. The multi-layer coupled capacitor of claim 14 , wherein the conductive metal comprises nickel or an alloy thereof.

16. The multilayer coupling capacitor of claim 1 , wherein the external terminals are electroplated layers.

17. The multilayer coupling capacitor according to claim 1 , wherein the external terminals are electrolessly plated layers.

18. The multi-layer coupling capacitor of claim 1 , wherein the external terminals comprise a conductive metal.

19. 20. The multi-layer coupled capacitor of claim 18, wherein the conductive metal comprises silver, gold, palladium, platinum, tin, nickel, chromium, titanium, tungsten, or combinations or alloys thereof.

20. 20. The multi-layer coupling capacitor of claim 18, wherein the conductive metal comprises copper or an alloy thereof.

21. A circuit board comprising the coupling capacitor of claim 1 .

22. A communication device comprising the coupling capacitor of claim 1 .

23. 20. The communication device of claim 16, comprising an Ethernet system, a wireless network router, a fiber optic communication system, or a storage device.

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