Integrated circuits with getter layers for hydrogen uptake.

Abstract

An integrated circuit (IC) substrate manufacturing process provides time-dependent device characteristic variation due to hydrogen absorption by including one or more gettering layers near devices that would otherwise absorb hydrogen and exhibit the variation as hydrogen migrates into the devices. The method includes forming or mounting the devices on an upper surface of a semiconductor wafer in a die region of the substrate, forming a semiconductor structure in the semiconductor die region, forming a getter layer above or adjacent to the devices in the die region, and processing the wafer by one or more processes that expose the wafer to a vapor having a hydrogen content, whereby the amount of hydrogen absorbed by the devices is reduced by the presence of the getter layer. The method produces a wafer including a semiconductor die having reduced hydrogen absorption by the devices, and a packaged IC including the die.

Description

[Technical field]

[0001] background 1. Field of disclosure The field of representative embodiments of this disclosure relates to integrated circuits (ICs), and more specifically to ICs having a getter layer integrated on a substrate to extract hydrogen that may be absorbed by devices otherwise affected by hydrogen absorption. [Background technology]

[0002] 2.Background Resistors with stable thermal properties are typically required for current sensing applications such as power audio output stages, battery monitors, and motor controllers. Such low temperature coefficient of resistance (TCR) resistors are typically used to generate a sense voltage proportional to the current through the device. Common materials for implementing such resistors on a semiconductor die are tantalum nitride (TaNx) and various silicon-chromium and silicon / chromium / nickel / titanium combinations.

[0003] The process applied in the manufacture of silicon wafers used to produce semiconductor dies uses vapors containing free hydrogen (silane (SiH4) gas, pure hydrogen (H2), and hydrogen-nitrogen (H X N Y) mixture) and the passage of the vapor, hydrogen can be absorbed from the vapor containing free hydrogen by the resistive material used to produce the thin film resistor on the die during both the deposition and annealing processes. When captured by the body of the thin film resistor, the absorbed hydrogen atoms behave in a manner similar to depletion carriers in a semiconductor. When a voltage is applied to the resistor, the resulting electric field modifies the resistance of the resistor as the resulting current causes the hydrogen to drift within the body of the resistor in the direction of the resulting current, and only restores when the current is removed or changes direction. The result is a time-dependent, signal-dependent, and nonlinear modulation of the resistor's resistance, which also depends on the temperature and physical geometry of the resistor. The resistance variation results in an inaccuracy in the linearity of any current measurement made using the resistor, which depends on the recent history of the current through the resistor, and also on the temperature of the resistor.

[0004] It would therefore be advantageous to provide ICs and IC substrates / wafers in which the time variations in properties caused by hydrogen absorption are prevented or reduced. Summary of the Invention [Means for solving the problem]

[0005] Time-dependent device characteristic variations due to the introduction of hydrogen into the device are prevented or reversed in integrated circuit (IC) substrates and methods of manufacturing IC substrates.

[0006] The method reduces time-dependent property variations of devices mounted or formed on a semiconductor wafer by inhibiting hydrogen absorption in the devices during fabrication. The method includes forming or mounting a device on an upper surface of the semiconductor wafer in a substrate die region, the device being a device of a material that absorbs hydrogen and exhibits an electrical property change dependent on the amount of absorbed hydrogen. The method also includes forming a semiconductor structure in the semiconductor die region, forming a getter layer over or adjacent the device in the die region, and processing the wafer with one or more processes that expose the wafer to a vapor having a hydrogen content, whereby the amount of hydrogen absorbed in the device is reduced by the presence of the getter layer.

[0007] The above summary is provided for a brief description and does not limit the scope of the claims. The following description describes exemplary embodiments according to this disclosure. Further embodiments and implementations will be apparent to those skilled in the art. Those skilled in the art will recognize that various equivalent technologies can be applied in place of or in conjunction with the embodiments described below, and all such equivalent technologies are encompassed by the present disclosure. [Brief description of the drawings]

[0008] [Figure 1A] FIG. 1A is a simplified circuit diagram illustrating an example power output stage that may be implemented with one or more sense resistors RS1 fabricated by a process according to an embodiment of the disclosure.

[0009] [Figure 1B] FIG. 1B is a pictorial diagram depicting an exemplary wafer 20 in accordance with an embodiment of the disclosure.

[0010] [Figure 1C] FIG. 1C is a pictorial diagram depicting an example integrated circuit 30 in accordance with an embodiment of the disclosure.

[0011] [Diagram 2]FIG. 2A is a graph 32 depicting the electrical effect of hydrogen absorption on a thin film resistor, and FIG. 2B is a graph 36 depicting the electrical effect of hydrogen absorption on a thin film resistor.

[0012] [Diagram 3] 3A-3C are pictorial diagrams depicting the behavior of absorbed hydrogen within resistor RP.

[0013] [Figure 4A] FIG. 4A is a cross-sectional view of an example substrate stack 50A that may be used to mount a die 22 of an example wafer 20 integrated circuit assembly 30 according to an embodiment of the disclosure.

[0014] [Figure 4B] FIG. 4B is a cross-sectional view of an example substrate stack 50B that may be used to mount a die 22 of an example wafer 20 integrated circuit assembly 30 in accordance with another embodiment of the disclosure.

[0015] [Figure 4C] FIG. 4C is a cross-sectional view of an example substrate stack 50C that may be used to mount a die 22 of an example wafer 20 integrated circuit assembly 30 in accordance with another embodiment of the disclosure.

[0016] [Figure 4D] FIG. 4D is a cross-sectional view of an example substrate stack 50D that may be used to mount a die 22 of an example wafer 20 integrated circuit assembly 30 in accordance with another embodiment of the disclosure.

[0017] [Diagram 5] FIG. 5 is a cross-sectional view of an exemplary substrate stack 60 that may be used to mount the die 22 of the exemplary wafer 20 integrated circuit assembly 30 in accordance with another embodiment of the disclosure.

[0018] [Figure 6A]FIG. 6A is a process flow diagram depicting an exemplary process that may be used to implement the substrate stack 50A of FIG. 4A according to an embodiment of the disclosure.

[0019] [Figure 6B] FIG. 6B is a process flow diagram depicting an exemplary process that may be used to implement the substrate stack 50B of FIG. 4B according to an embodiment of the disclosure.

[0020] [Figure 6C] FIG. 6C is a process flow diagram depicting an exemplary process that may be used to implement the substrate stack 50C of FIG. 4C according to an embodiment of the disclosure.

[0021] [Figure 6D] FIG. 6D is a process flow diagram depicting an exemplary process that may be used to implement the substrate stack 50D of FIG. 4D according to an embodiment of the disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS The present disclosure encompasses methods of manufacturing integrated circuits (ICs), wafers containing IC dies, and wafers / dies that reduce or eliminate hydrogen absorption by devices on the wafer that exhibit time-dependent electrical characteristics due to absorbed hydrogen. A getter layer is provided proximate the device such that the getter layer draws hydrogen from the device and captures the hydrogen without the hydrogen being absorbed by the device. The method also includes forming other semiconductor structures on the die and processing the wafer with one or more processes that expose the wafer to steam having a hydrogen content, whereby the amount of hydrogen absorbed by the device is reduced by the presence of the getter layer.

[0023] 1A, a simplified circuit diagram of an exemplary power output stage 10 that may be implemented with one or more sense resistors RS1 fabricated by a process according to an embodiment of the disclosure is shown. An input signal in is received by an amplifier A1, which provides an output to a bias circuit 12, which in turn provides a bias current to a load impedance Z L The power output signal is provided to the load impedance Z through the transistor N1 or the transistor P1. L The current level provided to is sensed by sense resistor R1, which creates a voltage drop that is sensed by amplifier A2, which provides an output to current measurement block 14, which creates an indication of the measured current, Current meas. While the current sensing in the depicted exemplary power output stage 10 is from the output of the exemplary power output stage 10, a pair of sense resistors can be used to measure the current through transistor P1 and transistor N1. The current through sense resistor RS1 is usually at a high current level and is sensed by the power supply voltage +V DD Since the voltages at which the exemplary power output stage 10 is integrated may be higher than the poly resistors in the integrated IC can withstand, thin film resistors are used to handle the higher current / voltage levels and to provide a low TCR with a stable resistance over thermal variations that may occur in the sense resistor RS1 due to the relatively high current levels. Thin film resistors may also be required due to the level of resistance of the sense resistor RS1 that is needed to produce an easily measurable sense voltage. The material used to fabricate the sense resistor RS1 is typically tantalum nitride (TaN), chrome-silicon, silicon / chrome / nickel combination, or other suitable low TCR material.

[0024] 1B, a diagram of an exemplary wafer 20 is illustrated in accordance with an embodiment of the disclosure. The wafer 20 is the result of a process described in more detail below and incorporates one or more thin-film resistors R and other semiconductor structures 23 (e.g., electrical circuitry including the exemplary power output stage 10 of FIG. 1) into each of a number of dies 22. In subsequent processing, the wafer 20 is singulated to obtain separate dies 22 for assembly into packaged ICs. Additionally, referring to FIG. 1C, a diagram depicting an exemplary IC 30 is shown in accordance with an embodiment of the disclosure. The exemplary IC includes one of the dies 22, an encapsulation 24 covering the die 22, and a number of terminals for making electrical contact with circuitry integrated on the die 22.

[0025] 2A, a graph 32 is shown depicting the electrical effects of hydrogen absorption on thin film resistors. Graph 32 illustrates the percent change in resistance over time of thin film resistors for two different fabrication facilities (fabs) at different levels of processing. For a first fab, fab1, curve 34A shows the change in resistance after alloy annealing while curve 34B shows the change in resistance over time before annealing. For a second fab, fab2, curve 34C shows the change in resistance after alloy annealing while curve 34D shows the change in resistance over time before annealing. The alloy annealing process uses H2 or H X N XAs with the introduction of hydrogen via the atmosphere, the observation that a certain amount of hydrogen has been introduced into the body of resistor RP is the cause of the time-dependent change in resistance. Referring now to FIG. 2B, another graph 36 is shown depicting the electrical effects of hydrogen absorption into a thin film resistor. Graph 32 illustrates the percent change in resistance of a thin film resistor over time with respect to an applied current. Curve 38A shows the change in resistance of thin film resistor RP in a wafer from fab1, and curve 38B shows the change in resistance of thin film resistor RP in a wafer from fab1, with the same current level applied to thin film resistor RP. At 40 minutes, the direction of the applied current is reversed, displaying a reversal of the effect, resulting in an increase in resistance. At 55 minutes, the resistance has decreased to a point where the resistance is less than the initial resistance before the current was applied, and then the resistance increases again.

[0026] 3A-3C, pictorial diagrams illustrating the behavior of absorbed hydrogen atoms 42 in a thin-film resistor RP are shown. FIG. 3A illustrates the initial arrangement of absorbed hydrogen atoms 42 in the body 40 of resistor RP, which is presumably uniform. FIG. 3B illustrates the distribution of absorbed hydrogen atoms 42 in the body 40 after a voltage is applied between terminals T1 and T2 of resistor RP for a time interval. The absorbed hydrogen atoms, acting as depletion carriers as described above, migrate to the right region 44B of body 40, leaving the left region 44B of body 40 free of absorbed hydrogen atoms. FIG. 3C illustrates the distribution of absorbed hydrogen atoms 42 in the body 40 after a reversed voltage is applied between terminals T1 and T2 of resistor RP. The absorbed hydrogen atoms 42, acting as depletion carriers as described above, migrate to the left region 44A of body 40, leaving the right region 44B of body 40 free of absorbed hydrogen atoms. For both the applied voltages shown in Figures 3B and 3C, the resistance of resistor R increases beyond that illustrated in Figure 3A until the applied voltage is removed and sufficient recovery time has elapsed (on the order of 10 minutes).

[0027] 4A, a cross-sectional view of an exemplary substrate stack 50A that may be used to mount an exemplary wafer 20 and die 22 of an integrated circuit assembly 30 according to an embodiment of the disclosure is shown. The body 40A of the thin-film resistor R is formed or mounted on an insulating layer 54C deposited on a base substrate 50. As described above, the body 40A may be tantalum nitride (TaN), chromium-silicon, silicon / chromium / nickel combination, or other suitable low-TCR resistance material. The insulating layer 54C (which may be, for example, silicon nitride (SiN), N-block, silicon carbide, etc.) serves as both an etch stop layer and a copper diffusion barrier. On top of the body 40A is deposited an insulating material layer 54B, which may be the same material as the insulating layer 54C. On top of the insulating layer 54B is deposited a gettering material layer 56, which will capture free hydrogen near the body 40A and prevent the body 40A from absorbing hydrogen. The gettering material forming the gettering material layer 56 can be an insulator (such as a metal oxide that extracts hydrogen) or a metal layer, but the metal getter layer is preferably implemented by a separate process and at a separate location to insulate the conductive material from other layers, as described in more detail below with reference to FIG. 5. For example, the gettering material can be lanthanum oxide, manganese oxide, etc. The metal gettering layer can be barium or another hydrogen gettering metal, such as zirconium or niobium. Another insulating layer 54A is optionally deposited on the gettering material layer 56 and can be the same material as the insulating layer 54C. A dielectric layer 58 is deposited over the body 40A and other structures on the base substrate 50, after which vias 53 and metal interconnects 52, including vias 53A that provide terminals for the thin film resistors R, are formed in the dielectric layer 58. The dielectric layer can be any suitable dielectric material having a low dielectric constant, such as, for example, silicon dioxide (SiO2) or fluorinated tetraethyl orthosilicate (FTEOS).

[0028] Additionally, referring to FIG. 6A, a process flow diagram is shown depicting an exemplary process that can be used to implement the substrate stack 50A of FIG. 4A according to an embodiment of the disclosure. First, the wafer is mechanically and chemically planarized (step 70) and a layer of SiN is deposited (step 71). The wafer is cleaned (step 72) and a thin film resistor (TFR) body 40A is deposited (step 73). The next layer of SiN, getter material, and hard mask is deposited (step 74) and a lithographic pattern for etching the TFR regions is applied and developed (step 75). The SiN layer, getter material layer, and hard mask / TFR layer are etched (step 76), after which the wafer is cleaned (step 77) and a dielectric is deposited (step 78). Via lithography is performed (step 79) and via locations are etched (step 80). Metal lithography to form trenches is performed (step 81), the metal is etched, and via punch-through is performed, including through the getter layer and any insulating layers overlying the via locations (step 82). A barrier / seed material is deposited (step 83), and copper is electroplated into the seed areas (step 84). Finally, another mechanical and chemical planarization is performed to finish the wafer (step 85).

[0029] 4B, a cross-sectional view of an exemplary substrate stack 50B that can be used to mount the die 22 of the exemplary wafer 20 integrated circuit assembly 30 according to an embodiment of the disclosure is shown. The substrate stack 50B is similar to the substrate stack 50A of FIG. 4A, and therefore only the differences between them are described below. In the substrate stack 50B, the gettering material layer 56 is deposited on both the top and four sides of the TFR body 40A, yet the insulating layer 54B is deposited first on the TFR body 42A. The gettering material layer 56 is in direct contact with the TFR body 40A, but only at the ends / sides of the TFR body 40A, and therefore the effect of the gettering material layer 56 on the resistor R is reduced. The insulating layer 54B is present, and therefore the insulating layer 54A surrounds the gettering material layer 56 at the sides of the TFR body 40A. The insulating layer 54C extends across the entire substrate as in the substrate stack 50A of FIG. 4A, but the gettering material layer 56 is masked and removed, so that the gettering material layer 56 does not inhibit hydrogen migration to the base substrate 50, which is required for passivation of the gate terminal of the device located below the base substrate 50 or at a level below the base substrate 50. Additionally, referring to FIG. 6B, a process flow diagram is shown depicting an exemplary process that may be used to implement the substrate stack 50B of FIG. 4B, according to an embodiment of the disclosure. The process flow of FIG. 6B is similar to the process flow depicted in FIG. 6A, and therefore only the differences between them are described below. Rather than depositing SiN, getter material, and hard mask in step 74 of FIG. 6A, only hard mask deposition is performed at that stage (step 74A of FIG. 6B), and the getter layer and the SiN layer are not etched in step 76A of FIG. 6B. A gettering material layer 56 and optionally another SiN insulating layer (insulating layer 54A) are deposited in a new step 74B in FIG. 6B, which is inserted after the wafer cleaning in step 77.

[0030] Referring now to FIG. 4C, a cross-sectional view of an exemplary substrate stack 50C that may be used to implement the die 22 of the exemplary wafer 20 integrated circuit assembly 30 according to an embodiment of the disclosure is shown. The substrate stack 50C is similar to the substrate stack 50B of FIG. 4B, and therefore only the differences between them will be described below. In the substrate stack 50C, an insulating layer 54B is deposited on both the sides and the top of the TFR body 40A, isolating the TFR body 40A from any contact with the gettering material layer 56. Additionally referring to FIG. 6C, a process flow diagram is shown depicting an exemplary process that may be used to implement the substrate stack 50C of FIG. 4C according to an embodiment of the disclosure. The process flow of FIG. 6C is similar to the process flow depicted in FIG. 6B, and therefore only the differences between them will be described below. After wafer cleaning in step 77, in the process of FIG. 6C, step 74C in FIG. 6C deposits a SiN insulating layer 54B, followed by a getter material layer 56 and optionally an insulating layer (insulating layer 54A).

[0031] Referring now to FIG. 4D, a cross-sectional view of an exemplary substrate stack 50D that may be used to mount the die 22 of the exemplary wafer 20 integrated circuit assembly 30 is shown according to another embodiment of the disclosure. The substrate stack 50D is similar to the substrate stack 50C of FIG. 4C, and therefore only the differences between them are described below. In the substrate stack 50D, before the TRF body 40A is formed or mounted on the base substrate 50, an insulating layer 54C is deposited, and a second getter material layer 56A and another insulating layer 54D are formed on the base substrate 50 in the region of the TRF body 40A, so that the TRF body 40A is effectively surrounded by a gettering material. In addition, referring to FIG. 6D, a process flow diagram is shown depicting an exemplary process that may be used to mount the substrate stack 50D of FIG. 4D according to an embodiment of the disclosure. The process flow of FIG. 6D is similar to the process flow depicted in FIG. 6C, and therefore only the differences between them are described below. After planarization in step 70, insulating layer 54C and second getter material layer 56A are deposited in step 71A. Alignment and lithography / etching are performed on the getter material layer in step 71B, which may be combined at this stage with other required lithography processes. In an etching process after TFR lithography in step 75, step 76B etches TRF body 42A and insulating layer 54D in step 76B. The formation of the structure above the next TRF body 42A continues as described above with reference to FIG. 6C.

[0032] 5, a cross-sectional view of an exemplary substrate stack 60 that may be used to mount a die 22 of an exemplary wafer 20 integrated circuit 30 according to an embodiment of the disclosure is shown. In the substrate stack 60, a getter layer 56B is deposited or attached above a dielectric layer 58, and an optional insulating layer 54E may be included as needed to isolate the getter layer 56B from the dielectric layer 58 or other features (e.g., circuit patterns, etc.). The substrate stack 60 is particularly suitable with metallic getter materials to provide isolation of the metal-formed getter layer 56B from other circuit features, as discussed above.

[0033] In summary, this disclosure shows a method of manufacturing an integrated circuit substrate and a structure of the integrated circuit substrate. The method is a method of reducing time-dependent variations during fabrication due to hydrogen absorption in the properties of devices mounted or formed on a semiconductor wafer. The method may include forming or mounting devices on an upper surface of the semiconductor wafer in a die region of the substrate, the devices being devices of a material that absorbs hydrogen and exhibits an electrical property change dependent on the amount of absorbed hydrogen. The method further includes forming a semiconductor structure in the semiconductor die region, forming a getter layer above or adjacent to the devices in the die region, and processing the wafer by one or more processes that expose the wafer to a steam having a hydrogen content, whereby the amount of hydrogen absorbed in the devices is reduced by the presence of the getter layer. A semiconductor wafer according to an embodiment of the disclosure may include a base wafer, a plurality of devices mounted or formed in the die region on the upper surface of the base wafer, the devices being devices of a material that absorbs hydrogen and exhibits an electrical property change dependent on the amount of absorbed hydrogen, the semiconductor structures formed on the upper surface of the base wafer in the die region of the base wafer, and a getter layer disposed above or adjacent to each individual device. An integrated circuit according to an embodiment of the disclosure may include a semiconductor die having devices mounted or formed on a substrate thereof, the devices being of a material that absorbs hydrogen and exhibits an electrical characteristic change dependent on the amount of absorbed hydrogen. The semiconductor die may include one or more semiconductor structures formed on a top surface of a substrate of the die and a getter layer disposed above or adjacent to the devices. The integrated circuit further includes an encapsulation formed around the die and a plurality of terminals provided on one or more outer surfaces of the encapsulation and connected to electrical terminals of the die.

[0034] In some embodiments, forming and mounting the device forms or mounts a tantalum nitride thin film or a chrome silicon resistor on the wafer. In some exemplary embodiments, forming the getter layer is performed by depositing a metal on a layer above the device, the layer being spaced from the device by one or more insulating layers. In some exemplary embodiments, forming the getter layer forms a getter layer adjacent to one or more surfaces of the device. In some exemplary embodiments, forming the getter layer may form a getter layer directly on one or more surfaces of the device. In some exemplary embodiments, forming the getter layer may further include depositing a device protective insulating layer on one or more surfaces of the device and depositing the getter layer on the device protective insulating layer. In some exemplary embodiments, the material of the getter layer is an insulating material, which in some exemplary embodiments may be a metal oxide. In some exemplary embodiments, the getter layer is formed only above the top surface of the device. In other exemplary embodiments, the getter layer is formed above the top surface of the device and adjacent to the sides of the device. In some exemplary embodiments, the getter layer is a second getter layer, and the method further includes forming a first getter layer on the wafer in a device loading or formation area in the die region prior to forming or mounting the device, and forming an insulating layer over the first getter layer, and forming or mounting the device forms or mounts the device on the insulating layer above the first getter layer. In some exemplary embodiments, the method further includes masking the first getter layer around the device to provide for hydrogen migration under the first getter layer, and stripping off the unmasked portions of the first getter layer.

[0035] While the disclosure has shown and described particular embodiments of the technology disclosed in this application, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made therein without departing from the spirit and scope of the disclosure. For example, the technology disclosed above may be applied to devices other than resistors susceptible to hydrogen absorption.

Claims

1. 1. A method for reducing time dependent variations in characteristics of devices mounted or formed on a semiconductor wafer during fabrication due to hydrogen absorption, the method comprising: forming or mounting said device on an upper surface of said semiconductor wafer in a substrate die area, said device being of a material that absorbs hydrogen and exhibits an electrical characteristic change dependent on the amount of absorbed hydrogen; forming a semiconductor structure in the semiconductor die region; forming a getter layer over or adjacent to the device in the die area; processing the wafer by one or more processes that expose the wafer to steam having a hydrogen content; Including, A method whereby the amount of hydrogen absorbed in the device is reduced by the presence of the getter layer.

2. The method of claim 1 , wherein forming or mounting the device comprises forming or mounting a tantalum nitride thin film or a silicon-chromium resistor on the wafer.

3. 2. The method of claim 1, wherein forming the getter layer is performed by depositing a metal in a layer above the device, the layer being spaced from the device by one or more insulating layers.

4. The method of claim 1 , wherein forming the getter layer comprises forming the getter layer adjacent to one or more surfaces of the device.

5. The method of claim 4 , wherein forming the getter layer comprises forming the getter layer directly on the one or more surfaces of the device.

6. The forming of the getter layer includes depositing a device-protecting insulating layer over one or more surfaces of the device; depositing the getter layer on the device-protecting insulating layer; The method of claim 4 , comprising:

7. The method of claim 4 , wherein the material of the getter layer is an insulating material.

8. The method of claim 7 , wherein the depositing comprises depositing a metal oxide.

9. The method of claim 7 , wherein the getter layer is formed only above a top surface of the device.

10. The method of claim 7 , wherein the getter layer is formed over a top surface of the device and on or adjacent a side surface of the device.

11. the getter layer is a second getter layer, and the method further comprises: forming a first getter layer on the wafer in a mounting or forming area of ​​the device in the die area prior to forming or mounting the device; forming an insulating layer on the first getter layer; Further comprising: The method of claim 7 , whereby forming or mounting the device forms or mounts the device on the insulating layer above the first getter layer.

12. masking the first getter layer around the device to provide for hydrogen migration beneath the first getter layer; removing unmasked portions of the first getter layer; The method of claim 11 further comprising:

13. A semiconductor wafer, the semiconductor wafer comprising: A base wafer; a plurality of devices mounted or formed on a die region on an upper surface of the base wafer, the devices being of a material that absorbs hydrogen and exhibits an electrical characteristic change that is dependent on the amount of absorbed hydrogen; a semiconductor structure formed on a top surface of the base wafer in a die region of the base wafer; a getter layer disposed above or adjacent to said individual devices; A semiconductor wafer comprising:

14. 14. The semiconductor wafer of claim 13, wherein the devices are tantalum nitride or silicon chrome thin film resistors.

15. 14. The semiconductor wafer of claim 13, wherein the getter layer is a metal layer disposed over the devices and spaced therefrom by one or more insulating layers.

16. 14. The semiconductor wafer of claim 13, wherein the getter layer is disposed adjacent one or more surfaces of the device.

17. 17. The semiconductor wafer of claim 16, wherein the getter layer is disposed directly over the one or more surfaces of the device.

18. 20. The semiconductor wafer of claim 16, further comprising a device protective insulating layer disposed on the one or more surfaces of the device, the getter layer being disposed on the device protective insulating layer.

19. 20. The semiconductor wafer of claim 16, wherein the getter layer is an insulating material.

20. 20. The semiconductor wafer of claim 19, wherein the insulating material is a metal oxide.

21. 20. The semiconductor wafer of claim 19, wherein the getter layer is disposed only over a top surface of the device.

22. 20. The semiconductor wafer of claim 19, wherein the getter layer is disposed over a top surface of the device and on or adjacent a side surface of the device.

23. the getter layer is a second getter layer, and the semiconductor wafer is a first getter layer on the wafer in a mounting or forming area of ​​the device in the die area; an insulating layer on the first getter layer; Further equipped with 20. The semiconductor wafer of claim 19, wherein the device is formed or mounted on the insulating layer.

24. 24. The semiconductor wafer of claim 23, wherein the first getter layer is limited to an area around the device to provide for hydrogen migration through gaps in the first getter layer during fabrication.

25. 1. An integrated circuit, comprising: a semiconductor die having a device mounted or formed on a substrate thereof, the device being a device of a material that absorbs hydrogen and exhibits an electrical characteristic change dependent on the amount of absorbed hydrogen, the semiconductor die including one or more semiconductor structures formed on a top surface of the substrate of the die and a getter layer disposed above or adjacent to the device; an encapsulation formed around the die; a plurality of terminals provided on one or more outer surfaces of the encapsulation and connected to electrical terminals of the die; An integrated circuit comprising:

26. 26. The integrated circuit of claim 25, wherein the device is a tantalum nitride or silicon-chromium thin film resistor.

27. 26. The integrated circuit of claim 25, wherein the getter layer is a metal layer disposed above the device and spaced therefrom by one or more insulating layers.

28. 26. The integrated circuit of claim 25, wherein the getter layer is disposed adjacent one or more surfaces of the device.

29. 30. The integrated circuit of claim 28, wherein the getter layer is disposed directly over the one or more surfaces of the device.

30. 30. The integrated circuit of claim 28, further comprising a device protective insulating layer disposed on one or more surfaces of the device, the getter layer being disposed on the device protective insulating layer.

31. 30. The integrated circuit of claim 28, wherein the getter layer is an insulating material disposed on the one or more surfaces of the device.

32. 32. The integrated circuit of claim 31, wherein the insulating material is a metal oxide.

33. 32. The integrated circuit of claim 31, wherein the getter layer is disposed only over a top surface of the device.

34. 32. The integrated circuit of claim 31, wherein the getter layer is disposed over a top surface of the device and on or adjacent a side surface of the device.

35. the getter layer is a second getter layer, and the die comprises: a first getter layer on the die in a mounting or forming area of ​​the device; an insulating layer on the first getter layer; Further equipped with 32. The integrated circuit of claim 31, wherein the device is formed or mounted on the insulating layer.

36. 36. The integrated circuit of claim 35, wherein the first getter layer is limited to an area around the device to provide for migration of hydrogen during fabrication through gaps in the first getter layer during fabrication.

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