Multi-level package substrate with stepped substrate traces

Abstract

The electronic device (100) includes a multi-level package substrate (101) with first and second levels (El, L2). The second level (L2) includes a first trace layer with a first conductive trace feature (106), a first conductive via (108) in contact with the first conductive trace feature (106), and a first dielectric layer (104). The first level (El) includes a second trace layer with a step-shaped second conductive trace feature (110). The second conductive trace feature (110) has a first portion (111) with a first thickness (113) and a second portion (112) with a second thickness (114) greater than the first thickness (113).

Description

[Technical field]

[0001] Increased functionality in packaged electronic devices has resulted in smaller packages to accommodate increased trace and die landing area density, resulting in ever-shrinking substrate lines and spaces. However, the reduction in cross-sectional area can make substrate traces more vulnerable to reliability issues during stress or electric field exposure, for example, in automotive or industrial applications. For example, cracks of substrate traces can occur in one or more substrate layers of the package substrate through package deflection at or near the edge or side of the semiconductor die edge caused by mechanical coupling of components with different coefficients or CTE during temperature cycling. Summary of the Invention

[0002] In one aspect, an electronic device includes a multi-level package substrate and a die, the multi-level package substrate having a first and a second level. The second level includes a first trace layer with a first conductive trace feature, a conductive first via contacting the first conductive trace feature, and a first dielectric layer. The second level includes a second trace layer with a second conductive trace feature having a first and second portion. The first portion has a first thickness and the second portion has a side and a second thickness, the second thickness being greater than the first thickness.

[0003] In another aspect, a multi-level package substrate has a first and a second level. The second level includes a first trace layer with a first conductive trace feature, a conductive first via contacting the first conductive trace feature, and a first dielectric layer. The second level includes a second trace layer with a second conductive trace feature having a first and second portion. The first portion has a first thickness and the second portion has a side and a second thickness, the second thickness being greater than the first thickness.

[0004] In a further aspect, a method includes forming a second level on a side of a core dielectric layer in a first plane in orthogonal first and second directions, the second level including a first trace layer with a first conductive trace feature, a first conductive via bordering the first conductive trace feature, and a first dielectric layer. The method also includes forming a first level extending on the second level in the second plane in the first and second directions. The first level includes a second trace layer with a second conductive trace feature having a first portion and a second portion. The first portion has a first thickness along an orthogonal third direction, the second portion has a side and a second thickness along the third direction, the side of the second portion faces away from the first plane, and the second thickness is greater than the first thickness. [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 is a perspective view of a flip chip ball grid array packaged electronic device with stepped substrate traces.

[0006] [Figure 1A] 1A is a partial cross-sectional side view of the electronic device taken along line 1A-1A of FIG. 1.

[0007] [Figure 1B] 1B is a partial cross-sectional top view of electronic device 100 taken along line 1B-1B of FIG. 1A.

[0008] [Figure 1C] FIG. 2 is a partial top view of a portion of a multi-level package substrate of an electronic device.

[0009] [Figure 1D] FIG. 2 is a partial top view of traces and die landing areas in a portion of a multi-level package substrate for an electronic device.

[0010] [Diagram 2]1 shows a flow chart of a method for manufacturing an electronic device.

[0011] [Diagram 3] 3 is a partial cross-sectional side view of the packaged electronic device of FIGS. 1-1D undergoing fabrication according to the method of FIG. 2. [Figure 4] 3 is a partial cross-sectional side view of the packaged electronic device of FIGS. 1-1D undergoing fabrication according to the method of FIG. 2. [Diagram 5] 3 is a partial cross-sectional side view of the packaged electronic device of FIGS. 1-1D undergoing fabrication according to the method of FIG. 2. [Figure 6] 3 is a partial cross-sectional side view of the packaged electronic device of FIGS. 1-1D undergoing fabrication according to the method of FIG. 2. [Figure 7] 3 is a partial cross-sectional side view of the packaged electronic device of FIGS. 1-1D undergoing fabrication according to the method of FIG. 2. [Figure 8] 3 is a partial cross-sectional side view of the packaged electronic device of FIGS. 1-1D undergoing fabrication according to the method of FIG. 2. [Figure 9] 3 is a partial cross-sectional side view of the packaged electronic device of FIGS. 1-1D undergoing fabrication according to the method of FIG. 2. [Figure 10] 3 is a partial cross-sectional side view of the packaged electronic device of FIGS. 1-1D undergoing fabrication according to the method of FIG. 2. [Figure 11] 3 is a partial cross-sectional side view of the packaged electronic device of FIGS. 1-1D undergoing fabrication according to the method of FIG. 2. [Figure 12] 3 is a partial cross-sectional side view of the packaged electronic device of FIGS. 1-1D undergoing fabrication according to the method of FIG. 2. [Figure 13] 3 is a partial cross-sectional side view of the packaged electronic device of FIGS. 1-1D undergoing fabrication according to the method of FIG. 2. [Figure 14] 3 is a partial cross-sectional side view of the packaged electronic device of FIGS. 1-1D undergoing fabrication according to the method of FIG. 2.

[0012] [Figure 15]FIG. 1 illustrates a partial cross-sectional side view of another flip chip ball grid array packaged electronic device including stepped substrate traces and a conductive lid.

[0013] [Figure 16] FIG. 1 illustrates a partial cross-sectional side view of another flip chip ball grid array packaged electronic device including stepped substrate traces and a flat conductive lid. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] In the drawings, like reference numbers refer to like elements throughout, and various features are not necessarily drawn to scale. Additionally, the term "couple" includes an indirect or direct electrical or mechanical connection, or a combination thereof. For example, when a first device couples to or is coupled with a second device, the connection may be through a direct electrical connection, or through an indirect electrical connection via one or more intervening devices and connections. One or more operational characteristics of various circuits, systems, and / or components are described below, in some cases, in the context of the functionality that results from the configuration and / or interconnection of various structures when the circuit elements are powered and operating.

[0015] 1-1D, FIG. 1 shows a perspective bottom view of a flip chip ball grid array (FCBGA) packaged electronic device 100 including a multi-level package substrate 101. FIG. 1A shows a partial cross-sectional side view of electronic device 100 taken along line 1A-1A in FIG. 1. FIG. 1B shows a partial cross-sectional top view of electronic device 100 taken along line 1B-1B in FIG. 1A, FIG. 1C shows a partial top view of a portion of multi-level package substrate 101, and FIG. 1D shows a partial top view of traces and die landing areas in a portion of multi-level package substrate 101.

[0016] The multilevel package substrate 101 includes four levels L1, L2, L3, and L4. In other examples, the multilevel package substrate includes any integer number of two or more levels. Each of the levels L1-L4 has patterned conductive features, such as copper, aluminum, or other conductive metals. The core dielectric layer 102 has opposing first and second sides. The first level L1 and the second level L2 are formed on or above a first side of the core dielectric layer 102 (e.g., the upper or top side in the orientation shown in Figures 1 and 1A), and the third level L3 and the fourth level L4 are formed on or below a second side of the core dielectric layer 102 (e.g., the lower or bottom side). The second level L2 extends on the top side of the core dielectric layer 102 in a second plane in orthogonal first and second directions X and Y, respectively. The core dielectric layer 102 and the levels L1-L4 are formed in a stack structure along a third direction Z perpendicular to the first and second directions X and Y. The first level L1 extends above the second level L2 in a second plane of the first and second directions X and Y. The third level L3 extends to the bottom side of the core dielectric layer 102 in a third plane of the first and second directions X and Y. The fourth level L4 extends above the third level L3 in a fourth plane of the first and second directions X and Y.

[0017] As best shown in FIG. 1A, the core dielectric layer 102 includes conductive plated through holes 103 (e.g., copper, aluminum, or other conductive metal) extending through the core dielectric layer 102 along a third direction Z orthogonal to the first and second directions X and Y. The second level L2 includes a first dielectric layer 104 and a first trace layer with first conductive trace features 106 on the top side of the core dielectric layer 102. The first conductive features 106 have a thickness 107 of, for example, 10-25 μm. The second level L2 also includes conductive first vias 108 that contact each of the first conductive trace features 106. In one example, the first dielectric layer 104 is a compression molded laminate layer that extends between and around different conductive features of the second level L2 and between adjacent levels in the multilevel package substrate 101. The molded dielectric features at the various levels in one example are or include electrically insulating dielectric materials, e.g., films such as Ajinomoto Build-Up Film (ABF) or fiberglass reinforced prepreg materials. The thickness and dielectric material at each level provides the withstand voltage according to the desired voltage isolation between the circuitry and its components for a given design.

[0018] The first level L1 includes a second trace layer with second conductive trace features 110 on the second level L2. One or more of the second conductive trace features 110 each have a step shape with a first portion 111 and a thicker second portion 112. The first portion 111 has a first thickness 113 along a third direction Z. Each second portion 112 has a side 117 (e.g., a top side facing upward in the illustrated orientation of FIG. 1A) that faces away from the first plane. Each second portion 112 has a second thickness 114 along the third direction Z. The second thickness 114 is thicker than the first thickness 113, and the top side of the second portion 112 extends a distance 115, e.g., 1-15 μm, above the top of the first portion 111. In one example, the first thickness 113 is 10-20 μm (e.g., 15 μm+ / -5 μm) and the second thickness 114 is 5-15 μm greater than the first thickness 113 (e.g., the additional thickness distance 115 is 10 μm+ / -5 μm). The stepped second conductive trace feature 110 in one example is formed in selected high stress areas or regions to reduce or avoid trace cracking, as illustrated in connection with Figures 1B-1D and further described below.

[0019] The electronic device 100 includes a top solder mask structure 116 with openings over portions of the top side 117 of the second portion 112 of the second conductive trace feature 110 for solder bonding to the conductive terminals of the semiconductor die 120. The solder connections are flip-chip solder connections of the conductive terminals 122 (e.g., copper posts or bumps) of the die 120 using conductive solder 124 to electrically couple each terminal 122 to the top side 117 of each second portion 112. The electronic device 100 also includes a package structure 128 that surrounds the die 120 and a portion of the multilevel package substrate 101. In one example, the package structure 128 is or includes a molded material such as plastic. In another example, the package structure 128 is or includes a ceramic material.

[0020] The third level L3 includes a third dielectric layer 130, a third trace layer with one or more third conductive trace features 132 on a second (e.g., bottom) side of the core dielectric layer 102, and conductive second vias 134 contacting the third conductive trace features 132. In one example, the multilevel package substrate 101 includes an optional second (e.g., bottom) solder mask 136 in the fourth level L4 covering a portion of the bottom side of the third dielectric layer 130. The third conductive features 132 have a thickness 137, for example, between 10 and 25 μm. In one example, the third dielectric layer 130 is a compression molded laminate layer that extends between and around different conductive features of the third level L3 and between adjacent levels in the multilevel package substrate 101. In one example, the molded dielectric layers 104 and 130 of the multi-level package substrate 101 are or include MJ1 ABF RLF dielectric material, and the package structure 128 is or includes epoxy molding compound (EMC).

[0021] The fourth level L4 includes a fourth trace layer with one or more fourth conductive trace features 140. One or more of the fourth conductive trace features 140 have a first portion 141 and a second portion 142. The first portion 141 of the fourth conductive trace feature 140 has a third thickness 143 along a third direction Z, and the second portion 142 of the fourth conductive trace feature 140 has a fourth thickness 144 along the third direction Z. The second portion 142 of each of the fourth conductive trace features 140 has a second side 147 that faces away from the third plane (e.g., downward in the orientation of FIG. 1A). The fourth thickness 144 is greater than the third thickness 143 of each of the fourth conductive trace features 140. The multi-level package substrate 101 has one or more solder balls 146 attached to a second side 147 (e.g., landing pads) of each of the fourth conductive trace features 140 to enable soldering of the electronic device 100 to a host system, such as a printed circuit board (not shown).

[0022] The fourth thickness 144 is greater than the third thickness 143, and the top side of the second portion 142 extends above the top of the first portion 141 a distance 145, e.g., 1-15 μm. In one example, the third thickness 143 is 10-20 μm (e.g., 15 μm+ / -5 μm), and the fourth thickness 144 is 5-15 μm greater than the third thickness 143 (e.g., the additional thickness distance 145 is 10 μm+ / -5 μm). The step-shaped fourth conductive trace feature 140 in one example is formed in selected high stress areas or regions to reduce or avoid trace cracking, as illustrated in connection with FIGS. 1B-1D and further described below.

[0023] In some implementations, packaged electronic device 100 may include an optional conductive lid structure (e.g., FIGS. 15 and 16, described below), such as copper or other thermally and electrically conductive metal, for heat dissipation during operation. The optional lid, if used, may extend over the top side of die 120 and may optionally contact the top side of die 120, for example, via an adhesive thermal interface material.

[0024] 1A and 1B, one or more regions 151, 152, and 153 of an electronic device may be subject to mechanical stress, for example, caused by thermal cycling during operation. Substrate traces may be susceptible to cracking in high stress areas, such as the die shadow region of an FCBGA package (as shown below), due to package deflection at the die edge caused by lid-to-substrate bonding during temperature cycling. This may be caused by mismatches in the coefficient of thermal expansion (CTE) of adjacent structures, such as the die 120, the multilevel package substrate 101, any included lid, and the package structure 128.

[0025] 1A and 1B show example first regions 151 and 152 having high thermally induced stress on conductive substrate traces in or near the die shadow areas proximate the lateral sides of the die 120. In one implementation, the second conductive feature 110 is provided with a step shape having a first portion 111 and a second portion 112 in one or both of the first regions 151 and / or 152 of the first level L1 proximate the lateral sides of the die 120. Different device designs can selectively include step-shaped second conductive feature 110 in any identified or selected area to mitigate or avoid trace cracking. FIG. 1A further shows a second region 153 of the fourth level L4 having high susceptibility to stress and substrate trace cracking, and the illustrated example includes a step-shaped fourth conductive trace feature 140 having first and second portions 141 and 142 disposed in the second region 153 of the fourth level L4 to reduce or avoid trace cracking in the multi-level package substrate 101.

[0026] The described examples provide a solution to mitigate or avoid substrate trace cracking, for example, by selective design of thicker portions 112 and / or 142 of copper or other trace metal within the same trace layer in high stress areas of the packaged electronic device 100. In another example, one or more trace layers in the multilevel package substrate 101 have stepped conductive features with three or more thicknesses selectively placed to mitigate stress during device operation. These solutions allow a given design to be tailored for identified or suspected CTE mismatch structural relationships, for example, adjacent to or along the die shadow regions and adjacent areas along the die corners and perimeters, where substrate traces have been found to crack due to higher trace density at these locations. As described below, stepped conductive trace features can be fabricated using existing lithography processes used in substrate manufacturing to selectively increase or thicken the cross-sectional area of ​​the conductive traces by increasing their height in the Z direction to maximize crack propagation paths. In this example, thicker (e.g., higher) copper thickness is strategically placed in high stress areas within the package to relieve stress and enable more robust chip-package interaction. An additional benefit is that the selectively increased thickness of the substrate trace conductor displaces areas where a higher CTE organic ABF dielectric would otherwise be placed (e.g., displaces areas of a dielectric layer or solder mask), thereby improving localized CTE mismatch due to the higher volume of copper used to expand margins.

[0027] FIG. 1B shows a top view of a device 100 having a die 120 flip-chip soldered to a respective landing area or side 117 of a multilevel package substrate 101, showing two exemplary first regions 151 and 152, the second level including one or more second conductive trace features 110 having a stepped shape with a first portion 111 and a thicker second portion 112. FIG. 1C illustrates a portion of the top side of the multilevel package substrate 101 of FIG. 1B in region 152. This portion includes several exemplary traces 110 having a stepped shape with first and second portions 111 and 112, illustrating the high trace and landing area density in the first region 152. FIG. 1D shows further detail of a portion of the region of FIG. 1C, further illustrating the narrow spacing between the routed trace features and the landing area side of the second portion 112 below the solder 124.

[0028] 1, the landing pad formed by the second side 147 has a circular shape and includes patterned conductive features on the fourth level L4 to facilitate attachment of the solder ball 146. The electronic device 100, coupled with the performance advantages associated with the multi-level packaging substrate 101, offers compatibility with existing PCB layout designs for FCBGA devices. This facilitates improved electronic device performance without requiring redesign of existing PCBs.

[0029] Also, referring to FIGS. 2-14, FIG. 2 shows a method 200 for manufacturing an electronic device, and FIGS. 3-14 show a packaged electronic device 100 undergoing manufacture according to the method 200. The method 200 is described as an example with layers built on both sides of a starting core layer. In various implementations, layers can be built on the bottom and top simultaneously, or one side (e.g., top or bottom) can be built first, and then one or more layers can be created on the other side. The method 200 includes, at 201-204, forming a second level L2 on the top side of the core dielectric layer 102, and forming a first level L1 on the second level L2. FIGS. 3-6 show the formation of the second level L2, which in one example is formed simultaneously with a third level L3, the details of which are not shown in FIGS. 3-10. At 201 in FIG. 2, conductive plated through holes 103 are formed through the core dielectric layer 102, as shown in FIG. 3. The second level formation begins at 202 in FIG. 2 with forming patterned trace layers on both sides of the core dielectric layer 102, including forming the first conductive trace features 106 of the first trace layer on the top side of the core dielectric layer 102 to a thickness 107 (e.g., 10-25 μm), and a third level patterned trace layer is simultaneously formed on the bottom side of the core dielectric layer 102. FIG. 3 shows an example where the electroplating process 300 is performed using a patterned plating mask (not shown). In another example, the second level L2 can be formed by a blanket deposition and etching process. At 203, a first laminate dielectric layer is formed on top of the patterned first trace layer (and a third dielectric layer is formed on the bottom side (not shown in FIG. 4)). 4 illustrates an example in which a deposition process 400 is performed to form a first dielectric layer 104 over the first conductive trace features 106 and the core dielectric layer 102. In one example, the process 400 is a compression molding operation to form a compression molded laminate dielectric layer 104 that extends between and around the different conductive trace features 106 of the second level L2 to form the top side of the second level L2.

[0030] The vias 108 of the second level L2 are formed at 204 and 205. At 204, a via opening or hole is formed through an upper portion of the dielectric layer 104, for example, using a laser drilling process 500 of FIG. 5 that forms a via opening 502 on the top side of the first dielectric layer 104 to expose a portion of a selected one of the first conductive trace features 106 of the first trace layer. At 205, a conductive via 108 is formed in the opening 502, for example, using a deposition process 600 shown in FIG. 6 that forms a seed layer (e.g., copper) 601 on the upper and lower dielectric layers and at the bottom and sidewalls of the via opening 502. The via processing can include a blanket deposition that fills the opening 502 and a planarization step (not shown). In another example, a masked electroplating operation is performed to form the conductive via 108, followed by mask removal and a compression molding process. In one example, a compression molding process forms molded dielectric features 104 on the exposed portions of the conductive trace features 106 of the first trace layer and the vias 108 of the second level L2 to an initial thickness covering the first trace layer and the first via layer, followed by a grinding process that grinds away the upper portions of the molded dielectric material 104 and exposes the upper portions of the vias 108. In another example, chemical etching is used. In a further example, a chemical mechanical polishing process is used.

[0031] 7-11, a first level L1 is formed at 206-211 of FIG. 2. At 206, a first plating mask is formed and patterned on the first laminate dielectric layer 104 and the seed layer 601. FIG. 7 shows an example where a process 700 is performed to form and pattern a first mask 702 on a second level L2. The first mask 702 exposes a first portion of the seed layer 601 on the second level L2 where a first portion 111 of a second conductive feature 110 is to be formed. At 207, a first portion 111 of a second conductive trace feature 110 is formed to a first thickness in an opening in the first plating mask 702. 8 illustrates an example in which an electroplating process 800 is performed to form a first portion 111 of a second conductive trace feature 110 (e.g., copper) to a first thickness (113) on an exposed first portion of the seed layer 601 of the second level L2 in an opening in a first plating mask 702. The first plating mask 702 is then removed at 208 in FIG.

[0032] At 209, a second plating mask is formed and patterned on the first laminate dielectric layer 104 of the second level L2 and on a portion of the first portion 111 of the second conductive trace feature 110, as well as on the bottom side (not shown). FIG. 9 shows an example where a process 900 is performed to form and pattern a second mask 902 on the second level L2 and a portion of the first portion 111 of the second conductive trace feature 110. The second mask 902 exposes a second portion of the first portion 111 of the second conductive trace feature 110 on which the second portion 112 is to be formed. At 210, the second portion 112 of the second conductive trace feature 110 is formed on the exposed second portion of the first portion 111 using the second mask 902. FIG. 10 illustrates an example where an electroplating process 1000 is performed using a second mask 902 to form a second portion 112 of the second conductive trace feature 110 on the exposed second portion of the first portion 111 of the second conductive trace feature 110. The second plating mask 902 is then removed and the remaining seed layer is etched at 211. In an example, a top side solder mask 116 and a bottom side solder mask 136 are formed at 212. FIG. 11 illustrates an example where a deposition process 1100 is performed to form a solder mask structure 116 with an opening 1102 on a portion of the top side 117 of the second portion 112 of the second conductive trace feature 110, the process 1100 simultaneously forming a bottom side solder mask 136 with an opening 1101. In an example, the deposition process 1100 is a printing process.

[0033] The method 200 continues at 213 of FIG. 2 with a die attach and solder or other electrical connection process to electrically couple the terminals 122 of the semiconductor die 120 to the top side of the second portion 112 of the second conductive trace feature 110. FIG. 12 illustrates an example in which a flip chip die attach and solder electrical connection process 1200 is performed in which solder 124 is used to electrically couple the conductive terminals 122 of the semiconductor die 120 to the top side of the second portion 112 of the respective second conductive trace feature 110. The illustrated example of electrical connection includes flip chip soldering in which solder is applied (e.g., dipped or otherwise deposited) to the bottom side of the conductive terminals 122 of the semiconductor die 120 and the semiconductor die 120 is placed with the respective terminals 122 on or above the respective landing areas on the top side of the second portion 112 of the second conductive trace feature 110. A thermal solder reflow process is performed which solders the die terminals 122 to the landing areas 101 .

[0034] The method 200 continues at 214 in FIG. 2 with package molding. FIG. 13 shows an example where a molding process 1300 is performed to encapsulate a portion of the multilevel package substrate 101 and the die 120 within a package structure 128. In one example, a bottom solder mask 136 is formed at 215, optionally after package molding. At 216 in FIG. 2, the method 200 also includes attaching a solder ball 146 to a bottom side of the fourth conductive trace feature 140. FIG. 14 shows an example where a ball attach process 1400 is performed to attach the solder ball 146 to a second side 147 of a conductive landing pad of the second portion 142 of the fourth conductive trace feature 140.

[0035] Next, at 217 in FIG. 2, a package separation process (not shown), such as sawing, laser cutting, etc., is performed. FIGS. 1-1D above show an exemplary completed electronic device 100. In another example, the solder mask formation at 212 or 215, as well as the ball attachment process at 216, may be omitted, and the exposed bottom side of the conductive landing pad second side 147 of the second portion 142 of the fourth conductive trace feature 140 may be soldered to a host PCB (not shown), for example, using solder paste, or the electronic device 100 may be placed in a socket of the host PCB, or connected by other suitable attachment techniques, for example, in a land grid array (LGA) application. In another implementation, instead of attaching solder balls, solder pads (not shown) may be attached to the conductive landing pad second side 147 on the multilevel package substrate 101 to facilitate later soldering to the host PCB or attachment to a socket (not shown) of the host PCB.

[0036] 15 illustrates another flip chip ball grid array packaged electronic device 1500 having a structure as described above with stepped substrate trace conductive trace features 110 and 140. The electronic device 1500 in this example includes a conductive lid 1501 with a bottom side attached to the top side of the die 120 with an adhesive thermal interface material 1502 (TIM) and legs attached to an outer portion of the top side of the multilevel package substrate 101 with an adhesive thermal interface material 1503. In one example, the packaged electronic device 1500 includes an underfill material 1506 that fills the space between the die 120 and the multilevel package substrate 101 around the conductive terminals 122.

[0037] 16 shows another flip chip ball grid array packaged electronic device 1600 having a structure as described above with stepped substrate trace conductive trace features 110 and 140. The electronic device 1600 in this example includes a flat conductive lid 1601 with a bottom side attached to the top side of the die 120 with an adhesive thermal interface material 1602 (TIM) and attached to an outer portion of the top side of the multilevel package substrate 101 with a spacer 1603. In one example, the packaged electronic device 1600 includes an underfill material 1606 that fills the space between the die 120 and the multilevel package substrate 101 around the conductive terminals 122.

[0038] The described example provides a solution to substrate trace cracking that can be tailored to areas of high stress regions (e.g., die shadow regions 151 and 152 on the top side and / or second region 153 on the bottom side), and stepped conductive trace features can be designed in specific or isolated areas where enhanced substrate trace integrity strength is beneficial. The example implementation provides robust substrate traces to accommodate device operation at high temperatures (e.g., 125° C.) and operation over a wide thermal range (e.g., −40° C. to 125° C.) due to stress direction dependent stress reduction (e.g., 25% stress reduction) compared to thinner trace features. The described example provides advantages over alternative solutions including implementation in packaged electronic device manufacturing using existing substrate processing equipment and processes. The described solution facilitates localized CTE matching improvement with the multilevel package substrate 101, for example, by replacing higher CTE ABF dielectric with lower CTE copper to reduce stress during temperature cycling of the packaged electronic device 100. Strategic placement of specific taller trace layers in high stress areas within the same level provides higher reliability margins by extending crack propagation due to increased Z-height and provides improved local CTE match to lower package stresses without the added cost of using new lower CTE substrate materials.

[0039] Modifications may be made to the described examples, and other implementations are possible, within the scope of the following claims.

Claims

1. 1. An electronic device comprising: a multi-level package substrate including a first level and a second level above the first level, the first level including a first trace layer having a first conductive trace feature, a first conductive via contacting the first conductive trace feature, and a first dielectric layer; and the second level including a second trace layer having a second conductive trace feature, the second conductive trace feature including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness; a die electrically coupled to the multi-level package substrate; Including, an electronic device, wherein a second portion of the second conductive trace feature is located within a selected area of ​​the second level, the selected area being along a periphery of the die;

2. 10. The electronic device of claim 1, The multi-level package substrate is a core dielectric layer having first and second opposing sides; a third level on a second side of the core dielectric layer, the third level including a third trace layer having a third conductive trace feature, a second conductive via contacting the third conductive trace feature, and a second dielectric layer; a fourth level above the third level, the fourth level including a fourth trace layer having fourth conductive trace features; a solder ball attached to the fourth conductive trace feature; and Further comprising: The electronic device, wherein the first level is on a first side of the core dielectric layer.

3. 3. The electronic device of claim 2, the fourth conductive trace feature includes a first portion having a third thickness and a second portion having a fourth thickness greater than the third thickness.

4. 4. The electronic device of claim 3, an electronic device, wherein the first thickness is 10 to 20 μm, the second thickness is 5 to 15 μm greater than the first thickness, the third thickness is 10 to 20 μm, and the fourth thickness is 5 to 15 μm greater than the third thickness.

5. 4. The electronic device of claim 3, The electronic device, wherein the selected areas of the second level include first areas of the second level adjacent lateral sides of the die.

6. 6. The electronic device of claim 5, The electronic device, wherein the first region of the second level is below the die.

7. 4. The electronic device of claim 3, the second level further includes a number of second conductive trace features, each of the number of second conductive trace features including a first portion having the first thickness and a second portion having the second thickness; the fourth level further includes a number of fourth conductive trace features, each of the number of fourth conductive trace features including a first portion having the third thickness and a second portion having the fourth thickness.

8. 10. The electronic device of claim 1, The electronic device, wherein the first thickness is 10 to 20 μm, and the second thickness is 5 to 15 μm greater than the first thickness.

9. 10. The electronic device of claim 1, the second level further includes a number of second conductive trace features, each of the number of second conductive trace features including a first portion having the first thickness and a second portion having the second thickness.

10. A multi-level package substrate, a first level including a first trace layer having a first conductive trace feature, a first conductive via contacting the first conductive trace feature, and a first dielectric layer; a second level above the first level, the second level including a second trace layer having a second conductive trace feature, the second conductive trace feature including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness; Including, A multilevel package substrate, wherein a second portion of the second conductive trace feature is located within a selected area of ​​the second level, the selected area along a periphery of a die attached to the multilevel package substrate.

11. 11. The multi-level package substrate of claim 10, a core dielectric layer having first and second opposing sides; a third level on a first side of the core dielectric layer, the third level including a third trace layer having a third conductive trace feature, a second conductive via contacting the third conductive trace feature, and a second dielectric layer; a fourth level above the third level, the fourth level including a fourth trace layer having fourth conductive trace features; a solder ball attached to the fourth conductive trace feature; and Further comprising: The multi-level package substrate, wherein the first level is on a first side of the core dielectric layer.

12. 12. The multi-level package substrate of claim 11, the fourth conductive trace feature includes a first portion having a third thickness and a second portion having a fourth thickness greater than the third thickness.

13. 13. The multi-level package substrate of claim 12, a multi-level package substrate, wherein the first thickness is 10 to 20 μm, the second thickness is 5 to 15 μm greater than the first thickness, the third thickness is 10 to 20 μm, and the fourth thickness is 5 to 15 μm greater than the third thickness.

14. 11. The multi-level package substrate of claim 10, The multi-level package substrate, wherein the selected areas on the second level include first areas on the second level adjacent lateral sides of the die.

15. The multi-level package substrate of claim 14, A multi-level package substrate, wherein the first region of the second level is below the die.

16. 11. The multi-level package substrate of claim 10, The multi-level package substrate, wherein the first thickness is 10 to 20 μm, and the second thickness is 5 to 15 μm greater than the first thickness.

17. 1. A method comprising: forming a first level on a side of the core dielectric layer, the first level including a first trace layer having a first conductive trace feature, a first conductive via contacting the first conductive trace feature, and a first dielectric layer; forming a second level on the first level, the second level including a second trace layer with a second conductive trace feature, the second conductive trace feature including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness; Including, The method, wherein a second portion of the second conductive trace feature is located within a selected area of ​​the second level, the selected area along a periphery of a die attached to the second level.

18. 18. The method of claim 17, forming a third level on a second side of the core dielectric layer, the third level including a third trace layer having a third conductive trace feature, a second conductive via contacting the third conductive trace feature, and a second dielectric layer; forming a fourth level on the third level, the fourth level including a fourth trace layer having a fourth conductive trace feature including a first portion having a third thickness and a second portion having a fourth thickness greater than the third thickness; The method further comprises:

19. 20. The method of claim 18, performing an electrical connection process to electrically couple conductive terminals of the die to the second level; attaching a solder ball to the fourth conductive trace feature; The method further comprises:

20. 18. The method of claim 17, The method, wherein forming the second level includes forming a first mask on the first level, forming a first portion of the second conductive trace feature, removing the first mask, forming a second mask on the first level, and forming a second portion of the second conductive trace feature.

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