Semiconductor package for edge-emitting laser diodes.

Abstract

A semiconductor package and a method for forming the same are provided herein. The semiconductor package has a cap, the cap includes a first window wafer with a first side and an opposite second side, a second window wafer, and a spacer wafer perforated with through holes, the through holes extending through the spacer wafer. The first and second sides of the first window wafer are parallel to each other, and at least one side includes an anti-reflective surface. The spacer wafer is disposed between the first window wafer and the second window wafer, and the first and second window wafers are bonded to the opposite sides of the spacer wafer. The window wafer and the spacer wafer together define a cavity in the cap. An edge-emitting laser diode is disposed on a submount and configured to direct a laser beam at normal incidence to the first side of the first window wafer. The cap is mounted on the submount, and the edge-emitting laser diode is encapsulated in the cavity.

Description

[Background technology]

[0001] (Related Applications) This application claims the benefit of U.S. Provisional Application No. 63 / 302,325, filed Jan. 24, 2022, which is incorporated by reference in its entirety.

[0002] A conventional semiconductor package for an edge-emitting laser diode (EELD) includes a cap consisting of a top and four sidewalls that create a cup shape. The top of the cap is a transparent window with two polished surfaces. The cap encloses a semiconductor chip, which either transmits or receives photons through the window top of the cap. Typical semiconductor chips encapsulated by a standard cap include photodiodes, IR detectors, LEDs, or VCSELs. A cross-section of a conventional EELD semiconductor package (e.g., a TO package) is shown in FIG. 1.

[0003] EELDs emit high-intensity photons from the cleaved sidewalls of a semiconductor chip. The conventional technique for mounting an EELD on a submount is to direct the laser beam 90° upwards towards a window mounted inside a protective metal cap. Summary of the Invention [Means for solving the problem]

[0004] According to an embodiment of the subject innovation, a semiconductor package is provided. The semiconductor package can include a cap. The cap can include a first window wafer having a first surface and an opposing second surface. The first surface and the second surface are parallel to each other, and the first surface and / or the second surface includes an anti-reflective surface. The cap can further include a second window wafer having a first surface and an opposing second surface, and a spacer wafer, the spacer wafer being perforated with a plurality of through holes, the plurality of through holes extending from the first surface of the spacer wafer to the opposing second surface of the spacer wafer. The spacer wafer is disposed between the first window wafer and the second window wafer, the first window wafer being bonded to the first surface of the spacer wafer, and the second window wafer being bonded to the second surface of the spacer wafer. The semiconductor package can further include an edge-emitting laser diode disposed on the submount and configured to direct a laser beam at normal incidence to the first surface of the first window wafer. The cap is mounted on the submount and the edge-emitting laser diode is encapsulated within the cavity.

[0005] According to another embodiment of the subject innovation, a semiconductor package is provided. The semiconductor package can include a cap. The cap can include a window wafer including a first side and an opposing second side. The first side and the second side are parallel to one another, and the first side and / or the second side include an anti-reflective surface. The cap can further include a cavity wafer including an array of cavities, the cavities extending from the first side of the cavity wafer to the opposing second side of the cavity wafer and including a bottom. The window wafer is bonded to the first side of the cavity wafer. The semiconductor package can further include an edge-emitting laser diode disposed on a submount and configured to direct a laser beam at normal incidence to the first side of the window wafer. The cap is mounted on the submount, and the edge-emitting laser diode is encapsulated within the cavity.

[0006] According to another embodiment of the subject innovation, a method of manufacturing a cap for use in an EELD semiconductor package is provided. The method may include bonding first and second window wafers to opposing sides of a spacer wafer to form a bonded wafer sandwich, the spacer wafer being disposed between the first window wafer and the second window wafer in the bonded wafer sandwich. The spacer wafer is perforated with a plurality of through holes, the plurality of through holes extending through the spacer wafer between the opposing sides of the spacer wafer, and a side of the first window wafer and / or the second window wafer includes an anti-reflective surface. The method may further include stacking a plurality of bonded wafer sandwiches on top of each other to form a block, adjacent bonded wafer sandwiches being secured together using an adhesive. The method may further include cutting through the block to form at least one plate and processing the plate by metallizing an edge portion of the plate. The method may further include cutting through the plate to form a bar, and then removing the adhesive from the bar to result in a cap.

[0007] According to another embodiment of the subject innovation, a method of manufacturing a cap for use in an EELD semiconductor package is provided. The method may include bonding a window wafer to a cavity wafer to form a bonded wafer sandwich, where the cavity wafer includes an array of cavities, the cavities extending from a first side of the cavity wafer to an opposing second side of the cavity wafer and including a bottom. The side of the window wafer includes an anti-reflective surface. The method may further include stacking a plurality of bonded wafer sandwiches on top of each other to form a block, where adjacent bonded wafer sandwiches are secured together using an adhesive. The method may further include cutting through the block to form at least one plate and processing the plate by metallizing an edge portion of the plate. The method may include cutting through the plate to form a bar and removing the adhesive from the bar to produce a cap. [Brief description of the drawings]

[0008] The following is a brief description of the drawings, which are presented for purposes of illustrating the exemplary embodiments disclosed herein and not for purposes of limiting same.

[0009] [Figure 1] FIG. 1 is a cross-sectional view of a conventional semiconductor package for an edge-emitting laser diode.

[0010] [Diagram 2] FIG. 2 is a cross-sectional view of an exemplary embodiment of a semiconductor package for EELD according to the present disclosure.

[0011] [Diagram 3] Figures 3A-3C are schematic diagrams of a set of components used to form the semiconductor package shown in Figure 2. Figure 3A is a schematic diagram of a window wafer shown in plan view (top) and side view (bottom). Figure 3B is a schematic diagram of a perforated spacer wafer shown in plan view (top) and side view (bottom). Figure 3C is a schematic diagram of a window wafer shown in plan view (top) and side view (bottom).

[0012] [Figure 4] 4A and 4B are schematic diagrams of a bonded wafer sandwich formed from the components shown in FIGS. 3A-3C.

[0013] [Diagram 5] FIG. 5 is a top view of the bonded wafer sandwich shown in FIGS. 4A-4B including cut lines for the singulation process.

[0014] [Figure 6] Figures 6A-6C are schematic diagrams of a cap used to form the semiconductor package shown in Figure 2. Figure 6A is a top view, Figure 6B is a front view, and Figure 6C is a bottom view.

[0015] [Figure 7] Figures 7A-7C are schematic diagrams of caps at various stages of processing: Figure 7A is a schematic diagram of a portion of a wafer showing an array of caps including cut lines, Figure 7B is a schematic diagram of the caps, and Figure 7C is a schematic diagram of the caps with a metallized edge.

[0016] [Figure 8] Figures 8A and 8B are schematic diagrams of the assembly of the EELD semiconductor package shown in Figure 2. In Figure 8A, the cap is not mounted on the submount. In Figure 8B, the cap is mounted on the submount for the EELD chip within the cavity of the semiconductor package.

[0017] [Figure 9] FIG. 9 is a cross-sectional view of another exemplary embodiment of a semiconductor package for EELD according to the present disclosure.

[0018] [Figure 10] Figures 10A and 10B are schematic diagrams of the set of components used to form the semiconductor package shown in Figure 9. Figure 10A is a schematic diagram of a window wafer shown in plan view (top) and side view (bottom). Figure 10B is a schematic diagram of a cavity wafer shown in plan view (top) and side view (bottom).

[0019] [Figure 11] 11A and 11B are schematic diagrams of bonded wafers formed from the components shown in FIGS. 10A and 10B.

[0020] [Figure 12] FIG. 12 is a top view of the bonded wafers shown in FIGS. 11A-11B including cut lines for the singulation process.

[0021] [Figure 13]Figures 13A-13C are schematic diagrams of a cap used to form the semiconductor package shown in Figure 9. Figure 13A is a top view, Figure 13B is a front view, and Figure 13C is a bottom view.

[0022] [Figure 14] 14A-14C are schematic diagrams of wafer bonding to form a bonded three-wafer sandwich.

[0023] [Figure 15] Figures 15A and 15B are schematic diagrams showing how bonded wafer sandwiches can be stacked and then cut vertically to produce plates. In Figure 15A, the bonded wafers of Figure 14 are stacked. A vertical cut path is shown for a block of bonded wafer sandwiches. In Figure 15B, a cut path is shown for a plate.

[0024] [Figure 16] FIG. 16 is a schematic diagram of a rod produced by cutting the plate shown in FIG. 15B.

[0025] [Figure 17] FIG. 17 shows the cap freed from the rod of FIG.

[0026] [Figure 18] FIG. 18 is a process flow diagram illustrating an exemplary implementation of a method for producing a cap from a stack of bonded wafers according to the present disclosure.

[0027] [Figure 19] FIG. 19 is a process flow diagram illustrating an example implementation of a method for producing a cap from a bonded wafer sandwich according to the present disclosure.

[0028] [Figure 20] FIG. 20 is a top view of the bonded wafer sandwich including cut lines to form strips.

[0029] [Figure 21] FIG. 21 is a schematic diagram of a strip mounted on a carrier shown in side view (top) and top view (bottom) according to the present disclosure.

[0030] [Figure 22] FIG. 22 is a plan view of the loaded strips including the cut lines for the singulation process.

[0031] [Diagram 23] FIG. 23 is a process flow diagram illustrating another exemplary implementation of a method for fabricating a cap by cutting a bonded wafer sandwich into strips to be processed. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] A more complete understanding of the processes and apparatus disclosed herein can be obtained by reference to the accompanying drawings, which are schematic representations based merely on the convenience and ease of demonstrating existing technology and / or the present developments, and as such are not intended to indicate the relative sizes and dimensions of the assemblies or components thereof.

[0033] Although specific terms are used in the following description for clarity, these terms are intended to refer only to the particular structures of the embodiments selected for illustration in the drawings, and are not intended to define or limit the scope of the present disclosure. In the drawings and the following description below, it should be understood that like numerical symbols refer to components of similar function.

[0034] The singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise.

[0035] As used in the specification and claims, the terms "comprise(s)," "include(s)," "having," "has," "can," "contain(s)," and variations thereof, as used herein, are intended to be open-ended transitional phrases, terms, or words that require the presence of the recited ingredients / steps and allow for the presence of other ingredients / steps as well. However, such descriptions should also be construed as describing compositions or processes that "consist of" and "consisting essentially of" the recited ingredients / steps, which allow for the presence of only the recited ingredients / steps, along with any unavoidable impurities that may result therefrom, and to the exclusion of other ingredients / steps.

[0036] Numerical values ​​in the specification and claims of this application should be understood to include numerical values ​​that are the same when reduced to the same number of significant figures and numerical values ​​that differ from the stated value by less than the experimental error of conventional measurement techniques of the type described herein to determine the value.

[0037] All ranges disclosed herein are inclusive of the recited endpoints and are independently combinable (e.g., the range "2 grams to 10 grams" includes the endpoints, i.e., 2 grams and 10 grams, and all intermediate values).

[0038] The modifier "about" used in connection with a quantity is inclusive of the stated value and has the meaning dictated by the context (e.g., includes at least the degree of error associated with measurement of the particular quantity). When used in conjunction with a specific value, it should also be considered to disclose that value. For example, the term "about 2" also discloses the value "2" and the range "about 2 to about 4" also discloses the range "2 to 4."

[0039] The edge-emitting laser diode (EELD) semiconductor package and cap fabrication method disclosed herein addresses an unmet need in the EELD industry for a lower cost, highly automatable surface mount package for EELD chips. In particular, the method provides a novel sequence of operations that results in a cap from a stack of bonded wafer stacks, which results in a lower cost surface mount package that can be assembled by a robot.

[0040] 2 is a cross-sectional view of an exemplary embodiment of a semiconductor package 100 for an edge-emitting laser diode (EELD) according to the present disclosure. The semiconductor package 100 can include a cap 102, a submount 112, and an edge-emitting laser diode (EELD) 110 disposed on the submount 112. The cap 102 is configured to be mounted on the submount 112 and to enclose the EELD 110 within a cavity 114 of the cap 102. When mounted on the cap 102, the submount 112 serves as a lid to cover or seal the cavity 114 in which the EELD 110 is disposed. The EELD 110 is configured to direct a laser beam LB through a sidewall of the cap 102, as described in more detail below.

[0041] 2-8, the cap 102 can be a three-layer structure comprising three wafers: a first window wafer 104, a second window wafer 108, and a spacer wafer 106. FIG. 3A illustrates the first window wafer 104 from a top view 302 and a side view 304. FIG. 3B illustrates the spacer wafer 106 from a top view 306 and a side view 308. FIG. 3C illustrates the second window wafer 108 from a top view 310 and a side view 312. The spacer wafer 106 can be sandwiched between the first window wafer 104 and the second window wafer 108 as shown in FIG. 4A. In some embodiments, the first window wafer 104 can comprise a first side 104a and an opposing second side 104b. The second window wafer 108 can comprise a first side 108a and an opposing second side 108b. The spacer wafer 106 can have a first surface 106a and an opposing second surface 106b. The spacer wafer 106 is a perforated wafer, with a plurality of through holes 116 extending from the first surface 106a of the spacer wafer 106 to the opposing second surface 106b of the spacer wafer 106. The plurality of through holes 116 is not limited to a specific shape and can include rectangular through holes, triangular through holes, and circular through holes. In FIG. 2-8, the spacer wafer 106 has a plurality of rectangular through holes 116 extending from the first surface 106a to the second surface 106b. In an example, the plurality of through holes 116 can be formed in the spacer wafer 106 through machining. By way of example, but not limitation, the through holes 116 can be formed in brittle materials (e.g., silicon, glass, sapphire, among others) by laser cutting, water jet cutting, photoetching, ultrasonic machining, and the like. It should be appreciated that the through-holes 116 may be formed in the spacer wafer 106 by techniques selected using sound engineering judgment without departing from the scope of the subject innovation.

[0042] The spacer wafer 106 can be disposed between the first window wafer 104 and the second window wafer 108, and the first and second window wafers 104, 108 are bonded to opposite sides 106a, 106b of the spacer wafer 106. For example, the first window wafer 104 can be bonded to the first side 106a, and the second window wafer 108 can be bonded to the second side 106b. In yet another example (not shown), the first window wafer 104 can be bonded to the second side 106b, and the second window wafer 108 can be bonded to the first side 106a. By way of example, and not limitation, each of the first and second window wafers 104, 108 can have a thickness of about 0.2 mm to 0.8 mm. In another example, the first and second window wafers 104, 108 can have a thickness of 0.5 mm. By way of example, and not limitation, the spacer wafer 106 can have a thickness of about 0.5 mm to 3.5 mm. In another example, the spacer wafer 106 can have a thickness of about 2 mm. It should be appreciated that each of the first window wafer 104, the spacer wafer 106, and the second window wafer 108 can have a circular shape with a diameter of about 150 mm to 200 mm. It should be appreciated that each of the first window wafer 104, the spacer wafer 106, and the second window wafer 108 can have a rectangular shape with a corresponding length and width. The thicknesses of the first window wafer 104, the second window wafer 108, and the spacer wafer 106 can be selected using sound engineering judgment without departing from the scope of the subject innovation.

[0043] The semiconductor package 100 is optimized for use with the EELD 110 based on the configuration of the first and / or second window wafers 104, 108 relative to the laser beam LB emitted by the EELD 110.

[0044] In a particular example, the EELD 110 can be configured to direct a laser beam LB perpendicular to the first side 104a and the second side 104b of the first window wafer 104. In these embodiments, the first window wafer 104 serves as a transmission window for photons emitted by the EELD 110 toward the first window wafer 104 at normal incidence. In such embodiments in which the first window wafer 104 serves as a transmission window, the first side 104a and the second side 104b can be parallel to each other. In an embodiment, at least one side 104a, 104b of the first window wafer 104 serving as a transmission window can include an anti-reflective (AR) surface. For example, the first window wafer 104 can be a double-sided polished (DSP) wafer. Depending on the wavelength of the EELD 110, the first window wafer 104 can comprise DSP fused silica, glass, sapphire, or silicon. An advantage of the present disclosure is that the laser beam LB from the EELD 110 can pass through the first window wafer 104 with minimal attenuation or distortion by employing a DSP window wafer having two parallel faces at normal incidence to the laser beam LB and further including an AR surface. The AR surface can be at least one of an AR coating, a filter coating, a textured surface, among others, but is not limited to this. In this example, the AR surface can be on at least one face 104a, 104b of the first window wafer 104.

[0045] In another example, the EELD 110 is configured to direct the laser beam LB perpendicular to the first and second faces 108a, 108b of the second window wafer 108. In these embodiments, the second window wafer 108 serves as a transmissive window for photons emitted by the EELD 110 toward the second window wafer 108 at normal incidence. In embodiments in which the second window wafer 108 serves as a transmissive window, the first and second faces 108a, 108b can be parallel to one another, and at least one of the faces 108a, 108b can include an AR surface. In some embodiments, the second window wafer 108 can be a double-sided polished (DSP) wafer. Depending on the wavelength of the EELD 110, the second window wafer 108 can comprise DSP fused silica, glass, sapphire, or silicon. An advantage of the present disclosure is that the laser beam LB from the EELD 110 can pass through the second window wafer 108 with minimal attenuation or distortion by employing a DSP window wafer having two parallel faces at normal incidence to the laser beam LB and further including an AR surface, which can be at least one of, but is not limited to, an AR coating, a filter coating, a textured surface, among others. In this example, the AR surface can be on at least one face 108a, 108b of the second window wafer 108.

[0046] It should be understood that at least one of the faces 104a, 104b, 108a, or 108b can include an AR surface. For example, a single face, such as the first face 104a, can include an AR surface. In another example, the first face 104a and the second face 104b can include an AR surface. In another example, the second face 104b can include an AR surface. In another example, the first face 108a can include an AR surface. In yet another example, the second face 108b can include an AR surface. In yet another example, the first face 108a and the second face 108b can include an AR surface. It should be understood that a window wafer that will serve as a transmission window for the EELD 110 can include at least one face with an AR surface. The laser beam LB from the EELD 110 can be transmitted through the window wafer sidewall with minimal attenuation or distortion by employing a DSP window wafer having two parallel faces at normal incidence to the laser beam LB and further including an AR surface on at least one face (e.g., but not limited to, including at least one of an AR coating, a filter coating, a textured surface, among others).

[0047] The semiconductor package 100 can be fabricated in less time while also reducing the amount of material and / or cost compared to conventional techniques for EELD semiconductor packages. For example, the semiconductor package 100 does not include a mirror, which in conventional EELD semiconductor packages is used to reflect the laser beam 90° upwards toward the top of the cap, which acts as a transmission window. Thus, conventional EELD semiconductor packages require very precise alignment of the EELD chip, mirror, and window, and achieving such precise alignment makes mass production very difficult. On the other hand, the present disclosure facilitates transmission of the laser beam LB through the window wafer sidewall of the cap without requiring a mirror to reflect the laser beam.

[0048] In some embodiments, it is contemplated that each of the first window wafer 104 and the second window wafer 108 are configured to act as a transmissive window for photons emitted by the EELD 110. In these embodiments, both the first and second window wafers 104, 108 can be DSP wafers, and each of the first and second window wafers 104, 108 can include an AR surface on one or both of the faces 104a, 104b and 108a, 108b, respectively.

[0049] For brevity, the following discussion in paragraphs 0049-0053 refers to an embodiment in which the first window wafer 104 is a transmissive window, the first and second faces 104a, 104b are arranged at normal incidence to the laser beam LB, and at least one of the first and second faces 104a, 104b includes an AR surface. However, the principles of the following discussion apply equally to an embodiment in which the second window wafer 108 is a transmissive window, the first and second faces 108a, 108b are arranged at normal incidence to the laser beam LB, and at least one of the first and second faces 108a, 108b includes an AR surface.

[0050] By way of example, but not limitation, the first side 104a of the first window wafer 104 can include an AR surface. In such an example, since the first side 104a is disposed proximal to the EELD 110, while the second side 104b is disposed distal to the EELD 110, it may be preferable for the first side 104a to include an AR surface. Thus, the laser beam LB is at normal incidence to the first side 104a. In another example, each of the first and second sides 104a, 104b of the first window wafer 104 can include an AR surface. In yet another example, the second side 104b of the first window wafer 104 can include an AR surface.

[0051] In another example, one or more AR surfaces can comprise an AR coating and / or a filter coating. In one non-limiting example, the AR coating can be applied (e.g., deposited on) the first side 104a of the first window wafer 104. In some embodiments, the first window wafer 104 is a DSP wafer that includes an AR surface (e.g., an AR coating on at least one of the first side 104a, the second side 104b, or a combination thereof). In another non-limiting example, a filter coating can be applied (e.g., deposited on) at least one of the sides 104a, 104b, or a combination thereof in a rectangular 2-D array to improve the quality of the laser beam LB emitted by the EELD 110. In yet another non-limiting example, the AR surface can comprise a high laser-induced damage threshold (LIDT) coating. A high LIDT such as that of a high LIDT coating can be greater than 1 J / cm for a pulsed laser at any given wavelength or over a range of wavelengths. 2 By way of example, a high LIDT may comprise an LIDT of at least 10 J / cm for a near infrared laser beam. 2 For higher power laser beams emitted at short distances from the first window wafer 104, it is beneficial for the first window wafer 104 to include a high LIDT coating. A high LIDT coating can be produced by mitigating defects in the coating.

[0052] In another example, one or more of the AR surfaces can include a textured surface configured to create an anti-reflective topography. In these embodiments, at least one of the first surface 104a, the second surface 104b, or a combination thereof, includes a textured surface for anti-reflective purposes. The textured surface can provide a high LIDT, which can be greater than 1 J / cm for a pulsed laser at any given wavelength or over a range of wavelengths. 2In some embodiments, the textured surface can comprise a textured area that can be formed of a matrix of discrete rectangular areas. In one non-limiting example, the textured surface comprises a "moth-eye" topography. Texturing can be accomplished by a wet or dry etching process performed through a lithographically defined mask.

[0053] In yet another example, one side 104a, 104b of the first window wafer 104 can have a textured surface for anti-reflection, while the opposite side 104a, 104b can be textured to form a lens (e.g., a Fresnel lens or a modern metalens). In some embodiments, the monochromatic nature of the laser beam LB emitted by the EELD 110 can improve compatibility with metalens. Alternatively, in other embodiments, the second side 104b, which is disposed distal to the EELD 110 and forms part of the exterior (e.g., the exterior surface), can be bonded with an array of lenses or microlenses. In these embodiments, reflection losses can be minimized if the added lenses have the same refractive index as the material that makes up the first window wafer 104.

[0054] In one example, the imprinted lenses can be applied to the first or second window wafers 104, 108 prior to wafer bonding, as long as the imprinted lenses can withstand the temperatures and pressures of wafer bonding. Alternatively, the imprinted microlenses can be applied to the first or second window wafers 104, 108 after wafer bonding and prior to the singulation process.

[0055] In some embodiments, the spacer wafer 106 is configured to have a substantially similar (e.g., matching) coefficient of thermal expansion (CTE) as the first and second window wafers 104, 108. A technique for achieving a substantially similar CTE (hereafter referred to as CTE matching) is by using the same material within the wafers 104, 106, and 108 (e.g., composition matching). As an example, the spacer wafer 106 can be made of the same material as the first and second window wafers 104, 108 to achieve a CTE match. In another embodiment, a CTE match can be achieved using an alternative material for the spacer wafer 106. In one non-limiting example, the cap 102 can comprise an Invar spacer wafer 106 and the first and second window wafers 104, 108 can comprise silicon or Borofloat 33 glass. In another non-limiting example, the cap 102 can comprise a silicon spacer wafer 106 and the first and second window wafers 104, 108 can comprise Borofloat 33 glass. In yet another non-limiting example, the cap 102 can comprise a Kovar spacer wafer 106 and the first and second window wafers 104, 108 can comprise sapphire. It should be appreciated that the spacer wafer 106 can be Invar, silicon, Kovar, fused silica, glass, sapphire, among others. It should further be appreciated that the first and second window wafers 104, 108 can be, but are not limited to, silicon, fused silica, glass, sapphire, Borofloat 33 glass, among others.

[0056] The spacer wafer 106 is disposed between the first window wafer 104 and the second window wafer 108, as shown in FIG. 4A, and the first and second window wafers 104, 108 are bonded to opposite sides 106a, 106b of the spacer wafer 106. As a non-limiting example, the first side 104a of the first window wafer 104 can be bonded to the first side 106a of the spacer wafer 106, and the first side 108a of the second window wafer 108 can be bonded to the second side 106b of the spacer wafer 106. It should be understood that various types of bonding can be utilized to bond the first and second window wafers 104, 108 to the opposite sides 106a, 106b of the spacer wafer 106. The type of bond for bonding the spacer wafer 106 to the first window wafer 104 and the second window wafer 108 may be selected using sound engineering judgment without departing from the scope of the subject innovation.

[0057] For example, hermetic bonding can be used to bond the first window wafer 104 to the first side 106a of the spacer wafer 106 and the second window wafer 108 to the second side 106b of the spacer wafer 106. Hermetic bonding can be accomplished in a vacuum wafer bonder using methods such as, but not limited to, solder bonding, direct bonding, anodic bonding, and the like. In a non-limiting example, solder bonding can be achieved by coating one side of the wafers (e.g., the first and second window wafers 104, 108) with solder (e.g., AuSn, CuSn, AuGe, AuSi, among others) and metallizing the matching area on the opposite wafer (e.g., the spacer wafer 106) with a solderable metal. In another non-limiting example, anodic bonding can be achieved by directly bonding an alkali-containing glass wafer (e.g., the first and second window wafers 104, 108) to a Si or other glass wafer (e.g., the spacer wafer 106). In another non-limiting example, a thin film of borosilicate glass can be deposited on a glass or metal wafer to allow for anodic bonding. In yet another non-limiting example, direct bonding, also known as fusion bonding, can be performed at a temperature of about 400° C. to bond the first and second window wafers 104, 108 to the opposing faces 106a, 106b of the spacer wafer 106. Direct bonding is sensitive to the surface roughness of the wafer because it relies on weak physical forces (e.g., the formation of covalent bonds between a Si substrate and a silicon dioxide (SiO2) substrate) that disappear over a distance of only a few nanometers (nm). Thus, the wafer surface needs to be very smooth for fusion bonding. For example, the wafer can have a surface roughness value (Ra) below 0.3 nm to 0.5 nm.

[0058] In other embodiments, wafer bonding is incorporated to bond the first window wafer 104 to the first side 106a of the spacer wafer 106 and the second window wafer 108 to the second side 106b of the spacer wafer 106. It should be understood that wafer bonding can be performed in a single step (e.g., bonding the spacer wafer 106 to the first window wafer 104 and to the second window wafer 108) or in two successive steps (e.g., bonding the spacer wafer 106 to the first window wafer 104 and then to the second window wafer 108, or vice versa).

[0059] In some embodiments, wafer bonding can be performed at room temperature using a laser. It should be appreciated that bonding the window wafer to the spacer wafer via laser bonding provides many advantages. First, laser bonding can be performed at low temperatures, such as room temperature, which advantageously mitigates heat-related damage to any previously formed optical coatings and other active layers. Thus, the first and second window wafers 104, 108 and / or the spacer wafer 106 can be coated prior to laser treatment. Additionally, laser bonding provides minimal heat load since the heat affected zone (i.e., the laser treatment zone) is very small, e.g., only a few micrometers. Beneficially, the low heat allows for the use of less bulk / material, and therefore thinner materials. Second, laser bonding provides a direct bond between the spacer wafer and the window wafer without requiring additive materials such as adhesives and without leaving gaps between the window wafer (e.g., the first window wafer 104 or the second window wafer 108) and the spacer wafer (e.g., the spacer wafer 106). It should be understood that the lack of adhesive means no outgassing, and direct laser bonding does not require metal or metal-seed layers to bond. In a non-limiting example, direct laser bonding for wafer-level chip-scale packaging can enable glass / glass seals.

[0060] It should be appreciated that laser bonding is a wafer-level process that allows for highly efficient and scalable device manufacturing. It should be appreciated that laser bonding helps optimize the coefficient of thermal expansion (CTE), and the CTE match between the wafer materials allows for a strong hermetic seal between the materials. In some non-limiting examples, laser bonding can be used to bond a glass spacer wafer to a glass window wafer, or a glass spacer wafer to a Si window wafer. It is contemplated that an infrared (IR) laser can be used as the laser source to bond a Si spacer wafer to a Si window wafer.

[0061] In some embodiments, the wafers 104, 106, 108 can be bonded together without forming a hermetic bond. In these embodiments, an organic adhesive can be used to bond the spacer wafer 106 to the first and second window wafers 104, 108. Preferably, the adhesive has minimal outgassing during B-staging and curing (e.g., low outgassing adhesives as defined by NASA and ASTM E595), but it is not required. It should be appreciated that cost reduction can be achieved by not using a hermetic bond to bond the wafers 104, 106, 108, since glue bonding can be performed in air on a hot plate, while anodic bonding and solder bonding typically require sophisticated wafer bonders that are performed under vacuum (e.g., a costly process).

[0062] 4A-4B and 5, an example of a bonded wafer sandwich 122 (e.g., a stack of bonded wafers) is illustrated that includes three wafers: a first window wafer 104, a spacer wafer 106, and a second window wafer 108. In this embodiment, the spacer wafer 106 is disposed between (e.g., or sandwiched between) the first window wafer 104 and the second window wafer 108, and the first and second window wafers 104, 108 are bonded to opposing sides 106a, 106b of the spacer wafer 106. The bonded wafer sandwich 122 can be oriented for dicing or sawing the bonded wafer sandwich 122 into individual pieces to produce the caps 102, in a process referred to as singulation.

[0063] Prior to dicing / sawing, the bonded wafer sandwich 122 is positioned with the processed window wafer as the top surface. The processed window wafer is a DSP window wafer configured to serve as a transmission window. In the embodiment shown in FIG. 5, the first window wafer 104 is the top surface. The bonded wafer sandwich 122 can then be diced along cut lines 118 and 120 to yield, by singulation, the caps 102. It should be understood that the bonded wafer sandwich 122 can be diced along cut lines 118 and 120 simultaneously or one at a time (e.g., sequentially).

[0064] FIG. 5 depicts cut lines 118 and 120, which extend through the bonded wafer sandwich 122. The cut line 118 can be positioned such that a downward cut along the cut line 118 extends through (e.g., intersects) the through holes 116, such that a downward cut along the cut line 118 cuts through the through holes 116 in the bonded wafer sandwich 122 and forms the cavity 114. In some examples, the through holes 116 can be cut into sections of substantially equal size, which can provide a substantially uniform cavity 114. The cut line 120 can be positioned orthogonal to the cut line 118. The cut line 120 can be positioned such that a downward cut along the cut line 120 extends between a plurality of the through holes 116, without intersecting the through holes 116, such that a downward cut along the cut line 120 cuts through three layers of wafer material. For example, dicing along cut line 120 cuts through the spacer wafer wall that defines through hole 116 without the path of cut line 120 intersecting through through hole 116 .

[0065] Dicing along cut lines 118 and 120 results in the cap 102 shown in FIGS. 6A-6C. In some implementations, cut line 118 extends through rectangular through hole 116 such that dicing along cut line 118 separates the larger rectangular through hole 116 into two smaller rectangular openings that are substantially equal in size. In some implementations, bonded wafer sandwich 122 can be diced along cut lines 118, 120 using a diamond saw, a water jet, an ultrasonic jet, or other suitable method. In some embodiments, bonded wafer sandwich 122 can be either brazed or on blue tape adhesive to hold bonded wafer sandwich 122 during dicing.

[0066] 6A-6C and 7, there is an exemplary embodiment of a three-wafer cap 102 formed by singulation. In this embodiment, the cap 102 comprises four sidewalls and a lid or top. In particular, the first window wafer 104 forms one sidewall of the cap 102, the second window wafer 108 forms the second sidewall of the cap 102, and the spacer wafer 106 forms two sidewalls and the top of the cap 102. The first window wafer 104, the spacer wafer 106, and the second window wafer 108 together define an uncovered cavity 114 (e.g., an open cavity) within the cap 102. In some embodiments, singulation results in caps 102 in which two of the four sidewalls of each cap 102 comprise the DSP window wafer.

[0067] 7A-7C, there is an example of a cap 102 formed from dicing the bonded wafer sandwich 122 shown in FIG. 5. The cap 102 may have an edge 124 resulting from singulation. In some embodiments, the surface of the edge 124 may be ground and / or polished to improve flatness and reduce surface roughness. In some embodiments, the inner width of the cavity 114 of the cap 102 after singulation has the same dimension as the thickness of the starting spacer wafer 106. In some examples, the thickness of the starting spacer wafer 106 is between 0.5 mm and 3.5 mm, and the inner width of the cavity 114 of the cap 102 after singulation matches the thickness of the starting spacer wafer 106, between 0.5 mm and 3.5 mm. In one particular example, the thickness of the spacer wafer 106 is 2 mm, and after singulation, this thickness dimension of 2 mm becomes the inner width of the cavity 114 of the cap 102.

[0068] In some embodiments, the edge 124 can be metallized, such as by forming a metal surface 126 on the edge 124, to facilitate bonding of the edge 124 to a metal surface (e.g., 128, FIGS. 8A-8B) on the submount (e.g., 112, FIGS. 8A-8B). In some embodiments, the composition of the metal surface 126 can be selected to be compatible with (e.g., match) a metal surface (e.g., 128, FIGS. 8A-8B) on the submount (e.g., 112, FIGS. 8A-8B). In certain embodiments, metallizing the edge 124 can be performed by use of a paint or ink designed to form a hermetic solderable metal surface on the edge 124. Because the edge 124 of each cap 102 is not defined until after singulation, the metallization of the edge 124 can be performed in a manner compatible with mass production of the caps 102. In some implementations, these paints or inks may require drying and baking steps to maximize the bond strength between the metal in the paint / ink and the material of the lip 124 (e.g., glass, sapphire, silicon, among others). The paints and inks are typically filled with metal particles or flakes such as Ni or Ag. The paints or inks can be applied to these caps 102 in large quantities using automated machines for pad printing or dip coating.

[0069] In some embodiments, the lip 124 of the cap 102 can be coated with a thin film metallization stack by a physical vapor deposition (PVD) process (e.g., sputtering or evaporation), where the ceiling of the cap 102 can be masked with a metal or photoresist. In these embodiments, the thin film metallization stack can comprise Gelot metallization from Materion Balzers Optics. It should be appreciated that such thin film metallization can improve compatibility with solder.

[0070] 8A and 8B, there is a schematic diagram of a cap 102 encasing an EELD 110 on a submount 112. In this embodiment, the cap 102 includes a metal surface 126 on a bottom edge 124 of the cap 102. When the cap 102 is mounted on the submount 112, the metal surface 126 engages a complementary metal surface 128 on the submount 112. In some embodiments, the submount 112 is made from ceramic. In such an embodiment, the EELD 110 is bonded to the ceramic submount 112 with a via (not shown) to the backside. In an embodiment, a DSP metal spacer can be inserted between the EELD 110 and the submount 112 to provide a vertical distance for the laser beam LB to spread out from the edge of the EELD chip before reaching a sidewall (e.g., the first surface 104a of the first window wafer 104 in FIG. 2). It should be appreciated that the semiconductor package 100 provided herein has a smaller footprint and volume and is compatible with fully automated (robotic) assembly. In addition, the semiconductor package 100 provided herein allows the cap 102 to be mounted on a co-fired AlN submount 112, which provides better thermal performance than conventional semiconductor packages.

[0071] 9, there is a cross-sectional view of another exemplary embodiment of a semiconductor package 200 for an edge-emitting laser diode (EELD) according to the present disclosure. The semiconductor package 200 can include a cap 202, a submount 212, and an EELD 210 disposed on the submount 212. The cap 202 is configured to be mounted on the submount 212 and to enclose the EELD 210 within a cavity 214 of the cap 202. When mounted on the cap 202, the submount 212 acts as a lid that covers or seals the cavity 214, and the EELD 210 is disposed within the cavity 214. The EELD 210 is configured to direct a laser beam LB through a sidewall of the cap 202, as described in more detail below.

[0072] 9-13C, the cap 202 can be a two-layer structure comprising two wafers: a window wafer 204 and a cavity wafer 206. FIG. 10A illustrates the window wafer 204 from a top view 402 and a side view 404. FIG. 10B illustrates the cavity wafer 206 from a top view 406 and a side view 408. In some embodiments, the window wafer 204 can comprise a first side 204a and an opposing second side 204b. The cavity wafer 206 can include an array of cavities 216 extending from the first side 206a of the cavity wafer 206 to the opposing second side 206b of the cavity wafer. The array of cavities 216 includes a bottom such that the cavities do not extend completely through the cavity wafer 206. The array of cavities 216 is not limited to a specific shape and can include rectangular cavities, triangular cavities, and circular cavities. 9-13C, the cavity wafer 206 has an array of rectangular cavities 216 that extend from a first side 206a of the cavity wafer 206 toward a second side 206b of the cavity wafer 206 and include a bottom.

[0073] In one example, the array of cavities 216 can be formed in the cavity wafer 206 through machining. By way of example, and not limitation, the array of cavities 216 can be formed by chemical etching, dry etching (e.g., deep reactive ion etching), ultrasonic machining, computer numerical control (CNC) machining, and the like. In some non-limiting examples, the cavities can be molded directly into a monolithic glass cavity wafer. In some non-limiting examples, the array of cavities 216 can be formed in a glass or Si cavity wafer by ultrasonic machining or wet etching. In other non-limiting examples, the array of cavities 216 can be formed in an Invar or Kovar cavity wafer by machining with an end mill or by wet etching. The surface flatness and surface roughness at the bottom of the cavities 216 is not important since the bottom of the cavities will be the ceiling in the cap 202. It should be appreciated that the array of cavities 216 may be formed in cavity wafer 206 by techniques selected using sound engineering judgment without departing from the scope of the subject innovation.

[0074] The cavity wafer 206 can be bonded to the first side 204a of the window wafer 204. In another example, the cavity wafer 206 can be bonded to the second side 204b of the window wafer 204. By way of example, and not by way of limitation, the window wafer 204 can have a thickness of about 0.2 mm to 0.8 mm. In another example, the window wafer 204 can have a thickness of 0.5 mm. By way of example, and not by way of limitation, the cavity wafer 206 can have a thickness of about 0.5 mm to 3.5 mm. In another example, the cavity wafer 206 can have a thickness of about 2 mm. It should be understood that each of the window wafer 204 and the cavity wafer 206 can have a circular shape with a diameter of about 150 mm to 200 mm. It should be understood that each of the window wafer 204 and the cavity wafer 206 can have a rectangular shape with a corresponding length and width. The thicknesses of the window wafer 204 and the cavity wafer 206 may be selected using sound engineering judgment without departing from the scope of the subject innovation.

[0075] The semiconductor package 200 is optimized for use with the EELD 210 based on the configuration of the window wafer 204 relative to the laser beam LB emitted by the EELD 210 .

[0076] In a particular example, the EELD 210 can be configured to direct a laser beam LB perpendicular to the first side 204a and the second side 204b of the window wafer 204. In these embodiments, the window wafer 204 serves as a transmission window for photons emitted by the EELD 210 toward the window wafer 204 at normal incidence. In such embodiments in which the window wafer 204 serves as a transmission window, the first side 204a and the second side 204b can be parallel to each other. In some embodiments, at least one side 204a, 204b of the window wafer 204 serving as a transmission window can include an AR surface. In some embodiments, the window wafer 204 can be a double-sided polished (DSP) wafer. Depending on the wavelength of the EELD 210, the window wafer 204 can comprise DSP fused silica, glass, sapphire, or silicon. An advantage of the present disclosure is that the laser beam LB from the EELD 210 can pass through the window wafer 204 with minimal attenuation or distortion by employing a DSP window wafer having two parallel faces at normal incidence to the laser beam LB and further including an AR surface. The AR surface can be at least one of, but not limited to, an AR coating, a filter coating, a textured surface, among others. In this example, the AR surface can be on at least one face 204a, 204b of the window wafer 204.

[0077] It should be understood that at least one of the faces 204a, 204b can include an AR surface. For example, a single face, such as the first face 204a, can include an AR surface. In another example, the first face 204a and the second face 204b can include an AR surface. In yet another example, the second face 204b can include an AR surface.

[0078] It should be appreciated that the window wafer 204, which serves as a transmission window for the EELD 210, can include at least one surface with an AR surface. The laser beam LB from the EELD 210 can be transmitted through the window wafer sidewall with minimal attenuation or distortion by employing a DSP window wafer having two parallel faces at normal incidence to the laser beam LB and further including an AR surface on at least one face (e.g., including, but not limited to, at least one of an AR coating, a filter coating, a textured surface, among others).

[0079] The semiconductor package 200 can be fabricated in less time while also reducing the amount of material and / or cost compared to conventional techniques for EELD semiconductor packages. For example, the semiconductor package 200 does not include a mirror, which in conventional EELD semiconductor packages is used to reflect the laser beam 90° upwards toward the top of the cap, which acts as a transmission window, and thus conventional EELD semiconductor packages require very precise alignment of the EELD chip, mirror, and window, and achieving such precise alignment makes mass production very difficult. On the other hand, the present disclosure facilitates transmission of the laser beam LB through the window wafer sidewall of the cap without requiring a mirror to reflect the laser beam.

[0080] In the following embodiments, the window wafer 204 is a transmissive window, the first and second faces 204a, 204b are positioned at normal incidence to the laser beam LB, and at least one of the first and second faces 204a, 204b includes an AR surface.

[0081] By way of example, but not limitation, the first side 204a, 204b of the window wafer 204 can include an AR surface. In such an example, it may be preferred that the first side 204a includes an AR surface since the first side 204a is disposed proximal to the EELD 210 while the second side 204b is disposed distal to the EELD 110. Thus, the laser beam LB is at normal incidence to the first side 204a. In other examples, both sides 204a, 204b of the window wafer 204 can include an AR surface.

[0082] In another example, one or more AR surfaces can comprise an AR coating and / or a filter coating. In one non-limiting example, the AR coating can be applied (e.g., deposited on) the first side 204a of the window wafer 204. In some embodiments, the window wafer 204 is a DSP wafer that includes an AR surface, e.g., an AR coating, on at least one of the first side 204a, the second side 204b, or a combination thereof. In another non-limiting example, a filter coating can be applied (e.g., deposited on) at least one of the sides 204a, 204b, or a combination thereof in a rectangular 2-D array to improve the quality of the laser beam LB emitted by the EELD 210. In yet another non-limiting example, the AR surface can comprise a high LIDT coating. A high LIDT such as that of a high LIDT coating can be applied to ... 2 By way of example, a high LIDT may comprise an LIDT of at least 10 J / cm for a near infrared laser beam. 2 For higher power laser beams emitted at short distances from the window wafer 204, it is beneficial for the window wafer 204 to include a high laser induced damage threshold (LIDT). High LIDT coatings can be produced by mitigating defects in the coating.

[0083] In another example, one or more of the AR surfaces can comprise a textured surface configured to create an anti-reflective topography. In these embodiments, at least one of the first surface 204a, the second surface 204b, or a combination thereof, includes a textured surface for anti-reflective purposes. The textured surface can provide a high LIDT, which can be greater than 1 J / cm for a pulsed laser at any given wavelength or over a range of wavelengths. 2 In some embodiments, the textured surface can comprise a textured area that can be formed of a matrix of discrete rectangular areas. In one non-limiting example, the textured surface comprises a "moth-eye" topography. Texturing can be accomplished by a wet or dry etching process performed through a lithographically defined mask.

[0084] In yet another example, one side 204a, 204b of the window wafer 204 can have a textured surface for anti-reflection, while the opposite side 204a, 204b can be textured to form a lens (e.g., a Fresnel lens or a modern metalens). In some embodiments, the monochromatic nature of the laser beam LB emitted by the EELD 210 can improve compatibility with metalens. Alternatively, in other embodiments, the second side 204b, which is disposed distally from the EELD 210 and forms part of the exterior (e.g., the exterior surface), can be bonded with an array of lenses or microlenses. In these embodiments, reflection losses can be minimized if the added lenses have the same refractive index as the material that makes up the first window wafer 204.

[0085] In one example, the imprinted lenses can be applied to the window wafer 204 prior to wafer bonding, as long as the imprinted lenses can withstand the temperatures and pressures of wafer bonding. Alternatively, the imprinted microlenses can be applied to the window wafer 204 after wafer bonding and prior to the singulation process.

[0086] In some embodiments, the cavity wafer 206 is configured to have a substantially similar (e.g., matching) coefficient of thermal expansion (CTE) as the window wafer 204. A technique for achieving a substantially similar CTE (hereafter referred to as CTE matching) is by using the same material within the wafers 204, 206 (e.g., composition matching). As an example, the cavity wafer 206 can be made of the same material as the window wafer 204 to achieve a CTE match. In another embodiment, a CTE match can be achieved using an alternative material for the cavity wafer 206. In one non-limiting example, the cap 202 can comprise an Invar cavity wafer 206 and the window wafer 204 can comprise silicon or Borofloat 33 glass. In another non-limiting example, the cap 202 can comprise a silicon cavity wafer 206 and the window wafer 204 can comprise Borofloat 33 glass. In yet another non-limiting example, the cap 202 can comprise a Kovar cavity wafer 206 and the window wafer 204 can comprise sapphire. It is to be understood that the cavity wafer 206 can be Invar, silicon, Kovar, fused silica, glass, sapphire, among others. Additionally, it is to be understood that the window wafer 204 can be, but is not limited to, silicon, fused silica, glass, sapphire, Borofloat 33 glass, among others.

[0087] 11A and 11B show bonding of the window wafer 204 to the cavity wafer 206. It should be understood that various types of bonds can be utilized to bond the window wafer 204 to the first side 206a of the cavity wafer 206. The type of bond for bonding the cavity wafer 206 to the window wafer 204 can be selected using sound engineering judgment without departing from the scope of the subject innovation.

[0088] For example, hermetic bonding can be used to bond the window wafer 204 to the first side 206a of the spacer wafer 206. Hermetic bonding can be accomplished in a vacuum wafer bonder using methods such as, but not limited to, solder bonding, direct bonding, anodic bonding, etc. In a non-limiting example, solder bonding can be achieved by coating one side of a wafer (e.g., the window wafer 204) with solder (e.g., AuSn, CuSn, AuGe, AuSi, among others) and metallizing the matching area on the opposite wafer (e.g., the cavity wafer 206) with a solderable metal. In another non-limiting example, anodic bonding can be achieved by directly bonding an alkali-containing glass wafer (e.g., the window wafer 204) to a Si or other glass wafer (e.g., the cavity wafer 206). In another non-limiting example, a thin film of borosilicate glass can be deposited on the glass or metal wafer to enable anodic bonding. In yet another non-limiting example, direct bonding, also known as fusion bonding, can be performed at a temperature of about 400° C. to bond the window wafer 204 to the first side 206a of the cavity wafer 206. Direct bonding is sensitive to the surface roughness of the wafer because it relies on weak physical forces (e.g., the formation of a covalent bond between a Si substrate and a silicon dioxide (SiO2) substrate) that disappear over a distance of only a few nanometers (nm). Thus, the wafer surface needs to be very smooth for fusion bonding. For example, the wafer may have a surface roughness value (Ra) below 0.3 nm to 0.5 nm.

[0089] In other embodiments, wafer bonding is incorporated to bond the window wafer 204 to the first side 206a of the cavity wafer 206. In some embodiments, the wafer bonding can be performed at room temperature using a laser. It should be appreciated that bonding the window wafer to the spacer wafer via laser bonding provides many advantages. First, the laser bonding can be performed at low temperatures, such as room temperature, which advantageously mitigates heat-related damage to any previously formed optical coatings and other active layers. Thus, the window wafer 204 and / or the cavity wafer 206 can be coated prior to the laser treatment. Furthermore, laser bonding provides minimal heat load since the heat affected zone (i.e., the laser treatment zone) is very small, e.g., only a few micrometers. Beneficially, the low heat allows for the use of less bulk / material, and therefore thinner materials. Second, laser bonding provides a direct bond between the window wafer (e.g., window wafer 204) and the cavity wafer (e.g., cavity wafer 206) without requiring additive materials such as adhesives and without leaving gaps between the window wafer (e.g., window wafer 204) and the cavity wafer (e.g., cavity wafer 206). The lack of adhesives means no outgassing, and it should be understood that direct laser bonding does not require metal or metal-seed layers to bond. In a non-limiting example, direct laser bonding for wafer-level chip-scale packaging can enable glass / glass seals.

[0090] It should be appreciated that laser bonding is a wafer-level process that allows for highly efficient and scalable device manufacturing. It should be appreciated that laser bonding helps optimize the coefficient of thermal expansion (CTE), and the CTE match between the wafer materials allows for a strong hermetic seal between the materials. In some non-limiting examples, laser bonding can be used to bond a glass cavity wafer to a glass window wafer, or a glass cavity wafer to a Si window wafer. It is contemplated that an infrared (IR) laser can be used as the laser source to bond a Si cavity wafer to a Si window wafer.

[0091] In some embodiments, the wafers 204, 206 can be bonded together without forming a hermetic bond. In these embodiments, an organic adhesive can be used to bond the cavity wafer 206 to the window wafer 204. Preferably, the adhesive has minimal outgassing (e.g., low outgassing adhesives as defined by NASA and ASTM E595) during B-staging and curing, but it is not required. It should be understood that cost reduction can be provided by not using a hermetic bond to bond the wafers 204, 206, since glue bonding can be performed in air on a hot plate, while anodic bonding and solder bonding typically require sophisticated wafer bonders that are performed under vacuum (e.g., costly processes).

[0092] 11A-11B and 12, an example of a bonded wafer 222 (e.g., a stack of bonded wafers) is illustrated that includes two wafers: a window wafer 204 bonded to a first side 206a of a cavity wafer 206. The bonded wafer 222 can be prepared for dicing or sawing the bonded wafer 222 into individual pieces to produce the caps 202, in a process referred to as singulation.

[0093] Prior to dicing / sawing, the bonded wafers 222 are positioned with the DSP window wafer 204 as the top surface. The bonded wafers 222 can then be diced along cut lines 218 and 220 to yield, by singulation, the caps 202. It should be understood that the bonded wafers 222 can be diced along cut lines 218 and 220 simultaneously or one at a time (e.g., sequentially).

[0094] FIG. 12 depicts cut lines 218 and 220, which extend through bonded wafers 222. Cut line 218 can be positioned to extend through (e.g., intersect with) the array of cavities 216, such that a downward cut along cut line 218 cuts through the array of cavities 216 in bonded wafers 222 and forms cavities 214. In some examples, the array of cavities 216 can be cut into sections of substantially equal size, which can provide substantially uniform cavities 214. Cut line 220 can be positioned orthogonal to cut line 218. Cut line 220 can be positioned to extend between, but not intersect, the array of cavities 216, such that a downward cut along cut line 220 cuts through two layers of wafer material. For example, dicing along cut lines 220 cuts through the cavity wafer walls that define the array of cavities 216 without the path of cut lines 220 intersecting the array of cavities 216 .

[0095] Dicing along cut lines 218 and 220 results in the cap 202 shown in Figures 13A-13C. In some implementations, cut line 218 extends through the array of rectangular cavities 216 such that dicing along cut line 218 separates the larger rectangular cavity 216 into two smaller rectangular openings that are substantially equal in size. In some implementations, bonded wafers 222 can be diced along cut lines 218, 220 using a diamond saw, a water jet, an ultrasonic jet, or other suitable method. In some embodiments, bonded wafers 222 can be either brazed or on blue tape adhesive to hold the bonded wafers 222 during dicing.

[0096] Still referring to Figures 13A-13C, there is an exemplary embodiment of a two-wafer (e.g., two-layer) cap 202 formed by singulation. In this example, the cap 202 comprises four sidewalls and a lid or top. In particular, the window wafer 204 forms one sidewall of the cap 202, and the cavity wafer 206 forms three sidewalls and the top of the cap 202. The window wafer 204 and the cavity wafer 206 together define an uncovered cavity 214 (e.g., an open cavity) within the cap 202. In some embodiments, singulation results in caps 202 in which one of the four sidewalls of each cap 202 comprises the DSP window wafer.

[0097] Although not shown, the cap 202 formed from dicing of the bonded wafers 222 may include an edge (e.g., similar to 124 in FIG. 7B) resulting from singulation. In some embodiments, the surface of the edge may be ground and / or polished to improve flatness and reduce surface roughness.

[0098] Although not shown, in some embodiments, the edge can be metallized, such as by forming a metal surface (e.g., similar to 126 in FIG. 7C) on the edge to facilitate bonding of the edge to a metal surface on the submount 212 (e.g., similar to 128 in FIGS. 8A-8B). In some embodiments, the composition of the metal surface can be selected to be compatible with (e.g., match) the metal surface on the submount 212. In certain embodiments, metallizing the edge can be performed by use of a paint or ink designed to form a hermetic solderable metal surface on the edge. Because the edge of each cap 202 is not defined until after singulation, the metallization of the edge can be done in a manner that is compatible with mass production of the caps 202. In some implementations, these paints or inks may require drying and firing steps to maximize the bond strength between the metal in the paint / ink and the material of the edge (e.g., glass, sapphire, silicon, among others). The paints and inks are typically filled with metal particles or flakes such as Ni or Ag. The paints or inks can be applied to these caps 202 in large quantities using automated machines for pad printing or dip coating.

[0099] In some embodiments, the edge of the cap 202 can be coated with a thin film metallization stack by a physical vapor deposition (PVD) process (e.g., sputtering or evaporation), where the roof of the cap 202 can be masked with a metal or photoresist. In these embodiments, the thin film metallization stack can comprise Gelot metallization from Materion Balzers Optics. It should be appreciated that such thin film metallization can improve compatibility with solder.

[0100] Referring back to FIG. 9, there is a cross-sectional view of the cap 202 encasing the EELD 210 on the submount 212. In some embodiments, the cap 202 can include a metal surface on the bottom edge of the cap 202. When the cap 202 is mounted on the submount 212, the metal surface can engage a complementary metal surface on the submount 212. In some embodiments, the submount 212 is made of ceramic. In some examples, the EELD 210 can be bonded to the ceramic submount 212 with a via (not shown) to the backside. In some embodiments, a DSP metal spacer can be inserted between the EELD 210 and the submount 212 to provide a vertical distance for the laser beam LB to spread out from the edge of the EELD chip before reaching the sidewall (e.g., the first surface 204a of the window wafer 204 in FIG. 9). It should be appreciated that the semiconductor package 200 provided herein has a smaller footprint and volume and is compatible with fully automated (robotic) assembly. In addition, the semiconductor package 200 provided herein allows the cap 202 to be mounted on a co-fired AlN submount 212, which provides better thermal performance than conventional semiconductor packages.

[0101] Below is a description of an example implementation of method 600 (FIG. 18 with reference to FIGS. 14A-17) by which the example three-wafer cap 502 of FIG. 17, as well as other caps (e.g., two-wafer cap 202 of FIGS. 13A-13C), may be reliably and efficiently manufactured in large quantities using the techniques disclosed herein. Method 600 will be described with reference to FIGS. 14A-17, which illustrate various stages in the fabrication of cap 502.

[0102] 14A-18, the method 600 begins at flow chart step 602 with processing of a wafer to form a bonded wafer. In some implementations, the processed wafers are bonded to form a bonded wafer sandwich 522 comprising three wafers. The wafers can be processed by forming an AR surface on at least one side of a window wafer and forming a plurality of through holes in a spacer wafer, as described above with respect to FIGS. 2-8B. In other implementations, the processed wafers are bonded to form a bonded wafer sandwich (e.g., 222 in FIGS. 11A-11B) comprising two wafers. The wafers can be processed by forming an AR surface on at least one side of a window wafer and forming an array of cavities in a cavity wafer, as described above with respect to FIGS. 9-13C. As illustrated in Figures 14A-14C, bonding the processed wafers can include bonding the first and second window wafers 504, 508 to opposing sides 506a, 506b of the spacer wafer 506 such that the spacer wafer 506 is sandwiched between the first and second window wafers 504, 508. The spacer wafer 506 is perforated with a plurality of through holes 516 extending from the first side 506a of the spacer wafer 506 to the opposing second side 506b of the spacer wafer 506. In the embodiment of Figure 14A, the first and second window wafers 504, 508 are made of glass and the spacer wafer 506 is made of glass. In the embodiment of Figure 14B, the first and second window wafers 504, 508 are made of glass and the spacer wafer 506 is made of silicon. However, the window wafers and the spacer wafer are not limited to these materials and can comprise other materials as described above. FIG. 14C shows a bonded wafer sandwich 522 in which a spacer wafer 506 is sandwiched between the first and second window wafers 504, 508, and the spacer wafer 506 is bonded to the first and second window wafers 504, 508 by a bonding process including, but not limited to, anodic bonding, solder bonding, direct bonding, laser bonding, among others.In some examples, the spacer wafer 506 can be bonded to the first and second window wafers 504, 508 by fusion bonding, laser bonding, or eutectic bonding.

[0103] Alternatively, processing the wafers to form a bonded wafer may include bonding a window wafer to a cavity wafer to form a two-layer bonded wafer (e.g., 222 in FIG. 11A). In this example, the bonded wafer comprises two wafers bonded together as described above with respect to FIGS. 9-13C.

[0104] 604 is a step of stacking a plurality of bonded wafers to form a block. In some implementations, a plurality of bonded wafer sandwiches are stacked to form a block. Stacking a plurality of bonded wafer sandwiches together to form a block facilitates mass production manufacturing. In FIG. 15A, there is an example block 530 comprising six rectangular bonded wafer sandwiches 522. It should be understood that the block of method 600 is not limited to any particular shape and / or number of bonded wafer sandwiches, and the illustration is used for the purpose of illustrating the principles of method 600. In some embodiments, a temporary adhesive (e.g., 536 in FIG. 15B), i.e., glue, can be used to hold the bonded wafer sandwiches 522 together, so that the block 530 is stable and retains its form / structure. Before the temporary adhesive is cured, it is important to establish precise alignment of the cavities between the stack of bonded wafer sandwiches 522. The temporary adhesive can be selected to withstand temperatures in excess of 200° C. One example of a high temperature temporary adhesive (eg, capable of withstanding temperatures in excess of 200° C.) is a fugitive adhesive.

[0105] 606 is the step of cutting through the blocks 530 to form a plate. FIG. 15A depicts vertical cutting paths, i.e., saw paths 532, that extend through the bonded wafer sandwiches 522 of the blocks 530. Cutting in the direction of arrow 538 from the top 530a of the blocks 530 to the bottom 530b of the blocks 530 along the saw paths 532 cuts through each bonded wafer sandwich 522 and through the through holes 516 in each bonded wafer sandwich 522, forming cavities (e.g., 514 in FIG. 15B) in the resulting plate (e.g., 540 in FIG. 15B). In some examples, the through holes are cut into two pieces of substantially similar dimensions. In one example, the cuts along the saw paths 532 can be performed using a wire saw (MWS), which allows multiple cuts of the blocks 530 to be performed simultaneously.

[0106] 608 is a step of processing the plate. In FIG. 15B there is an example of a plate 540 resulting from a saw cut along saw path 532, with the cavity 514 and the edges surrounding the cavity 514 (e.g., 124 in FIG. 7B) exposed at the surface of the plate 540. This allows various processing steps to be performed on the plate 540. In another example, the processing includes grinding the edges of the plate 540 to generate a substantially flat surface. Grinding the edges of the plate 540 can be performed to remove chatter left by the saw cut. In one example, the processing includes performing a soft ultrasonic cleaning of the plate 540. In yet another example, the processing includes metallizing the edges of the plate 540, preferably after the grinding step. In some embodiments, the window wafer sidewalls can be masked to mitigate the application of a metal coating to the window wafer sidewalls. Methods for metallizing the edges include physical vapor deposition (PVD) (eg, sputtering and evaporation), screen printing, ink dipping, and pad printing, among others.

[0107] 610 is the step of cutting through the plate to form rods. Figure 15B depicts the cutting paths, i.e., saw paths 534, that extend through the plate 540. A downward cut from the top of the plate 540 to the bottom of the plate 540 along the saw paths 534 results in multiple rods 550, as shown in Figure 16. In one example, the cuts along the saw paths 534 can be performed using a MWS, which allows multiple cuts in the plate 540 to be performed simultaneously.

[0108] 612 is the step of removing the temporary adhesive from the wand 550, freeing the cap 502. FIG. 16 shows wands 550, each of which includes multiple caps 502 held together by temporary adhesive 536. In some implementations, the temporary adhesive 536 can be removed by exposing the wand 550 to a solvent. In one example, the wand 550 can be placed in a solvent to remove the temporary adhesive and free the cap 502 from the wand 550. FIG. 17 shows a cap 502 including a cavity 514 and a metal surface 526 on a bottom edge of the cap 502.

[0109] It should be appreciated that method 600 allows for metallization of all edges of plate 540 simultaneously, which eliminates the need to metallize the edges of each cap one at a time. Caps for conventional EELD semiconductor packages may have an external footprint as small as 3 mm by 3 mm, and therefore metallizing the caps one at a time is slow and expensive. Method 600 disclosed herein provides a plate including a cavity and an upwardly facing, exposed edge, thereby facilitating masking and metallizing all edges on the plate at once. By facilitating metallizing all edges on the plate at once, method 600 saves time and money over conventional techniques for manufacturing EELD semiconductor packages. Additionally, method 600 provides for dissolving the temporary adhesive and freeing the cap including the already metallized edge. Thus, there is no handling / flipping of cap 502 until the part is finished according to method 600.

[0110] The following is a description of an example implementation of method 700 as shown in Figure 19, by which three-wafer caps (e.g., 102 of Figures 6A-7C) and two-wafer caps (e.g., 202 of Figures 13A-13C) can be reliably manufactured using the techniques disclosed herein. Method 700 will be described with reference to Figures 4A-7C and 11A-13C, which illustrate various stages in the fabrication of a cap (e.g., 102 of Figures 6A-7C or 202 of Figures 13A-13C).

[0111] 4A-7C, method 700 begins at flowchart step 702 with processing of wafers to form a bonded wafer. In some implementations, the processed wafers are bonded to form a bonded wafer sandwich (e.g., 122 in FIGS. 4A-4B) comprising three wafers. The wafers can be processed by forming an AR surface on at least one side of a window wafer and forming a plurality of through holes in a spacer wafer, as described above with respect to FIGS. 2-8. 4A-4B show that bonding of the processed wafers to form a bonded wafer sandwich can include bonding the first and second window wafers 104, 108 to opposing sides 106a, 106b of a spacer wafer 106 containing a plurality of through holes 116 by a bonding process including, but not limited to, anodic bonding, solder bonding, direct bonding, laser bonding, among others, whereby the spacer wafer 106 is sandwiched between and bonded to the first and second window wafers 104, 108. In some examples, the spacer wafer 506 can be bonded to the first and second window wafers 504, 508 by fusion bonding, laser bonding, or eutectic bonding.

[0112] In other implementations, the processed wafers are bonded to form a bonded wafer sandwich (e.g., 222 in FIGS. 11A-11B) comprising two wafers. The wafers can be processed by forming an AR surface on at least one side of the window wafer and forming an array of cavities in the cavity wafer as described above with respect to FIGS. 9-13C. By way of example, FIGS. 11A-11B show that bonding the processed wafers to form a bonded wafer sandwich can include bonding the window wafer 204 to a side 206a of the cavity wafer 206 that includes the array of cavities 216, such that the cavity wafer 206 is bonded to the window wafer 204 by a bonding process including, but not limited to, anodic bonding, solder bonding, direct bonding, laser bonding, among others. In some examples, the cavity wafer 206 can be bonded to the window wafer 204 by fusion bonding, laser bonding, or eutectic bonding.

[0113] 704 is a step of cutting through the bonded wafer sandwich to form caps (e.g., 102 in FIGS. 6A-7C or 202 in FIGS. 13A-13C), each of which includes a cavity (e.g., 114 in FIGS. 6A-7C or 214 in FIGS. 13A-13C), as shown in FIGS. 5 and 12. The bonded wafer sandwich comprising three wafers 122 can be diced along cut lines 118 to cut through through-holes 116 in the bonded wafer sandwich 122, and along cut lines 120 to cut through the spacer wafer walls defining the through-holes and by singulation to yield the caps 102. It should be understood that the bonded wafer sandwich 122 can be diced along cut lines 118 and 120 simultaneously or one at a time (e.g., sequentially). In some implementations, the bonded wafers 122 are positioned with the DSP window wafer as the top surface prior to dicing / sawing the bonded wafer sandwich 122 along cut lines 118, 120 using a diamond saw, water jet, ultrasonic jet, or other suitable method.

[0114] The bonded wafer sandwich comprising the two wafers 222 can be diced along cut lines 218 to cut through the array of cavities 216 in the bonded wafer sandwich 222, and along cut lines 220 to cut through the cavity wafer walls defining the array of cavities and, by singulation, yield the caps 202. It should be appreciated that the bonded wafers 222 can be diced along cut lines 218 and 220 simultaneously or one at a time (e.g., sequentially). In some implementations, the bonded wafer 222 is positioned with the DSP window wafer as the top surface prior to dicing / sawing the bonded wafer sandwich 222 along cut lines 218, 220 using a diamond saw, water jet, ultrasonic jet, or other suitable method.

[0115] At 706, the cap (e.g., 102 in FIGS. 6A-7C or 202 in FIGS. 13A-13C) can be processed and metallized. In a non-limiting example, the cap can be placed on a plate for further processing. In some embodiments, the cap can have a lip resulting from singulation, and the surface of the lip can be ground and / or polished to improve flatness and reduce surface roughness. In some embodiments, the lip can be metallized, such as by forming a metal surface on the lip to facilitate bonding of the lip to a metal surface on the submount. In some embodiments, metallizing the lip can be performed by use of a paint or ink designed to form a hermetic solderable metal surface on the lip. In another embodiment, the lip of the cap can be coated with a thin film metallization stack by a physical vapor deposition (PVD) process (e.g., sputtering or evaporation), where the ceiling of the cap can be masked by metal or photoresist.

[0116] The following is a description of an example implementation of method 900 as shown in Figure 23, by which multi-wafer caps (e.g., 3-wafer cap 102 of Figures 7A-7C or 2-wafer cap 202 of Figures 13A-13C) may be reliably and efficiently manufactured in large quantities using the techniques disclosed herein. Method 900 will be described with reference to Figures 4A-7C and 11A-13C, which illustrate various stages in the fabrication of a cap (e.g., 102 of Figures 7A-7C or 202 of Figures 13A-13C), and Figures 20-22 in light of method 700.

[0117] Method 900 begins at flowchart step 902 with the processing of wafers to form a bonded wafer sandwich, such as bonded wafer sandwich 822 shown in Figure 20. Bonded wafer sandwich 822 comprises multiple wafers, such as, for example, two wafers (e.g., 222 of Figures 11A-11B) or three wafers (e.g., 122 of Figures 4A-4B). The processing of wafers to form a bonded wafer sandwich, such as bonded wafer sandwich 822, is described in method 700 above and will not be repeated for the sake of brevity.

[0118] 904 is a step of cutting through the bonded wafer sandwich 822 to form strips 860 containing a plurality of cavities 814, as shown in FIGS. 20-21. In some embodiments, the bonded wafer sandwich 822 is a three-wafer bonded wafer sandwich (e.g., 122 in FIG. 4A) that can be diced along cut lines 818 to cut through through-holes (e.g., 816 in FIG. 20) in the bonded wafer sandwich 822, and along cut lines 820 to cut through selected spacer wafer walls that define the through-holes (e.g., 816 in FIG. 20) to produce strips 860. In other embodiments, the bonded wafer sandwich 822 is a two-wafer bonded wafer sandwich (e.g., 222 in FIG. 11A ) that can be diced along cut lines 818 to cut through an array of cavities (e.g., 816 in FIG. 20 ) in the bonded wafer sandwich 822, and along cut lines 820 to cut through selected cavity wafer walls that define the array of cavities (e.g., 816 in FIG. 20 ) to produce a strip 860 that includes a plurality of cavities 814. The strip 860 is not limited to any particular number of cavities 814. In a non-limiting example, the strip 860 includes four cavities 814. In another non-limiting example, the strip 860 includes five cavities 814.

[0119] It should be appreciated that the bonded wafer sandwich 822 can be diced simultaneously or one at a time (e.g., sequentially) along cut lines 818 and 820. In some implementations, the bonded wafers 822 are positioned with the DSP window wafer as the top surface prior to dicing / sawing the bonded wafer sandwich 822 along cut lines 818, 820 using a diamond saw, water jet, ultrasonic jet, or other suitable method.

[0120] 906 is the step of loading the strips onto a carrier or into an array holder for further processing. Figure 21 illustrates strips 860 loaded onto a carrier 862, such as a plate, from a side view 870 and from a top view 872. In this particular embodiment, each of the strips 860 includes four cavities 814, which reduces the time and cost of picking and loading individual caps for processing as described in method 700 above.

[0121] At 908, the strips 860 mounted on the carrier 862 or in the array holder can be processed and metallized. In some embodiments, the strips can be provided with edges, and the surfaces of the edges can be ground and / or polished to improve flatness and reduce surface roughness. In some embodiments, the edges can be metallized at a post-singulation stage, such as by forming a metal surface on the edges to facilitate bonding of the edges to a metal surface on the submount. In some embodiments, metallizing the edges can be performed by use of paints or inks designed to form a hermetic solderable metal surface on the edges. In another embodiment, the edges can be coated with a thin film metallization stack by a physical vapor deposition (PVD) process (e.g., sputtering or evaporation), where the roof of the strip can be masked with a metal or photoresist.

[0122] 910 is a step of cutting through the loaded strips 860 along cut lines 864, as shown in FIG. 22. Cutting or dicing the loaded strips 860 along cut lines 864 results in singulation of the strips 860 into caps (e.g., 102 in FIGS. 6A-7C or 202 in FIGS. 13A-13C), each of which includes a cavity 814. It should be understood that the loaded strips 860 can be diced along cut lines 864 simultaneously or one at a time (e.g., sequentially) using a diamond saw, water jet, ultrasonic jet, or other suitable method.

[0123] The following examples are further illustrative of the present disclosure. The semiconductor packages and methods of forming the semiconductor packages and components thereof (e.g., caps) are presented as exemplary, and various modifications can be derived in light of the foregoing disclosure within the scope of the present disclosure.

[0124] In some embodiments, a semiconductor package is provided, the semiconductor package including a cap, the cap comprising a first window wafer having a first side and an opposing second side, the first side and the second side being parallel to one another, the first side and / or the second side including an anti-reflective surface, a second window wafer having the first side and the opposing second side, and a spacer wafer perforated with a plurality of through holes, the plurality of through holes extending from the first side of the spacer wafer to the opposing second side of the spacer wafer, the spacer wafer being configured to be in contact with the first window wafer. and a spacer wafer disposed between the spacer wafer and a second window wafer, the first window wafer bonded to a first side of the spacer wafer and the second window wafer bonded to a second side of the spacer wafer, the first window wafer, the second window wafer, and the spacer wafer together defining a cavity in the cap, and an edge-emitting laser diode disposed on the submount and configured to direct a laser beam at normal incidence to the first side of the first window wafer, the cap being mounted on the submount, and the edge-emitting laser diode being encapsulated in the cavity.

[0125] In one embodiment of the semiconductor package, the antireflective surface comprises an antireflective coating, a filter coating, or a textured surface configured to form an antireflective topography. In a particular embodiment, the textured surface comprises a moth-eye topography in which the textured area is formed of a matrix of discrete rectangular areas.

[0126] In another embodiment of the semiconductor package, a first side of the first window wafer is disposed proximate to the edge-emitting laser diode and includes an anti-reflective surface, hi a particular embodiment, a second side of the first window wafer is disposed distal to the edge-emitting laser diode and is bonded to an array of lenses or microlenses.

[0127] In yet another embodiment of the semiconductor package, the first window wafer and / or the second window wafer are double-sided polished wafers.

[0128] In yet another embodiment of the semiconductor package, the first window wafer comprises DSP fused silica, glass, sapphire, Borofloat 33 glass, or silicon.

[0129] In another embodiment of the semiconductor package, each of the first and second window wafers has a thickness between 0.2 mm and 0.8 mm, and the spacer wafer has a thickness between 0.5 mm and 3.5 mm.

[0130] In yet another embodiment of the semiconductor package, the spacer wafer is configured to have a substantially similar coefficient of thermal expansion (CTE) as the first and second window wafers. In a particular embodiment, the spacer wafer is made of substantially the same material as the first window wafer and / or the second window wafer.

[0131] In yet another embodiment of the semiconductor package, each of the first window wafer, the second window wafer, and the spacer wafer has a circular shape and a diameter of 150 mm to 200 mm.

[0132] In yet another embodiment of the semiconductor package, the spacer wafer comprises Invar, silicon, Kovar, fused silica, glass, or sapphire.

[0133] In another embodiment of the semiconductor package, the submount is made from a ceramic.

[0134] In yet another embodiment, the plurality of through holes are rectangular, triangular, or circular.

[0135] In another embodiment, a semiconductor package is provided, the semiconductor package comprising: a cap, the cap comprising a window wafer having a first side and an opposing second side, the first side and the second side being parallel to one another, the first side and / or the second side comprising an antireflective surface; a cavity wafer, the cavity wafer extending from the first side of the cavity wafer toward the opposing second side of the cavity wafer and including a bottom, the window wafer being bonded to the first side of the cavity wafer, the window wafer and the cavity wafer together defining a cavity in the cap; and an edge-emitting laser diode disposed on a submount and configured to direct a laser beam at normal incidence to the first side of the window wafer, the cap being mounted on the submount, the edge-emitting laser diode being encapsulated in the cavity.

[0136] In one embodiment of the semiconductor package, the antireflective surface comprises an antireflective coating, a filter coating, or a textured surface configured to form an antireflective topography. In a particular embodiment, the textured surface comprises a moth-eye topography in which the textured area is formed of a matrix of discrete rectangular areas.

[0137] In another embodiment of the semiconductor package, a first side of the window wafer is disposed proximate to the edge-emitting laser diodes and includes an anti-reflective surface, hi a particular embodiment, a second side of the window wafer is disposed distal to the edge-emitting laser diodes and is bonded to an array of lenses or microlenses.

[0138] In yet another embodiment of the semiconductor package, the window wafer is a double-sided polished wafer.

[0139] In yet another embodiment of the semiconductor package, the window wafer comprises DSP fused silica, glass, sapphire, Borofloat 33 glass, or silicon.

[0140] In another embodiment of the semiconductor package, the cavity wafer is configured to have a substantially similar coefficient of thermal expansion (CTE) as the window wafer, hi a particular embodiment, the cavity wafer is made of substantially the same material as the window wafer.

[0141] In yet another embodiment of the semiconductor package, the window wafer and the cavity wafer each have a circular shape and a diameter of 150 mm to 200 mm.

[0142] In yet another embodiment of the semiconductor package, the cavity wafer comprises Invar, silicon, Kovar, fused silica, glass, or sapphire.

[0143] In another embodiment of the semiconductor package, the submount is made from a ceramic.

[0144] In yet another embodiment of the semiconductor package, the window wafer has a thickness between 0.2 mm and 0.8 mm, and the cavity wafer has a thickness between 0.5 mm and 3.5 mm.

[0145] In yet another embodiment of the semiconductor package, the cavities in the array of cavities are rectangular, triangular, or circular.

[0146] In some embodiments, a method of manufacturing a cap for use in an EELD semiconductor package is provided, the method including: bonding first and second window wafers to opposite sides of a spacer wafer to form a bonded wafer sandwich, the spacer wafer being disposed between the first window wafer and the second window wafer in the bonded wafer sandwich, the spacer wafer being perforated with a plurality of through holes, the plurality of through holes extending through the spacer wafer between opposite sides of the spacer wafer, a side of the first window wafer and / or the second window wafer including an anti-reflective surface; stacking a plurality of the bonded wafer sandwiches on top of each other to form a block, adjacent bonded wafer sandwiches being secured together using an adhesive; cutting through the block to form at least one plate; treating the plate by metallizing an edge portion of the plate; cutting through the plate to form a bar; and removing the adhesive from the bar to produce a cap.

[0147] In one embodiment of the method, the first and second window wafers are bonded to the spacer wafer by solder bonding, direct bonding, anodic bonding, laser bonding, or adhesive bonding. In a particular embodiment, bonding the first and second window wafers to the spacer wafer is performed in two successive steps, including bonding the spacer wafer to the first window wafer and bonding the second window wafer to the spacer wafer.

[0148] In another embodiment of the method, the adhesive is a temporary adhesive.

[0149] In yet another embodiment of the method, cutting through the block to form at least one plate includes cutting through a through hole in each bonded wafer sandwich to form a cavity in the at least one plate.

[0150] In yet another embodiment of the method, the adhesive is removed by exposing the rod to a solvent.

[0151] In another embodiment of the method, preparing the plate further comprises cleaning a surface of the plate and grinding the surface flat prior to metallizing an edge portion of the plate.

[0152] In some embodiments, a method of manufacturing a cap for use in an EELD semiconductor package is provided, the method including: bonding a window wafer to a cavity wafer to form a bonded wafer sandwich, the cavity wafer including an array of cavities, the cavities extending from a first side of the cavity wafer to an opposing second side of the cavity wafer including a bottom, and the side of the window wafer including an anti-reflective surface; stacking a plurality of the bonded wafer sandwiches on top of each other to form a block, adjacent bonded wafer sandwiches being secured together using an adhesive; cutting through the block to form at least one plate; treating the plate by metallizing an edge portion of the plate; cutting through the plate to form a bar; and removing the adhesive from the bar to produce a cap.

[0153] In one embodiment of the method, the window wafer is bonded to the cavity wafer by solder bonding, direct bonding, anodic bonding, laser bonding, or adhesive bonding.

[0154] In another embodiment of the method, the adhesive is a temporary adhesive.

[0155] In yet another embodiment of the method, cutting through the block to form at least one plate includes cutting through an array of cavities in each bonded wafer sandwich to form the cavities in the at least one plate.

[0156] In yet another embodiment of the method, the adhesive is removed by exposing the rod to a solvent.

[0157] In another embodiment, preparing the plate further comprises cleaning the surface of the plate and grinding the surface flat prior to metallizing an edge portion of the plate.

[0158] In some embodiments, a method of making a cap for use in an EELD semiconductor package is provided, the method including: processing a wafer to form a bonded wafer, where processing the wafer includes bonding first and second window wafers to opposite sides of a spacer wafer to form a bonded wafer sandwich, the spacer wafer being disposed between the first window wafer and the second window wafer in the bonded wafer sandwich, the spacer wafer being perforated with a plurality of through holes, the plurality of through holes extending through the spacer wafer between opposite sides of the spacer wafer, a side of the first window wafer and / or the second window wafer including an anti-reflective surface; cutting through the bonded wafer sandwich to form caps, each including a cavity; and processing the caps by metallizing an edge of the cap.

[0159] In one embodiment of the method, the first and second window wafers are bonded to the spacer wafer by solder bonding, direct bonding, anodic bonding, laser bonding, or adhesive bonding.

[0160] In another embodiment of the method, cutting through the bonded wafer sandwich includes cutting through a through hole in the bonded wafer sandwich and cutting through a spacer wafer wall defining the through hole to create a cap.

[0161] In yet another embodiment of the method, treating the cap further comprises cleaning a surface of the cap and grinding the surface flat prior to metallizing a lip of the cap.

[0162] In some embodiments, a method of making a cap for use in an EELD semiconductor package is provided, the method including processing a wafer to form a bonded wafer, where processing the wafer includes bonding first and second window wafers to opposite sides of a spacer wafer to form a bonded wafer sandwich, where the spacer wafer is disposed between the first window wafer and the second window wafer in the bonded wafer sandwich, where the spacer wafer is perforated with a plurality of through holes, where the plurality of through holes extend through the spacer wafer between opposite sides of the spacer wafer, where a side of the first window wafer and / or the second window wafer includes an anti-reflective surface; cutting through the bonded wafer sandwich to form strips each including a plurality of cavities; mounting the strips on a carrier or in an array holder; processing the strips by metallizing an edge of each strip; and cutting through the mounted strips to produce caps each including a cavity.

[0163] In one embodiment of the method, the first and second window wafers are bonded to the spacer wafer by solder bonding, direct bonding, anodic bonding, laser bonding, or adhesive bonding.

[0164] In another embodiment of the method, cutting through the bonded wafer sandwich includes cutting through through holes in the bonded wafer sandwich and selectively cutting through spacer wafer walls defining the through holes to create strips.

[0165] In yet another embodiment of the method, each of the strips includes four cavities.

[0166] In yet another embodiment of the method, treating the strip further includes cleaning a surface of the strip and grinding the surface flat prior to metallizing an edge of the strip.

[0167] In some embodiments, a method of making a cap for use in an EELD semiconductor package is provided, the method including processing a wafer to form a bonded wafer, the window wafer being bonded to a cavity wafer to form a bonded wafer sandwich, the cavity wafer including an array of cavities extending from a first side of the cavity wafer to an opposing second side of the cavity wafer and including a bottom, the side of the window wafer including an anti-reflective surface; cutting through the bonded wafer sandwich to form caps, each including a cavity; and treating the caps by metallizing an edge of the cap.

[0168] In one embodiment of the method, the window wafer is bonded to the cavity wafer by solder bonding, direct bonding, anodic bonding, laser bonding, or adhesive bonding.

[0169] In another embodiment of the method, cutting through the bonded wafer sandwich includes cutting through an array of cavities in the bonded wafer sandwich and cutting through cavity wafer walls that define the array of cavities to produce caps.

[0170] In yet another embodiment of the method, treating the cap further comprises cleaning a surface of the cap and grinding the surface flat prior to metallizing a lip of the cap.

[0171] In some embodiments, a method of making a cap for use in an EELD semiconductor package is provided, the method including: processing a wafer to form a bonded wafer, where processing the wafer includes bonding a window wafer to a cavity wafer to form a bonded wafer sandwich, the cavity wafer including an array of cavities, the cavities extending from a first side of the cavity wafer to an opposing second side of the cavity wafer and including a bottom, and the side of the window wafer includes an anti-reflective surface; cutting through the bonded wafer sandwich to form strips each including a plurality of cavities; mounting the strips on a carrier or in an array holder; processing the strips by metallizing an edge of each strip; and cutting through the mounted strips to produce caps each including a cavity.

[0172] In one embodiment of the method, the window wafer is bonded to the cavity wafer by solder bonding, direct bonding, anodic bonding, laser bonding, or adhesive bonding.

[0173] In another embodiment of the method, cutting through the bonded wafer sandwich includes cutting through an array of cavities in the bonded wafer sandwich and cutting through a cavity wafer wall that defines the array of cavities to create strips.

[0174] In yet another embodiment of the method, each of the strips includes four cavities.

[0175] In yet another embodiment of the method, treating the strips further includes cleaning the surface of the strips and grinding the surface flat prior to metallizing an edge of each strip.

[0176] Although the embodiments discussed herein are related to the systems, devices, and methods discussed above, these embodiments are intended to be exemplary and are not intended to limit the applicability of these embodiments only to those discussions set forth herein. The embodiments and discussions herein can be readily incorporated into any of these systems and methodologies by one of ordinary skill in the art.

[0177] The above examples are merely illustrative of some possible embodiments of various aspects of the present innovation, and equivalent alterations and / or modifications will occur to those skilled in the art upon reading and understanding of this specification and the accompanying drawings. In particular, with respect to the various functions performed by the components (assemblies, devices, systems, circuits, etc.) described above, the terms used to describe such components (including references to "means") are intended to correspond to any component or combination thereof that performs the stated function of the described components (e.g., is functionally equivalent), even if it is not a structural equivalent of the disclosed structures that perform the function illustrated in the implementation of the present innovation, unless otherwise indicated. In addition, although a particular feature of the present innovation may be disclosed for only one of several implementations, such feature may be combined with one or more other features of other implementations, as may be desired and advantageous for any given or particular application. To the extent the terms "including," "includes," "having," "has," "with," or variations thereof are used in the detailed description and / or claims, such terms are also intended to be inclusive in a manner similar to the term "comprising."

[0178] This written description uses examples to disclose the invention including the best mode, and also to enable those skilled in the art to practice the invention, including making and using any device or system and performing any incorporated methods. The patentable scope of the innovation is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal wording of the claims, or if they include equivalent structural elements with insignificant differences from the literal wording of the claims.

[0179] In the present specification and claims, reference will be made to a number of terms having the following meanings. The singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Approximate language may be applied throughout the specification and claims to modify quantitative expressions that may vary permissibly without resulting in a change in the basic function to which it is related, as used herein. Thus, a value modified by a term such as "about" should not be limited to the precise value stated. In some cases, approximation language may correspond to the accuracy of an instrument for measuring the value. Furthermore, unless specifically stated otherwise, use of the terms "first," "second," etc. does not denote any order or importance, but rather, the terms "first," "second," etc. are used to distinguish one element from another.

[0180] As used herein, the terms "may" and "may be" indicate the possibility of an occurrence within a set of circumstances, i.e., the possession of a specified quality, characteristic, or function, and / or condition another verb by expressing one or more of the abilities, capabilities, or possibilities associated with the conditional verb. Thus, the use of "may" and "may be" indicates that in some circumstances, the modified term is clearly appropriate, capable, or preferred for the indicated capacity, function, or use, while recognizing that the modified term may sometimes not be appropriate, capable, or preferred. For example, in some circumstances, a certain event or capacity may be expected, while in other circumstances, the event or capacity may not occur, i.e., this distinction is respected by the terms "may" and "may be."

[0181] The best mode for carrying out the innovation has been described for the purpose of illustrating the best mode known to the applicant at the time and enabling a person skilled in the art to practice the innovation, including making and using a device or system and implementing a method incorporating the same. The examples are illustrative only and are not meant to limit the innovation as contemplated by the scope and merit of the claims. The innovation has been described with reference to preferred and alternative embodiments. Obviously, modifications and alterations will occur to those skilled in the art upon perusal and understanding of the specification. It is intended to include all such modifications and alterations insofar as they are within the scope of the appended claims or their equivalents. The patentable scope of the innovation may include other examples as defined by the claims and as occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal wording of the claims, or if they include equivalent structural elements with insignificant differences from the literal wording of the claims.

[0182] It will be understood that various of the above-disclosed and other features and functions, or alternatives thereof, may be desirably combined into many other different systems or applications. It will be further understood that various presently unforeseen or unanticipated alternatives, modifications, variations, or improvements therein may subsequently be made by those skilled in the art, which are also intended to be encompassed by the following claims.

Claims

1. A semiconductor package comprising: A cap, the cap comprising: a first window wafer having a first side and an opposing second side, the first side and the second side being parallel to one another, the first side and / or the second side including an anti-reflective surface; a second window wafer having a first side and an opposing second side; a spacer wafer perforated with a plurality of through holes; Equipped with the plurality of through holes extend from a first side of the spacer wafer to an opposing second side of the spacer wafer, the spacer wafer being disposed between the first window wafer and the second window wafer, the first window wafer being bonded to the first side of the spacer wafer, and the second window wafer being bonded to the second side of the spacer wafer; a cap, the first window wafer, the second window wafer, and the spacer wafer together defining a cavity in the cap; and an edge-emitting laser diode disposed on a submount; Equipped with the edge-emitting laser diode is configured to direct a laser beam at normal incidence onto a first surface of the first window wafer; the cap is mounted on the submount and the edge-emitting laser diode is encapsulated within the cavity.

2. 10. The semiconductor package of claim 1, wherein the anti-reflective surface comprises an anti-reflective coating, a filter coating, or a textured surface configured to form an anti-reflective topography.

3. 3. The semiconductor package of claim 2, wherein the textured surface comprises a moth-eye topography, the textured area being formed in a matrix of discrete rectangular areas.

4. 2. The semiconductor package of claim 1, wherein the first side of the first window wafer is disposed proximate to the edge-emitting laser diode and includes the anti-reflective surface.

5. 5. The semiconductor package of claim 4, wherein the second surface of the first window wafer is disposed distal to the edge-emitting laser diode and is bonded to an array of lenses or microlenses.

6. The semiconductor package of claim 1 , wherein the first window wafer and / or the second window wafer is a double-sided polished wafer.

7. 10. The semiconductor package of claim 1, wherein the first window wafer comprises DSP fused silica, glass, sapphire, Borofloat 33 glass, or silicon.

8. 2. The semiconductor package of claim 1, wherein each of the first and second window wafers has a thickness between 0.2 mm and 0.8 mm, and the spacer wafer has a thickness between 0.5 mm and 3.5 mm.

9. 10. The semiconductor package of claim 1, wherein said spacer wafer is configured to have a substantially similar coefficient of thermal expansion (CTE) as said first and second window wafers.

10. 10. The semiconductor package of claim 9, wherein the spacer wafer is made of substantially the same material as the first window wafer and / or the second window wafer.

11. 2. The semiconductor package of claim 1, wherein each of the first window wafer, the second window wafer, and the spacer wafer has a circular shape and a diameter between 150 mm and 200 mm.

12. 10. The semiconductor package of claim 1, wherein the spacer wafer comprises Invar, silicon, Kovar, fused silica, glass, or sapphire.

13. The semiconductor package of claim 1 , wherein the submount is made of ceramic.

14. The semiconductor package of claim 1 , wherein the plurality of through holes are rectangular, triangular, or circular.

15. 1. A method of manufacturing a cap for use in an EELD semiconductor package, the method comprising: bonding first and second window wafers to opposite sides of a spacer wafer to form a bonded wafer sandwich, the spacer wafer being disposed between the first window wafer and the second window wafer in the bonded wafer sandwich, the spacer wafer being perforated with a plurality of through holes, the plurality of through holes extending through the spacer wafer between opposite sides thereof, a side of the first window wafer and / or the second window wafer comprising an anti-reflective surface; stacking a plurality of bonded wafer sandwiches on top of one another to form a block, adjacent bonded wafer sandwiches being secured together using an adhesive; cutting through said block to form at least one plate; treating the plate by metallizing an edge portion of the plate; cutting through the plate to form a rod; removing the adhesive from the rod to create a cap; and A method comprising:

16. 16. The method of claim 15, wherein the first and second window wafers are bonded to the spacer wafer by solder bonding, direct bonding, anodic bonding, laser bonding, or adhesive bonding.

17. Bonding the first and second window wafers to the spacer wafer includes: bonding the spacer wafer to the first window wafer; bonding the second window wafer to the spacer wafer; 17. The method of claim 16, carried out in two successive steps comprising:

18. The method of claim 15, wherein the adhesive is a temporary adhesive.

19. 16. The method of claim 15, wherein cutting through the block to form at least one plate includes cutting through the through holes in each bonded wafer sandwich to form cavities in the at least one plate.

20. The method of claim 15, wherein the adhesive is removed by exposing the rod to a solvent.

21. Processing the plate comprises: cleaning the surface of the plate; grinding said surface flat prior to metallizing the edge of said plate; The method of claim 15 further comprising:

22. 1. A method of making a cap for use in an EELD semiconductor package, the method comprising: processing the wafer to form a bonded wafer, said processing the wafer including bonding first and second window wafers to opposite sides of the spacer wafer to form a bonded wafer sandwich; the spacer wafer is disposed between the first window wafer and the second window wafer in the bonded wafer sandwich, the spacer wafer being perforated with a plurality of through holes, the plurality of through holes extending through the spacer wafer between opposing sides of the spacer wafer, and a side of the first window wafer and / or the second window wafer includes an anti-reflective surface; cutting through the joined wafer sandwich to form caps, each cap including a cavity; treating said cap by metallizing an edge of said cap; A method comprising:

23. 23. The method of claim 22, wherein the first and second window wafers are bonded to the spacer wafer by solder bonding, direct bonding, anodic bonding, laser bonding, or adhesive bonding.

24. Cutting through the bonded wafer sandwich comprises: cutting through the through hole in the bonded wafer sandwich; cutting through a spacer wafer wall defining said through hole to produce said cap; 23. The method of claim 22, comprising:

25. Treating the cap includes: Cleaning the surface of the cap; grinding said surface flat prior to metallizing said edge of said cap.

23. The method of claim 22, further comprising:

26. 1. A method of making a cap for use in an EELD semiconductor package, the method comprising:

2. Processing a wafer to form a bonded wafer, the processing comprising: bonding first and second window wafers to opposite sides of a spacer wafer to form a bonded wafer sandwich, the spacer wafer being disposed between the first window wafer and the second window wafer in the bonded wafer sandwich, the spacer wafer being perforated with a plurality of through holes, the plurality of through holes extending through the spacer wafer between opposite sides of the spacer wafer, a side of the first window wafer and / or the second window wafer comprising an anti-reflective surface; cutting through the bonded wafer sandwich to form strips each including a plurality of cavities; mounting said strips on a carrier or in an array holder; treating each strip by metallizing an edge of said strip; cutting through said mounted strips to produce caps each including a cavity; A method comprising:

27. 27. The method of claim 26, wherein the first and second window wafers are bonded to the spacer wafer by solder bonding, direct bonding, anodic bonding, laser bonding, or adhesive bonding.

28. Cutting through the bonded wafer sandwich comprises: cutting through the through hole in the bonded wafer sandwich; selectively cutting through a spacer wafer wall defining said through hole to create said strip; 27. The method of claim 26, comprising:

29. 27. The method of claim 26, wherein each of the strips includes four cavities.

30. Treating the strips includes: cleaning the surface of said strip; grinding said surface flat prior to metallizing said edges of said strips; 27. The method of claim 26, further comprising:

Images