Process for fabricating a dual semiconductor-on-insulator structure

Abstract

The invention relates to a process for producing a double semiconductor-on-insulator structure, comprising the steps of providing a first donor substrate and a handle substrate (1), forming a weakened zone in the donor substrate to define a first semiconductor layer (2b) to be transferred, bonding the first donor substrate to the handle substrate (1) with a first electrically insulating layer (2a) at the interface and detaching at the weakened zone, treating the surface of the first transferred semiconductor layer (2b) including (E1) rapid thermal annealing, (E2) thermal oxidation followed by deoxidation, (E3) smoothing heat treatment at a temperature above 1000°C in a non-oxidizing atmosphere, and (E4) chemical mechanical polishing, providing a second donor substrate for a second semiconductor layer (3b) to be transferred, and transferring the layer (3b) with a second electrically insulating layer (3a) at the interface.

Description

[Technical field]

[0001] The present invention relates to a process for fabricating a dual semiconductor-on-insulator structure. [Background technology]

[0002] A semiconductor-on-insulator structure is a multi-layer structure comprising a handle substrate, generally made of a semiconductor such as silicon, an electrically insulating layer, generally an oxide layer such as a silicon oxide layer, disposed on the handle substrate, and a semiconductor layer, generally a silicon layer, disposed on the insulating layer. Such a structure is called a "semiconductor-on-insulator" structure, and in particular a "silicon-on-insulator" (SOI) structure, when the semiconductor is silicon. The oxide layer is then said to be "buried" and is called a "BOX" (for "buried oxide"). In the following, the term "SOI" is generally adopted to denote semiconductor-on-insulator structures.

[0003] In addition to the SOI structure with one BOX layer and one semiconductor layer disposed on the BOX layer, a "dual SOI" structure has been fabricated. The "dual SOI" structure comprises a handle substrate, a first oxide layer or lower buried oxide layer disposed on the handle substrate, a first semiconductor layer or lower semiconductor layer disposed on the first oxide layer, a second oxide layer or upper buried oxide layer disposed on the first semiconductor layer, and a second semiconductor layer or upper semiconductor layer disposed on the second oxide layer. In this double SOI structure, the first oxide layer and the first semiconductor layer constitute a first SOI disposed on the lower part of the structure, and the second oxide layer and the second semiconductor layer constitute a second SOI disposed on the upper part of the structure.

[0004] One known process for making SOI structures is a process called Smart Cut™. The Smart Cut™ process involves implanting atomic species, such as hydrogen (H) and / or helium (He), to create a weakened zone in a donor substrate, bonding the donor substrate to a receiver substrate via an electrically insulating layer, and then detaching the donor substrate at the weakened zone to transfer a thin layer from the donor substrate to the receiver substrate. The donor and receiver substrates are preferably in the form of semiconductor wafers with a diameter of 300 mm. The electrically insulating layer can be formed on the donor substrate or on the receiver substrate.

[0005] One solution proposed to obtain a double SOI is to perform two successive Smart-Cut™ processes: during the second Smart-Cut™ process, the SOI obtained after the first Smart-Cut™ process is used as a second receiver substrate to which a second donor substrate is bonded via a second electrically insulating layer.

[0006] The effectiveness of bonding during the second Smart-Cut™ process depends on the quality of the surface of the first SOI, which acts as the receiver substrate. In particular, the effectiveness of bonding during the second Smart-Cut™ process depends on the roughness and defect density of said surface after the removal of the first donor substrate along the weakened zone during the first Smart-Cut™ process. In particular, during bonding during the second Smart-Cut™ process, defects and other surface irregularities cause holes to form in the final double SOI between the receiver substrate and the second donor substrate. Said holes are often detrimental to the electrical performance level of the structure and the mechanical strength of the assembly.

[0007] A surface treatment may be performed to reduce the surface roughness and defect density of the first SOI after removing the first donor substrate.

[0008] Commonly used surface treatments include thermal treatments such as rapid thermal annealing or annealing in a furnace. It is also possible to carry out chemical mechanical polishing. Finally, chemical treatments can be applied which successively cause the surface in question to be oxidized and then deoxidized.

[0009] However, applying these techniques does not make it possible to achieve a surface quality that is sufficient to allow proper bonding of a second donor substrate to said surface in the course of a new layer transfer step. Summary of the Invention

[0010] One object of the present invention is to propose a process for making a double semiconductor-on-insulator structure that ensures that the donor substrate of the second semiconductor layer is properly bonded to the receiver substrate resulting from the first Smart-Cut™ process.

[0011] To this end, the present invention provides a process for fabricating a double semiconductor-on-insulator structure, comprising the following steps: Providing a first donor substrate and a handle substrate; forming weakened zones in the first donor substrate to define a first semiconductor layer to be transferred; bonding a first donor substrate to a handle substrate, where a first electrically insulating layer is at an interface between the handle substrate and the first donor substrate, and detaching the first donor substrate at the weakened zone to obtain a semiconductor-on-insulator structure comprising, from back side to front side, the handle substrate, the first electrically insulating layer and the first transferred semiconductor layer; - treating a free surface of a first transferred semiconductor layer; Providing a second donor substrate for a second semiconductor layer to be transferred; transferring said second semiconductor layer onto a front surface of a semiconductor-on-insulator structure, a second electrically insulating layer being at the interface between the first transferred semiconductor layer and a second donor substrate, wherein the step of treating the surface of the first transferred semiconductor layer comprises the following successive steps: E1: Rapid thermal annealing; E2: a sequence including thermal oxidation followed by deoxidation; E3: Smoothing heat treatment at a temperature exceeding 1000°C in a non-oxidizing atmosphere; E4: Chemical mechanical polishing and transferring the second semiconductor layer, We propose a process that includes:

[0012] A free surface of the first semiconductor layer is obtained from detaching the first donor substrate along a weakened zone. A process for treating said surface is optimized in order to reduce the roughness and defect density of said surface. Said process further allows to reduce the width of the ring at the outer edge of the second receiver substrate. The joint reduction of the defect density, the roughness, the width of the ring and the irregularity of the ring at the outer edge of the wafer (phenomenon known by the term "jagged edge") limits the number of holes formed when bonding the donor substrate of the second semiconductor layer.

[0013] According to other optional features of the invention, taken alone or in any combination, where this is technically possible, The smoothing heat treatment step E3 is a long thermal annealing carried out at a temperature between 1050 ° C and 1250 ° C for a period of a few minutes to a few hours in a pure or mixed hydrogen or argon atmosphere; The heat treatment step E3 is a rapid thermal annealing A rapid thermal annealing step E3 is carried out at a temperature between 1100 ° C and 1250 ° C for a period of a few seconds to about 100 seconds in an atmosphere containing pure or mixed hydrogen or argon, The rapid thermal annealing step E1 is carried out at a temperature between 1100 ° C and 1250 ° C for a period of a few seconds to about 100 seconds in an atmosphere containing pure or mixed hydrogen or argon, The thermal oxidation step E2 is carried out for a period of several minutes to several hours at a temperature between 800°C and 1100°C in an atmosphere containing oxygen or water vapor, The deoxidation operation of step E2 is carried out by exposing the surface to be treated to a hydrofluoric acid solution, the handle substrate and each donor substrate are in the form of a wafer having a diameter of 300 mm; the weakened zone in the first donor substrate is formed by implanting hydrogen atoms; The step of transferring the second semiconductor layer includes: forming weakened zones in a second donor substrate to define a second semiconductor layer to be transferred; bonding a second donor substrate to the front surface of the semiconductor-on-insulator structure, a second electrically insulating layer being at an interface between the front surface of the semiconductor-on-insulator structure and the first donor substrate; removing the second donor substrate at the weakened zone to obtain a dual semiconductor-on-insulator structure comprising, from back to front, a handle substrate, a first electrically insulating layer, a first transferred semiconductor layer, a second electrically insulating layer and a second transferred semiconductor layer; Including, the weakened zone in the second donor substrate is formed by implanting hydrogen atoms; the second electrically insulating layer is formed by oxidizing the front surface of the first transferred semiconductor layer, so that when the second semiconductor layer is transferred, said first electrically insulating layer is inserted between the first and second semiconductor layers, said additional oxidation step being carried out after treating the free surface of the first semiconductor layer, a second electrically insulating layer is formed by oxidizing a portion of a second donor substrate, so that when the second semiconductor layer is transferred, the first electrically insulating layer is also transferred and interposed between the first semiconductor layer and the second semiconductor layer; a first electrically insulating layer is formed by oxidizing a front surface of the handle substrate prior to bonding the first donor substrate to the handle substrate such that the first electrically insulating layer is interposed between the handle substrate and the first transferred semiconductor layer; A first electrically insulating layer is formed by oxidizing a portion of a first donor substrate prior to bonding the first donor substrate on its oxidized side to a handle substrate such that the first electrically insulating layer is interposed between the handle substrate and the first transferred semiconductor layer. [Brief description of the drawings]

[0014] Other features and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings. [Figure 1] FIG. 2 is a cross-sectional view of the intermediate semiconductor-on-insulator structure obtained after the first layer transfer. [Diagram 2] FIG. 1 is a cross-sectional view of a first layer transfer from a first donor substrate to a front side of a handle substrate, in which a first electrically insulating layer is formed on the surface of the first donor substrate. [Diagram 3] FIG. 2 is a cross-sectional view of a first layer transfer from a first donor substrate to a front side of a handle substrate, in which a first electrically insulating layer is formed on the surface of the handle substrate. [Figure 4] FIG. 1 illustrates a sequence of processing steps according to the process of the present invention. [Diagram 5] FIG. 13 shows the final double semiconductor-on-insulator structure obtained after the second layer transfer. [Figure 6] FIG. 2 is a cross-sectional view of a second single crystal semiconductor layer transfer with a second donor substrate, where a second electrically insulating layer is formed on the second donor substrate. [Figure 7]3 is a cross-sectional view of a second monocrystalline semiconductor layer transfer with a second donor substrate, where a second electrically insulating layer is formed on the structure of FIG. 2. For ease of reading, the drawings are not necessarily drawn to scale. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The dual semiconductor-on-insulator substrate structure includes, from back side to front side, a handle substrate, a first buried oxide layer corresponding to the first electrically insulating layer, a first monocrystalline semiconductor layer, a second buried oxide layer corresponding to the second electrically insulating layer, and a second monocrystalline semiconductor layer.

[0016] The first electrically insulating layer and the first monocrystalline semiconductor layer together form a first semiconductor-on-insulator structure, referred to as a lower SOI structure, and the second electrically insulating layer and the second monocrystalline semiconductor layer together form a second semiconductor-on-insulator structure, referred to as an upper SOI structure.

[0017] The present invention relates to preparing a lower SOI structure by first transferring a first monocrystalline semiconductor layer according to a Smart-Cut™ process; an intermediate surface treatment process; preparing an upper SOI structure by second transferring a monocrystalline semiconductor layer; The present invention relates to a process for preparing a dual semiconductor-on-insulator structure, comprising inter alia:

[0018] The invention more particularly relates to an intermediate surface treatment process carried out following the Smart-Cut™ process for transferring a first monocrystalline semiconductor layer, the Smart-Cut™ process and other layer transfer processes being known.

[0019] The surface treatment process of the present invention is optimized to improve bonding quality during second layer transfer and to minimize the surface roughness and defect density formed after performing the first Smart-Cut™ process.

[0020] By roughness what is meant below is 1×1 μm 2 and 30×30 μm 2 is the maximum peak-to-valley extent measured by atomic force microscope (AFM) for the surface contour between and.

[0021] Regarding defect density, the defect density is defined as the number of particles deposited on the free surface of the wafer and / or the number of structural defects, such as holes or scratches, on the surface of the wafer. These defects are of various sizes, for example between 60 nm and a few microns. The defects may result from impurities created by locally removing the irregular edges of the ring (jagged edges) or otherwise from contamination. The defect density is measured with the aid of an instrument using light scattering technology, such as the SP2 instrument from KLA-Tencor.

[0022] The process further aims to widen the effective bonding zone of the second transferred layer so as to reduce the width of the peripheral ring of the second SOI substrate.

[0023] What is called the ring is the peripheral area of ​​the SOI substrate where the monocrystalline semiconductor layer was not transferred. This ring is due to the fact that the substrate traditionally has a peripheral chamfer several millimeters wide where the donor substrate cannot be bonded to the receiver substrate. During the Smart-Cut™ process, the monocrystalline semiconductor layer of the donor substrate is therefore transferred to the receiver substrate only in the central zone where bonding took place. In some cases, an isolated zone of the donor substrate may nevertheless be transferred to the ring. The ring then has an irregular jagged edge rather than a perfectly circular shape.

[0024] In the case of a double SOI structure, the problem of irregular rings therefore occurs twice, i.e. when making the first SOI substrate and then when making the second SOI substrate, and therefore has a significant impact on the useful width of the upper semiconductor layer, so that if the width of the ring as a result of the first layer transfer is typically between 0.7 mm and 1.5 mm, the width of the "double ring" as a result of the second layer transfer is between 3 mm and 4 mm.

[0025] The surface treatment process according to the invention is characterized in that it is an already known surface treatment process comprising four successive steps, each step making it possible to act on one or the other of the parameters defined below.

[0026] However, each of the steps of the surface treatment process, when performed individually, does not make it possible to achieve the expected performance level for a good quality, effective bond, free of defects such as holes and overly wide rings at the bonding interface, in the context of producing a double SOI structure.

[0027] The various steps of the intermediate surface treatment process and their influence on the quality of the treated surface are described in detail below. For informational purposes, embodiments for preparing the lower and upper SOI structures are also described.

[0028] Preparation of the bottom SOI structure First, a first lower semiconductor-on-insulator or SOI structure is prepared by a first transfer of a monocrystalline semiconductor layer, said structure being shown in Figure 1. The first transfer comprises the following steps: Providing a first donor substrate for a first monocrystalline semiconductor layer 2b and a handle substrate 1; - forming weakened zones in said first donor substrate to define a first semiconductor layer 2b to be transferred; - bonding a first donor substrate to a handle substrate 1, where a first electrically insulating layer 2a is at the interface between the handle substrate 1 and the first donor substrate; Detaching the first donor substrate at the weakened zone. The process is carried out by the Smart-Cut™ process, which includes

[0029] The handle substrate 1 takes the form of a circular semiconductor wafer, preferably a wafer with a diameter of 300 mm. The handle substrate is, for example, a silicon wafer. The handle substrate is preferably an ultra-flat silicon wafer with a chamfer that is less wide and steeper than that of conventional wafers.

[0030] The width of the edge chamfer of the wafer can be evaluated with the aid of the ZDD148 characteristic, which corresponds to the second derivative of the wafer edge contour 2 mm from the edge of the wafer, in other words, the inverse function of the radius of curvature of this wafer edge. Conventionally, the ZDD148 of a silicon wafer with a diameter of 300 mm is -20 nm / mm 2 and -200nm / mm 2 ZDD148 is measured with the aid of a KLA-Tencor wafer site instrument. Ultra-flat silicon wafers have a surface roughness of between 0 nm / mm 2 and -20nm / mm 2 It has ZDD148 characteristics between.

[0031] The use of an ultra-flat silicon wafer allows the width of the peripheral ring to be reduced.

[0032] The first donor substrate is a monocrystalline semiconductor substrate, for example a monocrystalline silicon substrate. The first donor substrate is in the form of a wafer generally having the same diameter as the handle substrate.

[0033] The weakened zone can be created by co-implanting helium and hydrogen atoms into the first donor substrate of the first semiconductor layer. The helium and hydrogen are implanted with an energy between 10 keV and 100 keV and the implanted dose is 1 cm. 2 10 per 15 atoms and 1cm 2 10 per 17 Alternatively, the weakened zone is preferably created by implanting hydrogen atoms. Co-implanting helium and hydrogen atoms has the advantage that it allows the donor substrate to break more cleanly along the weakened zone, which is typically between 30×30 μm 2 This results in an underside roughness of the transferred semiconductor layer of the order of 50 or 60 Å RMS as measured by AFM, but also the appearance of the jagged edge phenomenon. The thicker the transferred semiconductor layer, the more pronounced this phenomenon becomes. Implanting only hydrogen atoms has the advantage of eliminating the jagged edge phenomenon, but on the other hand gives a greater roughness to the transferred semiconductor layer. 30×30 μm 2 The roughness measured by AFM is in this case of the order of 80 Å RMS. However, the process described below makes it possible to obtain a final surface of the first transferred semiconductor layer that is smooth enough to make it possible to form a second SOI substrate. As a result, implanting only hydrogen atoms is preferred to co-implanting helium and hydrogen atoms, in view of the advantages it offers in terms of limiting jagged edges.

[0034] Detachment along the weakened zone may be induced by mechanical action, the application of thermal energy, an optional combination, or any other suitable means.

[0035] According to the embodiment shown in Fig. 2, a first electrically insulating layer 2a is formed on the first donor substrate prior to forming a weakened zone in the first donor substrate by implanting atoms through the first electrically insulating layer 2a. The first donor substrate is bonded to the handle substrate 1 on its electrically insulating side such that said first electrically insulating layer 2a is transferred simultaneously with the first semiconductor layer 2b and is interposed between the handle substrate 1 and the first transferred semiconductor layer 2b. The first electrically insulating layer 2a is formed, for example, by oxidizing the front surface of the first donor substrate, thus, if the first donor substrate is a silicon substrate, the first electrically insulating layer 2a is a silicon oxide layer.

[0036] According to an alternative embodiment shown in Fig. 3, a first electrically insulating layer 2a is formed on the front side of the handle substrate 1 prior to bonding a first donor substrate to said handle substrate, such that said first electrically insulating layer 2a is interposed between said handle substrate 1 and the first transferred semiconductor layer 2b. The first electrically insulating layer 2a is for example formed by oxidizing the front side of the handle substrate 1, thus, if the handle substrate 1 is a silicon substrate, the first electrically insulating layer 2a is a silicon oxide layer.

[0037] The front surface of the lower SOI structure formed upon removal of the first donor substrate along the weakened zone has a roughness and defect density that is linked to the quality of the implantation of the atomic species in the first donor substrate when performing the first Smart-Cut™ process. As mentioned above, the roughness can be relatively large, on the order of 50 Å RMS to 80 Å RMS, depending on the implanted species.

[0038] During the second layer transfer to prepare the upper SOI structure, certain defect densities and surface roughness can lead to the formation of holes or defects at the moment of bonding the second donor substrate. As an example, a roughness of more than 5 Å RMS can lead to a defect size of 1 cm. 2 This results in a hole density of about several holes per unit area.

[0039] The holes can cause devices to malfunction that are to be made from an SOI substrate having said holes. Moreover, the holes are distributed non-uniformly across the substrate. This non-uniformity of defects causes a high variability in behavior between different devices obtained from the same substrate.

[0040] This results in devices fabricated on portions of the substrate with high hole density either not being operational or having high variability in behavior, which is unacceptable to manufacturers of microelectronic devices, especially photonic devices.

[0041] Moreover, the handle substrate 1 wafer and the first donor substrate wafer do not have edges that are perpendicular to the surface, but have a chamfer or "edge roll-off". The first donor substrate is therefore not bonded to the handle substrate over the entire surface of the substrate up to the edge of the substrate, but only up to the chamfer, and thus the transferred part of the donor substrate does not extend over the entire surface of the handle substrate. The peripheral ring is defined on the outside by the edge of the receiver substrate and on the inside by the edge of the transferred layer. For a 300 mm wafer, the peripheral ring CP typically has a width of between 0.7 mm and 1.5 mm with respect to the edge of the wafer.

[0042] In practice, as mentioned before, the rings often have an irregular shape (jagged edges) due to the transition zone where the bonding was not performed correctly. The transition zone represents a potential source of defect density, in particular parts of said zone can separate and be deposited on the surface of the SOI. During the second layer transfer to prepare the upper SOI structure, such surface finishing can further lead to the formation of a large number of holes or defects and to a width of the double ring, much larger than that of the ring resulting from the first layer transfer, of the order of 3-4 mm. Such a width is not acceptable, among other things, in the case of applications in photonics, which requires that it is possible to make chips up to 3 mm from the edge of the silicon wafer.

[0043] A process that allows the expected performance levels to be achieved is described below.

[0044] Surface treatment prior to second layer transfer The front surface of the first semiconductor layer is formed when the first donor substrate is detached along a weakened zone as a result of the Smart-Cut™ process. The invention relates to a process for treating said surface. The treatment process according to the invention aims not only to reduce the roughness and defect density of said surface, but also to reduce the width of the peripheral ring, thus improving the quality of the bonding of the second donor substrate.

[0045] The step of treating the free surface of the first semiconductor layer 2b and / or the second semiconductor layer according to the invention comprises the following steps, which are illustrated in the diagram of FIG. 4: (E1) rapid thermal annealing; (E2) Oxidation / deoxygenation sequence; (E3) Long thermal annealing, known by those skilled in the art as batch annealing; (E4) Chemical Mechanical Polishing This involves continuously executing

[0046] Alternatively, the long thermal annealing step (E3) can be replaced by a rapid thermal annealing step (E3').

[0047] What is meant by "rapid thermal annealing" is annealing for a period of a few seconds or tens of seconds in a controlled atmosphere. Such annealing is generally designated by the acronym RTA. Rapid thermal annealing (E1) is carried out at temperatures between 1100°C and 1250°C for 1s to 90s. Rapid thermal annealing (E1) is carried out in an atmosphere containing a mixture of argon and hydrogen or in an atmosphere of pure argon.

[0048] Rapid thermal annealing makes it possible to reinforce the bonding interface between the handle substrate and the transferred semiconductor layer. Rapid thermal annealing also makes it possible to smooth the surface of the transferred semiconductor layer by causing the atoms present at the surface to reorganize, and also makes it possible to restore the crystal lattice that may have been damaged by the implantation. However, it is not sufficient to achieve the level of roughness required to make it possible to bond a second donor substrate and then transfer the semiconductor layer of the second donor substrate to the first SOI.

[0049] The subsequent oxidation / deoxidation step (E2) comprises the following successive operations: Thermal oxidation operation (E2a) and Chemical deoxygenation (E2b) and It should be understood that the sequence includes:

[0050] The oxidation operation (E2a) may for example be carried out by heating the structure at a temperature between 800° C. and 1100° C. for a period of a few minutes to a few hours under an oxidizing atmosphere, for example of water vapor (wet oxidation) or only oxygen (dry oxidation). During this oxidation, both sides of the first SOI are oxidized. The deoxidation operation (E2b) may for example be carried out by exposing the front side of the structure to a hydrofluoric (HF) acid solution for a period of a few seconds to a few minutes in order to remove the oxide layer formed on the front side, without removing the oxide layer on the back side of the structure.

[0051] This oxidation / deoxidation step consumes the silicon surface by oxidation and subsequent removal. The consumption of the surface silicon makes it possible not only to adjust the thickness of the semiconductor layer, but also to remove defects on the surface of the transferred layer that appeared after the layer transfer by Smart-Cut™.

[0052] Long thermal annealing or batch annealing corresponds to thermal annealing for a period of the order of minutes to hours, typically more than 15 minutes, advantageously carried out in a furnace under controlled atmosphere. The use of a furnace makes it possible to process several substrates at the same time.

[0053] Thermal annealing (E3) is carried out in an inert atmosphere, for example in an atmosphere of pure or mixed hydrogen or argon, at a temperature between 1050° C. and 1250° C. for a period ranging from a few minutes to a few hours.

[0054] Thermal annealing (E3) makes it possible to smooth the surface of the transferred semiconductor layer and therefore to reduce its roughness.

[0055] The surface treatment process according to the invention finally comprises a final chemical-mechanical polishing step (E4).

[0056] In the process of chemical mechanical polishing or CMP, the surface to be polished is modified with the aid of a chemical agent, for example a suspension of colloidal silica particles in a mother liquor, and the modified surface is removed by mechanical abrasion. The rotation speed and pressure used during the CMP step (E4) are optimized to remove material from the surface of the transferred semiconductor layer or the second electrically insulating layer uniformly, but without degrading the finish of said surface, in particular without increasing the roughness of said surface.

[0057] In particular, this chemical mechanical polishing makes it possible to remove surface particles. In addition, insofar as this polishing is carried out to the edge of the substrate, it also makes it possible to gradually reduce the irregularities in the thickness of the first SOI up to the edge of the wafer in the ring of the first SOI, which allows the second bonding closer to the edge of the wafer. This reduces the width of the ring resulting from the second transfer by Smart Cut™.

[0058] Alternatively, a rapid thermal annealing (E3') is carried out at a temperature between 1100° C. and 1250° C. for a few seconds up to about 100 seconds in an atmosphere containing, for example, argon or hydrogen, either alone or in admixture.

[0059] Preparation of the upper SOI structure Referring to FIG. 5, a second upper semiconductor-on-insulator structure or SOI structure is formed on the lower SOI structure by a second transfer of a second monocrystalline semiconductor layer 3b originating from a second donor substrate onto the front side of the first semiconductor-on-insulator structure, with a second electrically insulating layer 3a at the interface between the first transferred semiconductor layer and the second donor substrate.

[0060] The second donor substrate is a monocrystalline semiconductor substrate, for example a monocrystalline silicon substrate. The second donor substrate takes the form of a circular wafer, typically having the same diameter as the handle substrate. According to one embodiment, the second layer transfer comprises: - forming weakened zones in a second donor substrate to define a second semiconductor layer 3b to be transferred; Bonding a second donor substrate to the front side of the semiconductor-on-insulator structure, a second electrically insulating layer 3a being at the interface between the front side of the semiconductor-on-insulator structure and the first donor substrate; removing the second donor substrate at the weakened zone to obtain a dual semiconductor-on-insulator structure as shown in FIG. The process is carried out according to a second Smart-Cut™ process, which includes:

[0061] As with the first donor substrate, the weakened zone of the second donor substrate can be created by co-implanting helium and hydrogen atoms into the second semiconductor layer of the second donor substrate. Alternatively, the weakened zone is created by implanting hydrogen atoms.

[0062] As an alternative to the Smart-Cut™ process, the second layer transfer can be performed by thinning the second donor substrate on the side of the second donor substrate opposite the side bonded to the second electrically insulating layer until the desired thickness for the second semiconductor layer 3b is obtained.

[0063] According to the embodiment shown in Fig. 6, a second electrically insulating layer 3a is formed on a second donor substrate, so that when the second semiconductor layer 3b is transferred, said second electrically insulating layer 3a is also transferred and inserted between the first semiconductor layer 2b and said second semiconductor layer 3b. The second electrically insulating layer 3a is prepared, for example, by oxidizing the second donor substrate, so that if the second donor substrate is a silicon substrate, the second electrically insulating layer 3a is a silicon oxide layer.

[0064] In embodiments in which the second layer transfer is performed according to a second Smart-Cut™ process, the second electrically insulating layer 3a is preferably formed in the second donor substrate prior to a weakened zone being formed in the second donor substrate by implanting atoms through the second electrically insulating layer 3a.

[0065] According to an alternative embodiment shown in Fig. 7, a second electrically insulating layer 3a is formed on the first semiconductor layer 2b such that, when the second semiconductor layer 3b is transferred, said second electrically insulating layer 3a is inserted between the first semiconductor layer 2b and the second semiconductor layer 3b. The second electrically insulating layer 3a is prepared, for example, by oxidizing the front surface of the first transferred semiconductor layer 2b, so that if the first donor substrate is a silicon substrate, the second electrically insulating layer 3a is a silicon oxide layer. The additional step of forming the second electrically insulating layer 3a is carried out after treating the free surface of the first semiconductor layer 2b. Alternatively, steps (E1), (E2) and (E3) of the process can be performed on the free surface of the first transferred semiconductor layer 2b before the step of forming the second electrically insulating layer 3a, and step (E4) can be performed, respectively, on the surface of the first transferred semiconductor layer 2b and on the surface of the second electrically insulating layer 3a, before and after the step of forming the second electrically insulating layer 3a.

[0066] The free surface of the second electrically insulating layer 3a can advantageously be cleaned once or several times prior to the second transfer of the second monocrystalline semiconductor layer 3b.

[0067] As an example, carrying out the surface treatment process according to the invention, in particular combining thermal smoothing and CMP steps, in combination with the use of an "ultra-flat" handle substrate, makes it possible to obtain SOI structures with a very low number of holes or even no holes and with a double ring width of less than 3 mm.

[0068] Optionally, a treatment of the free surface of the second semiconductor layer 3b may also be carried out in order to reduce defects in this layer and to smooth its surface in order to obtain the properties required for subsequent applications of said layer (fabrication of electronic components, epitaxy, etc.). These treatments are known to those skilled in the art and include, for example, rapid thermal annealing.

Claims

1. A process for fabricating a dual semiconductor-on-insulator structure comprising the following steps: Providing a first donor substrate and a handle substrate (1); - forming weakened zones in said first donor substrate to define a first semiconductor layer (2b) to be transferred; bonding the first donor substrate to the handle substrate (1), with a first electrically insulating layer (2a) at the interface between the handle substrate (1) and the first donor substrate, and detaching the first donor substrate at the weakened zone to obtain a semiconductor-on-insulator structure comprising, from back to front, the handle substrate (1), the first electrically insulating layer (2a) and the first transferred semiconductor layer (2b); - treating a free surface of the first transferred semiconductor layer (2b); Providing a second donor substrate for a second semiconductor layer (3b) to be transferred; transferring the second semiconductor layer (3b) onto the front side of the semiconductor-on-insulator structure, a second electrically insulating layer (3a) being at the interface between the first transferred semiconductor layer (2b) and the second donor substrate; Including, The step of treating the surface of the first transferred semiconductor layer (2b) comprises the following successive steps: (E1) rapid thermal annealing; and (E2) a sequence including thermal oxidation followed by deoxidation; (E3) a smoothing heat treatment at a temperature exceeding 1000° C. in a non-oxidizing atmosphere; (E4) Chemical mechanical polishing The process includes:

2. 2. Process according to claim 1, characterized in that said smoothing heat treatment step (E3) is a long thermal annealing carried out at a temperature between 1050° C. and 1250° C. for a period ranging from a few minutes to a few hours, in a pure or mixed hydrogen or argon atmosphere.

3. 2. The process according to claim 1, characterized in that the heat treatment step (E3) is rapid thermal annealing.

4. A process according to any one of claims 1 to 3, characterized in that the rapid thermal annealing step (E3) is carried out at a temperature between 1100 °C and 1250 °C for a period of a few seconds to about 100 seconds, in an atmosphere containing pure or mixed hydrogen or argon.

5. A process according to any one of claims 1 to 4, characterized in that the rapid thermal annealing step (E1) is carried out at a temperature between 1100 °C and 1250 °C for a period of a few seconds to about 100 seconds, in an atmosphere containing pure or mixed hydrogen or argon.

6. 6. The process according to claim 1, characterized in that the thermal oxidation operation of step (E2) is carried out at a temperature between 800° C. and 1100° C. in an atmosphere containing oxygen or water vapor, for a period ranging from a few minutes to a few hours.

7. The process according to any one of claims 1 to 6, characterized in that the deoxidation operation of step (E2) is carried out by exposing the surface to be treated to a hydrofluoric acid solution.

8. A process according to any one of the preceding claims, characterized in that the handle substrate (1) and each donor substrate are in the form of a wafer having a diameter of 300 mm.

9. Process according to any one of the preceding claims, characterized in that the weakened zone in the first donor substrate is formed by implanting hydrogen atoms.

10. The step of transferring the second semiconductor layer (3b) comprises: forming weakened zones in said second donor substrate to define a second semiconductor layer (3b) to be transferred; bonding the second donor substrate to the front side of the semiconductor-on-insulator structure, a second electrically insulating layer (3a) being at the interface between the front side of the semiconductor-on-insulator structure and the first donor substrate; detaching the second donor substrate at the weakened zone to obtain a double semiconductor-on-insulator structure comprising, from back to front, the handle substrate (1), the first electrically insulating layer (2a), the first transferred semiconductor layer (2b), the second electrically insulating layer (3a) and the second transferred semiconductor layer (3b); The process according to any one of claims 1 to 9, characterized in that it comprises

11. The process of claim 10, wherein the weakened zone in the second donor substrate is formed by implanting hydrogen atoms.

12. 12. The process according to any one of claims 1 to 11, characterized in that the second electrically insulating layer (3a) is formed by oxidizing the front surface of the first transferred semiconductor layer (2b) so that, when the second semiconductor layer (3b) is transferred, the first electrically insulating layer (3a) is inserted between the first semiconductor layer (2b) and the second semiconductor layer (3b), and the additional oxidation step is carried out after treating the free surface of the first semiconductor layer (2b).

13. The process according to any one of claims 1 to 11, characterized in that the second electrically insulating layer (3a) is formed by oxidizing a part of the second donor substrate, so that when the second semiconducting layer (3b) is transferred, the first electrically insulating layer (3a) is also transferred and is interposed between the first semiconducting layer (2b) and the second semiconducting layer (3b).

14. The process according to any one of claims 1 to 13, characterized in that the first electrically insulating layer (2a) is formed by oxidizing the front surface of the handle substrate (1) prior to bonding the first donor substrate to the handle substrate, such that the first electrically insulating layer (2a) is interposed between the handle substrate (1) and the first transferred semiconductor layer (2b).

15. 14. The process according to any one of claims 1 to 13, characterized in that the first electrically insulating layer (2a) is formed by oxidizing a part of the first donor substrate prior to bonding the first donor substrate with its oxidized side to the handle substrate (1), such that the first electrically insulating layer (2a) is interposed between the handle substrate (1) and the first transferred semiconductor layer (2b).

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