Electrostatic Discharge Protection System for Microdevices
Patent Information
- Application Number
- JP2024539249
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2022-02-17
- Publication Date
- 2025-03-07
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
【0037】 【0037】 本明細書で開示するディスプレイデバイス及びシステムの設計は、ESD損傷の低減をもたらし、それによりディスプレイシステムの発光効率及び全体的な性能を向上させる。したがって、マイクロレンズアレイを用いてディスプレイシステムを実装すると、従来のディスプレイを使用する場合と比べて、拡張現実(AR)及び仮想現実(VR)、ヘッド·アップ·ディスプレイ(HUD)、モバイル·デバイス·ディスプレイ、ウェアラブル·デバイス·ディスプレイ、高解像度プロジェクタ、及び自動車用ディスプレイのディスプレイ要件をよりよく満たすことができる。
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Figure 2025506084000001_ABST
Abstract
Description
[Technical field]
[0001] Technical Field The present disclosure relates generally to display devices and techniques, and more specifically to electrostatic discharge protection systems for microdevices. [Background technology]
[0002] background
[0002] Display technology is becoming increasingly important in today's commercial electronic devices. These display panels are widely used in stationary large screens such as liquid crystal display televisions (LCD TVs) and organic light emitting diode televisions (OLED TVs), as well as in portable electronic devices such as laptops, smartphones, tablets, and wearable electronic devices.
[0003]
[0003] Electrostatic discharge (ESD) is one of the most common threats to the reliability of electronic components. An ESD-related event occurs when a finite amount of charge is transferred from one object to another, such as from a human body to a micro device. This process leads to a very large current flowing through the micro device in a very short time. In fact, more than 35% of chip damage can be attributed to an ESD-related event. Common failures due to ESD include contact damage, current leakage, short circuits, gate oxide breakdown, and burnout. ESD failures are either unpredictable or not easy to diagnose after failures occur.
[0004]
[0004] Furthermore, designing on-chip ESD structures to protect integrated circuits from ESD stress is a high priority task in the semiconductor industry. With the continuous advances in metal-oxide semiconductor and other processing technologies, ESD-induced failures become more and more prominent. In fact, many semiconductor companies around the world are struggling to meet the increasingly stringent ESD protection requirements for various electronics applications, and it is certain that the availability of effective and robust ESD protection solutions will become an important and essential element for the prosperity and commercialization of the electronics industry.
[0005]
[0005] In addition, micro light emitting diode (LED) panels have been widely researched worldwide. However, micro LEDs lack ESD protection, which may lead to damage to the micro LED panels and limit their implementation and reliability. Summary of the Invention [Means for solving the problem]
[0006] overview
[0006] There is a need for improved display designs that help to ameliorate and address the shortcomings of conventional display systems, such as those discussed above. In particular, there is a need for display panels with improved stability and reliability that have better images.
[0007]
[0007] In some embodiments, an integrated circuit (IC) chip requires protection against ESD at all pins of the packaged device. The ESD clamp is ideally in a high impedance state with a tolerable capacitive load and is triggered only when an ESD pulse is detected, thereby protecting the input / output (I / O) circuitry. When an ESD pulse occurs on an IC pad, the protection device clamps most of the ESD current energy to the ground bus. The clamp device needs to be fully compatible with the I / O function.
[0008]
[0008] Various embodiments include a display panel with an integrated micro LED array. A display panel typically includes an array of pixel light sources (e.g., LEDs, OLEDs) electrically coupled to corresponding pixel drive circuits (e.g., FETs). The micro LED panel includes an IC backplane and a micro LED array electrically formed on the IC backplane.
[0009]
[0009] In some embodiments, the present disclosure provides an ESD protection system for micro devices, especially for micro LED panels, to solve the problem that micro LED panels are always damaged by external electrostatic discharge.
[0010]
[0010] To achieve the above objectives, some exemplary embodiments of the present disclosure provide an electrostatic discharge (ESD) protection system for a micro device, the system including: a pixel driving circuit electrically connected to at least one micro LED pixel for controlling the on or off of the micro LED pixel, the micro LED pixel being electrically connected to a second level voltage (Vcom); and a first ESD protection unit including a first ESD clamp and a second ESD clamp, the first ESD clamp being electrically connected to the first level voltage (Vdd) and the second level voltage (Vcom), and the second ESD clamp being electrically connected to a third level voltage (Vss) and the second level voltage (Vcom).
[0011] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the cathode of the micro LED pixel is connected to a second level voltage (Vcom).
[0012]
[0012] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the first level voltage (Vdd) is higher than the third level voltage (Vss), and the third level voltage (Vss) is higher than the second level voltage (Vcom).
[0013]
[0013] In some exemplary embodiments or any combination of exemplary embodiments of the micro device ESD protection system, the first level voltage (Vdd) is a positive voltage, the third level voltage (Vss) is zero, and the second level voltage (Vcom) is a negative voltage.
[0014] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the first ESD clamp is a power ESD clamp and the second ESD clamp is a power ESD clamp.
[0015]
[0015] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system of the micro device, the first ESD clamp includes a first MOS transistor, the gate of the first ESD protection unit is connected to the source of the first ESD protection unit and a second level voltage (Vcom), the drain of the first ESD protection unit is connected to a first level voltage (Vdd), and the first ESD protection unit has a parasitic on the first MOS transistor.
[0016]
[0016] In some exemplary embodiments or any combination of exemplary embodiments of the micro device ESD protection system, the second ESD clamp includes a second MOS transistor, the gate of the second ESD protection unit is connected to the source of the second ESD protection unit and a second level voltage (Vcom), the drain of the second ESD protection unit is connected to a third level voltage (Vss), and the second ESD protection unit has a parasitic on the second MOS transistor.
[0017] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the first MOS transistor is an NMOS and the second MOS transistor is an NMOS.
[0018] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the first ESD clamp or the second ESD clamp may include: a first type semiconductor substrate; a first type well region formed in a first type semiconductor substrate; a second type of well formed around the first type of well region; a second type deep well formed at the bottom of the second type well and at the bottom of the first type well region; a second type source formed in the first type well region; a second type drain formed in the first type well region; a first implanted region formed adjacent the second type drain; a gate formed on the first-type well region between the second-type source and the second-type drain and connected to the second-type source and the first implanted region; and a second implantation region formed beside the second type of well.
[0019]
[0019] In some exemplary embodiments or any combination of exemplary embodiments of the micro device ESD protection system, the first type is P type and the second type is N type, the first implantation region is a first P+ implantation region, and the second implantation region is a second P+ implantation region.
[0020]
[0020] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, in the first ESD clamp, the second type well and the second type drain are connected to a first level voltage (Vdd), the second implantation region is connected to a third level voltage (Vss), and the first implantation region, the second type source, and the gate are connected to a second level voltage (Vcom), and in the second ESD clamp, the second type well, the second type drain, and the second implantation region are connected to the third level voltage (Vss), and the first implantation region, the second type source, and the gate are connected to the second level voltage (Vcom).
[0021] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the first ESD protection unit is formed in a semiconductor substrate.
[0022]
[0022] In some exemplary embodiments or any combination of exemplary embodiments of the micro device ESD protection system, at least one micro LED pixel is a micro LED pixel array, and a pixel drive circuit controls the on or off of each of the micro LED pixels in the micro LED pixel array.
[0023] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, a first ESD protection unit is connected to each of the micro LED pixels.
[0024] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the micro pixel drive circuit is connected to a first level voltage (Vdd) and to the micro LED pixel.
[0025]
[0025] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the system further includes a second ESD protection unit, the second ESD protection unit connected to a first level voltage (Vdd) and a third level voltage (Vss).
[0026] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the first ESD protection unit and the second ESD protection unit are formed in a semiconductor substrate.
[0027]
[0027] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the second ESD protection unit includes a plurality of second ESD sub-clamps, a first end of each of the second ESD sub-clamps is connected to a first level voltage (Vdd) and to the pixel driving circuit, a second end of each of the second ESD sub-clamps is connected to a third level voltage (Vss), and the second ESD sub-clamps are connected in parallel with each other.
[0028] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the second ESD protection unit includes a power rail ESD clamp.
[0029]
[0029] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system of a micro device, the micro device is selected from a micro inorganic LED device or a micro organic LED device, and the micro LED pixel is selected from an inorganic micro LED or an organic micro LED.
[0030]
[0030] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the system further includes a third ESD protection unit, a first end of the third ESD protection unit connected to a first level voltage (Vdd) and a second end of the third ESD protection unit connected to a third level voltage (Vss).
[0031] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the third ESD protection unit is connected to the input / output circuitry.
[0032]
[0032] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system of the micro device, the third ESD protection unit includes at least two third ESD sub-clamps, which are connected in series with each other.
[0033]
[0033] In some exemplary embodiments or any combination of exemplary embodiments of the micro device ESD protection system, a first end of the micropixel driving circuit is connected to a fourth level voltage (Vdd'') and a second end of the micropixel driving circuit is connected to the microLED pixel.
[0034]
[0034] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the system further includes a fourth ESD protection unit, a first end of the fourth ESD protection unit is connected to a fourth level voltage (Vdd'') and a second end of the fourth ESD protection unit is connected to a third level voltage (Vss).
[0035] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the third level voltage (Vss) is lower than the fourth level voltage (Vdd'').
[0036] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the pixel drive circuit includes at least one switch.
[0037]
[0037] The display device and system designs disclosed herein provide reduced ESD damage, thereby improving the luminous efficiency and overall performance of the display system. Thus, implementing a display system with a microlens array can better meet the display requirements of augmented reality (AR) and virtual reality (VR), head-up displays (HUD), mobile device displays, wearable device displays, high-resolution projectors, and automotive displays compared to using traditional displays.
[0038]
[0038] It should be noted that the above-mentioned various embodiments can be combined with any other embodiment described herein. The features and advantages described herein are not all-inclusive, and many additional features and advantages will be apparent to those skilled in the art, especially when considering the drawings, the specification, and the claims. Furthermore, it should be noted that the language used in this specification is primarily selected for readability and educational purposes, and may not be selected to fully describe or define the scope of the subject matter of the present invention.
[0039] BRIEF DESCRIPTION OF THE DRAWINGS
[0039] In order to allow the present disclosure to be understood in more detail, a more specific description may be given by referring to the features of various embodiments, some of which are illustrated in the accompanying drawings. However, the accompanying drawings are merely illustrative of the relevant features of the present disclosure and therefore should not be considered as limiting, since the description may admit of other advantageous features.
[0040]
[0040] For convenience, "up" is used to mean away from the substrate of the light-emitting structure and "down" means toward the substrate, and other directional terms such as top, bottom, above, below, underneath, directly below, etc. should be interpreted accordingly. [Brief description of the drawings]
[0041] [Figure 1] FIG. 1 shows a schematic block diagram of an electrostatic discharge (ESD) protection system for a microdisplay, according to some embodiments. [Diagram 2]
[0042] 1 illustrates a circuit diagram of an ESD protection system for a microdisplay, according to some embodiments. [Diagram 3]
[0043] 1 illustrates a circuit diagram of an ESD protection system according to some embodiments. [Figure 4]
[0044] 1 illustrates a cross-sectional view of a first ESD protection clamp according to some embodiments. [Diagram 5]
[0045] 1 illustrates a cross-sectional view of a second ESD protection clamp according to some embodiments. [Figure 6]
[0046] 1 illustrates a circuit diagram of an ESD protection unit according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0042]
[0047] According to common practice, the various features illustrated in the drawings may not be drawn to scale. Thus, dimensions of the various features may be arbitrarily expanded or reduced for clarity. Moreover, some drawings may not show all components of a given system, method, or device. Finally, like reference numbers may be used throughout the specification and drawings to denote like features.
[0043] Detailed Description
[0048] Numerous details have been described herein to provide a thorough understanding of the exemplary embodiments illustrated in the accompanying drawings. However, some embodiments may be practiced without many of those specific details, and the claims are limited only by the features and aspects specifically recited in the claims. Moreover, well-known processes, components, and materials have not been described in exhaustive detail so as not to unnecessarily obscure aspects related to the embodiments described herein.
[0044]
[0049] In order to solve the problems in the related art as described above, in some embodiments of the present disclosure, an ESD protection system for a micro device is provided. Figure 1 shows a schematic block diagram of an electrostatic discharge (ESD) protection system for a micro display according to some embodiments. Figure 2 shows a circuit diagram of an ESD protection system for a micro display according to some embodiments.
[0045]
[0050] 1 and 2, the ESD protection system of the micro device includes a pixel driving circuit 01 and a first ESD protection unit 021. The pixel driving circuit 01 is electrically connected to at least one micro LED pixel 00 and controls the at least one micro LED pixel 00 to be turned on or off. Here, the micro LED pixel 00 is further electrically connected to a second level voltage 04 (Vcom). The first ESD protection unit 021 includes a first ESD clamp 0211 and a second ESD clamp 0212. The first ESD clamp 0211 is electrically connected to the first level voltage 03 (Vdd) and the second level voltage 04 (Vcom). The second ESD clamp 0212 is electrically connected to the third level voltage 05 (Vss) and the second level voltage 04 (Vcom). One end of the micropixel driving circuit 01 is connected to a fourth level voltage 07 (Vdd'') and another end of the micropixel driving circuit 01 is connected to the microLED pixel 00. In another embodiment, one end of the micropixel driving circuit 01 is connected to a first level voltage 03 (Vdd) and another end of the micropixel driving circuit 01 is connected to the microLED pixel 00.
[0046]
[0051] FIG. 3 shows a circuit diagram of an ESD protection system according to some embodiments. Referring to FIG. 3 and FIG. 1 and FIG. 2, the ESD protection system of FIG. 1 further includes a second ESD protection unit 022 and a third ESD protection unit 023. One end of the second ESD protection unit 022 is connected to the first level voltage 03 (Vdd), and the other end of the second ESD protection unit 022 is connected to the third level voltage 05 (Vss). Furthermore, one end of the third ESD protection unit 023 is connected to the first level voltage 03 (Vdd), and another end of the third ESD protection unit 023 is connected to the third level voltage 05 (Vss). Furthermore, the second ESD protection unit 022 includes at least two second ESD sub-clamps 0221 and 0222. These second ESD sub-clamps 0221 and 0222 are preferably connected in parallel with each other. Here, one end of each of the second ESD sub-clamps 0221 and 0222 is connected to a first level voltage 03 (Vdd), and the other end of each of the second ESD sub-clamps is connected to a third level voltage 05 (Vss).
[0047]
[0052] FIG. 6 shows a circuit diagram of an ESD protection unit according to some embodiments. As shown in FIG. 6, the second ESD sub-clamps 0221 and 0222 are formed by gate-grounded N-type metal oxide semiconductor (NMOS) ESD networks, which can be seen in FIG. 6. FIG. 6 is an exemplary diagram of a power pin ESD network consisting of gate-grounded n-channel metal oxide semiconductor field effect transistor (MOSFET) devices. In some embodiments, the structure 022L on the left side of FIG. 6 is the actual power clamp, and the structure 022R on the right side of FIG. 6 illustrates the principle of a power clamp ESD protection system. A gate-grounded N-type metal oxide semiconductor (NMOS) ESD network such as 022L is a network for complementary metal oxide semiconductor (CMOS) technology. Typically, it is an n-channel MOSFET with the MOSFET drain connected to the power pin 602 of V'DD, which also has its gate and source connected to the ground power rail 604. This circuit remains "off" in normal operation. When the signal pin 602 exceeds the MOSFET snapback voltage, the circuit discharges to the V'SS power rail. In some examples, the snapback voltage is the voltage applied to a transistor when avalanche breakdown or impact ionization in the transistor provides enough base current to turn the transistor on. When the voltage on the signal pin 602 falls below ground potential, the MOSFET drain biases the p-well or p-substrate region to achieve electrostatic protection purposes.
[0048]
[0053] In some embodiments, the second ESD protection unit 022, the third ESD protection unit 023, and the fourth ESD protection unit 024 are power rail ESD clamps, for which reference may be made to the description of FIG.
[0049]
[0054] 1-3, an input / output (IO) circuit 06 for receiving a signal from an outside circuit is formed beside the pixel driving circuit 01. A third ESD protection unit 023 for providing ESD protection to the IO circuit 06 is connected to the IO circuit 06. The IO circuit 06 may be formed around the pixel driving circuit 01 or around the micro LED pixel 00 in another embodiment. The third ESD protection unit 023 includes at least two third ESD sub-clamps, for example, third ESD sub-clamps 0231 and 0232, connected in series with each other. In some examples, the third ESD sub-clamp 0231 is a PMOS and the third ESD sub-clamp 0232 is an NMOS. One end of one third ESD sub-clamp 0231 is connected to the first level voltage 03 (Vdd), and the other end of the third ESD sub-clamp 0231 is connected to another third ESD sub-clamp 0232, which is connected to the third level voltage 05 (Vss). Furthermore, the gate and source of the third ESD sub-clamp 0231 are connected to the first level voltage 03 (Vdd), the drain of the third ESD sub-clamp 0231 is connected to the source of the third ESD sub-clamp 0232, and the gate and drain of the third ESD sub-clamp 0232 are connected to the third level voltage 05 (Vss). The IO circuit 06 is connected to the drain of the third ESD sub-clamp 0231 and the source of the third ESD sub-clamp 0232.
[0050]
[0055] In some embodiments, the first level voltage 03 (Vdd) is preferably higher than the second level voltage 04 (Vcom). The first level voltage 03 (Vdd) is higher than the fourth level voltage 07 (Vdd''). The third level voltage 05 (Vss) is higher than the second level voltage 04 (Vcom). And the first level voltage 03 (Vdd) is higher than the third level voltage 05 (Vss). The second level voltage 04 (Vcom) is a negative voltage that will be applied to the micro LED pixel 00 because the micro LED pixel 00 cannot be operated under high voltage values. In some embodiments, the first level voltage 03 (Vdd) is preferably a positive voltage, the fourth level voltage 07 (Vdd'') is a positive voltage, and the third level voltage 05 (Vss) is zero. For example, the voltage of Vdd can be 1V to 3V, the voltage of Vdd'' can be 1V to 2V, the voltage of Vss can be 0V, and the voltage of Vcom can be -5V to 0V.
[0051]
[0056] 2 and 3, in some embodiments, the ESD protection system 500 further includes a fourth ESD protection unit 024. One end of the fourth ESD protection unit 024 is connected to a fourth level voltage 07 (Vdd''), and the other end of the fourth ESD protection unit 024 is connected to a third level voltage 05 (Vss).
[0052]
[0057] 3 and 2, here the first ESD clamp 0211 is a negative power ESD clamp. The first ESD clamp 0211 includes a first MOS transistor. Furthermore, the first ESD clamp 0211 has a parasitic on the first MOS transistor. The gate of the first ESD clamp 0211 is connected to the drain of the first ESD clamp 0211 and the second level voltage 04 (Vcom). The source of the first ESD clamp 0211 is connected to the first level voltage 03 (Vdd). A first parasitic diode is parasitic on the first MOS transistor. In some embodiments, when the second level voltage 04 (Vcom) is a negative voltage, the first MOS transistor is preferably an NMOS. Here, the cathode of the micro LED pixel 00 is connected to the second level voltage 04 (Vcom). Furthermore, the second ESD clamp 0212 is a negative power ESD clamp. The second ESD clamp 0212 includes a second MOS transistor, and further, the second ESD clamp 0212 has a parasitic on the second MOS transistor. The gate of the second ESD clamp 0212 is connected to the drain of the second ESD clamp 0212 and the second level voltage 04 (Vcom). The source of the second ESD clamp 0212 is connected to the third level voltage 05 (Vss). Further, the second ESD clamp 0212 has a parasitic on the second MOS transistor. In some embodiments, when the second level voltage 04 (Vcom) is a negative voltage, the second MOS transistor is preferably an NMOS.
[0053]
[0058] Referring to Fig. 3, the pixel driving circuit 01 includes at least one switch, for example, switches 011, 012, and 013. The switches 011, 012, and / or 013 are preferably formed by transistors. The switches 011, 012, and 013 are connected in series to realize three levels of controlling the micro LED pixel on or off, so as to control the light emission intensity and light emission time. For example, the switches 011, 012, and 013 are connected in series to respectively control the current of the micro pixel driving circuit 01 on or off, and to control the PWM signal from the outer circuit on or off, and to control the scanning signal from the outer circuit on or off.
[0054]
[0059] In this embodiment, the micro LED pixel 00 shown in FIG. 1 and FIG. 2 can be replaced with a micro LED pixel array, and the pixel driving circuit 01 in FIG. 1 and FIG. 2 controls the on or off of each of the micro LED pixels in the micro LED pixel array. A first ESD clamp 0211 is preferably connected to each micro LED pixel 00. In another embodiment, the first ESD clamp 0211 may include at least two first ESD sub-clamps, each of which is connected to the second level voltage 04 (Vcom) and the first level voltage 03 (Vdd), respectively. The second ESD clamp 0212 may include at least two second ESD sub-clamps, each of which is connected to the second level voltage 04 (Vcom) and the third level voltage 05 (Vss), respectively.
[0055]
[0060] In some embodiments, the first ESD protection clamp 0211, the second ESD protection clamp 0212, the second ESD protection unit 022, the third ESD protection unit 023, and the fourth ESD protection unit 024 are all formed in one semiconductor substrate. In some embodiments, the first ESD protection clamp 0211, the second ESD protection clamp 0212, the second ESD protection unit 022, the third ESD protection unit 023, and the fourth ESD protection unit 024 cannot be formed in the same semiconductor substrate.
[0056]
[0061] 4 and 3, FIG. 4 shows a cross-sectional view of a first ESD protection clamp 0211 according to some embodiments. The ESD protection clamp is an ESD protection unit. The semiconductor substrate 400 can be a first type semiconductor substrate, such as a silicon substrate, as an IC backside. In some embodiments, the first ESD clamp 0211 includes a first type well region 403, a second type well 401, a second type deep well 402, a second type drain 404, a second type source 405, a first implanted region 406, a gate 408, and a second implanted region 407. Furthermore, the first type well region 403 is formed in the first type semiconductor substrate 400. The second type well 401 is formed around the first type well region 403. The second type deep well 402 is formed at the bottom of the second type well 401 and the bottom of the first type well region 403. A second-type drain 404 is formed in the first-type well region 403. A second-type source 405 is formed in the first-type well region 403. A first implanted region 406 is formed beside the second-type source 405. A gate 408 is formed on the first-type well region 403 between the second-type drain 404 and the second-type source 405, and is connected to the second-type source 405 and the first implanted region 406. A second implanted region 407 is formed beside the second-type shallow well 401.
[0057]
[0062] In some examples, the first type is P-type and the second type is N-type, but this is not limited to the scope of the present disclosure. As shown in FIG. 4, in some embodiments, an N-deep well 402 is formed in a P-type substrate 400, and an N-well 401 is formed on top of and around the N-deep well 402, thereby forming a P-type well region 403 surrounded by the N-well 401. The N-deep well 402 is formed at the bottom of the N-well 401 and at the bottom of the P-type well region 403. An N+ drain 404 is formed in the P-type well region 403, and an N+ source 405 is formed in the P-type well region 403. A gate 408 is formed on the P-type well region 403 between the N+ drain 404 and the N+ source 405. The gate 408 is connected to the N+ source 405 and the first P+ implanted region 406. A first P+ implanted region 406 is formed in the P-type well region 403 and is adjacent to the N+ source 405. A second P+ implanted region 407 is formed beside or around the N-well 401.
[0058]
[0063] In the first ESD clamp 0211, the N+ drain 404, N-well 401 are connected to a first level voltage 03 (Vdd), e.g., Vdd03 in FIG. 3 and FIG. 4. The second P+ implanted region 407 is connected to a third level voltage 05 (Vss), e.g., Vss05 in FIG. 3 and FIG. 4. The N+ source 405, the first P+ implanted region 406, and the gate 408 are connected to a second level voltage 04 (Vcom), e.g., Vcom04 in FIG. 3 and FIG. 4. In some embodiments, the second P+ implanted region 407 is connected to Vss as ground. In some embodiments, the gate 408 can be a gate structure including several layers of materials, such as dielectric layers, spacers, etc. The gate 408 is a conventional gate structure, which is understood by those skilled in the art and will not be described herein.
[0059]
[0064] 5 and 3, FIG. 5 shows a cross-sectional view of a second ESD protection clamp 0212 according to some embodiments. The ESD protection clamp is an ESD protection unit. The second ESD protection clamp 0212 is further formed in the semiconductor substrate 500. In some embodiments, the second ESD protection clamp 0212 includes a first type well region 503, a second type well 501, a second type deep well 502, a second type source 505, a second type drain 504, a first implanted region 506, a gate 508, and a second implanted region 507. Furthermore, the first type well region 503 is formed in the first type semiconductor substrate 500. The second type well 501 is formed around the first type well region 503. The second type deep well 502 is formed at the bottom of the second type well 501 and at the bottom of the first type well region 503. A second-type source 505 is formed in the first-type well region 503. A second-type drain 504 is formed in the first-type well region 503. A first implanted region 506 is formed beside the second-type source 505. A gate 508 is formed on the first-type well region 503 between the second-type source 505 and the second-type drain 504 and is connected to the second-type source 505 and the first implanted region 506. A second implanted region 507 is formed beside the second-type well 501.
[0060]
[0065] In some examples, the first type is P-type and the second type is N-type, but this is not limited to the scope of the present disclosure. As shown in FIG. 5, in some embodiments, an N-deep well 502 is formed in a P-type substrate 500, an N-well 501 is formed on and around the top of the N-deep well 502, and a P-well region 503 is surrounded by the N-well 501 and the N-deep well 502. The N-well 501 is formed around the P-well region 503. The N-deep well 502 is formed at the bottom of the N-well 501 and the bottom of the P-type well region 503. An N+ implanted region 504 as an N+ drain is formed in the P-well region 503, and an N+ implanted region 505 as an N+ source is formed in the P-type well region 503. A gate 508 is formed on the P-well region 503 between the N+ drain 504 and the N+ source 505. A gate 508 is connected to the N+ source 505 and to a first P+ implanted region 506. The first P+ implanted region 506 is formed in the P-type well region 503 and is adjacent to the N+ source 505. A second P+ implanted region 507 is formed beside or around the N-well 501.
[0061]
[0066] In the second ESD clamp 0212, the N+ implanted region 504, the N-well 501, and the second P+ implanted region 507 are connected to a third level voltage (Vss), e.g., Vss05 in FIG. 3 and FIG. 5. In some embodiments, the N+ implanted region 505, the first P+ implanted region 506, and the gate 508 are connected to a second level voltage (Vcom), e.g., Vcom04 in FIG. 3 and FIG. 5. In some examples, the second P+ implanted region 507 is connected to Vss as ground, e.g., Vss05 in FIG. 3 and FIG. 5. In some embodiments, the gate 508 can be a gate structure including several layers of materials, such as dielectric layers, spacers, etc. The gate 508 is a conventional gate structure, which is understood by those skilled in the art and will not be described herein.
[0062]
[0067] In some embodiments, the micro device with one or more ESD protection units, such as shown in FIG. 3, is selected from one of a micro-inorganic LED device and / or a micro-organic LED device. In some embodiments, the micro-LED pixel 00 is selected from an inorganic micro-LED or an organic micro-LED. For example, the micro device may be a micro-display panel. The micro-LED display panel includes a micro-LED array forming a pixel array, such as a 640*480 pixel array. In some embodiments, the length of the micro-LED display panel may not exceed 100, 200, 300, 400, or 500 microns, and the width of the micro-LED display panel may not exceed 100, 200, 300, 400, or 500 microns. In some embodiments, the length of the micro-LED display panel may not exceed 1 cm, and the width of the micro-LED display panel may not exceed 1 cm. In some embodiments, the length of the micro-LED display panel may not exceed 2 cm, and the width of the micro-LED display panel may not exceed 2 cm. In some embodiments, the length of the micro LED display panel cannot exceed 10 cm, and the width of the micro LED display panel cannot exceed 10 cm. In some embodiments, the length of the micro LED display panel cannot exceed 20 cm, and the width of the micro LED display panel cannot exceed 20 cm. The micro LED display panel also includes an IC backside. The micro LED display panel includes a micro LED array including a plurality of inorganic micro LEDs for showing a display image. The micro LED array is electrically connected and coupled to the IC backside. The first ESD protection clamp 0211, the second ESD protection clamp 0212, the second ESD protection unit 022, the third ESD protection unit 023, the fourth ESD protection unit 024, and the pixel driving circuit 01 are formed in the IC backside (semiconductor substrate 400). In some embodiments, the ESD protection unit is part of the IC circuit for protecting the IC circuit under electrostatic discharge conditions.The ESD protection unit can prevent current leakage from the IC circuit inside the back of the IC.
[0063]
[0068] Here, the micro LED can be selected from inorganic LED or organic LED. On the back of the IC, the micro LED array is electrically connected to an electrode connection area, and a signal line area is formed around the electrode connection area. The back of the IC receives a signal such as image data from the outside through the signal line, and thereby controls the corresponding micro LED to emit light. The back of the IC generally uses an 8-bit digital-to-analog converter (DAC). The 8-bit DAC has 256 display levels, each level corresponding to one gray level, that is, the 8-bit DAC can provide 256 different gray levels. Any level among the 256 gray levels can be applied to the micro LED, so that a gray level ranging from 0 to 255 can be displayed by one pixel. Optionally, the luminance value of the micro LED can be controlled by the voltage amplitude or current amplitude of the signal obtained by the back of the IC, and the gray level can be indicated by the time interval, for example, the pulse width, of the signal.
[0064]
[0069] Those skilled in the art will appreciate that the microdisplay panel is not limited to the structures described above and may include more or fewer components than those shown, or some components may be combined, or different components may be utilized.
[0065]
[0070] It is understood by those skilled in the art that all or some of the steps for implementing the above-mentioned embodiments may be implemented by hardware, or may be implemented by a program that instructs related hardware. The program may be stored in a flash memory, a conventional computer device, a central processing module, a coordinating module, etc.
[0066]
[0071] The above description is merely an embodiment of the present disclosure, and the present disclosure is not limited to those embodiments. Any modifications, equivalent replacements, and improvements made without departing from the concept and principle of the present disclosure shall fall within the protection scope of the present disclosure.
[0067]
[0072] Further embodiments include various subsets of the above embodiments, including combinations or rearrangements of the embodiments as shown in FIGS. 1-6 into various other embodiments.
[0068]
[0073] Although the detailed description includes many details, they should not be construed as limiting the scope of the invention, but merely as describing different examples and aspects of the invention. It should be understood that the scope of the invention includes other embodiments not discussed in detail above. For example, the approach described above can also be applied to the integration of functional devices other than LEDs and OLEDs with control circuits other than pixel driving circuits. Examples of devices other than LEDs include vertical cavity surface emitting lasers (VCSELs), photodetectors, microelectromechanical systems (MEMS), silicon photonic device, power electronic devices, and distributed feedback lasers (DFBs). Examples of other control circuits include current drivers, voltage drivers, transimpedance amplifiers, and logic circuits.
[0069]
[0074] The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the embodiments described herein and variations thereof. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the subject matter disclosed herein. Thus, the present disclosure is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein.
[0070]
[0075] Features of the present invention may be implemented in, using, or with the aid of a computer program product, such as a storage medium or computer-readable storage medium having instructions stored therein that can be used to program a processing system to perform any of the features presented herein. Storage media include, but are not limited to, high-speed random access memories, such as DRAM, SRAM, DDR, RAM, or other random access solid-state memory devices, and may also include non-volatile memories, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid-state storage devices. Memory optionally includes one or more storage devices located remotely from the CPU. The memory, or alternatively, a non-volatile memory device within the memory, includes a non-transitory computer-readable storage medium.
[0071]
[0076] Stored on any machine-readable medium, features of the present invention may be embodied in software and / or firmware for controlling the hardware of a processing system and for enabling the processing system to utilize the results of the present invention and interact with other mechanisms. Such software or firmware may include, but is not limited to, application code, device drivers, operating systems, and execution environments / containers.
[0072]
[0077] It will be understood that although terms such as "first" and "second" may be used herein to describe various elements or steps, these elements or steps are not to be limited by these terms, but are used only to distinguish one element or step from another.
[0073]
[0078] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the scope of the claims. When used in the description of the embodiments and in the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly dictates otherwise. As used herein, the term "and / or" is understood to refer to and include any and all possible combinations of one or more of the associated listed items. As used herein, the terms "comprises" and / or "comprising" are further understood to specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.
[0074]
[0079] As used herein, the term "if" may be interpreted to mean "when" or "as soon as" or "in response to determining" or "in accordance with a determination that" or "in response to detecting" the stated condition precedent is true, depending on the context. Similarly, the phrases "determined (that the stated condition precedent is true)" or "if (the stated condition precedent is true)" or "when (the stated condition precedent is true)" may be interpreted to mean "upon determining" or "in response to determining" or "in accordance with a determination that" or "upon detecting" or "in response to detecting" the stated condition precedent is true, depending on the context.
[0075]
[0080] The foregoing description has been described with reference to specific embodiments for explanatory purposes. However, the above illustrative discussion is not intended to be exhaustive or to limit the scope of the claims to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments have been chosen and described to best explain the principles of operation and practical applications, thereby enabling others skilled in the art to best utilize the invention and various embodiments.
Claims
1. 1. An electrostatic discharge (ESD) protection system for a micro device, comprising: a pixel drive circuit electrically connected to at least one micro LED pixel for controlling the on or off of the micro LED pixel, the micro LED pixel being electrically connected to a second level voltage (Vcom); a first ESD protection unit including a first ESD clamp and a second ESD clamp, the first ESD clamp being electrically connected to a first level voltage (Vdd) and the second level voltage (Vcom), and the second ESD clamp being electrically connected to a third level voltage (Vss) and the second level voltage (Vcom).
2. 10. The micro device ESD protection system of claim 1, wherein the cathode of the micro LED pixel is connected to the second level voltage (Vcom).
3. 2. The micro device ESD protection system of claim 1, wherein the first level voltage (Vdd) is greater than the third level voltage (Vss), and the third level voltage (Vss) is greater than the second level voltage (Vcom).
4. 4. The micro device ESD protection system of claim 3, wherein the first level voltage (Vdd) is a positive voltage, the third level voltage (Vss) is zero, and the second level voltage (Vcom) is a negative voltage.
5. 2. The micro device ESD protection system of claim 1, wherein the first ESD clamp is a power ESD clamp and the second ESD clamp is a power ESD clamp.
6. 2. The micro device ESD protection system of claim 1, wherein the first ESD clamp includes a first MOS transistor, a gate of the first ESD protection unit is connected to a source of the first ESD protection unit and to the second level of voltage (Vcom), a drain of the first ESD protection unit is connected to the first level of voltage (Vdd), and the first ESD protection unit has a parasitic on the first MOS transistor.
7. 7. The ESD protection system of claim 6, wherein the second ESD clamp includes a second MOS transistor, a gate of the second ESD protection unit is connected to a source of the second ESD protection unit and to the second level of voltage (Vcom), a drain of the second ESD protection unit is connected to the third level of voltage (Vss), and the second ESD protection unit is parasitic on the second MOS transistor.
8. 8. The micro device ESD protection system of claim 7, wherein the first MOS transistor is an NMOS and the second MOS transistor is an NMOS.
9. The first ESD clamp or the second ESD clamp comprises: a first type semiconductor substrate; a first type well region formed in the first type semiconductor substrate; a second type well formed around the first type well region; and a second-type deep well formed at a bottom of the second-type well and at a bottom of the first-type well region; a second type source formed in the first type well region; a second type drain formed in the first type well region; a first implanted region formed adjacent said second type drain; a gate formed on the first-type well region between the second-type source and the second-type drain, the gate being connected to the second-type source and the first implanted region; a second implanted region formed beside said second type well.
10. 10. The micro device ESD protection system of claim 9, wherein the first type is P-type and the second type is N-type, the first implanted region is a first P+ implanted region, and the second implanted region is a second P+ implanted region.
11. In the first ESD clamp, the second type well and the second type drain are connected to the first level voltage (Vdd), the second implanted region is connected to the third level voltage (Vss), and the first implanted region, the second type source, and the gate are connected to the second level voltage (Vcom); 10. The micro device ESD protection system of claim 9, wherein in the second ESD clamp, the second type well, the second type drain, and the second implanted region are connected to the third level voltage (Vss), and the first implanted region, the second type source, and the gate are connected to the second level voltage (Vcom).
12. The micro device ESD protection system of claim 1 , wherein the first ESD protection unit is formed in a semiconductor substrate.
13. 2. The micro device ESD protection system of claim 1, wherein the at least one micro LED pixel is a micro LED pixel array, and the pixel drive circuit controls the on or off of each of the micro LED pixels in the micro LED pixel array.
14. 14. The micro device ESD protection system of claim 13, wherein the first ESD protection unit is connected to each of the micro LED pixels.
15. 2. The micro device ESD protection system of claim 1, wherein the micro pixel drive circuit is connected to the first level voltage (Vdd) and to the micro LED pixel.
16. 2. The ESD protection system of claim 1, wherein the system further comprises a second ESD protection unit, the second ESD protection unit being connected to the first level voltage (Vdd) and the third level voltage (Vss).
17. 20. The micro device ESD protection system of claim 16, wherein the first ESD protection unit and the second ESD protection unit are formed in a semiconductor substrate.
18. 17. The ESD protection system of claim 16, wherein the second ESD protection unit includes a plurality of second ESD sub-clamps, a first end of each of the second ESD sub-clamps is connected to the first level of voltage (Vdd) and to the pixel drive circuit, a second end of each of the second ESD sub-clamps is connected to the third level of voltage (Vss), and the second ESD sub-clamps are connected in parallel with each other.
19. 20. The micro device ESD protection system of claim 16, wherein the second ESD protection unit comprises a power rail ESD clamp.
20. 10. The micro device ESD protection system of claim 1, wherein the micro device is selected from a micro inorganic LED device or a micro organic LED device, and the micro LED pixel is selected from an inorganic micro LED or an organic micro LED.
21. 2. The ESD protection system of claim 1, wherein the system further comprises a third ESD protection unit, a first end of the third ESD protection unit being connected to the first level voltage (Vdd) and a second end of the third ESD protection unit being connected to the third level voltage (Vss).
22. 22. The micro device ESD protection system of claim 21, wherein the third ESD protection unit is connected to an input / output circuit.
23. 22. The ESD protection system of claim 21, wherein the third ESD protection unit includes at least two third ESD sub-clamps, the third ESD sub-clamps being connected in series with each other.
24. 2. The micro device ESD protection system of claim 1, wherein a first end of the micro pixel driving circuit is connected to a fourth level voltage (Vdd'') and a second end of the micro pixel driving circuit is connected to the micro LED pixel.
25. 25. The ESD protection system of claim 24, wherein the system further includes a fourth ESD protection unit, a first end of the fourth ESD protection unit being connected to a fourth level voltage (Vdd'') and a second end of the fourth ESD protection unit being connected to a third level voltage (Vss).
26. 26. The micro device ESD protection system of claim 25, wherein the third level voltage (Vss) is lower than the fourth level voltage (Vdd'').
27. The micro device ESD protection system of claim 1 , wherein the pixel drive circuit includes at least one switch.