Electrostatic Discharge Protection System for Microdevices
Patent Information
- Application Number
- JP2024539416
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2022-02-17
- Publication Date
- 2025-03-07
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
【0038】 【0038】 本明細書で開示するディスプレイデバイス及びシステムの設計は、ESD損傷の低減をもたらし、それによりディスプレイシステムの発光効率及び全体的な性能を向上させる。したがって、マイクロレンズアレイを用いてディスプレイシステムを実装すると、従来のディスプレイを使用する場合と比べて、拡張現実(AR)及び仮想現実(VR)、ヘッドアップディスプレイ(HUD)、モバイルデバイスディスプレイ、ウェアラブルデバイスディスプレイ、高解像度プロジェクタ及び自動車用ディスプレイのディスプレイ要件をよりよく満たすことができる。
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Figure 2025506087000001_ABST
Abstract
Description
[Technical field]
[0001] Technical Field The present disclosure relates generally to display devices and techniques, and more specifically to ESD protection systems for micro devices. [Background technology]
[0002] background
[0002] Display technology is becoming more and more important in today's commercial electronic devices. These display panels are widely used in stationary large screens such as liquid crystal display televisions (LCD TVs) and organic light emitting diode televisions (OLED TVs), as well as portable electronic devices such as laptops, smartphones, tablets, and wearable electronic devices.
[0003]
[0003] Electrostatic discharge (ESD) is one of the most common threats to the reliability of electronic components. An ESD-related event occurs when a finite amount of charge is transferred from one object to another, such as from a human body to a micro device. This process leads to a very large current flowing through the micro device in a very short time. In fact, more than 35% of chip damage can be attributed to an ESD-related event. Common failures due to ESD include contact damage, current leakage, short circuits, gate oxide breakage and burnout. ESD failures are not predictable or easy to diagnose after failures occur.
[0004]
[0004] Furthermore, designing on-chip ESD structures to protect integrated circuits from ESD stress is a high priority in the semiconductor industry. With the continuous advances in metal-oxide semiconductor and other processing technologies, ESD-induced failures are becoming more and more prominent. In fact, many semiconductor companies around the world are struggling to meet the increasingly stringent ESD protection requirements for various electronics applications, and it is certain that the availability of effective and robust ESD protection solutions will become an important and essential element for the prosperity and commercialization of the electronics industry.
[0005]
[0005] In addition, micro light emitting diode (LED) panels have been widely researched worldwide. However, micro LEDs lack ESD protection, which may lead to damage to the micro LED panels and also limit their implementation and reliability. Summary of the Invention [Means for solving the problem]
[0006] overview
[0006] There is a need for improved display designs that help to ameliorate and address the shortcomings of conventional display systems, such as those discussed above. In particular, there is a need for display panels with improved stability and reliability that have better images.
[0007]
[0007] In some embodiments, an integrated circuit (IC) chip requires protection against ESD at all pins of the packaged device. The ESD clamp is ideally in a high impedance state with a tolerable capacitive load and is triggered only when an ESD pulse is detected, thereby protecting the input / output (I / O) circuitry. When an ESD pulse occurs on an IC pad, the protection device clamps most of the ESD current energy to the ground bus. The clamp device needs to be fully compatible with the I / O function.
[0008]
[0008] Various embodiments include a display panel with an integrated micro LED array. A display panel typically includes an array of pixel light sources (e.g., LEDs, OLEDs) electrically coupled to corresponding pixel drive circuitry (e.g., FETs). A micro LED panel includes an IC backplane and a micro LED array electrically formed on the IC backplane.
[0009]
[0009] In some embodiments, the present disclosure provides an electrostatic discharge (ESD) protection system for micro devices, particularly micro LED panels, to solve the problem that micro LED panels are constantly damaged by external electrostatic discharge.
[0010]
[0010] To achieve the above objectives, in one aspect, the present disclosure provides an ESD protection system for a micro device, the system including a pixel driving circuit electrically connected to at least one micro LED pixel, the pixel driving circuit for controlling the micro LED pixel to be on or off, and a first ESD protection unit electrically connected to the micro LED pixel.
[0011] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the micro LED pixel is connected to a second level voltage (Vcom).
[0012] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the cathode of the micro LED pixel is connected to a second level voltage (Vcom).
[0013]
[0013] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the first ESD protection unit is connected to a third level voltage (Vss) and a second level voltage (Vcom).
[0014] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the third level voltage (Vss) is higher than the second level voltage (Vcom).
[0015]
[0015] In some exemplary embodiments or any combination of exemplary embodiments of the micro device ESD protection system, the third level voltage (Vss) is zero and the second level voltage (Vcom) is a negative voltage.
[0016] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the first ESD protection unit includes a power ESD clamp.
[0017]
[0017] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the first ESD protection unit includes a MOS transistor, the gate of the first ESD protection unit is connected to the source of the first ESD protection unit and to a second level voltage (Vcom), the drain of the first ESD protection unit is connected to a third level voltage (Vss), and the first ESD protection unit is parasitic on the MOS transistor.
[0018] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the MOS transistor is an NMOS.
[0019]
[0019] In some exemplary embodiments or any combination of exemplary embodiments of the micro device ESD protection system, the first ESD protection unit includes a P-type semiconductor substrate, a P-well region formed in the P-type semiconductor substrate, an N-well formed around the P-well region, a deep N-well formed at a bottom of the N-well and at a bottom of the P-well region, an N+ drain formed in the P-well region, an N+ source formed in the P-well region, a first P+ implanted region in the P-well region formed next to the N+ source, a gate formed on the P-well region between the N+ source and the N+ drain and connected to the N+ source and the first P+ implanted region, and a second P+ implanted region formed next to the N-well in the P-type semiconductor substrate.
[0020]
[0020] In some exemplary embodiments or any combination of exemplary embodiments of the micro device ESD protection system, the N well, the N+ drain and the second P+ implanted region are connected to a third level voltage (Vss), and the first P+ implanted region, the N+ source and the gate are connected to a second level voltage (Vcom).
[0021]
[0021] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, at least one micro LED pixel is a micro LED pixel array, and a pixel drive circuit controls the on or off of each of the micro LED pixels in the micro LED pixel array.
[0022] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, a first ESD protection unit is connected to each of the micro LED pixels.
[0023] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the micropixel driving circuit is connected to a first level voltage (Vdd) and to the microLED pixel.
[0024]
[0024] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the system further includes a second ESD protection unit, the second ESD protection unit connected to a first level voltage (Vdd) and a third level voltage (Vss).
[0025]
[0025] In some exemplary embodiments or any combination of exemplary embodiments of the micro device ESD protection system, the second ESD protection unit includes a plurality of second ESD sub-clamps, a first end of each of the second ESD sub-clamps is connected to a first level voltage (Vdd) and to the pixel driving circuit, a second end of each of the second ESD sub-clamps is connected to a third level voltage (Vss), and the second ESD sub-clamps are connected in parallel with each other.
[0026]
[0026] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the first level voltage (Vdd) is higher than the second level voltage (Vcom), the third level voltage (Vss) is higher than the second level voltage (Vcom), and the first level voltage (Vdd) is higher than the third level voltage (Vss).
[0027]
[0027] In some exemplary embodiments or any combination of exemplary embodiments of the micro device ESD protection system, the second level voltage (Vcom) is a negative voltage, the first level voltage (Vdd) is a positive voltage, and the third level voltage (Vss) is zero.
[0028] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the second ESD protection unit includes a power rail ESD clamp.
[0029] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the first ESD protection unit and the second ESD protection unit are formed in a semiconductor substrate.
[0030]
[0030] In some exemplary embodiments or any combination of exemplary embodiments of the micro device ESD protection system, the micro device is selected from one of a micro inorganic LED device and a micro organic LED device, and the micro LED pixel is selected from an inorganic micro LED or an organic micro LED.
[0031]
[0031] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the system further includes a third ESD protection unit, a first end of the third ESD protection unit is connected to a first level voltage (Vdd) and a second end of the third ESD protection unit is connected to a third level voltage (Vss).
[0032] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the third ESD protection unit is connected to an input / output (IO) circuit.
[0033]
[0033] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system of the micro device, the third ESD protection unit includes at least two third ESD sub-clamps, and the third ESD sub-clamps are connected in series with each other.
[0034]
[0034] In some exemplary embodiments or any combination of exemplary embodiments of the micro device ESD protection system, a first end of the micro pixel driving circuit is connected to a fourth level voltage (Vdd'') and a second end of the micro pixel driving circuit is connected to the micro LED pixel.
[0035]
[0035] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the system further includes a fourth ESD protection unit, a first end of the fourth ESD protection unit is connected to a fourth level voltage (Vdd'') and a second end of the fourth ESD protection unit is connected to a third level voltage (Vss).
[0036] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the third level voltage (Vss) is lower than the fourth level voltage (Vdd'').
[0037] In some exemplary embodiments or any combination of exemplary embodiments of the ESD protection system for a micro device, the pixel drive circuit includes at least one switch.
[0038]
[0038] The display device and system designs disclosed herein provide reduced ESD damage, thereby improving the luminous efficiency and overall performance of the display system. Thus, implementing a display system using microlens arrays can better meet the display requirements of augmented reality (AR) and virtual reality (VR), head-up displays (HUD), mobile device displays, wearable device displays, high-resolution projectors, and automotive displays compared to using traditional displays.
[0039]
[0039] It should be noted that the various embodiments described above can be combined with any other embodiment described herein. The features and advantages described herein are not all-inclusive, and many additional features and advantages will be apparent to those skilled in the art, especially in view of the drawings, the specification, and the claims. Furthermore, it should be noted that the language used herein is primarily selected for readability and educational purposes, and may not be selected to fully describe or define the scope of the subject matter of the present invention.
[0040] BRIEF DESCRIPTION OF THE DRAWINGS
[0040] In order to make the present disclosure more fully understandable, a more specific description may be given by referring to the features of various embodiments, some of which are illustrated in the accompanying drawings. However, the accompanying drawings are merely illustrative of the relevant features of the present disclosure and therefore should not be considered as limiting, since the description may admit of other advantageous features.
[0041]
[0041] For convenience, "above" is used to mean away from the substrate of the light-emitting structure and "below" means toward the substrate, and other directional terms such as top, bottom, upward, downward, below, underneath, etc. should be interpreted accordingly. [Brief description of the drawings]
[0042] [Figure 1] 1 shows a schematic block diagram of a microdisplay electrostatic discharge (ESD) protection system according to some embodiments. [Diagram 2]
[0043] 1 illustrates a circuit diagram of an ESD protection system for a microdisplay according to some embodiments. [Diagram 3]
[0044] 1 illustrates a circuit diagram of an ESD protection system according to some embodiments. [Figure 4]
[0045] 1 illustrates a cross-sectional view of an ESD protection system according to some embodiments. [Diagram 5]
[0046] 1 illustrates a circuit diagram of an ESD protection system for a microdisplay according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0043]
[0047] According to common practice, the various features illustrated in the drawings may not be drawn to scale. As such, dimensions of the various features may be arbitrarily expanded or reduced for clarity. Moreover, some drawings may not show all components of a given system, method, or device. Finally, like reference numbers may be used throughout the specification and drawings to denote like features.
[0044] Detailed Description
[0048] Numerous details have been described herein to provide a thorough understanding of the exemplary embodiments illustrated in the accompanying drawings. However, some embodiments may be practiced without many of those specific details, and the claims are limited only by the features and aspects specifically recited in the claims. Moreover, well-known processes, components, and materials have not been described in exhaustive detail so as not to unnecessarily obscure aspects related to the embodiments described herein.
[0045]
[0049] In order to solve the problems in the related art as described above, some embodiments of the present disclosure provide an ESD protection system for a micro device. Figure 1 shows a schematic block diagram of an electrostatic discharge (ESD) protection system for a micro display according to some embodiments.
[0046]
[0050] FIG. 2 illustrates a circuit diagram of an ESD protection system for a microdisplay according to some embodiments, such as the ESD protection system illustrated in FIG.
[0047]
[0051] 1 and 2, the ESD protection system of the micro device includes a pixel driving circuit 01 and a first ESD protection unit 021. The pixel driving circuit 01 is electrically connected to at least one micro LED pixel 00, such as a micro LED pixel array, for controlling the on or off of the at least one micro LED pixel 00. In some embodiments, the first ESD protection unit 021 is electrically connected to the micro LED pixel 00. Here, the pixel driving circuit 01 is connected to a first level voltage (Vdd) 03 and the micro LED pixel 00. Furthermore, a first end of the micro pixel driving circuit 01 is connected to the first level voltage (Vdd) 03, and a second end of the micro pixel driving circuit 01 is connected to the micro LED pixel 00. In some embodiments, the second end of the micro pixel driving circuit 01 is connected to the cathode of the micro LED pixel 00, and the micro LED pixel 00 is connected to a second level voltage (Vcom) 04. In some embodiments, the second ESD protection unit 022 is connected to the first level voltage 03 and to the third level voltage 05. In some embodiments, the second ESD protection unit 022 includes a second ESD clamp.
[0048]
[0052] 1 and 2, in some embodiments, the first ESD protection unit 021 includes a first ESD clamp, where one end of the first ESD protection unit 021, for example the first ESD clamp, is connected to a third level voltage (Vss) 05. The other end of the first ESD protection unit 021 is connected to a second level voltage (Vcom) 04. The second ESD protection unit 022 is connected to the first level voltage (Vdd) 03 and the third level voltage (Vss) 05.
[0049]
[0053] In some embodiments, it is preferred that the second level voltage (Vcom) 04 is a negative voltage, the first level voltage (Vdd) 03 is a positive voltage, and the third level voltage (Vss) 05 is a positive voltage or zero. For example, the voltage of Vdd may be 1 to 2V, the voltage of Vss may be 0V, and / or the voltage of Vcom may be -5 to 0V.
[0050]
[0054] 3 shows a circuit diagram of an ESD protection unit according to some embodiments. For example, FIG. 3 shows a circuit diagram of an ESD protection unit or ESD clamp as shown in FIG. 1 and FIG. 2 according to one embodiment of the present disclosure.
[0051]
[0055] 3 and 2, in some embodiments, the first ESD protection unit 021 and / or the second protection unit 022 are power rail ESD clamps. FIG. 3 is an exemplary diagram of a power pin ESD network consisting of gate-grounded n-channel metal oxide semiconductor field effect transistor (MOSFET) devices. In some embodiments, the structure 021L on the left side of FIG. 3 is the actual power clamp, and the structure 021R on the right side of FIG. 3 illustrates the principle of a power clamp ESD protection system. A gate-grounded N-type metal oxide semiconductor (NMOS) ESD network such as 021L is a network for complementary metal oxide semiconductor (CMOS) technology. Typically, V' DD It is an n-channel MOSFET with its MOSFET drain connected to the power pin 302, which also has its source and gate connected to the ground power rail 304. The circuit remains "off" during normal operation. When the signal pin 302 exceeds the MOSFET snapback voltage, the circuit turns off at V' SSThe snapback voltage is the voltage applied to the transistor when avalanche breakdown or impact ionization in the transistor provides enough base current to turn the transistor on. When the voltage on the signal pin 302 falls below ground potential, the MOSFET drain biases the p-well or p-substrate region to achieve electrostatic protection purposes.
[0052]
[0056] In some embodiments, as shown in FIG. 1-FIG. 3, the first ESD protection unit 021 is preferably a negative power ESD clamp. Referring to FIG. 2, the first ESD protection unit 021 includes a MOS transistor, and the first ESD protection unit has a parasitic effect on the MOS transistor. Here, the gate of the first ESD protection unit 021 is connected to the source of the first ESD protection unit 021 and the second level voltage (Vcom) 04. Furthermore, the drain of the first ESD protection unit 021 is connected to the third level voltage (Vss) 05. In some embodiments, when the second level voltage (Vcom) 04 is a negative voltage, the MOS transistor is preferably an NMOS. Here, the cathode of the micro LED pixel 00 is connected to the second level voltage (Vcom) 04.
[0053]
[0057] FIG. 4 illustrates a cross-sectional view of an ESD protection system according to some embodiments.
[0054]
[0058] The semiconductor substrate 400 in FIG. 4 may be a first type silicon substrate. In some embodiments, the first ESD protection unit 021 includes a first type well region 403, a second type well 401, a second type deep well 402, a second type source 405, a second type drain 404, a first implanted region 406, a gate 408, and a second implanted region 407. Further, the first type well region 403 is formed in the first type semiconductor substrate 400. The second type well 401 is formed around the first type well region 403. The second type deep well 402 is formed at the bottom of the second type well 401 and the bottom of the first type well region 403. The second type source 405 is formed in the first type well region 403. The second type drain 404 is formed in the first type well region 403. A first implanted region 406 is formed beside the second type source 405. A gate 408 is formed on the first type well region 403 between the second type source 405 and the second type drain 404 and is connected to the second type source 405 and the first implanted region 406. A second implanted region 407 is formed beside the second type well 401.
[0055]
[0059] In some embodiments, the first ESD protection unit 021 and the second ESD protection unit 022 are both formed in a semiconductor substrate. In some examples, the first type is P-type and the second type is N-type, but this is not limited to the scope of the present disclosure.
[0056]
[0060] As shown in FIG. 4, in some embodiments, a deep N-well 402 is formed in a P-type substrate 400, an N-well 401 is formed on and around the top of the deep N-well 402, and a P-well region 403 is surrounded by the N-well 401 and the deep N-well 402. The N-well 401 is formed around the P-well region 403. The deep N-well 402 is formed at the bottom of the N-well 401 and at the bottom of the P-well region 403. An N+ implanted region 404 as an N+ drain is formed in the P-well region 403, and an N+ implanted region 405 as an N+ source is formed in the P-well region 403. A gate 408 is formed on the P-well region 403 between the N+ drain 404 and the N+ source 405. The gate 408 is connected to the N+ source 405 and the first P+ implanted region 406. A first P+ implanted region 406 is formed in the P-well region 403 and is adjacent to the N+ source 405. A second P+ implanted region 407 is formed beside or around the N-well 401. In some embodiments, the N+ implanted region 404, the N-well 401, and the second P+ implanted region 407 are connected to a third level voltage (Vss), e.g., Vss05 in FIG. 1 and FIG. 2. In some embodiments, the N+ implanted region 405, the first P+ implanted region 406, and the gate 408 are connected to a second level voltage (Vcom), e.g., Vcom04 in FIG. 1 and FIG. 2. In some examples, the second P+ implanted region 407 is connected to Vss as ground, e.g., Vss05 in FIG. 1 and FIG. 2. In some embodiments, the gate 408 can be a gate structure including several layers of materials, such as dielectric layers, spacers, etc. The gate 408 is a conventional gate structure, which is understood by those skilled in the art and will not be described herein. In some embodiments, 4011 is an implant region, such as an N+ implant region.
[0057]
[0061] FIG. 5 shows a circuit diagram of a microdisplay ESD protection system according to some embodiments.
[0058]
[0062] In some embodiments, the micro LED pixel 00 shown in Figures 1 and 2 can be replaced with a micro LED pixel array, and the pixel driving circuit 01 in Figures 1 and 2 controls the on or off of each of the micro LED pixels in the micro LED pixel array. A second ESD protection unit 022 is preferably connected to each micro LED pixel. In another embodiment, the second ESD protection unit 022 may include a plurality of second ESD protection units 022, each of which is connected to a first level voltage (Vdd) 03 and a third level voltage Vss 05, respectively, and connected to each micro LED pixel.
[0059]
[0063] 5, in some embodiments, the second ESD protection unit 022 includes multiple second ESD protection units 022, such as 0221 and 0222. In some embodiments, one end of each of the second ESD protection units 022 is connected to a first level voltage 03 (Vdd) that connects to the pixel driving circuit 01 (as shown in FIGS. 1 and 2), and the other end of each of the second ESD protection units 022 is connected to a third level voltage 05 (Vss).
[0060]
[0064] Referring to FIG. 5, FIG. 1 and FIG. 2, in another embodiment, one end of the micropixel driving circuit 01 is connected to a fourth level voltage 07 (Vdd″), and another end of the micropixel driving circuit 01 is connected to the microLED pixel 00. The pixel driving circuit 01 includes at least one switch, such as switches 011, 012 and 013. The switches 011, 012 and / or 013 are preferably formed by transistors. The switches 011, 012 and 013 are connected in series to realize a three-level control of the microLED pixel on or off, so as to control the light emission intensity and light emission time. For example, the switches 011, 012 and 013 are connected in series to respectively control the current on or off of the micropixel driving circuit 01, control the PWM signal from outside on or off, and control the scanning signal from outside on or off.
[0061]
[0065] In addition, the ESD protection system 500 of Figure 5 further includes a third ESD protection unit 023. One end of the third ESD protection unit 023 is connected to the first level voltage 03 (Vdd), and another end of the third ESD protection unit 023 is connected to the third level voltage 05 (Vss).
[0062]
[0066] Here, an input / output (IO) circuit 06 for receiving a signal from outside or outputting a signal to an external circuit is formed beside the pixel driving circuit 01. A third ESD protection unit 023 for providing ESD protection for the IO circuit 06 is connected to the IO circuit 06. In some embodiments, the IO circuit 06 may be formed around the micro LED pixel 00, away from the pixel 00, for example, 10 microns to 50 mm or more, for example, 10 microns, 20 microns, 100 microns, 300 microns, 500 microns, 1 mm, 5 mm, 10 mm, 20 mm, 30 mm, 40 mm, or 50 mm. The third ESD protection unit 023 includes at least two third ESD sub-clamps, for example, third ESD sub-clamps 0231, 0232, connected in series with each other. In some examples, the third ESD sub-clamp 0231 is a PMOS and the third ESD sub-clamp 0232 is an NMOS. One end of one third ESD sub-clamp 0231 is connected to the first level voltage 03 (Vdd), and the other end of the third ESD sub-clamp 0231 is connected to another third ESD sub-clamp 0232, which is connected to the third level voltage 05 (Vss). Furthermore, the gate and source of the third ESD sub-clamp 0231 are connected to the first level voltage 03 (Vdd), the drain of the third ESD sub-clamp 0231 is connected to the source of the third ESD sub-clamp 0232, and the gate and drain of the third ESD sub-clamp 0232 are connected to the third level voltage 05 (Vss). The IO circuit 06 is connected to the drain of the third ESD sub-clamp 0231 and the source of the third ESD sub-clamp 0232.
[0063]
[0067] In some embodiments, the first level voltage 03 (Vdd) is preferably higher than the second level voltage 04 (Vcom). The first level voltage 03 (Vdd) is higher than the fourth level voltage 07 (Vdd''). The third level voltage 05 (Vss) is higher than the second level voltage 04 (Vcom). Also, the first level voltage 03 (Vdd) is higher than the third level voltage 05 (Vss). Since the micro LED pixel 00 cannot operate under high voltage values, the second level voltage 04 (Vcom) is a negative voltage and is applied to the micro LED pixel 00. In some embodiments, the first level voltage 03 (Vdd) is preferably a positive voltage, the fourth level voltage 07 (Vdd'') is a positive voltage, and the third level voltage 05 (Vss) is zero. For example, the voltage of Vdd may be 1 to 3V, the voltage of Vdd'' may be 1 to 2V, the voltage of Vss may be 0V, and the voltage of Vcom may be -5 to 0V.
[0064]
[0068] 5, in some embodiments, the ESD protection system 500 further includes a fourth ESD protection unit 024. One end of the fourth ESD protection unit 024 is connected to a fourth level voltage 07 (Vdd''), and the other end of the fourth ESD protection unit 024 is connected to a third level voltage 05 (Vss).
[0065]
[0069] In some embodiments, the second ESD protection unit 022, the third ESD protection unit 023, and the fourth ESD protection unit 024 are power rail ESD clamps, for which the description in FIG. 3 may be referred to.
[0066]
[0070] In some embodiments, the micro device with one or more ESD protection units, e.g., 500, is selected from one of a micro-inorganic LED device and / or a micro-organic LED device. In some embodiments, the micro-LED pixel is selected from an inorganic micro-LED or an organic micro-LED. For example, the micro device can be a micro-display panel. The micro-LED display panel includes a micro-LED array forming a pixel array, such as a 640*480 pixel array. In some embodiments, the length of the micro-LED display panel cannot exceed 100, 200, 300, 400 or 500 microns, and the width of the micro-LED display panel cannot exceed 100, 200, 300, 400 or 500 microns. In some embodiments, the length of the micro-LED display panel cannot exceed 1 cm, and the width of the micro-LED display panel cannot exceed 1 cm. In some embodiments, the length of the micro-LED display panel cannot exceed 2 cm, and the width of the micro-LED display panel cannot exceed 2 cm. In some embodiments, the length of the micro-LED display panel cannot exceed 10 cm, and the width of the micro-LED display panel cannot exceed 10 cm. In some embodiments, the length of the micro LED display panel cannot exceed 20 cm, and the width of the micro LED display panel cannot exceed 20 cm. The micro LED display panel also includes an IC backside. The micro LED display panel includes a micro LED array including a plurality of inorganic micro LEDs for showing a display image. The micro LED array is electrically connected and coupled to the IC backside. The one or more ESD protection units and the pixel driving circuit are formed in the IC backside. In some embodiments, the one or more ESD protection units are part of the IC circuit for protecting the IC circuit under electrostatic discharge conditions. The ESD protection units can prevent current leakage of the IC circuit in the IC backside.
[0067]
[0071] Here, the micro LED can be selected from inorganic LED or organic LED. On the back of the IC, an electrode connection area is electrically connected to the micro LED array, and a signal line area is formed around the electrode connection area. The back of the IC acquires a signal such as image data from the outside through the signal line, and thereby controls the corresponding micro LED to emit light. The back of the IC generally uses an 8-bit digital-to-analog converter (DAC). The 8-bit DAC has 256 display levels, each level corresponding to one gray level, that is, the 8-bit DAC can provide 256 different gray levels. Any level of the 256 gray levels can be applied to the micro LED, so that gray levels ranging from 0 to 255 can be displayed by one pixel. Optionally, the luminance value of the micro LED can be controlled by the voltage amplitude or current amplitude of the signal acquired by the back of the IC, and the gray level can be indicated by the time interval, for example, the pulse width, of the signal.
[0068]
[0072] Those skilled in the art will appreciate that the microdisplay panel is not limited to the structures described above and may include more or less components than those shown, or some components may be combined, or different components may be utilized.
[0069]
[0073] It is understood by those skilled in the art that all or some of the steps for implementing the above-mentioned embodiments can be implemented by hardware, or by a program that instructs related hardware. The program can be stored in a flash memory, a conventional computer device, a central processing module, a coordinating module, etc.
[0070]
[0074] The above description is merely the embodiment of the present disclosure, and the present disclosure is not limited to those embodiments. Any modifications, equivalent replacements and improvements made without departing from the concept and principle of the present disclosure shall be included within the protection scope of the present disclosure.
[0071]
[0075] Further embodiments include various subsets of the above embodiments, including those embodiments as shown in Figures 1-5 that are combined or rearranged into various other embodiments.
[0072]
[0076] Although the detailed description includes many details, they should not be interpreted as limiting the scope of the invention, but merely as describing different examples and aspects of the invention. It should be understood that the scope of the invention includes other embodiments not discussed in detail above. For example, the approach described above can also be applied to the integration of functional devices other than LEDs and OLEDs with control circuits other than pixel driving circuits. Examples of devices other than LEDs include vertical cavity surface emitting lasers (VCSELs), photodetectors, microelectromechanical systems (MEMS), silicon photonic device, power electronic devices, and distributed feedback lasers (DFBs). Examples of other control circuits include current drivers, voltage drivers, transimpedance amplifiers, and logic circuits.
[0073]
[0077] The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the embodiments described herein and variations thereof. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the subject matter disclosed herein. Thus, the present disclosure is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein.
[0074]
[0078] Features of the present invention may be implemented in or with or using a computer program product, such as a storage medium or computer readable storage medium having instructions stored therein that can be used to program a processing system to perform any of the features presented herein. Storage media include high speed random access memories, such as DRAM, SRAM, DDR, RAM or other random access solid state memory devices, but are not limited to, and may also include non-volatile memories, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices or other non-volatile solid state storage devices. The memory optionally includes one or more storage devices located remotely from the CPU. The memory, or alternatively, a non-volatile memory device within the memory, includes a non-transitory computer readable storage medium.
[0075]
[0079] Stored on any machine-readable medium, features of the present invention may be embodied in software and / or firmware to control the hardware of a processing system and to enable the processing system to utilize the results of the present invention and interact with other mechanisms. Such software or firmware may include, but is not limited to, application code, device drivers, operating systems, and execution environments / containers.
[0076]
[0080] In this specification, terms such as "first," "second," etc. may be used to describe various elements or steps, but it will be understood that these elements or steps should not be limited by these terms. These terms are used only to distinguish one element or step from another element or step.
[0077]
[0081] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the scope of the claims. When used in the description of the embodiments and in the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. As used herein, the term "and / or" will be understood to refer to and include any and all possible combinations of one or more of the associated listed items. As used herein, the terms "comprise" and / or "comprising" will be further understood to specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.
[0078]
[0082] As used herein, the term "if" may be interpreted to mean "if," or "when," or "response to determining," or "pursuant to a determination that," or "response to detecting that," depending on the context. Similarly, the phrases "if" or "if" or "when" may be interpreted to mean "upon determining," or "in response to determining," or "pursuant to a determination that," or "upon detecting," or "in response to detecting" that the stated predecessor condition is true, depending on the context.
[0079]
[0083] The foregoing description has been described with reference to specific embodiments for explanatory purposes. However, the above exemplary discussion is not intended to be exhaustive or to limit the scope of the claims to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments have been chosen and described to best explain the principles of operation and practical applications so as to enable others skilled in the art to best utilize the invention and various embodiments.
Claims
1. 1. An electrostatic discharge (ESD) protection system for a micro device, comprising: a pixel drive circuit electrically connected to at least one micro LED pixel, the pixel drive circuit for controlling the micro LED pixel to be turned on or off; a first ESD protection unit electrically connected to the micro LED pixel; 23. An electrostatic discharge (ESD) protection system comprising:
2. 10. The micro device ESD protection system of claim 1, wherein the micro LED pixel is connected to a second level voltage (Vcom).
3. 3. The micro device ESD protection system of claim 2, wherein the cathode of the micro LED pixel is connected to the second level voltage (Vcom).
4. 3. The ESD protection system of claim 2, wherein the first ESD protection unit is connected to a third level voltage (Vss) and to the second level voltage (Vcom).
5. 5. The micro device ESD protection system of claim 4, wherein the third level voltage (Vss) is higher than the second level voltage (Vcom).
6. 6. The micro device ESD protection system of claim 5, wherein the third level voltage (Vss) is zero and the second level voltage (Vcom) is a negative voltage.
7. The micro device ESD protection system of claim 1 , wherein the first ESD protection unit comprises a power ESD clamp.
8. 5. The ESD protection system of claim 4, wherein the first ESD protection unit includes a MOS transistor, a gate of the first ESD protection unit is connected to a source of the first ESD protection unit and to the second level voltage (Vcom), a drain of the first ESD protection unit is connected to the third level voltage (Vss), and the first ESD protection unit is parasitic on the MOS transistor.
9. 9. The micro device ESD protection system of claim 8, wherein the MOS transistor is an NMOS.
10. The first ESD protection unit comprises: A P-type semiconductor substrate; a P-well region formed in the P-type semiconductor substrate; an N-well formed around the P-well region; a deep N-well formed at a bottom of the N-well and at a bottom of the P-well region; an N+ drain formed within the P-well region; an N+ source formed in the P-well region; a first P+ implant region in the P-well region formed next to the N+ source; a gate formed on the P-well region between the N+ source and the N+ drain and connected to the N+ source and the first P+ implanted region; a second P+ implanted region formed in a P-type semiconductor substrate next to said N-well; 5. The micro device ESD protection system of claim 4, comprising:
11. 11. The micro device ESD protection system of claim 10, wherein the N-well, the N+ drain and the second P+ implanted region are connected to the third level voltage (Vss), and the first P+ implanted region, the N+ source and the gate are connected to the second level voltage (Vcom).
12. 2. The micro device ESD protection system of claim 1, wherein the at least one micro LED pixel is a micro LED pixel array, and the pixel drive circuit controls the on or off of each of the micro LED pixels in the micro LED pixel array.
13. 13. The micro device ESD protection system of claim 12, wherein the first ESD protection unit is connected to each of the micro LED pixels.
14. 3. The micro device ESD protection system of claim 2, wherein the micro pixel drive circuit is connected to a first level voltage (Vdd) and to the micro LED pixel.
15. 15. The ESD protection system of claim 14, further comprising a second ESD protection unit, the second ESD protection unit being connected to the first level voltage (Vdd) and to a third level voltage (Vss).
16. 16. The ESD protection system of claim 15, wherein the second ESD protection unit includes a plurality of second ESD sub-clamps, a first end of each of the second ESD sub-clamps is connected to the first level of voltage (Vdd) and to the pixel driving circuit, a second end of each of the second ESD sub-clamps is connected to the third level of voltage (Vss), and the second ESD sub-clamps are connected in parallel with each other.
17. 17. The micro device ESD protection system of claim 16, wherein the first level voltage (Vdd) is greater than the second level voltage (Vcom), the third level voltage (Vss) is greater than the second level voltage (Vcom), and the first level voltage (Vdd) is greater than the third level voltage (Vss).
18. 20. The micro device ESD protection system of claim 17, wherein the second level voltage (Vcom) is a negative voltage, the first level voltage (Vdd) is a positive voltage, and the third level voltage (Vss) is zero.
19. 16. The micro device ESD protection system of claim 15, wherein the second ESD protection unit includes a power rail ESD clamp.
20. 16. The micro device ESD protection system of claim 15, wherein the first ESD protection unit and the second ESD protection unit are formed in a semiconductor substrate.
21. 10. The micro device ESD protection system of claim 1, wherein the micro device is selected from one of a micro inorganic LED device and a micro organic LED device, and the micro LED pixel is selected from an inorganic micro LED or an organic micro LED.
22. 3. The micro device ESD protection system of claim 2, further comprising a third ESD protection unit, a first end of the third ESD protection unit being connected to a first level voltage (Vdd) and a second end of the third ESD protection unit being connected to a third level voltage (Vss).
23. 23. The micro device ESD protection system of claim 22, wherein the third ESD protection unit is connected to an IO circuit.
24. 25. The ESD protection system of claim 24, wherein the third ESD protection unit includes at least two third ESD sub-clamps, and the third ESD sub-clamps are connected in series with each other.
25. 3. The micro device ESD protection system of claim 2, wherein a first end of the micro pixel driving circuit is connected to a fourth level voltage (Vdd'') and a second end of the micro pixel driving circuit is connected to the micro LED pixel.
26. 3. The ESD protection system of claim 2, further comprising a fourth ESD protection unit, a first end of the fourth ESD protection unit being connected to a fourth level voltage (Vdd'') and a second end of the fourth ESD protection unit being connected to a third level voltage (Vss).
27. 27. The micro device ESD protection system of claim 26, wherein the third level voltage (Vss) is lower than the fourth level voltage (Vdd'').
28. The micro device ESD protection system of claim 1 , wherein the pixel drive circuit includes at least one switch.