Method and apparatus for symmetric aging of clock trees - Patents.com

Abstract

In a particular aspect, an apparatus includes a gating circuit having an enable input, a signal input, and an output, where the enable input is configured to receive an enable signal. The apparatus also includes a toggle circuit having an output, where the toggle circuit is configured to toggle a logic state at an output of the toggle circuit based on the enable signal. The apparatus further includes a multiplexer having a first input, a second input, and an output, where the first input of the multiplexer is coupled to the output of the gating circuit and the second input of the multiplexer is coupled to the output of the toggle circuit. The multiplexer is configured to select one of the first input and the second input based on the enable signal and to couple the selected one of the first input and the second input to the output of the multiplexer.

Description

[Background technology]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to and the benefit of nonprovisional application Ser. No. 17 / 655,697, filed in the United States Patent Office on March 21, 2022, the entire contents of which are incorporated herein by reference as if fully set forth below and for all applicable purposes.

[0002] Field Aspects of the present disclosure relate generally to aging, and more particularly, to mitigating aging.

[0003] background A system may include a clock source (e.g., a phase-locked loop) configured to generate a clock signal for timing the operation of one or more circuits (e.g., sequential logic, a processor, a memory, etc.) in the system. The system may also include a clock path for distributing the clock signal from the clock source to one or more circuits. A challenge facing clock distribution is that degradation of asymmetries in the clock path over time can cause duty cycle distortion in the clock signal, which can lead to timing issues (e.g., timing violations) in one or more circuits. Summary of the Invention

[0004] SUMMARY OF THE DISCLOSURE The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This Summary is not an extensive overview of all contemplated implementations, and is not intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the Detailed Description presented later.

[0005] A first aspect relates to an apparatus. The apparatus includes a gating circuit having an enable input, a signal input, and an output, the enable input configured to receive an enable signal. The apparatus also includes a toggle circuit having an output, the toggle circuit configured to toggle a logic state at an output of the toggle circuit based on the enable signal. The apparatus further includes a multiplexer having a first input, a second input, and an output, the first input of the multiplexer being coupled to the output of the gating circuit and the second input of the multiplexer being coupled to the output of the toggle circuit. The multiplexer is configured to select one of the first input and the second input based on the enable signal and to couple the selected one of the first input and the second input to the output of the multiplexer.

[0006] A second aspect relates to a method of balancing aging in a clock path, the method including receiving an enable signal, passing a clock signal to the clock path if the enable signal has a first logic state, gating the clock signal if the enable signal has a second logic state, toggling a logic state of a toggle circuit in response to an edge of the enable signal, and passing the logic state of the toggle circuit to the clock path if the clock signal is gated. [Brief description of the drawings]

[0007] [Figure 1] 1 illustrates an example of a system including a clock source, a gating circuit, a clock path, and a circuit in accordance with certain aspects of the present disclosure. [Figure 2A] 1 illustrates an example of a clock path including a clock buffer in accordance with certain aspects of the present disclosure. [Figure 2B] 1 illustrates an example in which the input of a clock path is held low in idle mode, according to certain aspects of the present disclosure. [Figure 2C]1 illustrates an example of a duty cycle shift in a clock path due to asymmetric aging in accordance with certain aspects of the present disclosure. [Figure 2D] 1 illustrates an example in which the input of a clock path is held high in idle mode, according to certain aspects of the present disclosure. [Figure 2E] 1 illustrates another example of a duty cycle shift in a clock path due to asymmetric aging in accordance with certain aspects of the present disclosure. [Diagram 3] 1 illustrates an example of a system including a toggle circuit and a multiplexer in accordance with certain aspects of the present disclosure. [Figure 4A] 1 illustrates an example implementation of a toggle circuit in accordance with certain aspects of the present disclosure. [Figure 4B] 1 illustrates another example implementation of a toggle circuit in accordance with certain aspects of the present disclosure. [Diagram 5] 1 illustrates an example implementation of a gating circuit in accordance with certain aspects of the present disclosure. [Figure 6] 1 illustrates one embodiment of a latch between a gating circuit and a select input of a multiplexer in accordance with certain aspects of the present disclosure. [Figure 7] FIG. 11 is a timing diagram illustrating one example of toggling in accordance with certain aspects of the present disclosure. [Figure 8] 1 illustrates an example of a system including a duty cycle monitor and control circuit in accordance with certain aspects of the present disclosure. [Figure 9] 1 is a flow chart illustrating a method for balancing aging in clock paths in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The detailed description of the present invention, set forth below in connection with the accompanying drawings, is intended as an illustration of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description of the present invention includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0009] 1 illustrates an example of a system 110 including a clock source 115, a gating circuit 120, a clock path 130, and a circuit 140, in accordance with certain aspects. The circuit 140 may include sequential logic, a processor, a memory, etc. The clock source 115 is configured to generate a clock signal and output the clock signal at an output 118. The clock source 115 may be implemented using a phase-locked loop (PLL) or another type of clock source. The clock signal is used to time the operation of the circuit 140.

[0010] Clock path 130 has an input 132 and an output 134. Output 134 is coupled to circuit 140. Clock path 130 is configured to receive a clock signal at input 132 and distribute the clock signal to circuit 140. As used herein, a "clock signal" may be a periodic signal that oscillates between high and low. A clock signal has a duty cycle, which may be expressed as the percentage or fraction of a clock period (i.e., clock cycles) that the clock signal is high (i.e., 1).

[0011] The gating circuit 120 (also referred to as a clock gating cell) has a signal input 122, an enable input 124, and an output 126. The signal input 122 is coupled to an output 118 of a clock source 115, and the output 126 is coupled to an input 132 of a clock path 130. The enable input 124 is configured to receive an enable signal, and the signal input 122 is configured to receive a clock signal. In operation, the gating circuit 120 is configured to pass the clock signal to the output 126 or gate (i.e., block) the clock signal based on the enable signal. For example, the gating circuit 120 can be configured to pass the clock signal to the output 126 when the enable signal has a first logic state, and gate the clock signal when the enable signal has a second logic state. The first logic state can be high (i.e., 1) and the second logic state can be low (i.e., 0), or vice versa. Thus, in this embodiment, when the enable signal transitions from a first logic state to a second logic state, the gating circuit 120 begins gating the clock signal, and when the enable signal transitions from the second logic state to the first logic state, the gating circuit 120 stops gating the clock signal.

[0012] In certain aspects, the enable signal is provided by a power management circuit 160 that is coupled to the enable input 124. In these aspects, the power management circuit 160 uses the enable signal to control whether the gating circuit 120 passes the clock signal to the clock path 130 or gates (i.e., blocks) the clock signal. In one embodiment, the power management circuit 160 can save power by using the enable signal to cause the gating circuit 120 to pass the clock signal (e.g., set the enable signal to a first logic state) when the circuit 140 is active, and to cause the gating circuit 120 to gate the clock signal (i.e., set the enable signal to a second logic state) when the circuit 140 is in an idle mode (i.e., not active). Clock gating is a known technique for reducing dynamic power consumption when a circuit is not active.

[0013] 1 shows one gating circuit 120 between clock source 115 and clock path 130, it should be understood that system 110 may include more than one clock gating circuit (e.g., at various locations along clock path 130). It should also be understood that clock path 130 may include multiple branches (not shown) forming a clock tree for distributing the clock signal to one or more other circuits (not shown) other than circuit 140 shown in FIG.

[0014] Due to aging effects such as bias temperature instability (BTI), the performance of clock path 130 may degrade over time. For example, BTI stress on clock path 130 during idle mode may cause duty cycle shifts in clock path 130 over time, which may lead to timing issues (e.g., timing violations) in circuit 140.

[0015] An example of duty cycle shift caused by aging will now be discussed with reference to Figures 2A-2E. Figure 2A illustrates an example where clock path 130 includes clock buffers 220-1-220-4 coupled in series between input 132 and output 134. Although four clock buffers 220-1-220-4 are shown in Figure 2A for simplicity, it should be understood that clock path 130 may include multiple clock buffers. In the example illustrated in Figure 2A, each of clock buffers 220-1-220-4 is implemented using a corresponding complementary inverter including a corresponding one of transistors 225-1-225-4 (e.g., n-type field effect transistors) and a corresponding one of transistors 230-1-230-4 (e.g., p-type field effect transistors). However, it should be understood that each of clock buffers 220-1-220-4 may be implemented using other types of circuits or logic gates.

[0016] When circuit 140 is in active mode, gating circuit 120 passes the clock signal to input 132 of clock path 130, and the clock signal propagates through clock buffers 220-1 to 220-4 to circuit 140. When circuit 140 is in idle mode, gating circuit 120 gates the clock signal, preserving (i.e., holding) input 132 of clock path 130 high or low.

[0017] FIG. 2B illustrates an embodiment in which gating circuit 120 holds input 132 of clock path 130 low (i.e., logic 0) in idle mode. FIG. 2B also illustrates the logic states at the inputs and outputs of each of clock buffers 220-1 through 220-4. In this embodiment, output 134 of clock path 130 is low (i.e., logic 0) in idle mode. In this embodiment, transistors 230-1, 225-2, 230-3, and 225-4 are turned on in idle mode, and transistors 225-1, 230-2, 225-3, and 230-4 are turned off in idle mode. In FIG. 2B, transistors 230-1, 225-2, 230-3, and 225-4 that are turned on in idle mode are shown in bold. The transistors 230-1, 225-2, 230-3, and 225-4 that are turned on in idle mode are stressed in idle mode, while the transistors 225-1, 230-2, 225-3, and 230-4 that are turned off in idle mode are not stressed in idle mode. This leads to asymmetric aging, where the transistors 230-1, 225-2, 230-3, and 225-4 that are stressed in idle mode age faster than the transistors 225-1, 230-2, 225-3, and 230-4 that are not stressed in idle mode.

[0018] In this example, the asymmetric aging increases the delay of the falling edge at the output 134 of the clock path 130 relative to the delay of the rising edge at the output 134 of the clock path 130 by shifting the threshold voltages of the transistors 230-1, 225-2, 230-3, and 225-4. The increase in the delay of the falling edge relative to the delay of the rising edge causes a duty cycle shift in the clock path 130. One example of this duty cycle shift is shown in the timing diagram shown in FIG. 2C. In the example shown in FIG. 2C, a clock signal 250 having a 50% duty cycle is input to the clock path 130 in active mode. FIG. 2C also shows the clock signal 260 at the output 134 of the clock path 130 after propagating through the clock path 130. The clock path 130 transmits the rising edge of the clock signal 250 with a delay T r , and the falling edge of the clock signal 250 is delayed by a delay T f As shown in Figure 2C, the falling edge delay T f is the delay of the rising edge T due to the degradation of the asymmetry over time. r In this embodiment, the longer delay of the falling edge increases the duty cycle of clock signal 260 at output 134 of clock path 130 (i.e., results in a duty cycle greater than 50%).

[0019] In the embodiment shown in FIG. 2B and FIG. 2C, the gating circuit 120 holds the input 132 of the clock path 130 low in the idle mode. Asymmetry degradation over time also occurs when the gating circuit 120 holds the input 132 of the clock path 130 high in the idle mode. In this regard, FIG. 2D illustrates an embodiment in which the gating circuit 120 holds the input 132 of the clock path 130 high (i.e., logic 1) in the idle mode. FIG. 2D also illustrates the logic states at the inputs and outputs of each clock buffer 220-1 through 220-4. In this embodiment, the output 134 of the clock path 130 is high (i.e., logic 1) in the idle mode. In this embodiment, the transistors 225-1, 230-2, 225-3, and 230-4 are turned on in the idle mode, and the transistors 230-1, 225-2, 230-3, and 225-4 are turned off in the idle mode. 2D, transistors 225-1, 230-2, 225-3, and 230-4 that are turned on in idle mode are shown in bold. Transistors 225-1, 230-2, 225-3, and 230-4 that are turned on in idle mode are stressed in idle mode, while transistors 230-1, 225-2, 230-3, and 225-4 that are turned off in idle mode are not stressed in idle mode, which leads to asymmetric aging, where transistors 225-1, 230-2, 225-3, and 230-4 that are stressed in idle mode age faster than transistors 230-1, 225-2, 230-3, and 225-4.

[0020] In this example, the asymmetric aging increases the delay of the rising edge at the output 134 of the clock path 130 relative to the delay of the falling edge at the output 134 of the clock path 130 by shifting the threshold voltages of the stressed transistors 225-1, 230-2, 225-3, and 230-4 in the idle mode. The increase in the delay of the rising edge relative to the delay of the falling edge causes a duty cycle shift in the clock path 130. One example of this duty cycle shift is shown in the timing diagram shown in FIG. 2E. In the example shown in FIG. 2E, a clock signal 250 having a 50% duty cycle is input to the clock path 130 in the active mode. FIG. 2E also shows the clock signal 270 at the output 134 of the clock path 130 after propagating through the clock path 130. The clock path 130 shifts the rising edge of the clock signal 250 at the output 134 of the clock path 130 with a delay T r , and the falling edge of the clock signal 250 is delayed by a delay T f As shown in Figure 2E, the rising edge delay T r is the delay of the falling edge T due to the degradation of the asymmetry over time. f In this embodiment, the longer delay of the rising edge reduces the duty cycle of clock signal 270 at output 134 of clock path 130 (i.e., results in a duty cycle less than 50%).

[0021] Thus, the degradation of the asymmetry in idle mode over time causes a duty cycle shift (i.e., duty cycle distortion) in clock path 130. The duty cycle shift increases or decreases the duty cycle of the clock signal depending, for example, on whether gating circuit 120 holds input 132 of clock path 130 low or high in idle mode and the number of clock buffers 220-1 through 220-4 in clock path 130. The duty cycle shift can lead to timing issues in circuit 140. For embodiments in which circuit 140 includes sequential logic (e.g., flops), the duty cycle shift can result in violations of setup and / or hold times.

[0022] To address duty cycle shifts (i.e., distortion) due to asymmetric aging, aspects of the present disclosure provide a toggle circuit that, instead of holding the clock path input at the same logic state in idle mode, alternately holds the clock path input low and high in idle mode. By alternately holding the clock path input low and high, the toggle circuit helps to balance the aging of transistors in the clock path and reduce duty cycle distortion, as discussed further below.

[0023] 3 illustrates one embodiment of a system 310 that includes the clock source 115, the gating circuit 120, the clock path 130, and the circuit 140 discussed above. The system 310 also includes a toggle circuit 320 and a multiplexer 330 that serve to balance aging in the clock path 130 according to certain aspects, as discussed further below.

[0024] In this embodiment, toggle circuit 320 has an input 322 and an output 324. Toggle circuit 320 is configured to receive an enable signal at input 322 and to toggle (i.e., change) a logic state at output 324 in response to an edge of the enable signal. Thus, if the current logic state at output 324 is 1 (i.e., high), toggle circuit 320 changes the logic state at output 324 to 0 (i.e., low) at an edge of the enable signal. If the current logic state at output 324 is 0, toggle circuit 320 changes the logic state at output 324 to 1 at an edge of the enable signal. In one embodiment, toggle circuit 320 is positive edge triggered, where toggle circuit 320 toggles the logic state at output 324 at a rising edge of the enable signal. In another embodiment, toggle circuit 320 is negative edge triggered, where toggle circuit 320 toggles the logic state at output 324 at a falling edge of the enable signal. Toggle circuit 320 may be implemented using a toggle flop or another type of toggle circuit. As discussed further below, toggle circuit 320 is used to alternately hold input 132 of clock path 130 low and high in idle mode to balance aging in clock path 130.

[0025] The multiplexer 330 has a first input 332, a second input 334, an output 336, and a selection input 338. The first input 332 is coupled to the output 126 of the gating circuit 120, the second input 334 is coupled to the output 324 of the toggle circuit 320, and the output 336 is coupled to the input 132 of the clock path 130. In a particular aspect, the multiplexer 330 is configured to receive an enable signal at the selection input 338, select one of the first input 332 and the second input 334 based on the enable signal, and couple the selected one of the first input 332 and the second input 334 to the output 336.

[0026] In one embodiment, the multiplexer 330 is configured to select the first input 332 when the enable signal has a first logic state and to select the second input 334 when the enable signal has a second state. As described above, the gating circuit 120 is configured to pass the clock signal when the enable signal has a first logic state and to gate the clock signal when the enable signal has a second logic state. Thus, in this embodiment, the multiplexer 330 couples the output 126 of the gating circuit 120 to the input 132 of the clock path 130 when the gating circuit 120 passes the clock signal. In this case, the multiplexer 330 passes the clock signal from the gating circuit 120 to the clock path 130. Also, in this embodiment, the multiplexer 330 couples the output 324 of the toggle circuit 320 to the input 132 of the clock path 130 when the gating circuit 120 gates the clock signal in the idle mode. As a result, the output 324 of toggle circuit 320 controls whether the input 132 of clock path 130 is held low or high in idle mode.

[0027] Next, an exemplary operation of the system 310 will be described in accordance with certain aspects.

[0028] In this embodiment, power management circuit 160 causes gating circuit 120 to gate the clock signal when circuit 140 is in idle mode (i.e., not active) to conserve power. To do this, power management circuit 160 sets the enable signal to a second logic state in idle mode, which causes gating circuit 120 to gate the clock signal and causes multiplexer 330 to select second input 334. Because multiplexer 330 has selected second input 334 in idle mode, output 324 of toggle circuit 320 is coupled to input 132 of clock path 130 in idle mode, and therefore determines whether input 132 of clock path 130 is held low or high in idle mode.

[0029] Over time, the power management circuit 160 causes the gating circuit 120 to gate the clock signal for a number of idle periods, where each "idle period" is a period during which the circuit 140 is in an idle mode (i.e., not active). The idle periods are separated by active periods, where each "active period" is a period during which the circuit 140 is active. During each active period, the power management circuit 160 causes the gating circuit 120 to pass the clock signal (e.g., by setting the enable signal to a first logic state) and causes the multiplexer 330 to select the first input 332.

[0030] For each idle period, the enable signal has a rising edge and a falling edge. This is because the enable signal transitions from a first logic state to a second logic state at the beginning of the idle period to gate the clock signal, and transitions from the second logic state to the first logic state at the end of the idle period to ungate the clock signal. For an embodiment in which the first logic state is 1 and the second logic state is 0, the gating circuit 120 starts gating the clock signal at the beginning of the idle period at the falling edge of the enable signal, and stops gating the clock signal at the end of the idle period at the rising edge of the enable signal. For an embodiment in which the first logic state is 0 and the second logic state is 1, the gating circuit 120 starts gating the clock signal at the beginning of the idle period at the rising edge of the enable signal, and stops gating the clock signal at the end of the idle period at the falling edge of the enable signal. Thus, in both embodiments, the enable signal has both a rising edge and a falling edge for each idle period.

[0031] Because the enable signal has both a rising edge and a falling edge for each idle period, toggle circuit 320 toggles the logic state at output 324 once for each idle period, regardless of whether toggle circuit 320 is positive-edge triggered or negative-edge triggered. The toggling for each idle period causes output 324 of toggle circuit 320 to alternate between low (i.e., 0) and high (i.e., 1) for multiple idle periods. Thus, if output 324 of toggle circuit 320 is 1 during the current idle period, output 324 will be 0 during the next idle period, and vice versa.

[0032] Because output 324 of toggle circuit 320 alternates between low and high for multiple idle periods and multiplexer 330 couples output 324 of toggle circuit 320 to input 132 of clock path 130 in idle mode, output 324 of toggle circuit 320 alternately holds input 132 of clock path 130 low and high for multiple idle periods. Thus, if input 132 of clock path 130 is held low during the current idle period, input 132 of clock path 130 will be held high during the next idle period, and vice versa.

[0033] Assuming that the cumulative duration of idle periods during which input 132 of clock path 130 is held low is approximately equal to the cumulative duration of idle periods during which input 132 of clock path 130 is held high, input 132 of clock path 130 spends approximately equal amounts of time held low and time held high in idle mode. As a result, the aging of the transistors in clock path 130 (e.g., transistors 225-1 through 225-4 and transistors 230-1 through 230-4) is approximately balanced (i.e., symmetric). Balanced (i.e., symmetric) aging reduces duty cycle distortion compared to when input 132 of clock path 130 is held at the same logic state for each idle period, causing asymmetric aging of the transistors in clock path 130.

[0034] 4A illustrates an example implementation of a toggle circuit 320 according to certain aspects. In this example, the toggle circuit 320 includes a flop 410 (e.g., a D flip-flop) and an inverter 420. The flop 410 has a clock input 412, a data input 414, and an output 416. The clock input 412 is coupled to an input 322 of the toggle circuit 320 for receiving an enable signal, and the output 416 is coupled to an output 324 of the toggle circuit 320. The inverter 420 has an input 422 and an output 424. The input 422 of the inverter 420 is coupled to the output 416 of the flop 410, and the output 424 of the inverter 420 is coupled to the data input 414 of the flop 410. Thus, the inverter 420 inverts the logic state at the output 416 of the flop 410 and inputs the inverted logic state to the data input 414 of the flop 410.

[0035] In one embodiment, flop 410 is positive edge triggered, where flop 410 is configured to latch the logic state at data input 414 on the rising edge of the enable signal and output the latched logic state at output 416. In this embodiment, an inverter 420 between the output 416 of flop 410 and the data input 414 of flop 410 causes the logic state at output 416 of flop 410 (and therefore output 324 of toggle circuit 320) to toggle on the rising edge of the enable signal.

[0036] In another embodiment, flop 410 is negative edge triggered, in which case flop 410 is configured to latch the logic state at data input 414 on the falling edge of the enable signal and output the latched logic state at output 416. In this embodiment, an inverter 420 between the output 416 of flop 410 and the data input 414 of flop 410 causes the logic state at output 416 of flop 410 (and therefore output 324 of toggle circuit 320) to toggle on the falling edge of the enable signal.

[0037] 4B illustrates another exemplary implementation of a toggle circuit 320 according to certain aspects. In this example, the toggle circuit 320 includes a flop 430 (e.g., a D flip-flop) having a clock input 432, a data input 434, a first output 436, and a second output 438. The first output 436 and the second output 438 are complementary (i.e., the logic state at the second output 438 is the inverse of the logic state at the first output 436). In this example, the clock input 432 is coupled to the input 322 of the toggle circuit 320 to receive an enable signal, and the first output 436 is coupled to the output 324 of the toggle circuit 320. The second output 438 of the flop 430 is coupled to the data input 434 of the flop 430.

[0038] In one embodiment, flop 430 is positive edge triggered, where flop 430 is configured to latch the logic state at data input 434 on the rising edge of the enable signal, output the latched logic state at first output 436, and output the inverse of the latched logic state at second output 438. In this embodiment, coupling data input 434 to second output 438 causes the logic state at first output 436 of flop 430 (and therefore output 324 of toggle circuit 320) to toggle on the rising edge of the enable signal.

[0039] In another embodiment, flop 430 is negative edge triggered, in which case flop 430 is configured to latch the logic state at data input 434 on the falling edge of the enable signal, output the latched logic state at first output 436, and output the inverse of the latched logic state at second output 438. In this embodiment, coupling data input 434 to second output 438 causes the logic state at first output 436 of flop 430 (and therefore output 324 of toggle circuit 320) to toggle on the falling edge of the enable signal.

[0040] It should be understood that toggle circuit 320 is not limited to the example implementation shown in FIGS. 4A and 4B, and that toggle circuit 320 can be implemented using other types of toggle circuits.

[0041] 5 illustrates an exemplary implementation of the gating circuit 120 according to certain aspects. In this example, the gating circuit 120 includes a latch 510 and a gate 520. The latch 510 has a first input 512, a second input 514, and an output 516. The first input 512 is coupled to the enable input 124 of the gating circuit 120 to receive an enable signal, and the second input 514 is coupled to the signal input 122 of the gating circuit 120 to receive a clock signal. In certain aspects, the latch 510 is configured to latch the logic state of the enable signal at a falling edge of the clock signal and output the latched logic state of the enable signal at the output 516. In these aspects, the latch 510 can be implemented using a negative edge triggered flop or another type of latch.

[0042] The gate 520 has a first input 522, a second input 524, and an output 526. The first input 522 is coupled to the output 516 of the latch 510, the second input 524 is coupled to the signal input 122 of the gating circuit 120 for receiving a clock signal, and the output 526 is coupled to the output 126 of the gating circuit 120. In the embodiment of FIG. 5, the gate 520 includes an AND gate, which may be implemented using a NAND gate and an inverter. However, it should be understood that the gate 520 is not limited to this embodiment.

[0043] In this embodiment, the first logic state of the enable signal is 1 and the second logic state of the enable signal is 0. When the enable signal is 1, the latch 510 latches a 1 on the falling edge of the clock signal and outputs a 1 to the first input 522 of the gate 520. The 1 at the first input 522 of the gate 520 causes the gate 520 to pass the clock signal at the second input 524 to the output 526 (and therefore the output 126 of the gating circuit 120). Thus, in this embodiment, the gating circuit 120 passes the clock signal when the enable signal is 1.

[0044] When the enable signal is a 0, the latch 510 latches a 0 on the falling edge of the clock signal and outputs a 0 to the first input 522 of the gate 520. The 0 at the first input 522 of the gate 520 causes the gate 520 to output a 0 at the output 526 (and therefore the output 126 of the gating circuit 120) regardless of the logic state of the clock signal at the second input 524 of the gate 520. This effectively blocks the clock signal at the second input 524 from the output 526, thereby gating the clock signal. Therefore, in this embodiment, the gating circuit 120 gates the clock signal when the enable signal is a 0. By latching the logic state of the enable signal at the falling edge of the clock signal, the latch 510 ensures that the gate 520 begins gating the clock signal when the clock signal is low (i.e., 0), helping to prevent glitches at the output 126 of the gating circuit 120.

[0045] It should be appreciated that the gating circuit 120 is not limited to the exemplary implementation shown in FIG. 5, and that the gating circuit 120 can be implemented using various configurations of one or more logic gates and one or more latches.

[0046] In certain aspects, one or more latches may be used to control the timing of input of the enable signal to the select input 338 of the multiplexer 330. In this regard, FIG. 6 illustrates one embodiment of a second latch 610 coupled between the output 516 of the latch 510 in the gating circuit 120 and the select input 338 of the multiplexer 330. In this embodiment, the second latch 610 has a first input 612, a second input 614, and an output 616. The first input 612 is coupled to the output 516 of the latch 510 in the gating circuit 120 and therefore receives the enable signal from the output 516 of the latch 510. The second input 614 is coupled to the clock source 115 (shown in FIG. 3) for receiving a clock signal, and the output 616 is coupled to the select input 338 of the multiplexer 330. In certain aspects, the second latch 610 is configured to latch the logic state of the enable signal on a rising edge of the clock signal and output the latched logic state of the enable signal to the select input 338 of the multiplexer 330 via an output 616. In these aspects, the second latch 610 may be implemented using a positive edge triggered flop or another type of latch.

[0047] In this embodiment, the multiplexer 330 can be configured to select the first input 332 when the enable signal is 1 and to select the second input 334 when the enable signal is 0. Thus, in this embodiment, when the gating circuit 120 passes the clock signal, the multiplexer 330 selects the first input 332, and when the gating circuit 120 gates the clock signal, the multiplexer 330 selects the second input 334. As described above, the gating circuit 120 in this embodiment starts gating the clock signal when the enable signal transitions from 1 to 0. In this embodiment, the second latch 610 delays the transition of the enable signal from 1 to 0 by up to a half period of the clock signal relative to the output 516 of the latch 510 in the gating circuit 120. As a result, when the gating circuit 120 starts gating the clock signal, the multiplexer 330 switches from the first input 332 to the second input 334 after a delay of approximately half a clock period. This helps to ensure that the multiplexer 330 does not switch from the first input 332 to the second input 334 before the clock signal has been gated.

[0048] FIG. 7 is a timing diagram illustrating one example of toggling in accordance with certain aspects of the disclosure. More specifically, FIG. 7 illustrates one example of an enable signal (labeled “Enable”) and a signal at the output 336 of the multiplexer 330 (labeled “Mux Out”). In the example of FIG. 7, when the enable signal is 1, the clock signal is ungated and when the enable signal is 0, the clock signal is gated. Therefore, in this example, during idle periods, the enable signal is 0. As shown in FIG. 7, the output 336 of the multiplexer 330 toggles between 1 and 0 over the idle period due to the toggling of the toggle circuit 320. In the example of FIG. 7, the output 336 of the multiplexer 330 toggles between 1 and 0 over the idle period due to the toggling of the toggle circuit 320. In the example of FIG. 7, the output 336 of the multiplexer 330 is 0 only during odd idle periods (e.g., t 1 , t 3 ,...), and is 1 (i.e., high) during even idle periods (e.g., t 2 , t4 , ...) is 0 (i.e., low). However, it should be understood that the present disclosure is not limited to this example.

[0049] Assuming that the accumulated duration of idle periods during which input 132 of clock path 130 is at 0 (i.e., held low) is approximately equal to the accumulated duration of idle periods during which input 132 of clock path 130 is at 1 (i.e., held high), input 132 of clock path 130 will spend approximately equal amounts of time held low and time held high in idle mode, which balances the aging of transistors in clock path 130. Balanced (i.e., symmetric) aging reduces duty cycle shifts in clock path 130.

[0050] However, in some cases, the accumulated duration of idle periods during which input 132 of clock path 130 is a 0 (i.e., held low) is not approximately equal to the accumulated duration of idle periods during which input 132 of clock path 130 is a 1 (i.e., held high). This can lead to a duty cycle shift in clock path 130 that drives the duty cycle of the clock signal at output 134 of clock path 130 outside of an acceptable range. Duty cycle shifts in clock path 130 may also be caused by environmental conditions and / or other factors.

[0051] To address this, the system may include circuitry configured to disable (i.e., override) toggling in idle mode if a duty cycle shift in clock path 130 drives the clock signal at output 134 of clock path 130 out of tolerance. In this case, the circuitry may hold input 132 of clock path 130 high or low depending on whether the accumulated duration of idle periods during which input 132 of clock path 130 is held low is longer or shorter than the accumulated duration of idle periods during which input 132 of clock path 130 is held high. For example, if a duty cycle shift in clock path 130 is caused by the accumulated duration of idle periods during which input 132 of clock path 130 is held low is longer than the accumulated duration of idle periods during which input 132 of clock path 130 is held high, the circuitry may hold input 132 of clock path 130 high in idle mode to move the duty cycle shift in the opposite direction. Once the duty cycle of the clock signal returns to within the acceptable range, the circuit can re-enable toggling in idle mode.

[0052] 8 illustrates one embodiment of a system 805 that includes the gating circuit 120, toggle circuit 320, multiplexer 330, and clock path 130 discussed above. System 805 also includes a duty cycle monitor 810 and a control circuit 820, according to certain aspects. In this embodiment, toggle circuit 320 also has a reset input 832 and a set input 834.

[0053] In one embodiment, the reset input 832 is asserted by inputting a 1 to the reset input 832, and the set input 834 is asserted by inputting a 1 to the set input 834. However, it should be understood that the present disclosure is not limited to this embodiment. When the reset input 832 is asserted, the toggle circuit 320 disables (i.e., overrides) toggling and outputs a 0 at the output 324. When the set input 834 is asserted, the toggle circuit 320 disables (i.e., overrides) toggling and outputs a 1 at the output 324. When neither the reset input 832 nor the set input 834 is asserted, the toggle circuit 320 enables toggling and operates in the manner described above with reference to FIG. 3.

[0054] Duty cycle monitor 810 has an input 812 and an output 814. Input 812 may be coupled to output 134 of clock path 130. In a particular aspect, duty cycle monitor 810 is configured to measure the duty cycle of the clock signal at output 134 of clock path 130 and output a measurement signal at output 814 indicative of the measured duty cycle. Because duty cycle monitor 810 is coupled, in this example, to output 134 of clock path 130, duty cycle monitor 810 is able to measure a shift in the duty cycle of the clock signal caused by clock path 130.

[0055] The control circuit 820 has an input 822, a first output 824, and a second output 826. The input 822 is coupled to the output of the duty cycle monitor 810, the first output 824 is coupled to a reset input 832 of the toggle circuit 320, and the second output 826 is coupled to a set input 834 of the toggle circuit 320.

[0056] During operation, the control circuit 820 receives the measurement signal from the duty cycle monitor 810 via the input 822. The control circuit 820 can then determine whether the measurement signal is within an acceptable range. The acceptable range may correspond to a range of duty cycles that do not result in a timing violation in the circuit 140. In one embodiment, the acceptable range may be defined by a first threshold and a second threshold. In this embodiment, the control circuit 820 can determine that the measurement signal is within the acceptable range if the measurement signal is between the first and second thresholds. If the measurement is between the first and second thresholds, the control circuit 820 deasserts both the reset input 832 and the set input 834 of the toggle circuit 320. In this case, the toggle circuit 320 toggles the output 324 as described above with reference to FIG. 3.

[0057] In this example, the first threshold may define an upper limit of a tolerance range, and if the measurement signal exceeds the first threshold, the duty cycle is deemed too high. When the measurement signal exceeds the first threshold, the control circuit 820 asserts one of the reset input 832 and the set input 834. For example, if the measurement signal exceeds the first threshold when the accumulated duration of idle periods during which the input 132 of the clock path 130 is held low is longer than the accumulated duration of idle periods during which the input 132 of the clock path 130 is held high, the control circuit 820 may hold the input 132 of the clock path 130 high by asserting the set input 834. On the other hand, if the measurement signal exceeds the first threshold when the accumulated duration of idle periods during which input 132 of clock path 130 is held low is less than the accumulated duration of idle periods during which input 132 of clock path 130 is held high, control circuit 820 can hold input 132 of clock path 130 low by asserting reset input 832. Whether the measurement signal exceeds the first threshold when the accumulated duration of idle periods during which input 132 of clock path 130 is held low is greater than or less than the accumulated duration of idle periods during which input 132 of clock path 130 is held high can depend, for example, on the number of clock buffers in clock path 130 and / or the implementation of the clock buffers in clock path 130.

[0058] In this example, the second threshold may define a lower limit of the tolerance range, and if the measurement signal falls below the second threshold, the duty cycle of the clock signal is deemed too low. When the measurement signal falls below the second threshold, control circuit 820 asserts one of reset input 832 and set input 834. For example, if the measurement signal falls below the second threshold when the accumulated duration of idle periods during which input 132 of clock path 130 is held low is longer than the accumulated duration of idle periods during which input 132 of clock path 130 is held high, control circuit 820 may hold input 132 of clock path 130 high by asserting set input 834. On the other hand, if the measurement signal falls below the second threshold when the accumulated duration of idle periods during which input 132 of clock path 130 is held low is less than the accumulated duration of idle periods during which input 132 of clock path 130 is held high, control circuit 820 can hold input 132 of clock path 130 low by asserting reset input 832. Whether the measurement signal falls below the second threshold when the accumulated duration of idle periods during which input 132 of clock path 130 is held low is greater than or less than the accumulated duration of idle periods during which input 132 of clock path 130 is held high can depend, for example, on the number of clock buffers in clock path 130 and / or the implementation of the clock buffers in clock path 130.

[0059] In this example, control circuit 820 asserts a different one of reset input 832 and set input 834 when the measurement signal is above a first threshold and when the measurement signal is below a second threshold. For example, if control circuit 820 asserts reset input 832 when the measurement signal is above the first threshold, control circuit 820 asserts set input 834 when the measurement signal is below the second threshold. On the other hand, if control circuit 820 asserts set input 834 when the measurement signal is above the first threshold, control circuit 820 asserts reset input 832 when the measurement signal is below the second threshold.

[0060] 9 illustrates a method 900 for balancing aging in a clock path, which may correspond to clock path 130.

[0061] An enable signal is received at block 910. For example, the enable signal may be received by the gating circuit 120, the toggle circuit 320, and / or the multiplexer 330.

[0062] If the enable signal has a first logic state, then the clock signal is passed to the clock path, at block 920. The clock signal may be passed by the gating circuit 120 and / or the multiplexer 330.

[0063] If the enable signal has a second logic state, the clock signal is gated in block 930. For example, the clock signal may be gated by the gating circuit 120. The first logic state may be 1 and the second logic state may be 0, or vice versa.

[0064] In block 940, the logic state of the toggle circuit is toggled in response to an edge of the enable signal. For example, the logic state of the toggle circuit may be toggled by the toggle circuit 320. The edge of the enable signal may be a rising edge or a falling edge.

[0065] If the clock signal is gated, the logic state of the toggle circuit is passed to the clock path in block 950. For example, the logic state of the toggle circuit may be passed to the clock path by multiplexer 330.

[0066] The power management circuit 160 and the control circuit 620 may each be implemented using a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete hardware components (e.g., logic gates), or any combination thereof, designed to perform the functions described herein. The functions described herein may be performed by a processor executing software that contains code for performing those functions. The software may be stored on a computer readable storage medium, such as a RAM, a ROM, an EEPROM, an optical disk, and / or a magnetic disk.

[0067] Example implementations are described in the following numbered clauses. 1. An apparatus comprising: a gating circuit having an enable input, a signal input, and an output, the enable input configured to receive an enable signal; a toggle circuit having an output, the toggle circuit configured to toggle a logic state at an output of the toggle circuit based on an enable signal; a multiplexer having a first input, a second input, and an output, the first input of the multiplexer being coupled to the output of the gating circuit and the second input of the multiplexer being coupled to the output of the toggle circuit, the multiplexer comprising: selecting one of the first input and the second input based on an enable signal; a multiplexer configured to couple a selected one of the first input and the second input to an output of the multiplexer. 2. The apparatus of clause 1, wherein the signal input of the gating circuit is coupled to a clock source. 3. The apparatus of clause 2, wherein the output of the multiplexer is coupled to a clock path that includes a clock buffer coupled in series. 4. The apparatus of any one of clauses 1-3, wherein the toggle circuit is configured to toggle a logic state at an output of the toggle circuit in response to an edge of the enable signal. 5. a gating circuit configured to receive a clock signal at a signal input, to pass the clock signal to an output of the gating circuit when the enable signal is high, and to gate the clock signal when the enable signal is low; the multiplexer is configured to select the first input when the enable signal is high and to select the second input when the enable signal is low; Any one of the devices in clauses 1 to 4. 6. a gating circuit configured to receive a clock signal at a signal input, to pass the clock signal to an output of the gating circuit when the enable signal is low, and to gate the clock signal when the enable signal is high; the multiplexer is configured to select the first input when the enable signal is low and to select the second input when the enable signal is high; Any one of the devices in clauses 1 to 4. 7. Toggle circuit, a flop having a data input, a clock input, and an output, the clock input of the flop being configured to receive an enable signal, and the output of the flop being coupled to an output of the toggle circuit; The apparatus of any one of clauses 1-6, comprising an inverter coupled between an output of the flop and a data input of the flop. 8. Toggle circuit, The apparatus of any one of clauses 1-6, comprising a flop having a data input, a clock input, a first output, and a second output, wherein the clock input of the flop is configured to receive an enable signal, the first output is coupled to the output of the toggle circuit, and the second output is coupled to the data input, and the first output and the second output are complementary. 9. a clock path coupled to the output of the multiplexer, the clock path including serially coupled clock buffers; a duty cycle monitor coupled to the clock path; a control circuit coupled to the duty cycle monitor and coupled to at least one of a set input and a reset input of the toggle circuit. Any one of the devices in clauses 1 to 8. 10. a duty cycle monitor configured to measure a duty cycle of a clock signal on the clock path and output a measurement signal indicative of the measured duty cycle to the control circuit; the control circuit is configured to assert one of the set and reset inputs of the toggle circuit when the measurement signal exceeds a threshold; Apparatus of clause 9. 11. a duty cycle monitor configured to measure a duty cycle of a clock signal on the clock path and output a measurement signal indicative of the measured duty cycle to the control circuit; the control circuit is configured to assert one of the set and reset inputs of the toggle circuit when the measurement signal is below a threshold; Apparatus of clause 9. 12. a duty cycle monitor configured to measure a duty cycle of a clock signal on the clock path and output a measurement signal indicative of the measured duty cycle to the control circuit; the control circuit is configured to assert a reset input of the toggle circuit when the measurement signal is above a first threshold and to assert a set input of the toggle circuit when the measurement signal is below a second threshold. Apparatus of clause 9. 13. a duty cycle monitor configured to measure a duty cycle of a clock signal on the clock path and output a measurement signal indicative of the measured duty cycle to the control circuit; the control circuit is configured to assert a set input of the toggle circuit when the measurement signal is above a first threshold and to assert a reset input of the toggle circuit when the measurement signal is below a second threshold. Apparatus of clause 9. 14. The gating circuit is a latch having a first input, a second input, and an output, the first input of the latch being coupled to an enable input of the gating circuit and the second input of the latch being coupled to a signal input of the gating circuit; 14. The apparatus of any one of clauses 1-13, comprising: a gate having a first input, a second input, and an output, wherein the first input of the gate is coupled to the output of the latch, the second input of the latch is coupled to a signal input of the gating circuit, and the output of the gate is coupled to the output of the gating circuit. 15. The apparatus of clause 14, wherein the gate comprises an AND gate. 16. A method for balancing aging in a clock path, comprising: Receiving an enable signal; passing the clock signal to the clock path if the enable signal has a first logic state; gating the clock signal when the enable signal has a second logic state; toggling a logic state of the toggle circuit in response to an edge of the enable signal; and passing a logic state of the toggle circuit to the clock path if the clock signal is gated. 17. The method of clause 16, wherein the first logic state is one and the second logic state is zero. 18. The method of clause 16, wherein the first logic state is 0 and the second logic state is 1. 19. The method of any one of clauses 16-18, wherein the edge of the enable signal is a rising edge. 20. The method of any one of clauses 16-18, wherein the edge of the enable signal is a falling edge.

[0068] Within the scope of this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect electrical coupling between two structures.

[0069] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. 1. An apparatus comprising: a gating circuit having an enable input, a signal input, and an output, the enable input configured to receive an enable signal; a toggle circuit having an output, the toggle circuit configured to toggle a logic state at the output of the toggle circuit based on the enable signal; a multiplexer having a first input, a second input, and an output, the first input of the multiplexer being coupled to the output of the gating circuit and the second input of the multiplexer being coupled to the output of the toggle circuit, the multiplexer comprising: selecting one of the first input and the second input based on the enable signal; a multiplexer configured to couple the selected one of the first input and the second input to the output of the multiplexer; An apparatus comprising:

2. The apparatus of claim 1 , wherein the signal input of the gating circuit is coupled to a clock source.

3. 3. The apparatus of claim 2, wherein the output of the multiplexer is coupled to a clock path that includes serially coupled clock buffers.

4. 2. The apparatus of claim 1, wherein the toggle circuit is configured to toggle the logic state at the output of the toggle circuit in response to an edge of the enable signal.

5. the gating circuit is configured to receive a clock signal at the signal input, to pass the clock signal to the output of the gating circuit when the enable signal is high, and to gate the clock signal when the enable signal is low; the multiplexer is configured to select the first input when the enable signal is high and to select the second input when the enable signal is low.

2. The apparatus of claim 1.

6. the gating circuit is configured to receive a clock signal at the signal input, to pass the clock signal to the output of the gating circuit when the enable signal is low, and to gate the clock signal when the enable signal is high; the multiplexer is configured to select the first input when the enable signal is low and to select the second input when the enable signal is high.

2. The apparatus of claim 1.

7. The toggle circuit, a flop having a data input, a clock input, and an output, the clock input of the flop configured to receive the enable signal, and the output of the flop coupled to the output of the toggle circuit; an inverter coupled between the output of the flop and the data input of the flop; The apparatus of claim 1 , comprising:

8. The toggle circuit, 2. The apparatus of claim 1, comprising: a flop having a data input, a clock input, a first output, and a second output, wherein the clock input of the flop is configured to receive the enable signal, the first output is coupled to the output of the toggle circuit, and the second output is coupled to the data input, and the first output and the second output are complementary.

9. a clock path coupled to the output of the multiplexer, the clock path including serially coupled clock buffers; a duty cycle monitor coupled to the clock path; a control circuit coupled to the duty cycle monitor and to at least one of a set input and a reset input of the toggle circuit; The apparatus of claim 1 further comprising:

10. the duty cycle monitor is configured to measure a duty cycle of a clock signal on the clock path and output a measurement signal indicative of the measured duty cycle to the control circuit; the control circuitry is configured to assert one of the set input and the reset input of the toggle circuit when the measurement signal exceeds a threshold.

10. The apparatus of claim 9.

11. the duty cycle monitor is configured to measure a duty cycle of a clock signal on the clock path and output a measurement signal indicative of the measured duty cycle to the control circuit; the control circuitry is configured to assert one of the set input and the reset input of the toggle circuit when the measurement signal is below a threshold.

10. The apparatus of claim 9.

12. the duty cycle monitor is configured to measure a duty cycle of a clock signal on the clock path and output a measurement signal indicative of the measured duty cycle to the control circuit; the control circuitry is configured to assert the reset input of the toggle circuit when the measurement signal is above a first threshold and to assert the set input of the toggle circuit when the measurement signal is below a second threshold.

10. The apparatus of claim 9.

13. the duty cycle monitor is configured to measure a duty cycle of a clock signal on the clock path and output a measurement signal indicative of the measured duty cycle to the control circuit; the control circuitry is configured to assert the set input of the toggle circuit when the measurement signal is above a first threshold and to assert the reset input of the toggle circuit when the measurement signal is below a second threshold.

10. The apparatus of claim 9.

14. The gating circuit comprises: a latch having a first input, a second input, and an output, the first input of the latch being coupled to the enable input of the gating circuit and the second input of the latch being coupled to the signal input of the gating circuit; a gate having a first input, a second input, and an output, the first input of the gate being coupled to the output of the latch, the second input of the latch being coupled to the signal input of the gating circuit, and the output of the gate being coupled to the output of the gating circuit; The apparatus of claim 1 , comprising:

15. The apparatus of claim 14 , wherein the gate comprises an AND gate.

16. 1. A method for balancing aging in a clock path, comprising: Receiving an enable signal; passing a clock signal to the clock path if the enable signal has a first logic state; gating the clock signal when the enable signal has a second logic state; toggling a logic state of a toggle circuit in response to an edge of the enable signal; passing the logic state of the toggle circuit to the clock path when the clock signal is gated; A method comprising:

17. 17. The method of claim 16, wherein the first logic state is one and the second logic state is zero.

18. 17. The method of claim 16, wherein the first logic state is zero and the second logic state is one.

19. 17. The method of claim 16, wherein the edge of the enable signal is a rising edge.

20. 17. The method of claim 16, wherein the edge of the enable signal is a falling edge.

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