SYSTEM AND METHOD FOR REDUCING REFLECTED POWER AFTER A STATE TRANSITION - Patent application

Abstract

A method is described for reducing reflected power associated with a high frequency (HF) radio frequency (RF) generator after a transition state. The method includes controlling the HF RF generator to divide a state of an HF RF signal into a plurality of sub-states. The plurality of sub-states includes a first sub-state and a second sub-state. The method further includes controlling the HF RF generator to apply a first reference high frequency value in the first sub-state and a second reference high frequency value in the second sub-state. The method includes applying a first set of HF offset values ​​from the first reference high frequency value in the first sub-state and applying a second set of HF offset values ​​from the second reference high frequency value in the second sub-state.

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE The embodiments described in this disclosure relate to systems and methods for reducing reflected power after a state transition. [Background technology]

[0002] The discussion of the background art provided herein is intended to generally present the context of the present disclosure. The work of the presently named inventors, to the extent that their work is described in this background art section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted expressly or impliedly as prior art to the present disclosure.

[0003] The plasma tool includes a radio frequency (RF) generator, a match, and a plasma reactor. The RF generator is coupled to the plasma reactor through the match. A semiconductor wafer is placed in the plasma reactor for processing. The RF generator generates an RF signal, which is provided to the plasma reactor through the match. In addition to the RF signal, a process gas is provided to the plasma reactor for processing the semiconductor wafer. However, power is reflected from the plasma reactor back to the HF RF generator. This reduces the efficiency of the processing of the semiconductor wafer.

[0004] It is in this context that the embodiments described in this disclosure are made. Summary of the Invention

[0005] The embodiments of the present disclosure provide a system and method for reflected power after a state transition. It should be appreciated that the embodiments can be implemented in numerous ways, such as a process, an apparatus, a system, a piece of hardware, or a method on a computer-readable medium. Some embodiments are described below.

[0006] In one embodiment, a method for reducing reflected power associated with a high frequency (HF) radio frequency (RF) generator after a transition state is described. The method includes controlling the HF RF generator to divide a state of an HF RF signal into a plurality of sub-states. The plurality of sub-states includes a first sub-state and a second sub-state. The method further includes controlling the HF RF generator to apply a first reference high frequency value in the first sub-state and a second reference high frequency value in the second sub-state. The method includes applying a first set of HF offset values ​​from the first reference high frequency value in the first sub-state and applying a second set of HF offset values ​​from the second reference high frequency value in the second sub-state.

[0007] In one embodiment, a controller for reducing reflected power associated with an HF RF generator after a transition state is described. The controller includes a processor that controls the HF RF generator to divide a state of the HF RF signal into a plurality of sub-states. The plurality of sub-states includes a first sub-state and a second sub-state. The processor further controls the HF RF generator to apply a first reference high frequency value in the first sub-state and a second reference high frequency value in the second sub-state. The processor applies a first set of HF offset values ​​from the first reference high frequency value in the first sub-state. The processor applies a second set of HF offset values ​​from the second reference high frequency value in the second sub-state. The controller includes a memory device coupled to the processor.

[0008] In one embodiment, a system for reducing reflected power associated with an HF RF generator after a transition state is described. The system includes a LF RF generator that generates a low frequency (LF) RF signal. The HF RF generator generates the HF RF signal. The system includes a matcher coupled to the LF RF generator and the HF RF generator. The system includes a controller coupled to the LF RF generator and the HF RF generator. The controller controls the HF RF generator to divide a state of the HF RF signal into a plurality of sub-states. The plurality of sub-states includes a first sub-state and a second sub-state. The controller controls the HF RF generator to apply a first reference high frequency value in the first sub-state and a second reference high frequency value in the second sub-state. The controller applies a first set of HF offset values ​​from the first reference high frequency value in the first sub-state. The controller applies a second set of HF offset values ​​from the second reference high frequency value in the second sub-state.

[0009] Some advantages of the systems and methods described herein include reducing the reflected power after a state transition. The state transition causes a disturbance in the plasma impedance. As a result of the disturbance, a larger amount of power is reflected toward the HF RF generator immediately after the state transition. The reflected larger amount of power may be referred to herein as a power glitch. In order to reduce the amount of reflected power in a precise and detailed manner, the state immediately after the state transition is divided into a predetermined number of sub-states. The division takes into account the impedance change that occurs over the duration of the state. For each sub-state, a reference high frequency value and a number of HF offsets are determined to reduce the power reflected toward the HF RF generator after the state transition. By dividing the state into a predetermined number of states and by applying the reference high frequency value and the HF offset separately to each of the sub-states, the power reflected toward the HF RF generator is reduced in a precise manner. For example, the sub-states include a first sub-state and a second sub-state. In this example, by determining a reference high frequency value for the second sub-state, the power reflected towards the HF RF generator is taken into account in a more accurate manner.

[0010] Certain other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0011] The embodiments are understood by reference to the following description in conjunction with the accompanying drawings.

[0012] [Figure 1] FIG. 1 is a diagram of an embodiment of a plasma system to illustrate the use of a low frequency (LF) radio frequency (RF) generator and a high frequency (HF) RF generator.

[0013] [Figure 2A] 1 is a graph showing a clock signal.

[0014] [Figure 2B] 1 is a graph to illustrate multi-state pulsing of an RF signal generated by a LF RF generator and an HF RF generator.

[0015] [Figure 2C] 1 is a graph to illustrate a method for reducing power glitches after a state transition.

[0016] [Diagram 3] 1 is a graph illustrating a voltage signal generated by a voltage (V) sensor.

[0017] [Figure 4] 1 is a graph illustrating one embodiment of a method for reducing power glitches. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The following embodiments describe a system and method for reducing high frequency (HF) radio frequency (RF) reflected power after a state transition in a detailed and precise manner. It will be apparent that the present embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail in order not to unnecessarily obscure the present embodiments.

[0019] 1 is a diagram of one embodiment of a plasma system 100 to illustrate the use of a low frequency (LF) RF generator 102 and an HF RF generator 104. System 100 includes LF RF generator 102, HF RF generator 104, a host computer 106, a matching box 107, and a plasma chamber 108. Plasma system 100 further includes a voltage (V) sensor 110 and a power (P) sensor 112.

[0020] As an example, the LF RF generator 102 has an operating frequency of 400 kilohertz (kHz) or 2 megahertz (MHz). Also, as an example, the HF RF generator 104 has an operating frequency of 27 MHz or 60 MHz. Examples of the host computer 106 include a desktop, a laptop, a tablet, a controller, and a smartphone. An example of the matcher 107 is an impedance matching circuit or an impedance matcher or a matcher circuit or an impedance matching network. For illustration, the matcher 107 includes a first branch circuit and a second branch circuit. Each branch circuit includes one or more matcher network elements. Examples of the matcher network elements include a capacitor, an inductor, and a resistor. An example of the plasma chamber 108 is a capacitively coupled plasma (CCP) chamber.

[0021] The host computer 106 includes a processor 114 and a memory device 116. Examples of the processor 114 include a central processing unit (CPU), an application specific integrated circuit (ASIC), and a programmable logic device (PLD). Examples of the memory device 116 include read-only memory and random access memory.

[0022] The plasma chamber 108 includes a lower electrode LE and an upper electrode UE. A gap is formed between the lower electrode LE and the upper electrode UE, and a substrate S is disposed in the gap on an upper surface of the lower electrode LE for processing. An example of the substrate S includes a semiconductor wafer on which an integrated circuit is fabricated.

[0023] The processor 114 is coupled to the memory device 116. The processor 114 is coupled to the LF RF generator 102 via a transmission cable 118 and to the HF RF generator 104 via a transmission cable 120. An example of a transmission cable includes an electrical cable that transfers data in a parallel or serial manner or using a Universal Serial Bus (USB) protocol. The LF RF generator 102 has an output 122 that is coupled to an input 126 of the matcher 107 via an RF cable 124. Similarly, the HF RF generator 104 has an output 128 that is coupled to an input 132 of the matcher 107 via an RF cable 130. The matcher 107 has an output 134 that is coupled to the lower electrode LE via an RF transmission line 136. A first branch of the matching circuit 107 is coupled between the input 126 and the output 134, and a second branch of the matching circuit 107 is coupled between the input 132 and the output 134. The upper electrode UE is coupled to ground potential.

[0024] The V sensor 110 is coupled to the processor 114 via a transfer cable 138, and the P sensor 112 is coupled to the processor 114 via a transfer cable 140. The V sensor 110 is coupled to an output 134 of the matcher 134. The P sensor 112 is also coupled to an output 128 of the HF RF generator 104.

[0025] The processor 114 generates a recipe signal 142, which includes a low frequency and one or more power levels of an RF signal 150 to be generated by the LF RF generator 102. As an example, the low frequency is equal to the operating frequency of the LF RF generator 102. The processor 114 sends the recipe signal 142 to the LF RF generator 102 via the transmission cable 118. The processor 114 also generates a recipe signal 144, which includes a high frequency and one or more power levels of an RF signal 152 to be generated by the HF RF generator 104. As an example, the high frequency is equal to the operating frequency of the HF RF generator 104. The processor 114 sends the recipe signal 144 to the HF RF generator 104 via the transmission cable 120.

[0026] Upon receiving recipe signal 142, LF RF generator 102 generates an RF signal 150 having a low frequency and one or more power levels as indicated in recipe signal 142. LF RF generator 102 sends RF signal 150 to matcher 107 via output 122, RF cable 124, and input 126. Similarly, upon receiving recipe signal 144, HF RF generator 104 generates an RF signal 152 having a high frequency and one or more power levels as indicated in recipe signal 144. HF RF generator 104 sends RF signal 152 to matcher 107 via output 128, RF cable 130, and input 132.

[0027] Upon receiving RF signal 150, the first branch of matcher 107 matches the impedance of a load coupled to output 134 with the impedance of a source coupled to input 126 to modify the impedance of RF signal 150 to provide a first modified RF signal. An example of a load coupled to output 134 includes RF transmission line 136 and plasma chamber 108. An example of a source coupled to input 126 includes RF cable 124 and LF RF generator 102. Similarly, upon receiving RF signal 152, the second branch of matcher 107 matches the impedance of a load coupled to output 134 of matcher 107 with the impedance of a source coupled to input 132 of matcher 107 to modify the impedance of RF signal 152 to provide a second modified RF signal.

[0028] The matcher 107 combines, such as sums, the first modified RF signal and the second modified RF signal to output a modified RF signal 154 at the output 134. The modified RF signal 154 is sent from the output 134 to the lower electrode LE via an RF transmission line 136. When one or more process gases, such as a fluorine-containing gas, an oxygen-containing gas, or a nitrogen-containing gas, are supplied to the gap between the lower electrode LE and the upper electrode UE in addition to the modified RF signal 154, a plasma is struck or maintained in the gap. The plasma processes the substrate S. Examples of processing the substrate S include etching features in the substrate S, depositing material on the substrate S, and cleaning the substrate S.

[0029] While the substrate S is being processed, the V sensor 110 measures the voltage at the output 134, outputs a voltage signal 156, and sends the voltage signal 156 to the processor 114 via the transfer cable 138. Similarly, while the substrate S is being processed, the P sensor 112 measures the power, such as transmitted power or reflected power, at the output 134, outputs a power signal 158, and sends the power signal 158 to the processor 114 via the transfer cable 140.

[0030] In one embodiment, the V sensor 110 is coupled at any point on the RF transmission line 136.

[0031] In one embodiment, the P sensor 112 is coupled at any point on the RF cable 130.

[0032] 2A is one embodiment of a graph 200 to illustrate a clock signal 202. As an example, the clock signal 202 is generated by the processor 114 (FIG. 1). The x-axis of the graph 200 plots time t, ranging from time t0 to time t36. The y-axis of the graph 200 plots the voltage of the clock signal 202. The clock signal 202 periodically transitions between a logic level 1 and a logic level 0. Logic level 1 represents V5 volts, and logic level 0 represents V0 volts. The value V5 is greater than the value V0.

[0033] Clock signal 202 transitions from logic level 0 to logic level 1 at time t0 and remains at logic level 1 from time t0 to time t17. At time t17, clock signal 202 transitions from logic level 1 to logic level 0 and remains at logic level 0 from time t17 to time t34. The transitions between logic level 1 and logic level 0 repeat from time t34 to time t78. Clock signal 202 has cycle n from time t0 to time t34, followed consecutively by cycle (n+1) from time t34 to time t78, where n is a positive integer.

[0034] The processor 114 sends a clock signal 202 to the LF RF generator 102 via the transmission cable 118 and to the HF RF generator 104 via the transmission cable 120 to cause the generators 102 and 104 to operate in synchronization with the clock signal 202. For example, after receiving the clock signal 202, the LF RF generator 102 generates a set of states for the RF signal 150 during cycle n and repeats the set of states during cycle (n+1). Similarly, the HF RF generator 104 generates a set of states for the RF signal 152 during cycle n and repeats the set of states during cycle (n+1).

[0035] 2B is one embodiment of a graph 210 to illustrate multi-state pulsing of each of RF signals 150 and 152 (FIG. 1). Graph 210 plots an envelope 212 having a power level versus time t of RF signal 150 and an envelope 214 having a power level versus time t of RF signal 152. The power levels of RF signals 150 and 152 are plotted on the y-axis and time t is plotted on the x-axis. The x-axis of graph 210 is the same as the x-axis of graph 200 (FIG. 2A). The y-axis of graph 210 has power levels ranging from P0 to P12. The power levels plotted on the y-axis of graph 120 increase from P0 to P12. As an example, power level P0 is 0. Examples of the envelope of an RF signal include the peak-to-peak amplitude of the RF signal and the zero-to-peak amplitude of the RF signal.

[0036] During cycle n, envelope 212 has power level P12 from time t0 to time t4, and transitions from power level P12 to power level P0 at time t4. Additionally, during cycle n, envelope 212 attains power level P0 at time t6, and remains at power level P0 from time t6 to time t22. During cycle n, envelope 212 transitions from power level P0 to power level P5 at time t22, and attains power level P5 at time t23. Moreover, during cycle n, envelope 212 remains at power level P5 from time t23 to time t27, and transitions from power level P5 to power level P8 at time t27. During cycle n, envelope 212 attains power level P8 at time t28, and remains at power level P8 from time t28 to time t33. Also during cycle n, envelope 212 transitions from power level P8 to power level P12 at time t33, and achieves power level P12 at time t34. In this manner, power levels P12, P0, P5, and P8 of envelope 212 repeat during each cycle of clock signal 202 (FIG. 2A).

[0037] Similarly, during cycle n, envelope 214 has a power level P4 from time t0 to time t4, and transitions from power level P4 to power level P0 at time t4. Furthermore, during cycle n, envelope 214 attains power level P0 at time t6, and remains at power level P0 from time t6 to time t22. During cycle n, envelope 214 transitions from power level P0 to power level P2 at time t22, and attains power level P2 at time t23. Moreover, during cycle n, envelope 214 remains at power level P2 from time t23 to time t27, and transitions from power level P2 to power level P1 at time t27. During cycle n, envelope 214 attains power level P1 at time t28, and remains at power level P1 from time t28 to time t33. Also during cycle n, envelope 214 transitions from power level P1 to power level P4 at time t33, and achieves power level P4 at time t34. In this manner, power levels P4, P0, P2, and P1 of envelope 214 repeat during each cycle of clock signal 202 (FIG. 2A).

[0038] Each power level of the RF signal is a steady state of the RF signal. For example, power level P12 is a steady state S1x of RF signal 150, power level P0 is a steady state S2x of RF signal 150, power level P5 is a steady state S3x of RF signal 150, and power level P8 is a steady state S4x of RF signal 150. Similarly, as another example, power level P4 is a steady state S1y of RF signal 152, power level P0 is a steady state S2y of RF signal 152, power level P2 is a steady state S3y of RF signal 152, and power level P1 is a steady state S4y of RF signal 152.

[0039] The transition from steady state S2x to steady state S3x causes a power glitch in the delivered power associated with HF RF generator 104 (FIG. 1). For example, there is an increase in high frequency reflected power caused by the transition from steady state S2x to steady state S3x. The high frequency reflected power is the power reflected from plasma chamber 108 to HF RF generator 104 via RF transmission line 136, matching box 107, and RF cable 130. The delivered power of HF RF generator 104 is the difference between the delivered power of HF RF generator 104 and the high frequency reflected power. The delivered power of HF RF generator 104 is the power of RF signal 152, which is delivered from HF RF generator 104 to plasma chamber 108 via RF cable 130, matching box 107, and RF transmission line 136.

[0040] The transition from the steady state S2y to the steady state S3y is referred to herein as a transition state S23y or state transition. As an example, during the transition state, the power value of the envelope of the RF signal changes more frequently compared to the changes in the power value of the envelope of the RF signal during the steady state. As another example, during the steady state, the slope of the power level of the RF signal is substantially zero or zero. As yet another example, the power value of the envelope of the RF signal during the steady state is within a predetermined range, and the power value of the envelope of the RF signal during the transition state is outside the predetermined range. As another example, the power value of the steady state S2y is within a first predetermined range, the power value of the steady state S3y is within a second predetermined range, and the power value of the transition state S23y is outside the first and second predetermined ranges. For illustrative purposes, the power value of the transition state S23y is greater than the power value of the steady state S2y and less than the power value of the steady state S3y.

[0041] 2C is an embodiment of a graph 220 to illustrate a method for reducing power glitches. The graph 220 includes an envelope 214 versus time t. The graph 220 plots the power level of the envelope 214 of the RF signal 152 on the y-axis and time t on the x-axis. The processor 114 identifies the transition state S23y as having a value outside a predetermined range, such as a first predetermined range or a second predetermined range, and further identifies the steady state S3y as a state that immediately follows the transition state S23y and has a value within the predetermined range.

[0042] The processor 114 controls the HF RF generator 104 to divide the steady state S3y and the transition state S23y into a predetermined number of substates, such as substate S3ay and substate S3by. For example, the processor 114 generates a recipe signal 144 (FIG. 1) including information about the two substates S3ay and S3by, such as a first power level of the substate S3ay, a second power level of the substate S3by, a first duty cycle of occurrence of the substate S3ay, and a second duty cycle of occurrence of the substate S3by. Moreover, in this example, the information about the two substates S3ay and S3by includes a first reference high frequency value HF0 for the substate S3ay, a second reference high frequency value HF0' for the substate S3by, a first set of HF offset values ​​for the substate S3ay to be applied to the first high reference frequency value, and a second set of HF offset values ​​for the substate S3by to be applied to the second high reference frequency value. For illustrative purposes, the value HF0 is different from the value HF0', such as being greater than or less than the value HF0'. As another illustrative example, the value HF0 is equal to the value HF0'. In this example, the information about the two sub-states S3ay and S3by includes a first duty cycle at which the first high reference frequency value HF0, the first set of HF offset values, and the second set of HF offset values ​​are to be applied by the HF RF generator 104. Furthermore, in this example, the information about the two sub-states S3ay and S3by includes a second duty cycle at which the second high reference frequency value HF0', the second set of HF offset values, and the second set of HF offset values ​​are to be applied by the HF RF generator 104. In this example, the first duty cycle is a time period for the occurrence of the sub-state S3ay, and the second duty cycle is a time period for the occurrence of the sub-state S3by. Also, in this example, the first power level of the sub-state S3ay is equal to the second power level of the sub-state S3by.

[0043] Further, in this example, the processor 114 reads, e.g., accesses, from the memory device 116, the first duty cycle, the second duty cycle, the first power level, the second power level, the first reference high frequency value HF0, the first set of HF offset values, and the second reference high frequency value HF0′, the second set of HF offset values. In this example, a correspondence, e.g., a one-to-one relationship, between the first reference high frequency value and the first set of HF offset values ​​is stored in the memory device 116. Also, in this example, a correspondence, e.g., a one-to-one relationship, between the second reference high frequency value and the second set of HF offset values ​​is stored in the memory device 116.

[0044] Continuing with this example, in response to receiving the recipe signal 144, the HF RF generator 104 generates an RF signal 152 having a first reference high frequency value HF0 and a first set of HF offset values ​​from the first reference high frequency value HF0 during a first duty cycle of each cycle n, (n+1), etc. of the clock signal 202 (FIG. 2). Also in this example, in response to receiving the recipe signal 144, the HF RF generator 104 generates an RF signal 152 having a second reference high frequency value HF0' and a second set of HF offset values ​​from the second reference high frequency value HF0' during a second duty cycle of each cycle n, (n+1), etc. of the clock signal 202. In this example, in response to receiving the recipe signal 144, the HF RF generator 104 generates an RF signal 152 having the same power level during sub-states S3ax and S3ay.

[0045] It should be noted that a combination of steady state S3y and transition state S23y may be referred to herein as a state. For example, a state includes a transition from steady state S2y to steady state S3y and includes steady state S3y. As another example, when the transition from steady state S2y to steady state S3y is vertical or substantially vertical, a state includes steady state S3y and transition state S23y.

[0046] An example of a duty cycle is a time period or a time interval or a time window. For illustrative purposes, the first duty cycle is 100 microseconds and the second duty cycle is 100 microseconds. As another example, the first duty cycle is smaller or larger than the second duty cycle. For further illustrative purposes, the first duty cycle is a time interval from time t22 to time t24.5 and the second duty cycle is a time interval from time t24.5 to time t27. Also, as an example, the predetermined number of sub-states are received from a user via an input device coupled to the processor 114. Examples of input devices include a keyboard, a stylus, a keypad, and a mouse. Also, as an example, the first and second duty cycles are received from a user via an input device. As another example, the first and second duty cycles are empirically determined by the processor 114 to reduce power reflected back towards the HF RF generator 104 and stored in the memory device 116 for access by the processor 114.

[0047] Also, by way of example, the first high reference frequency value HF0 and the first set of HF offset values ​​are empirically determined. For the sake of example, the processor 114 operates the HF RF generator 104 at a number of reference high frequency values ​​during bin 0, which will be described further below, and obtains a value of high frequency reflected power from the P sensor 112 (FIG. 1) for each of the reference high frequency values. In the example, the processor 114 calculates a statistical value, such as an average or median, from the value of high frequency reflected power for each of the reference high frequency values. In the example, the processor 114 determines that the reference high frequency value HF0 among the reference high frequency values ​​in bin 0 is the reference high frequency value for which the statistical value of high frequency reflected power is the minimum value among all statistical values ​​of high frequency reflected power. Further, in the example, bin 0 occurs during cycles (nm) of the clock signal 202 (FIG. 2), where m is an integer less than n.

[0048] As another example, any of the first set of HF offset values ​​is empirically determined in the same manner as the first high reference frequency value HF0, except that any of the first set of HF offset values ​​is determined for a corresponding bin of cycles (nm). For further illustration, the processor 114 operates the HF RF generator 104 at a plurality of HF offset values ​​during bin 1, which will be further described below, and obtains a value of high frequency reflected power from the P sensor 112 for each of the HF offset values. Also, in a further example, bin 1 occurs during cycles (nm) of the clock signal 202. In a further example, each of the HF offset values ​​is an offset relative to a reference high frequency value HF0, such as subtracting from or adding to the reference high frequency value HF0. In a further example, the processor 114 calculates a statistical value, such as an average or median, from the values ​​of high frequency reflected power for each of the HF offset values. In a further example, the processor 114 determines that one of the HF offset values ​​among the HF offset values ​​in bin 1 is the HF offset value for which the statistical value of high frequency reflected power is the minimum value among all statistical values ​​of high frequency reflected power. In a further example, the one of the HF offset values ​​is stored in the memory device 116 as one of the first set of HF offset values ​​for access by the processor 114 to control the HF RF generator 104 during bin 1 of cycles n, (n+1), etc.

[0049] Also, in a further example, the first set of HF offset values ​​are determined by the processor 114 to have an inverse or substantially inverse relationship with the voltage signal 156. In a further example, the voltage signal 156 has a positive value during the time period between time t22 and time t24.5, and the HF offsets HF(-2), HF(-3), HF(-4), HF(-3), and HF(-2) for bins 1-5 are negatively offset relative to the reference high frequency value HF0. The HF offsets HF(-2), HF(-3), HF(-4), and HF(-2) are subtracted from the reference high frequency value HF0. In a further example, the voltage signal 156 has a negative value during the time period between time t24.5 and time t27, and the HF offsets HF(1), HF(2), HF(3), HF(4), HF(2), and HF(1) for bins 7-12 are positively offset relative to the reference high frequency value HF0. The HF offsets HF(1), HF(2), HF(3), and HF(4) are added to the reference high frequency value HF0.

[0050] Further, as an example, the second high reference frequency value HF0' and the second set of HF offset values ​​are empirically determined. For the sake of illustration, the processor 114 operates the HF RF generator 104 at a number of reference high frequency values ​​during bin 0', which will be described further below, and obtains a value of the high frequency reflected power from the P sensor 112 for each of the reference high frequency values. In the example, the processor 114 calculates a statistical value, such as an average or a median, from the value of the high frequency reflected power for each of the reference high frequency values. In the example, the processor 114 determines that the reference high frequency value HF0' among the reference high frequency values ​​in bin 0' is the reference high frequency value for which the statistical value of the high frequency reflected power is the minimum value among all the statistical values ​​of the high frequency reflected power. Further, in the example, bin 0' occurs during cycle (nm) of the clock signal 202.

[0051] As another example, any of the second set of HF offset values ​​is empirically determined in the same manner as the second high reference frequency value HF0', except that any of the second set of HF offset values ​​is determined for a corresponding bin of cycles (nm). For further illustration, the processor 114 operates the HF RF generator 104 at a plurality of HF offset values ​​during bin 1', which will be described further below, and obtains a value of high frequency reflected power from the P sensor 112 for each of the HF offset values. In a further example, bin 1' occurs during cycles (nm) of the clock signal 202. Also, in a further example, each of the HF offset values ​​is an offset, such as a subtraction from or an addition to the reference high frequency value HF0'. In a further example, the processor 114 calculates a statistical value, such as an average or median, from the values ​​of high frequency reflected power for each of the HF offset values. In a further example, the processor 114 determines that one of the HF offset values ​​among the HF offset values ​​in Bin 1' is the HF offset value for which the statistical value of the high frequency reflected power is the minimum value among all statistical values ​​of the high frequency reflected power. In a further example, the one of the HF offset values ​​is stored in the memory device 116 as one of the second set of HF offset values ​​for access by the processor 114 to control the HF RF generator 104 during Bin 1' of cycles n, (n+1), etc.

[0052] Also, in a further example, the second set of HF offset values ​​are determined by the processor 114 to have an inverse or substantially inverse relationship with the voltage signal 156. In a further example, the HF offsets HF(-1), HF(-2), HF(-3), HF(-2), and HF0 for bins 1'-5' are negatively offset relative to the reference high frequency value HF0'. The HF offsets HF(-2), HF(-3), HF(-2), and HF0 are subtracted from the reference high frequency value HF0'. In a further example, the HF offsets HF(2), HF(3), HF(4), HF(5), HF(4), and HF(1) for bins 7'-12' are positively offset relative to the reference high frequency value HF0'. The HF offsets HF(1), HF(2), HF(3), HF(4), and HF(5) are added to the reference high frequency value HF0'.

[0053] In one embodiment, the information about the two sub-states S3ay and S3by includes a hold-off period for each sub-state. For example, the information about the two sub-states includes a hold-off period 252 in sub-state S3ay, an aperture window 258 in sub-state S3ay, a hold-off period 254 in sub-state S3by, and an aperture window 260 in sub-state S3by. In this example, the hold-off periods 252 and 254 and the aperture windows 258 and 260 are stored in the memory device 116 for access by the processor 114. Further, in this example, a user provides a command to the processor 114 to not tune the frequency of the HF RF generator 104 during the hold-off periods 252 and 254 and to tune its frequency during the aperture windows 258 and 260. For illustrative purposes, the user provides the processor 114 with a time period for the hold-off period 252 via an input device. In the example, upon receiving the time period, the processor 114 identifies the hold-off period 252 and calculates the time period for the aperture window 258 by subtracting the time period for the hold-off period 252 from the time period of the first duty cycle. Also, in this example, there is no frequency tuning during the hold-off period. Furthermore, in this example, the time period between time t22 and time t23, where the transition state S23y occurs, is the hold-off period 252. In this example, the time period during which frequency tuning is not applied is referred to herein as the hold-off period, and the time period during which frequency tuning is applied is referred to herein as the aperture window. For illustration purposes, the hold-off period is the time period between two aperture windows of the steady state of the RF signal. For further illustration purposes, the time interval between the aperture window 258 and the aperture window 260 is the hold-off period 254. In a further example, aperture window 258 overlaps with a portion of substate S3ay and aperture window 260 overlaps with a portion of substate S3by.In a further example, the hold-off period 252 is immediately followed by an aperture window 258, which is the time period between times t23 and t24.5. In a further example, the aperture window 258 is immediately followed by a hold-off period 254, which is the time period between times t24.5 and t25.5. And in a further example, the hold-off period 254 is immediately followed by an aperture window 260, which is the time period between times t25.5 and t27. As an example, frequency tuning is the modification of an HF offset value, which is the frequency value of the RF signal 152, to reduce the reflected power or increase the transmitted power, as measured by the P sensor 112 during processing of the substrate S.

[0054] In one embodiment, the aperture window 260 has a different time interval than the time interval shown in FIG. 2C, such as being smaller or larger than the time interval shown in FIG. 2C.

[0055] Similarly, in one embodiment, aperture window 258 has a different time interval than that shown in FIG. 2C, such as being smaller or larger than the time interval shown in FIG. 2C.

[0056] Also, in one embodiment, the hold-off period 252 has a different time interval than the time interval shown in FIG. 2C, such as being smaller or larger than the time interval shown in FIG. 2C.

[0057] In one embodiment, the hold-off period 254 has a different time interval than that shown in FIG. 2C, such as being smaller or larger than the time interval shown in FIG. 2C.

[0058] In one embodiment, the predetermined number of sub-states is three or four.

[0059] FIG. 3 is an illustration of one embodiment of a graph 300 to illustrate the voltage signal 156 generated by the V sensor 110 (FIG. 1). The graph 300 plots voltage values ​​of the voltage signal 156 versus time t. The voltage values ​​range from -V6 to V0 and from V0 to V6. An example of a voltage value V0 is 0. Another example of a voltage value V0 is a negative voltage value. The voltage values ​​of the graph 300 are plotted on the y-axis and time t is plotted on the x-axis. A negative crossing 302 occurs at time t24.5. During the occurrence of the negative crossing 302, the voltage signal 156 has a negative slope and a voltage value V0. A cycle of the voltage signal 156 occurs for a time period from time t22 to time t27, with each cycle of the voltage signal 156 then occurring to repeat periodically for an equal amount of time.

[0060] 4 is a graph 400 to illustrate a method for reducing power glitches. The graph 400 plots HF offset value versus time t of the RF signal 152. The HF offset value is plotted on the y-axis and time t is plotted on the x-axis. The HF offset values ​​in the graph 400 range from HF(-4) to HF0 and from HF0 to HF5.

[0061] The processor 114 determines to divide the transition state S23y and state S3y into sub-states S3ay and S3by, during each of which a different reference high frequency value and a HF offset value from the reference high frequency value are applied. For example, the processor 114 divides a first duty cycle, which is a time period for occurrence of the sub-state S3ay, into a first predetermined number of bins, such as bin 1 and bins 2-12. In this example, each of the bins 1-12 has the same time interval. For illustration purposes, the time interval of bin 1 is equal to the time interval of bin 2. In this example, bin 6 is also referred to herein as bin 0. Continuing with this example, the processor 114 generates and sends in the recipe signal 144 (FIG. 1) information regarding the sub-state S3ay, including the time interval of bin 0 and instructions to apply the reference high frequency value HF0 during bin 0 of the sub-state S3ay of each cycle n, (n+1), etc. Moreover, the processor 114 further generates and sends in the recipe signal 144 information regarding the sub-state S3ay including the time intervals for each of bins 1-5 and 7-12, and instructions to apply a first set of HF offset values ​​from the reference high frequency value HF0 during bins 1-5 and 7-12 of the sub-state S3ay for each cycle n, (n+1), etc. For illustrative purposes, the processor 114 includes in the instructions that the HF RF generator 104 should generate an RF signal 152 having an HF offset HF(-2) in bin 1, an HF offset HF(-3) in bin 2, etc., up to an HF offset HF1 in bin 12.

[0062] Moreover, continuing with the example, the processor 114 divides the second duty cycle, which is the time period for occurrence of substate S3by, into a second predetermined number of bins, such as bin 1' and bins 2' through 12'. By way of example, the first predetermined number of bins is equal to the second predetermined number of bins. As another example, the first predetermined number of bins is greater than or less than the second predetermined number of bins. In this example, each of bins 1' through 12' has the same time interval. For purposes of example, the time interval of bin 1' is equal to the time interval of bin 2'. In this example, bin 6' is also referred to herein as bin 0'. Continuing with the example, the processor 114 generates and sends in the recipe signal 144 information regarding substate S3by, including the time interval of bin 0' and instructions to apply a reference high frequency value HF0' during bin 0' of substate S3by in each cycle n, (n+1), etc. Moreover, the processor 114 further generates and sends in the recipe signal 144 information regarding the sub-state S3by including the time intervals of each of bins 1'-5' and 7'-12' and instructions to apply HF offset values ​​from the reference high frequency value HF0' during bins 1'-5' and 7'-12' of the sub-state S3by of each cycle n, (n+1), etc. For illustration, the processor 114 includes in the instructions that the HF RF generator 104 should generate an RF signal 152 having an HF offset HF(-1) in bin 1', an HF offset HF(-2) in bin 2', etc., up to an HF offset HF1 in bin 12'.

[0063] Continuing with this example, the HF RF generator 104 receives a reference high frequency value HF0 and instructions to generate a reference high frequency value HF0 during bin 0 and generates an RF signal 152 having the reference high frequency value HF0 during a time interval of bin 0 of cycle n, (n+1), etc. Additionally, in this example, the HF RF generator 104 receives instructions to apply HF offset values ​​for bins 1-5 and 7-12 and the time intervals of bins 1-5 and 7-12 and generates an RF signal 152 having a respective one of the HF offset values ​​during a respective one of bins 1-5 and 7-12. For illustrative purposes, the HF RF generator 104 receives instructions to apply an HF offset HF(-2) during bin 1 and generates an RF signal 152 having an HF offset (-2) during bin 1 of cycle n, (n+1), etc.

[0064] Also in this example, the HF RF generator 104 receives a reference high frequency value HF0' and instructions to generate a reference high frequency value HF0' during bin 0' and generates an RF signal 152 having the reference high frequency value HF0' during the time interval of bin 0' of cycle n, (n+1), etc. Moreover, in this example, the HF RF generator 104 receives instructions to apply HF offset values ​​for bins 1'-5' and 7'-12 and the time interval of bins 1'-5' and 7'-12' and generates an RF signal 152 having a respective one of the HF offset values ​​during a respective one of the bins 1'-5' and 7'-12'. For illustrative purposes, the HF RF generator 104 receives instructions to apply an HF offset HF(-1) during bin 1' and generates an RF signal 152 having an HF offset (-1) during bin 1'.

[0065] In this example, by applying different reference high frequency values ​​and HF offset values ​​based on the reference high frequency values ​​in sub-states S3ax and S3ay, the power glitches are reduced in a precise manner. To illustrate, during each of the first and second duty cycles, the power reflected towards the HF RF generator 104 is reduced or the power delivered by the HF RF generator 104 is increased.

[0066] In accordance with commands received from a user, the HF offset value applied during the hold-off period is not modified, e.g., not tuned, by the processor 114 during processing of the substrate S. For example, the processor 114 avoids modifying the HF offset value during the hold-off period. In this example, the HF offset value applied during the hold-off period 252 of cycle n, (n+1), etc. is not modified by the processor 114 based on the power measured by the P sensor 112 (FIG. 1) during the hold-off period 252 of cycle n. For the sake of illustration, the processor 114 receives values ​​of power measured from the P sensor 112 during bins 1-5 of the hold-off period 252 of cycle n of the clock signal 202. In the example, the processor 114 stores the values ​​of power in the memory device 116. Further, in the example, the processor 114 does not modify the HF offset value to be applied during bins 1-5, e.g., cycle (n+1), based on the values ​​of power for bins 1-5 of cycle n. In the example, the processor 114 sends to the HF RF generator 104 in the recipe signal 144 (FIG. 1) the same HF offset value to be applied during cycle (n+1), etc. as that applied during cycle n. In the example, upon receiving the HF offset value, the HF RF generator 104 generates an RF signal 152 having the HF offset value during the hold-off period 252, such as cycle (n+1). In the example, the HF offset value, when modified, reduces the power reflected back toward the HF RF generator 104 during cycle (n+1), etc. Also in the example, the HF offset value is a frequency value of the RF signal 152 to be applied during bins 1-5 of cycle n, (n+1), etc., and a correspondence, such as a one-to-one relationship, between each of the HF offset values ​​and a respective one of bins 1-5 of the hold-off period 252 is stored in the memory device 116. In the illustrated example, the processor 114 applies the HF offset value during the hold-off period 252 of sub-state S3ay of cycle n, (n+1), etc.

[0067] In another example, the HF offset value applied during the hold-off period 254 is not modified by the processor 114 based on the power measured by the P sensor 112. For the sake of illustration, the processor 114 receives values ​​of power measured from the P sensor 112 during bins 1'-5' of the hold-off period 254 of cycle n of the clock signal 202. In the example, the processor 114 stores the values ​​of power in the memory device 116. Further, in the example, the processor 114 does not modify the HF offset value to be applied during bins 1'-5', such as cycle (n+1), based on the values ​​of power for bins 1'-5' of cycle n. In the example, the processor 114 sends, in the recipe signal 144 (FIG. 1), to the HF RF generator 104 the same HF offset value to be applied during cycle (n+1), such as that applied during cycle n. In the example, upon receiving the HF offset value, the HF RF generator 104 generates the RF signal 152 having the HF offset value during the hold-off period 254, such as cycle (n+1). In the example, the HF offset value, when modified, reduces power reflected back towards the HF RF generator 104. Also in the example, the HF offset value is a frequency value of the RF signal 152 to be applied during bins 1'-5' of the hold-off period 254 of cycle n, (n+1), etc., and a correspondence, such as a one-to-one relationship, between each of the HF offset values ​​and a respective one of the bins 1'-5' is stored in the memory device 116. In the example, the processor 114 applies the HF offset value during the hold-off period 254 of sub-state S3by of cycle n, (n+1), etc.

[0068] Moreover, according to commands received from a user, the HF offset value applied during the aperture window is tuned by the processor 114 during processing of the substrate S. For example, the HF offset value applied during the aperture window 258 is modified by the processor 114 based on the power measured by the P sensor 112. For the sake of illustration, the processor 114 receives the value of the power measured from the P sensor 112 during bins 7-12 of the aperture window 258 in cycle n of the clock signal 202. In the illustration, the processor 114 stores the value of the power in the memory device 116. Further, in the illustration, the processor 114 modifies the HF offset value to be applied during bins 7-12, such as cycle (n+1), based on the value of the power for bins 7-12 in cycle n. In the illustration, the processor 114 sends the modified HF offset value to be applied during cycle (n+1), etc., to the HF RF generator 104 in the recipe signal 144 (FIG. 1). In the example, upon receiving the HF offset value, the HF RF generator 104 generates an RF signal 152 having a modified HF offset value during an aperture window 258, such as cycle (n+1). In the example, the HF offset value, when modified, reduces power reflected back toward the HF RF generator 104. Also in the example, the HF offset value is a frequency value of the RF signal 152 to be applied during bins 7-12 of the aperture window 258, such as cycle (n+1), and a correspondence, such as a one-to-one relationship, between each of the HF offset values ​​and a respective one of the bins 7-12 is stored in the memory device 116. In the example, the processor 114 applies the modified HF offset value during the aperture window 258 of sub-state S3ay, such as cycle (n+1).

[0069] As another example, the HF offset value applied during the aperture window 260 is modified by the processor 114 based on the power measured by the P sensor 112. For the sake of illustration, the processor 114 receives the value of the power measured from the P sensor 112 during bins 7'-12' of the aperture window 260 for cycle n of the clock signal 202. In the example, the processor 114 stores the value of the power in the memory device 116. Further, in the example, the processor 114 modifies the HF offset value to be applied during bins 7'-12', such as cycle (n+1), based on the value of the power for bins 7'-12' for cycle n. In the example, the processor 114 sends the modified HF offset value to be applied during cycle (n+1), etc., to the HF RF generator 104 in the recipe signal 144 (FIG. 1). In the example, upon receiving the HF offset value, the HF RF generator 104 generates an RF signal 152 having a modified HF offset value during an aperture window 260, such as cycle (n+1). In the example, the HF offset value, when modified, reduces power reflected back toward the HF RF generator 104. Also in the example, the HF offset value is a frequency value of the RF signal 152 to be applied during bins 7'-12', such as cycle (n+1), and a correspondence, such as a one-to-one relationship, between each of the HF offset values ​​and a respective one of the bins 7'-12' is stored in the memory device 116. In the example, the processor 114 applies the HF offset value during an aperture window 260 of sub-state S3by, such as cycle (n+1).

[0070] In one embodiment, the processor 114 applies dynamic frequency tuning (DFT) to determine the reference high frequency value HF0 or HF0′ stored in the memory device 116. For example, in DFT, the processor 114 determines the high frequency value HF0 or HF0′ by rotating a high frequency impedance orbit on a Smith chart to minimize the power reflected back towards the HF RF generator 104.

[0071] The embodiments described herein may be practiced with a variety of computer system configurations including portable hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. The embodiments described herein may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a computer network.

[0072] In some embodiments, the controller is part of a system, which may be part of the examples described above. The system includes semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more platforms, and / or specific processing components (wafer pedestal, gas flow system, etc.) for processing. The system is integrated with electronics for controlling its operation before, during, and after processing of a semiconductor wafer or substrate. The electronics is referred to as a "controller," which may control various components or sub-parts of the system. The controller is programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow settings, fluid delivery settings, position and operation settings, wafer transfer in and out of tools and other transfer tools and / or load locks connected to or interfaced with the system, depending on the processing requirements and / or type of system.

[0073] In general, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, and the like. Integrated circuits include firmware that stores program instructions, chips defined as digital signal processors (DSPs), ASICs, PLDs, one or more microprocessors, or chips in the form of microcontrollers that execute program instructions (e.g., software). Program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing processes on or for a semiconductor wafer. The operational parameters, in some embodiments, are part of a recipe defined by a process engineer to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0074] The controller, in some embodiments, is part of or coupled to a computer that is integrated with, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or in all or part of a fab host computer system that allows remote access for wafer processing. The controller allows remote access to the system to monitor the current progress of a fabrication operation, to change parameters of a current process, to set up processing steps that follow a current process, or to start a new process, to examine the history of past fabrication operations, and to examine trends or performance metrics from multiple fabrication operations.

[0075] In some embodiments, a remote computer (e.g., a server) provides the process recipe to the system over a computer network, including a local network or the Internet. The remote computer includes a user interface that allows entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of settings for processing the wafer. It should be understood that those settings are specific to the type of process to be performed on the wafer and the type of tool the controller interfaces with or controls. Thus, as described above, the controller is distributed, such as by including one or more individual controllers that are networked together and function toward a common purpose, such as the process of implementing described herein. One example of a distributed controller for such purposes includes one or more integrated circuits on the chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that are combined to control the process in the chamber.

[0076] Without being limited thereto, in various embodiments, the plasma systems described herein include plasma etch chambers, deposition chambers, spin rinse chambers, metal plating chambers, clean chambers, bevel edge etch chambers, physical vapor deposition (PVD) chambers, chemical vapor deposition (CVD) chambers, atomic layer deposition (ALD) chambers, atomic layer etch (ALE) chambers, ion implantation chambers, track chambers, or any other semiconductor processing chambers related to or used in the creation and / or manufacturing of semiconductor wafers.

[0077] Additionally, while the operations described above have been described with respect to a parallel plate plasma chamber, e.g., a capacitively coupled plasma chamber, it should be noted that in some embodiments, the operations described above apply to other types of plasma chambers, including, e.g., plasma chambers including inductively coupled plasma (ICP) reactors, transformer coupled plasma (TCP) reactors, conductor tools, dielectric tools, electron cyclotron resonance (ECR) reactors, etc. For example, an X MHz RF generator, a Y MHz RF generator, and a Z MHz RF generator are coupled to an inductor in an ICP plasma chamber.

[0078] As described above, depending on the process operations to be performed by the tool, the controller communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to carry containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0079] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These computer-implemented operations manipulate physical quantities.

[0080] Some of the embodiments also relate to hardware units or devices for performing these operations. The device is specially constructed for a special purpose computer. When defined as a special purpose computer, the computer performs other processes, program executions or routines that are not part of its special purpose while still being capable of performing operations for its special purpose.

[0081] In some embodiments, the operations described herein are performed by a selectively activated computer or configured by one or more computer programs stored in a computer memory or obtained over a computer network. When data is obtained over a computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

[0082] One or more embodiments described herein may also be made as computer readable code on a non-transitory computer readable medium. A non-transitory computer readable medium is any data storage hardware unit, such as a memory device, that stores data, which is then read by a computer system. Examples of non-transitory computer readable media include hard drives, network attached storage (NAS), ROM, RAM, compact disk ROM (CD-ROM), CD recordable (CD-R), CD rewriteable (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, a non-transitory computer readable medium includes a computer readable tangible medium that is distributed across network-coupled computer systems such that the computer readable code is stored and executed in a distributed manner.

[0083] Although some of the method operations described above have been presented in a particular order, it should be understood that in various embodiments, other housekeeping operations are performed between the method operations, or the method operations are adjusted such that they occur at slightly different times or are distributed in a system that allows the method operations to occur at various intervals, or are performed in an order different from that described above.

[0084] Furthermore, it should be noted that in one embodiment, one or more features from any embodiment described above may be combined with one or more features of any other embodiment without departing from the scope described in the various embodiments described in this disclosure.

[0085] Although the above embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Thus, the present embodiments should be considered as illustrative rather than restrictive, and the embodiments should not be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

Claims

1. 1. A method for reducing reflected power associated with a high frequency (HF) radio frequency (RF) generator after a transient condition, comprising: controlling the HF RF generator to divide a state of an HF RF signal into a plurality of sub-states, the plurality of sub-states including a first sub-state and a second sub-state; controlling the HF RF generator to apply a first reference high frequency value in the first sub-state and a second reference high frequency value in the second sub-state; applying a first set of HF offset values ​​from the first reference high frequency value during the first sub-state; applying a second set of HF offset values ​​from the second reference high frequency values ​​during the second sub-state; A method comprising:

2. 2. The method of claim 1, wherein the states include the transition state and a steady state, during the steady state the HF RF signal has a power level within a predetermined range, and during the transition state the HF RF signal has a power level outside the predetermined range.

3. 2. The method of claim 1, wherein the controlling the HF RF generator to divide the state into the plurality of sub-states comprises: providing a first duty cycle of the first sub-state and a second duty cycle of the second sub-state to the HF RF generator; providing a first power level of the HF RF signal to be applied during the first duty cycle; providing a second power level of the HF RF signal to be applied during the second duty cycle, the first power level being equal to the second power level; A method comprising:

4. 10. The method of claim 1, accessing a hold-off period and an aperture window for each of the plurality of sub-states; tuning the frequency of the HF RF signal into the aperture window; The method further comprises:

5. 5. The method of claim 4, further comprising avoiding tuning the frequency of the HF RF signal during the hold-off period.

6. 2. The method of claim 1, wherein the first reference high frequency value is different from the second reference high frequency value.

7. 2. The method of claim 1, wherein the first substate comprises the transition state and a first portion of a steady state, and the second substate comprises a second portion of the steady state.

8. 1. A controller for reducing reflected power associated with a high frequency (HF) radio frequency (RF) generator after a transient condition, comprising: controlling the HF RF generator to divide a state of an HF RF signal into a plurality of sub-states, the plurality of sub-states including a first sub-state and a second sub-state; controlling the HF RF generator to apply a first reference high frequency value in the first sub-state and a second reference high frequency value in the second sub-state; applying a first set of HF offset values ​​from the first reference high frequency value during the first sub-state; applying a second set of HF offset values ​​from the second reference high frequency values ​​during the second sub-state; a processor configured to: a memory device coupled to the processor; A controller comprising:

9. 9. The controller of claim 8, wherein the states include the transition state and a steady state, during the steady state the HF RF signal has a power level within a predetermined range, and during the transition state the HF RF signal has a power level outside the predetermined range.

10. 9. The controller of claim 8, wherein to control the HF RF generator to divide the state into the plurality of sub-states, the processor: providing a first duty cycle of the first sub-state and a second duty cycle of the second sub-state to the HF RF generator; providing a first power level of the HF RF signal to be applied during the first duty cycle; providing a second power level of the HF RF signal to be applied during the second duty cycle, the first power level being equal to the second power level; A controller configured to:

11. 9. The controller of claim 8, wherein the processor: accessing a hold-off period and an aperture window for each of the plurality of sub-states; tuning the frequency of the HF RF signal into the aperture window; A controller configured to:

12. 12. The controller of claim 11, wherein the processor is configured to avoid tuning the frequency of the HF RF signal during the hold-off period.

13. 9. The controller of claim 8, wherein the first reference high frequency value is different from the second reference high frequency value.

14. 9. The controller of claim 8, wherein the first substate comprises the transition state and a first portion of a steady state, and the second substate comprises a second portion of the steady state.

15. 1. A system for reducing reflected power associated with a high frequency (HF) radio frequency (RF) generator after a transient condition, comprising: a low frequency (LF) RF generator configured to generate an LF RF signal; the HF RF generator configured to generate an HF RF signal; a matcher coupled to the LF RF generator and the HF RF generator; a controller coupled to the LF RF generator and the HF RF generator; wherein the controller controlling the HF RF generator to divide a state of the HF RF signal into a plurality of sub-states, the plurality of sub-states including a first sub-state and a second sub-state; controlling the HF RF generator to apply a first reference high frequency value in the first sub-state and a second reference high frequency value in the second sub-state; applying a first set of HF offset values ​​from the first reference high frequency value during the first sub-state; applying a second set of HF offset values ​​from the second reference high frequency values ​​during the second sub-state; A system configured to:

16. 16. The system of claim 15, wherein the states include the transition state and a steady state, during the steady state the HF RF signal has a power level within a predetermined range, and during the transition state the HF RF signal has a power level outside the predetermined range.

17. 16. The system of claim 15, wherein to control the HF RF generator to divide the state into the plurality of sub-states, the controller: providing a first duty cycle of the first sub-state and a second duty cycle of the second sub-state to the HF RF generator; providing a first power level of the HF RF signal to be applied during the first duty cycle; providing a second power level of the HF RF signal to be applied during the second duty cycle, the first power level being equal to the second power level; A system configured to:

18. 16. The system of claim 15, wherein the controller: accessing a hold-off period and an aperture window for each of the plurality of sub-states; tuning the frequency of the HFRF signal into the aperture window; A system configured to:

19. 20. The system of claim 18, wherein the controller is configured to avoid tuning the frequency of the HFRF signal during the hold-off period.

20. 16. The system of claim 15, wherein the first reference high frequency value is different from the second reference high frequency value.

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