Phase mode bit addressable sense register

Abstract

The shift register elements of the phase mode bit addressable sense register sample the changing AC or DC bias values ​​provided to the operational RQL circuit on the RQL IC via the clock resonator or DC bias lines. The shift register may be composed of a phase mode D flip-flop and multiple JTLs as data and clock lines. A method of using the sense register includes the steps of shifting in a data bit pattern while the bias parameter (e.g., AC amplitude, DC value, or phase) is set to a nominal value, stopping the logic clock that controls the shifting of values ​​through the sense register, changing the bias parameter value, inputting one assertion SFQ pulse or reciprocal pulse pair to the logic clock, returning the bias parameter to the nominal value, restarting the logic clock to shift out the output data bit pattern, and observing the output data bit pattern to determine the effect of the change in the bias parameter value.

Description

[Technical field]

[0001] The present disclosure relates generally to superconducting circuits, and more particularly to phase-mode bit-addressable sense resistors. [Background technology]

[0002] In the field of digital logic, the well-known and highly developed complementary metal-oxide semiconductor (CMOS) technology is widely used. As CMOS begins to mature as a technology, interest is growing in alternative technologies that may provide higher performance in terms of speed, power consumption, computational density, and interconnect bandwidth. As an alternative to CMOS technology, single flux quantum (SFQ) circuits utilize superconducting Josephson junctions (JJ), which have typical signal powers of about 4 nanowatts (nW), typical data rates of 20 gigabits per second (Gb / s) or higher, and operating temperatures of about 4 Kelvin.

[0003] A family of SFQ circuits known as reciprocal quantum logic (RQL) uses one or more resonator networks and / or bias lines to distribute one or more bias signals. The bias signals serve to bias the JJs in the logic gates of the RQL circuit and the Josephson transmission lines (JTLs) found in the gates of the RQL circuit or as connecting lines between gates for propagating SFQ signals in the RQL circuit. The AC bias signals can serve as one or more global clock signals that can help eliminate clock jitter as may be exhibited by prior superconducting circuit technologies such as rapid single flux quantum (RSFQ) logic. For example, RQL can utilize a multi-phase clock having an in-phase (I) clock signal and a quadrature (Q) clock signal that is approximately 90° out of phase with the I clock signal. Summary of the Invention

[0004] An exemplary RQL integrated circuit (IC) includes a phase-mode shift register having a first plurality of JTLs arranged in series as a data path, a second plurality of JTLs arranged in series as a logic clock path trunk, and a plurality of phase-mode D flip-flops. Each phase-mode D flip-flop has (1) a data input coupled to the data path and configured to receive an input from the data path, (2) a data output coupled to the data path and configured to provide an output to the data path, and (3) a logic clock input coupled to a branch of a respective logic clock path coupled to the logic clock path trunk. The first plurality of JTLs and the phase-mode D flip-flops in the data path are transformer coupled to one or more AC clock resonators of the RQL IC to receive AC clock bias signals of first two AC clock phases that are approximately 180 degrees apart in phase from each other. A second plurality of JTLs in the logical clock path trunk are transformer coupled to the one or more AC clock resonators of the RQL IC to receive AC clock bias signals of a second two AC clock phases that are approximately 180° apart in phase from each other, the first two AC clock phases being different from the second two AC clock phases.

[0005] An exemplary method includes setting at least one bias signal parameter of a bias signal provided to the RQL IC to a nominal value and initiating a logic clock signal provided to the logic clock path of the phase mode RQL shift register to shift in an input data bit pattern to the data path of the phase mode RQL shift register. The logic clock is then stopped and the value of the at least one bias signal parameter provided to the data path of the phase mode RQL shift register is changed to a value different from the nominal value. An assertion SFQ pulse pair, or a single SFQ pulse, is input to the logic clock path. Once the value of the at least one bias signal parameter is returned to the nominal value, the logic clock signal provided to the logic clock path of the phase mode RQL shift register is resumed to shift out an output data bit pattern to the data path of the phase mode RQL shift register. The output data bit pattern of the phase mode RQL shift register is observed. Based on observing the output data bit pattern, it is determined that varying the value of the at least one bias signal parameter has brought the value of the at least one bias signal parameter closer to (or whether it has approached) an optimal value for the at least one bias signal parameter. The bias signal parameter that is changed may be an AC bias amplitude, a DC bias value, or an AC bias signal phase.

[0006] Another exemplary RQL superconducting bias level sensing circuit for sensing a bias level supplied to an RQL circuit comprises a phase mode logic (PML) shift register including a plurality of PML shift register elements coupled in series with each other. Each PML shift register element includes a PML D flip-flop having a data input, a data output, and a logic clock input, the data input configured to be coupled to either a data output of a previous element in the PML shift register or an input data bit stream source. Each PML shift register element further includes a data output path portion having an input coupled to the data output of the PML D flip-flop and an output configured to be coupled to either a data input of a next element in the PML shift register or a circuit configured to receive an output data bit stream from the PML shift register, the data output path portion comprising first, second, and third JTL-based buffers coupled in series with each other between the input and output of the data output path portion. Each PML shift register element further includes a logic clock path trunk portion having an input configured to be coupled to either the logic clock path output of the next element in the PML shift register or a logic clock source, and an output configured to be coupled to either the logic clock path input of the previous element in the PML shift register and / or the logic clock path branch of the PML shift register element, the logic clock path trunk portion comprising fourth, fifth, sixth, seventh, and eighth JTL-based buffers coupled in series with each other between the input and output of the logic clock path trunk portion. Each PML shift register element further includes a branch of said logic clock path having an input coupled to the output of the logic clock path trunk portion of the PML shift register element and an output coupled to the logic clock input of the PML D flip-flop, the logic clock path branch comprising ninth and tenth JTL-based buffers coupled in series with each other between the input and output of the logic clock path branch. [Brief description of the drawings]

[0007] [Figure 1]FIG. 1 is a block diagram of an exemplary RQL bias level detection and adjustment system. [Figure 2A] FIG. 13 is a block diagram of an example set of RQL bias level sensors configured within a JTL-based RQL scan register bias level sensor wrapper for serial output. [Figure 2B] FIG. 13 is a block diagram of an example set of RQL bias level sensors configured within a JTL-based bias level sensor wrapper for parallel output. [Figure 2C] FIG. 1 is a block diagram of an exemplary set of RQL bias level sensors configured within a ring oscillator wrapper. [Diagram 3] 1 is a graph of an example margin shmoo plot of nominal AC and DC bias level operating margins for an operational RQL circuit and RQL bias level sensor. [Figure 4A] 11 is a graph of an example margin shmoo plot of AC and DC bias level operating margins for an operational RQL circuit and RQL bias level sensor showing the effect of changes in the AC amplitude of the applied bias signal; [Figure 4B-4D] 4B is a one-dimensional time plot of output pulse reception for a bias level sensor wrapper similar to that of FIG. 2A showing the effect of varying the AC amplitude of the applied bias signal as shown in FIG. 4A. [Figure 5A] 11 is a graph of an example margin shmoo plot of AC and DC bias level operating margins for an operational RQL circuit and RQL bias level sensor showing the effect of changing the DC value of the applied bias signal. [Figure 5B-5D] 5B is a one-dimensional time plot of output pulse reception for a bias level sensor wrapper similar to that of FIG. 2A, showing the effect of changing the DC value of the applied bias signal as shown in FIG. 5A. [Figure 6] FIG. 2B is a circuit diagram of an exemplary sampler stage configured for use in a bias level sensor such as that shown in FIG. 2A, the sampler stage including a JTL with a bias provided by a tap. [Figure 7] FIG. 2B is a block diagram of an example throttling logic as shown in FIG. 2A. [Figure 8] 7 is a block diagram of an example shift register including four instances of the example sampler stage of FIG. 6 that may be used as a bias level sensor as in FIG. 2A. [Figure 9] 7 is a block diagram of an example shift register including three instances of the example sampler stage of FIG. 6 that may be used as a bias level sensor as in FIG. 2A. [Figure 10] 7 is a block diagram of an example shift register including one instance of the example sampler stage of FIG. 6 that may be used as a bias level sensor as in FIG. 2A. [Figure 11] 7 is a block diagram of an example shift register including one instance of the example sampler stage of FIG. 6 that may be used as a bias level sensor as in FIG. 2A. [Figure 12] FIG. 13 is a block diagram of an exemplary specific phase bias level sensor for a Q clock. [Figure 13] FIG. 1 is a block diagram of an example specific phase bias level sensor for an I-clock. [Figure 14] FIG. 20 is a block diagram for explaining the symbols used in FIGS. 12, 13, 16, and 18. [Figure 15] FIG. 20 is a block diagram for explaining the symbols used in FIGS. 12, 13, 16, and 18. [Figure 16] FIG. 1 is a block diagram of an exemplary specific I-clock (Q-clock independent) bias level sensor. [Figure 17] 19 is a graph of an example AC and DC bias margin shmoo plot for the particular I-clock (Q-clock independent) bias level sensor of FIGS. 16 and 18. FIG. [Figure 18] FIG. 13 is a block diagram of another exemplary specific I-clock (Q-clock independent) bias level sensor. [Figure 19]1 is a graph of an exemplary minimum operational AC bias for a particular I-clock and a particular Q-clock bias level sensor as a function of deviation of the Q-clock phase from 90°. [Figure 20] FIG. 2 is a block diagram of an exemplary phase sampler. [Figure 21] FIG. 21 is a block diagram explaining the symbols used in FIG. 20. [Figure 22] 21 is a graph illustrating an example clock amplitude versus phase error for the example phase sampler of FIG. 20. [Diagram 23] 21 is a graph illustrating an example minimum operating bias signal AC amplitude for the phase sampler of FIG. 20. [Figure 24] FIG. 1 is a block diagram of a portion of a phase mode logic (PML) bias level sensor. [Diagram 25] FIG. 2B is a block diagram of an exemplary pulse generator-based bias level sensor as shown in a portion of a wrapper similar to that of FIG. 2A. [Figure 26A] FIG. 2 is a block diagram of an exemplary configuration of a bias level sensor disposed within a DC SQUID-based bias level sensor. [Figure 26B] FIG. 2 is a block diagram of an example DC SQUID-based output amplifier configured as a sensor to measure the level of an externally supplied output bias current IBIASOUT relative to an optimal level. [Figure 27A] FIG. 2 is a block diagram of an example feedback system for sensing and tuning the AC amplitude of the I and Q clocks. [Figure 27B] FIG. 2 is a block diagram of an example feedback system for detecting and tuning phase errors in I and Q clocks. [Figure 28] FIG. 1 is a flow diagram illustrating an exemplary method for adjusting or optimizing AC and DC bias points using bias level sensors integrated on the RQL IC. [Figure 29]FIG. 25 is a flow diagram illustrating an example method for adjusting or optimizing an AC (or, with modification, DC) bias point using a PML shift register similar to that of FIG. 24 integrated on a RQL IC. [Diagram 30] 13 is a flowchart illustrating an exemplary method for adjusting or optimizing the relative phase difference between the I-clock and the Q-clock using a phase-sensitive bias level sensor integrated on the RQL IC. [Diagram 31] FIG. 11 is a flow diagram illustrating an example method for adjusting or optimizing the AC bias amplitude of the I-clock and Q-clock and the phase difference between the I-clock and Q-clock on the RQL IC. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The computational functions of the RQL system may be performed at least in part by an operable digital circuit, which may include logic gates and JTLs. The operable circuit includes JJs biased by one or more bias signals of the RQL system, which may include both AC and DC bias signals, and the AC signals may act as one or more clocks for the RQL system to synchronize data and / or provide a time-based flow of the logic functions of the RQL system. The AC bias signals may provide clocks of different phases, such as a 0° clock or a 180° clock provided by an I-clock resonator, or a 90° clock or a 270° clock provided by a Q-clock resonator. The operational circuit may only operate correctly within certain margins of various operational parameters. Some of these operational parameters are related to the bias signals (e.g., clocks) provided to the RQL system. For example, the RQL system may malfunction if the DC bias level of the clock is too high or too low and falls outside the DC bias operating margins of the gates or JTLs in the RQL system. As another example, if the amplitude of the AC bias signal of the clock is too large or too small and falls outside the AC bias operating margin of the gate or JTL in the RQL system, this may be another cause of the malfunction of the RQL. As yet another example, if the relative phase difference of different clocks, such as the I-clock and the Q-clock, is too large or too small and falls outside the clock phase difference operating margin of the gate or JTL in the RQL system, this may be another cause of the malfunction of the RQL.

[0009] Flux, which is the time integral of a voltage, even when applied to conventional inductors or JJs, is the primary operating parameter that controls the function of RQL logic circuits. Due to manufacturing process variations and other factors, there can be significant variations in the AC and DC fluxes generated by the resonators and the tap transformers coupled to the resonators, which provide the bias signals to the RQL logic circuits. Variations in the inductors, dielectrics, and JJs that make up an operating RQL circuit cause variations in the amount of AC and DC flux required by those circuits. Changes in temperature, as well as aging, can affect the performance of RQL circuits. Given these changes and variations, the ideal values ​​of bias parameters such as AC amplitudes, DC values, and gate flux bias currents may not be the same for all RQL logic gates in a system.

[0010] The clock signal or signals provided to the RQL system may be generated by a function generator circuit operating at approximately room temperature (about 300K), while the RQL operational circuitry of the system may reside in a cryogenically cooled space operating at much lower temperatures, for example at about 4K or less, and may be several meters away from the function generator circuitry. Due to the low operating temperatures and thermal isolation requirements of the RQL system, it may not be possible to directly probe the integrated circuit (IC) on which the RQL system is implemented to ascertain bias signal parameters (such as DC levels, AC amplitudes, relative phase differences of AC clock signals, etc.) at various points on the IC to check that the bias signal parameters actually provided to the RQL operational circuitry are those intended to be provided or are within the operating margins of an otherwise operational circuit.

[0011] Measurements of the supplied bias levels, e.g., AC voltages and DC currents supplied on the RQL integrated circuits, as well as other bias parameters such as the relative phase differences between different bias signals, can provide the insight needed to adjust the bias levels generated at the bias sources outside the cooled space to ensure that the delivered bias levels and other parameters as delivered to the operational RQL circuit in the cooled space are consistent with optimal values ​​that are within, e.g., centered on, the operating margins of the operational RQL circuit. The measurements for each RQL IC, or a portion of each IC, can be used to adjust the bias levels to improved, optimal, or near-optimal values ​​to provide more reliable performance of the operational RQL circuit.

[0012] Thus, the bias level sensor may be provided as a sensing circuit fabricated on the RQL IC along with the operational circuitry of the RQL system. The bias level sensor may sense a signal parameter of the bias signal provided to the operational circuitry at various locations on the IC. The sensed signal parameter may be used in a manual or automatic feedback loop to inform adjustment of the bias signal provided to the RQL system such that a bias that remains within the operational margins of the operational circuitry is provided to the operational circuitry of the RQL system. In some examples, multiple bias level sensors may be embedded in a logic circuit, referred to herein as a wrapper, which activates the bias level sensors by interrogating the bias level sensors with, for example, a sampling signal, and reads out the results. By way of example, the sensors may be incorporated into an RQL scan register or a JTL testbed register.

[0013] In some examples, the bias level sensing circuit architecture and related methods described in this application allow for the determination of improved, near-optimal, or optimal bias levels by observing pulses generated by an ensemble of bias level sensing circuits. Exemplary bias level sensing circuits, referred to as samplers, act as a proxy for the operational RQL circuit. The samplers may be configured as a whole such that when the elements of the operational RQL circuit are at their optimal bias points, a particular portion of the samplers or a particular individual one (or more) of the samplers operate to transmit or generate bias level sensing output pulses as expected, and other samplers do not operate to transmit or generate bias level sensing output pulses as expected. Which samplers and how many samplers generate bias level sensing output pulses reveals information about the current bias of the operational RQL circuit, e.g., the current bias point of the operational RQL circuit. Digital logic may be utilized to count, reorder, and / or sort the bias level sensing output pulses, and search and optimization algorithms may be used to adjust bias signal generation parameters (e.g., bias levels) to improve the bias levels delivered and / or move the operating point closer to the optimal value.

[0014] The operating margin offset of the bias level sensor from the nominal operating margin of the operational RQL circuit may, in some examples, allow bias level measurements to be made without shutting down the operational RQL circuit. As an example, the bias transformer flux may be altered from a normal level to ensure that the bias sense circuit provides a useful output without having to move the bias level beyond the range in which the operational RQL circuit functions. One way to alter the bias transformer flux is to provide a bias level sensor with a transformer configured to generate a larger or smaller flux than normal by altering the mutual inductance to the clock resonator. Another way to alter the bias transformer flux is to insert a more or less inductance than nominal amount between the transformer and the bias level sensor. As another example, a dedicated bias sense circuit may be configured to start or stop operating at a level within the operating range of the logic circuit. This may be done by increasing or decreasing the size of the JJs and inductors in the circuit. When the performance of the bias transformers and their associated clock resonators is paramount, it may be preferable to drive the JJs directly from standard transformers, since only the variability of the JJs adds to that of the resonators and transformers. When the need for logic circuitry on the outputs of the clock resonators and bias transformers is noted, it may be advantageous to utilize sensing circuitry that differs minimally from the operational circuitry. This latter objective can be achieved by inserting additional inductance in series with the transformers, while keeping the transformers and the remaining logic sensing circuitry in standard configuration.

[0015] The operating margin offset may vary from sensor to sensor in a population of bias level sensors, which may be staging configured to provide sampling inputs and outputs for bias level measurement. Variations in the operating margin offset between sensors may be intentionally introduced by design (staging), for example, to cover a range around the nominal operating point of the operational RQL circuit. In such a case, the population of bias level sensors may be configured such that a percentage of the bias level sensors (e.g., about half of the bias level sensors) generate pulses when the operational logic is optimally biased with respect to AC amplitude. Thus, the AC amplitude bias level according to the needs of the operational RQL circuit may be determined by counting the pulses generated by the population. In another example, the spread of elements in the operating levels of the bias level sensors caused by manufacturing process variations may be used to provide a pulse count sensed output substantially equivalent to that using the above-mentioned staged sensors, without the intentional staging of the operating margin offsets of the bias level sensors. The reason for this is that when the operational circuit is optimally biased, if the bias on the sensor is near the limit of its functionality, even without a design for intentionally staggering the margins of the sensor, the operational RQL circuit will be near its optimal bias condition when approximately half of the bias level sensors are biased within their own operating margins, and will therefore generate a sense pulse when interrogated with a sample signal via the wrapper circuit.

[0016] 1 illustrates an exemplary RQL bias level sensing and adjustment system 100. An operational RQL circuit 102, which may include JTLs and logic gates, may be fabricated on an IC 106 as a chip along with one or more associated clock resonators 104, and the chip may be enclosed in a cryogenic cooling space configured to reduce the RQL operating temperature to, for example, low single digit Kelvin or below. As used herein, the term "operational RQL circuitry" refers to logic circuitry and associated infrastructure circuitry used to perform the useful computational operations for which the RQL IC 106 or system is designed, and is distinct from circuitry 118 on the RQL IC 106 used to perform sensing of parameters related to the bias signal provided to the RQL IC 106. Bias level sensors and wrappers 118 may be provided spatially distributed on the IC 106 (e.g., throughout the space on the IC occupied by the operational RQL circuitry) to improve bias level measurement accuracy.

[0017] The operational circuit 102 is coupled (e.g., inductively coupled) to one or more clock resonators 104 via multiple taps 108 to provide an AC bias to the operational circuit 102. The operational circuit may also be coupled to multiple DC bias lines 124 to provide a DC bias to the operational circuit 102. In some examples, the DC bias lines 124 may be configured to circulate around the clock resonator 104 to control the amount of DC bias applied to the operational RQL circuit 102 and / or the bias level sensor 118. In some examples, each bias tap 108 or 120 may have an AC transformer coupled to one or more ribs of the clock resonator 104, and another transformer may be coupled in series to the DC bias lines 124. Outside the cooled space, a bias signal generator 110 (or multiple bias signal generators, e.g., different signal generators for providing an I clock bias signal, a Q clock bias signal, and various DC bias signals) may generate one or more clock signals, such as an I clock 112 and a Q clock 114, for supply to the operational circuit 102 via a clock resonator 104 and associated taps 108 in the cooled space. The one or more bias signal generators 110 may also generate a DC bias signal for supply to the operational circuit 102 on the IC 106 via a DC bias line 124. The one or more clock signals and / or DC bias signals generated by the clock signal generator 110 may be based on different bias parameters 116, which may be in the form of adjustable or variable settings provided to or stored in the bias signal generator 110. Such bias parameters may include, by way of example, the clock frequency, the AC amplitude of the generated AC clocks (e.g., I and Q clocks), or one or more DC values ​​of the generated DC bias, and the phase difference between the Q and I clocks at the time of clock generation (which may nominally be approximately 90°, but in some cases may not be exactly 90°).

[0018] Also, the bias level sensor 118 may be fabricated on the same IC 106 as the operational RQL circuit 102 and may be configured to sample one or more bias signals (AC clock signals and / or DC bias signals) provided by one or more resonators 104 via a number (N) of sampling taps 120 and / or provided via a DC bias line 124. The bias level sensor may be configured within a wrapper, which may be used to introduce a sampling signal to the bias level sensor 118 and output a signal based on the sampling signal indicative of measurements of various clock parameters obtained by the bias level sensor. Such parameters may include any or all of the above parameters (parameters 116) used by the clock signal generator 110 to generate a clock signal outside the cooling space. The output of the bias level sensor and / or associated sensor wrapper 118 may be used to adjust the parameters provided to the clock signal generator 110 via a feedback loop 122 to ensure that the AC clock and / or DC bias signals provided in the operational RQL circuit 102 provide biases that meet the margin requirements of the operational RQL circuit 102. In some examples, the RQL bias level sensing and adjustment system 100 can provide bias feedback and adjustment without requiring the operational RQL circuit 102 to be deactivated or otherwise disabled.

[0019] FIG. 2A shows an example configuration 200 of RQL bias level sensors 202-212 wrapped in a JTL-based RQL scan register bias level sensor wrapper that is used to provide a serial output from a large number of bias level sensors instead of the otherwise parallel output. The bias level sensors 202-212, also referred to herein as samplers, can be thought of as existing on rungs of a ladder formed by the sensor wrappers. One such rung is labeled 214 in FIG. 2A. The rails of the ladder can be formed by JTLs 216-238, shown as triangles in FIG. 2A, or other circuitry configured to propagate SFQ pulses through the wrapper structure with inter-run propagation delays. While the example of FIG. 2A is shown as having one rail JTL between each ladder rung, each JTL 216-238 can be configured to have one or as many repeating RQL JTL circuit structures as desired to generate SFQ signal propagation delays of one or many AC clock cycles.

[0020] The bias level sensors 202-212 can take many different forms and can be configured to measure any of many different parameters, including AC bias signal amplitude, DC bias value, and inter-clock phase. Depending on the form of the bias level sensors 202-212, the stages can include suppression logic (SL) 240-250 configured to prevent assertion of multiple output pulses from propagating from the stage if the associated sampler is in a condition that causes it to spontaneously invert due to a manufacturing defect or excessive bias. In some examples, the suppression logic 240-250 on some or all stages of the wrapper can be omitted. The wrapper can also include an input transformer 252 configured to provide the wrapper with a sample signal consisting of at least one input SFQ pulse provided from a positive input node INP and a negative input node INN. The wrapper can also include an output amplifier 254 configured to output a voltage signal between a positive output node OUTP and a negative output node OUTN. The output amplifier 254 may take the form of, for example, a JTL binary vine tree (not shown) configured to split the input SFQ signal for feeding multiple stacked DC SQUIDs (e.g., four DC SQUIDs) arranged as a voltage adder.

[0021] In the exemplary configuration 200 of FIG. 2A, a sample signal provided as a SFQ pulse via an input transformer 252 propagates along the top rail from the proximal end of the wrapper ladder to the distal end, branching along the ladder's stages to generate multiple time-separated output voltage pulses at the ladder output between output nodes OUTP, OUTN. Because each rail JTL 216-238 generates an inter-stage propagation delay of at least one AC clock cycle, the output pulses are spaced apart in time, with earlier arriving output pulses having propagated through more proximal stages of the wrapper ladder (stages closer to the input / output end of the wrapper ladder) and later arriving output pulses having propagated through more distal stages of the wrapper ladder (stages further from the input / output end of the wrapper ladder). Exactly how many output pulses are generated for a given sample input pulse depends on how many samplers 202-212 are functioning with the provided bias signal(s) that are within the operating margin of the individual samplers 202-212. As described in more detail below, in some examples, the samplers 202-212 may include, for example, an AC bias amplitude XAC, a DC bias value X DC , or clock phase difference X phase The "X" in this nomenclature refers to a multiplier of the nominal bias level. For example, if the nominal bias level is 0.2V, then an actual applied bias level of 0.22V would have an X of 1.1 (110%). In other examples, the sensing system may rely on manufacturing process variations to provide samplers 202-212 with spread (varying over a range) of margins without having a purposefully designed stepped setting.

[0022] In some examples, such as the example 200 shown in FIG. 2A, the first and last stages (proximal and distal stages) of the wrapper ladder may be standard bias JTLs 256, 258 (without the self-inductance and / or mutual inductance corrections of the sampler stage 600 of FIG. 6) such that the first and last pulses provided at the wrapper output indicate the margin of a standard device for comparison with the margin of the samplers 202-212. The pulses generated by the standard bias JTLs 256, 258 provide pulses that serve to indicate the beginning and end of a pulse train generated when an input pulse is provided to INP / INN. In other examples, not shown, additional standard JTL stages may be provided at other stage locations interspersed along the wrapper ladder. Logic, for example, room temperature semiconductor logic (not shown), may evaluate the output of each sampler 202-212 individually, or the total number of functional samplers (each represented by its pulse) may be used as a measure of the overall bias of the sensing system. As will be described in more detail below, by introducing a gradation in the bias level sensed by the bias level sensors 202-212 contained in the stages of the RQL scan register 200, an output is generated that quantifies or digitizes the sensed bias parameter by generating a number of output pulses in the output pulse stream that is proportional to the sensed bias parameter, or by generating output pulses whose output timing is indicative of the sensed bias parameter.

[0023] FIG. 2B illustrates an exemplary configuration 260 of RQL bias level sensors 262-272 arranged with parallel outputs. The configuration 260 is similar to the RQL scan register configuration 200 of FIG. 2A, except that the outputs are provided in parallel rather than in series. The parallel output configuration 260 can also include suppression logic (SL) 280-290 configured to prevent assertion of multiple output pulses from propagating from each output if the associated sampler is in a condition that causes it to spontaneously flip due to a manufacturing defect or excessive bias. Each bias level sensor 262-272 can be located at a different location on the RQL IC 106 and can be tapped to one or more bias resonators 104 at different points along the resonator(s) 104 via a bias coupling transformer (not shown in FIG. 2C). An advantage of the serial output configuration of FIG. 2A over the parallel output configuration of FIG. 2B is that the configuration of FIG. 2A can conserve I / O on the RQL IC 106 in some examples. In some examples, the parallel outputs OUTA-OUTZ of FIG. 2B may be provided to built-in self-test (BIST) readable registers implemented on the RQL IC 106 for storage and later retrieval in a serial or parallel manner.

[0024] FIG. 2C illustrates an exemplary configuration 290 of bias level sensors (each labeled BLS) arranged as a ring oscillator. The number of bias levels in the ring oscillator can be arbitrarily large. The output of one bias level sensor serves as a sample signal input for the next bias level sensor in the ring. Each bias level sensor can be located at a different location on the RQL IC 106 and can be connected to one or more bias resonators 104 at different points along the resonators 104 via bias coupling transformers (not shown in FIG. 2C). Although not shown in FIG. 2C, the bias level sensors in the ring 290 can be interspersed with conventional JTLs on the ring to facilitate the propagation of SFQ pulses between the bias level sensors in the ring.

[0025] In the ring configuration 290 of FIG. 2C, an initial sampling assertion signal (SFQ pulse or reciprocal pulse pair) can be provided on the input RINGIN. The sampling pulse or pulse pair can propagate indefinitely in the ring 290 as long as all of the bias level sensors are operational (as long as the provided bias point is within the operational region of all bias level sensors in the ring). If the bias parameters are adjusted such that the provided bias parameters are outside the operational region of any one bias level sensor in the ring, the entire ring "breaks" and the sampling signal no longer propagates in the ring, but instead stops at the first non-operating bias level sensor it reaches. The continued operation of the ring can be seen through the output RINGOUT, which in full ring operation produces a SFQ pulse stream (or a stream of reciprocal pulse pairs) at a rate related to the size of the ring (one output pulse or pulse pair is produced for each revolution of the sample pulse in the ring) and stops outputting when the ring is deactivated due to a bias parameter adjustment. As explained in more detail below, the X AC Parameter, X DC Parameter and X phase The parameters can be scanned (iteratively adjusted) in an optimization procedure to find the minimum X that the ring oscillator will continue to function to produce an output at RINGOUT. AC The level provides an optimal bias for the operational RQL circuit 102. In some examples, more than one input sample pulse at a time can be fed to the operational ring, for example with multiple pulses separated in time, resulting in an increased frequency of output pulses.

[0026] In each of the above examples of Figures 2A-2C, the bias level sensor may be a JTL-based bias level sensor as described with respect to Figures 6, 8A, 9A, 10A, 11A, 12, 13, 16, and 18, a PML flip-flop-based bias level sensor as described with respect to Figure 25, a pulse generator-based bias level sensor as described with respect to Figure 25, or other types of bias level sensors suitable for arrangement in a series, parallel, or ring output configuration. Different bias level sensors in the same arrangement may be X AC , X DC , X phase , or other bias parameters.

[0027] The combination of operating margins for an RQL circuit can be described by a shmoo plot. For example, the AC and DC operating margins can be described by a two-dimensional shmoo plot. Graph 300 of FIG. 3 illustrates a first exemplary shmoo plot 302 representing the nominal AC and DC bias level operating margins for an operating RQL circuit 102 and a second exemplary shmoo plot 304 representing the average of the AC and DC bias level operating margins 304 for the RQL bias level sensors (e.g., samplers 202-212). The operating margin 302 for an operating RQL circuit can be expressed as: DC , X AC When expressed in space, the lower limit or X ACmin , where the amplitude of the AC clock is minimized in each margin Shmoo plot 302. ACmin ) is the X of the sampler margin shmoo plot DC , X AC Since it is a unique point in space, it is x with respect to the sampler AC and X DCWithin the center of the nominal margin shmoo plot 302 (e.g., the centroid or geometric center of the nominal margin shmoo plot 302), the X DC , X AC There exists an optimal bias point 306 for a working RQL circuit that is a unique point in space. A sampler (e.g., samplers 202-212) is a circuit that has a lower bound (X ACmin ) may be designed and positioned to be in the center of the nominal margin shmoo plot for the operational RQL circuit 102 at the optimal bias point 306.

[0028] One or more parameters of the bias signal (e.g., clock, DC bias) provided to the operational RQL circuit 102 (e.g., via one of the input lines 112, 114, 124 in FIG. 1), such as DC value or AC amplitude, may be adjusted until the output of the bias level sensor wrapper matches a desired, improved, or ideal bias condition. For example, the AC amplitude and DC level parameters may be adjusted to X AC X of a linearly-phased set of samplers AC Only the proximal half of the sampler returns an output pulse, and (as shown in FIG. 5C) DC The X in the center of a linearly stepped set of samplers DC When only one or some of the samplers are configured to return an output pulse, the operational RQL circuit 102 is said to be ideally biased with respect to the AC and DC parameters of the provided clock. Setting the lower limit point of the sampler's shmoo 304 near the optimal bias point 306 of the operational circuit's shmoo 302, as an example, can be used to measure the self-inductance and / or DC mutual inductance (X and / or X, respectively) that provide a corresponding bias signal to be measured for the sampler's JTL. AC Or X DCSetting the lower limit point of the sampler's shmoo 304 near the optimal bias point 306 of the operational circuit's shmoo 302 can be achieved by, as another example, setting one or more AC mutual inductances that provide one or more AC bias signals to the sampler's JTL, or by, as another example, inserting a self-inductance between the JTL and the transformer (tap). An optimization procedure such as procedure 2800 shown in FIG. 28 can be used to calibrate the bias signals, for example, to an ideal calibration or a calibration close to the ideal calibration. If the samplers are set such that their lower limits are near the optimal bias point 306, the optimization procedure 2800 can be performed such that the adjusted parameters of the clock(s) and / or DC bias signals are within the operating margins of the operational RQL circuit 102, meaning that the calibration of the bias signals can be performed with the operational RQL circuit continuously operating, even while the bias parameters are being adjusted, improved, or optimized.

[0029] Graph 400 of FIG. 4A illustrates an operational RQL circuit 102 and an AC bias level sensor (X AC Graph 400 shows exemplary shmoo plots 302, 404 of the operating margins at nominal AC and DC bias levels for an eight X sampler. AC Including margin 404 for sampler, but X AC The number of samplers may be less than or greater than eight in some examples. The graph 400, seen in conjunction with the one-dimensional time plots of FIGS. 4B-4D, illustrates an exemplary X-ray diffraction (XRD) graph that may be performed without interruption to the operation of an operational RQL circuit 102 having a nominal operating margin 302. AC The performance of the optimization method is shown in Figure 4. The AC amplitude of the applied bias signal can be varied, essentially shifting the bias point vertically up or down on the graph 400, until an optimal AC bias point 4C is determined. ACThe sampler may, for example, have a bias transformer with a self-inductance that varies in value to produce a varying offset in the AC response, and a nominal DC mutual inductance. AC The increased self-inductance between the JTL of the sampler and the corresponding sampler tap on the bias line causes the operating RQL circuit 102 to flip over as the clock amplitude increases, X AC This can have the additional beneficial effect of preventing the sampler from spontaneously inverting. AC The population of samplers may be configured such that the lower limit of each margin shmoo plot is centered around a bias point 306 that is initially considered or assumed to be optimal for the operation of the operational RQL circuit 102. As shown in FIG. AC The lower limit of the sampler's margin shmoo plot is centered near the middle of the nominal margin shmoo plot 302 of the operational RQL circuit.

[0030] 4B to 4D show, for example, a bias level sensor wrapper such as that shown in FIG. 2A that uses X as its bias level sensors 202 to 212. AC If a sampler is provided, this indicates receipt or non-receipt of an output pulse. In the example shown, X AC The sampler converts those shmoo plots into X DC -X AC They are arranged in the wrapper in order of levels that shift upwards in space. DC -X AC The sampler with the lowest shmoo plot in space is located near the proximal end of the bias level sensor wrapper, X DC -X AC The sampler with the highest shmoo plot in space is located near the distal end of the bias level sensor wrapper. The dashed patterns of the output pulses in Figures 4B-4D correspond to the same dashed patterns of the margin shmoo plot 404 in Figure 4A, and a certain dashed pattern of pulses in Figures 4B-4D corresponds to an X-axis shmoo plot with a margin depicted with the same dashed pattern in Figure 4A. AC4B-4D thus show the wrapper output effect of varying the AC amplitude of the applied bias signal as shown in FIG. 4A. If the applied AC bias is too low, the AC bias point 4B will be at most X AC is too low to fall within the operating margin of the sampler. Thus, the number of output pulses returned is relatively small, as shown in FIG. 4B. For example, as shown in FIG. AC If the samplers are arranged in a sequential (e.g., linear) stepped fashion, with the sampler configured with the lowest AC operating margin placed closest to the input / output end of the wrapper shown in FIG. 2A, the returning output pulses may be limited to the return of earlier pulses. In contrast, if the AC bias supplied is too high, the AC bias point 4D will be at most X AC This is too high to be within the operating margin of the sampler. Thus, the number of output pulses returned is relatively high, as shown in FIG. 4D. For example, as shown in FIG. 4B, AC If the samplers are linearly stepped, with the sampler configured with the highest AC operating margin positioned most distal to the input / output end of the wrapper shown in FIG. 2A, the returning output pulses may include not only the return of earlier pulses, but also some later pulse returns. The supplied AC bias 4C may be considered optimal, for example, when the number of returning output pulses is in the mid-range number, an example of which is shown in FIG. 4C, approximately half X AC The sampler operates and returns the output pulse, about half the X AC The sampler is inoperative and therefore does not return an output pulse. AC The sampler is aligned along the length of the RQL scan register wrapper as in Figure 2A with a lower bound on AC of X AC In this example, the RQL scan register wrapper in Figure 2A is distributed in ascending order in the x dimension. ACThe samplers may be configured to be arranged in other orders, including descending order, or in any known arrangement with no particular order, and the order may be appropriately taken into account when analyzing the output of the RQL scan register wrapper to determine improved or optimal bias levels. In other examples where the analysis of the wrapper output includes counting the number of samplers operating under given bias conditions, such as where sampler margin spread is achieved solely by process variation, the order is not important and need not be taken into account when analyzing the wrapper output to determine improved or optimized bias levels.

[0031] Graph 500 of FIG. 5A illustrates an operational RQL circuit 102 and a DC bias level sensor (X DC Graph 500 shows an example shmoo plot 302, 504 of the operating margins at nominal AC and DC bias levels for an eight X DC Including margin 504 for sampler, X DC The number of samplers may be less than or greater than eight in some examples. The graph 500, seen in conjunction with the one-dimensional time plots of FIGS. 5B-5D, illustrates an exemplary X-ray diffraction (XRD) graph that may be performed without interruption to the operation of an operational RQL circuit 102 having a nominal operating margin 302. DC The performance of the optimization method is shown in Figure 5. The DC value of the applied bias signal can be varied, essentially shifting the bias point horizontally left or right on the graph 500, until an optimal DC bias point 5C is determined. DC The sampler may, for example, detect the varying DC mutual inductance (M DC ) and a nominal AC mutual inductance. As an example, the DC bias point of the nominal operating margin 302 may be set to X DC The DC mutual inductance of the sampler is determined by having a mutual inductance with the DC bias line in each of the corresponding transformers of the sampler, such that the current in the DC bias line varies between 1.5 mA and 2.5 mA. DCSuch a change in DC mutual inductance can be, for example, DC For a sampler, given X DC This can be provided by changing the distance at which a DC transformer in the bias tap of the sampler couples with the corresponding DC bias line, thus making such coupling distance shorter or longer. AC As with samplers, X DC The samplers may be arranged in groups such that the lower limits of their margin shmoo plots are centered around a bias point 306 that is initially considered or assumed to be optimal for the operation of the operational RQL circuit 102. As shown in FIG. DC The lower limit of the sampler margin shmoo plot is centered near the middle of the nominal margin shmoo plot 302 for the operational RQL circuit.

[0032] 5B to 5D show a bias level sensor wrapper such as that shown in FIG. 2A, which uses X as its bias level sensors 202 to 212. DC 5B-5D correspond to the same dashed pattern in the margin shmoo plot 504 of FIG. 5A, and a pulse of a certain dashed pattern in FIG. 5B-5D corresponds to an X-shaped pulse having a margin depicted with the same dashed pattern in FIG. 5A. DC 5B-5D thus show the wrapper output effect of varying the DC value of the applied bias signal as shown in FIG. 5A. Optimization of the bias signal DC value can be performed with the bias signal AC amplitude set to its optimum level or slightly higher than its optimum level. If the applied DC bias is too low, then X DCIf the samplers are arranged in a sequential (e.g., linear) stepped manner, with the sampler configured with the lowest DC operating margin arranged closest to the input / output end of the wrapper shown in Figure 2A, the returning output pulses will be limited to the return of one or several earlier pulses, as shown in Figure 5B. In contrast, if the DC bias applied is too high (5D), the returning output pulses will be only the last one or several last pulses in time, which is the one or several X most distal to the input / output end of the wrapper shown in Figure 2A, as shown in Figure 5D. DC It can be said that the supplied DC bias 5C is optimal when the returning output pulses are only the central one or a few in time, as shown in FIG. 5C, which means that the central X DC Only the sampler is operational and therefore returns an output pulse, while the other X DC The sampler is not returned. DC The sampler is aligned along the length of the RQL scan register wrapper as shown in Figure 2A, with the lower bound of AC being X DC In this example, the RQL scan register wrapper in Figure 2A is distributed in ascending order in the x dimension. DC The samplers may be configured to be arranged in other orders, including descending order, or in any known arrangement with no particular order, and the order may be appropriately taken into account when analyzing the output of the RQL scan register wrapper to determine improved or optimal bias levels. In other examples where the analysis of the wrapper output includes counting the number of samplers operating under given bias conditions, such as where sampler margin spread is achieved solely by process variation, the order is not important and need not be taken into account when analyzing the wrapper output to determine improved or optimized bias levels.

[0033] In various instances, the wrapper AC Sampler only, X DC It may be configured to include only samplers or a mix of different types of samplers. ACOr X DC The margin offset stepwise configuration may be reversed from the ascending order described above, such that high margin samplers are placed proximally on the wrapper ladder and low margin samplers are placed distally on the wrapper ladder, or the stepwise configuration may adopt a pattern other than an ordered stepwise configuration, with associated changes in the expected pulse output. The linearly ordered low-to-high stepwise configuration described above is provided as an illustrative example only. In either example, whether the location of a sampler is distal or proximal to the input / output end of the bias level sensor wrapper is not a factor in determining the significance of the bias level adjustment / optimization of the corresponding output pulse, but rather, the margin offset set for the sampler is a factor in determining the significance of the bias level adjustment / optimization of the corresponding output pulse of the sampler.

[0034] A one-dimensional scanning procedure shown in FIGS. 4B-4D that varies only the applied AC bias may first be performed to find an improved or optimal applied AC bias level, and then a one-dimensional scanning procedure shown in FIGS. 5B-5D that varies only the applied DC bias may lead to a more accurate assessment or calibration of the applied DC bias level. Similarly, a one-dimensional scanning procedure shown in FIGS. 5B-5D that varies only the applied DC bias may first be performed to find an improved or optimal applied DC bias level, and then a one-dimensional scanning procedure shown in FIGS. 4B-4D that varies only the applied AC bias may lead to a more accurate assessment or calibration of the applied AC bias level. Thus, these two one-dimensional scanning procedures are AC and X DC 2A-2C may be implemented using the RQL scan registers 200, 260, 290 of FIGS. 2A-2C, for example, as bias level sensors 202-212 (or 262-272 or BLS) to provide outputs indicative of AC or DC bias levels. AC Sampler and X DC It may be used with either or both of the samplers. ACWhen used to measure X, any of the scan registers 200, 260, 290 will generate a specific number of pulses when an optimal level is reached. DC When used to measure, the result output by any of the scan registers 200, 260, 290 is the X DC The RQL scan registers 200, 260, 290 each provide a numerical result in some exemplary modes of operation, or in other exemplary modes of operation, the output may indicate the bias level in other ways. For example, the RQL scan registers 200, 260, 290 may enable examination of the output of a single bias level sensor located in the scan register to find its improved or optimal bias point by varying the applied AC and DC biases. In some examples, this procedure may be performed individually for multiple or all bias level sensors located in the scan register. In some examples, this procedure may be performed for individual bias level sensors located in various locations across the chip, not necessarily in a single scan register or all elements of any scan register. In such examples, the average values ​​of the individually measured improved or optimal applied AC and DC bias levels may be calculated and used as setpoints for the bias sources.

[0035] X DC -X AC Different methods can be used to scan the space to find improved or optimal AC and DC applied bias levels. A first exemplary scanning method scans all X DC -X AC Sampling at points, X DC -X ACA second exemplary scanning method may include creating a complete two-dimensional map of the space. A second exemplary scanning method may include limiting the scan to the discovered boundaries of the area of ​​motion, essentially "walking" in and out of the perimeter of the margin shmoo plot in a zigzag fashion to determine the boundary or perimeter contour. This second exemplary scanning method is a complete X-ray scanning method of the first exemplary scanning method. DC -X AC This can have the advantage of time efficiency over spatial sampling. DC -X AC The scanning method may include spiral or conical traversing of the space. A fourth exemplary scanning method may implement a successive approximation method such as that used in analog-to-digital converters (ADCs). A fifth exemplary scanning method may implement a delta-sigma algorithm. Other exemplary scanning methods may implement variations or combinations of the above methods to approach improved or optimal applied AC and / or DC bias levels. In any of these examples, the scanning method selected may use a closed loop to find and stabilize the bias levels, regardless of the type of scan(s) used and the on-chip configuration or placement of the bias level sensors used in the scanning method.

[0036] A sampler, such as bias level sensors 202-212 of FIG. 2A, can have any of a number of different forms. In some examples, a sampler consists of one or more JTLs or logic gates configured in series with one another, for example as a shift register, where at least one of the JTLs or logic gates in the shift register is specially configured to be sensitive to bias in a different manner than the other JTLs or logic gates in the operational RQL circuit 102. FIG. 6 illustrates an exemplary sampler stage 600 having a sampler JTL 602 coupled to a sampler bias tap 604, configured for use with a bias level sensor, such as any of bias level sensors 202-212 of FIG. 2A. An SFQ-based sample signal provided at a sampler JTL input terminal ai may be transmitted (i.e., propagated) to a sampler JTL output terminal qo when the sampler JTL 602 is operational. The operability of the sampler JTL 602 depends at least on the sampler JTL 602 being biased within its operational margin. Bias is provided to the sampler JTL 602 via bias line 606, which in the illustrated example includes bias lines 614, 616, and 618. The sampler JTL 602 is inductively coupled to the bias line 606 via the sampler tap 604. In the example shown in FIG. 6, the sampler tap 604 includes a DC coupling transformer 608 for inductively coupling the sampler JTL 602 to a DC bias line 614, an I clock coupling transformer 610 for inductively coupling the sampler JTL 602 to an I clock bias line 616, and a Q clock coupling transformer 612 for inductively coupling the sampler JTL 602 to a Q clock bias line 618. The following table shows the relationship between normalized mutual inductance and tap phase of the sampler tap 204, with the normalized AC mutual inductance M I , M Q We show how the normalized M can be modified to provide different clock phase biases to the sampler JTL602. DC X DC It can vary (from 1) for the sampler.

[0037] [Table 1]

[0038] In contrast to the JTL or gate found in the operational RQL circuit 102, the sampler JTL 602 is fed from the sampler bias tap 604 through a larger self-inductance, which in some examples is the bias inductor L 2 or, in another example, an AC offset inductor L between the sampler JTL 602 and the tap 604, as shown in FIG. offsetAC In this latter example, the AC offset inductor L offsetAC The sampler JTL 602 configured to exclude may otherwise be identical to the standard bias JTL used in the operational RQL circuit 102. Compared to the JTL found in the operational RQL circuit 102, the DC bias transformer 608 of the bias tap 604 may, in some examples, have a larger or smaller mutual inductance M coupling the sampler JTL 602 to the DC bias line 614. DC In order to provide a larger self-inductance of the sampler stage 600, the bias inductor L 2 or the AC offset inductor L offsetAC By including DC -X AC 4A , which is shifted vertically upward in space. In some examples, the AC offset inductor L offsetAC is omitted, and the bias inductor L 2 is made smaller than normal (smaller than JTL in the operational RQL circuit 102) so that the operating margin shmoo plot of the bias level sensor is substantially (X AC A reverse offset (not shown) can be realized by shifting the bias inductor L downward (in the L dimension). 2 , and the AC offset inductor L, if present. offsetAC can be provided, for example, by an induction network.

[0039] In an exemplary bias level sensor with reduced AC response, an AC offset inductor L in the sampler stage 600 offsetAC may be, for example, about 1.5 times the self-inductance of the sampler tap 604. offsetAC This self-inductance value of the corresponding sampler's shmoo plot is aligned with the bottom corner of the shmoo plot 302 of the operational RQL circuit 102. AC As an example, the AC offset inductor L in sampler stage 600 may have the effect of placing it at approximately the midpoint of the offsetAC may be about 29.25 pH, or may provide about 1.5 times the self inductance of the sampler tap 604, which may be, for example, about 19.3 pH. AC In an example implemented as bias level sensors 202-212 in the context of the wrapper shown in FIG. 2A to function for relatively low values ​​of RQL, the bias level sensors may respond to high AC bias levels by outputting a steady stream of RQL encoded logic "1's" (positive SFQ pulse followed by negative SFQ pulse) that flips every AC clock cycle. Corresponding suppression logic 240-250 prevents this continuous stream of RQL encoded logic "1's" by generating a stream of RQL encoded logic "0's" (no SFQ pulses) in response. Detection of the lower limit of the bias level sensor's margin shmoo plot can be used to calibrate the AC bias amplitude parameters to stabilize the RQL clock in an operating RQL system, as described above with respect to FIGS. 4A-4D.

[0040] Margin Shmoo Plots with Higher X AC In the exemplary bias level sensor, which is shifting in value, an AC offset inductor L in the sampler stage 600 of the bias level sensor offsetACcan be, for example, within a range of about 0.5 to 10 times the nominal tap self-inductance value, e.g., the tap self-inductance value of the JTL or gate used in the operational RQL circuit 102. For example, the AC offset inductor L offsetAC can be approximately 1.5 times as large as the tap self-inductance of the JTL and gates used in the operational RQL circuit 102. As an example, if the nominal self-inductance value of the bias taps provided to the JTLs or gates used in the operational RQL circuit 102 is approximately 19.3 pH, then the AC offset inductor L in the sampler stage 600 of the bias level sensor of FIG. offsetAC The inductance value of the sampler stage 600 may be between about 9.65 pH and about 193 pH, for example, between about 40 pH and about 50 pH, for example, about 29.0 pH. AC In an example implemented as bias level sensors 202-212 in the context of the wrapper shown in FIG. 2A to function for relatively high values ​​of AC bias, the bias level sensor may respond to low AC bias levels by outputting a continuous stream of RQL encoded logic "1's" (a positive SFQ pulse followed by a negative SFQ pulse) that flips every AC clock cycle. The corresponding suppression logic 240-250 prevents this continuous stream of RQL encoded logic "1's" by generating a stream of RQL encoded logic "0's" (no SFQ pulses) in response. Thus, the upper edge of the bias level sensor's margin shmoo plot can be detected without flooding the output of the RQL shift register wrapper with a continuous stream of "1's." While detection of the upper edge of the bias level sensor's margin shmoo plot may not be required to calibrate the AC bias amplitude parameters in an operating RQL system, in some examples it may be used as a diagnostic tool.

[0041] 6 provides an example in which a JTL 602 is used as a sample signal transmitting device. Although not shown, other exemplary sampler stages can be similar to the sampler stage 600 of FIG. 6, but have an RQL gate as the sample signal transmitting device instead of the sampler JTL 602. The RQL gate provides a desired mutual inductance M to the AC bias line to provide the desired clock phase. Q , M I and the desired X DC The RQL gate is biased by a modified bias of a sampler tap, such as sampler tap 604, with mutual inductance to the DC bias line to provide an offset. The RQL gate can, in some instances, shift the shmoo plot (operating region) to a higher X AC In order to raise the level of offsetAC The RQL gate, like the sampler JTL602, operates within its modified operating margins and fails (produces unexpected outputs or no output) outside of its modified operating margins.

[0042] FIG. 7 illustrates an exemplary suppression logic 700 as may be used to implement any instance of the suppression logic 240-250 of FIG. 2A. The suppression logic 700 includes a first superconducting path to a non-inverting input of an RQL A-NOT-B gate 704 (a two-input AND gate with a single inverting input) and a second path through several (e.g., four) JTLs 702 to generate a one-cycle delay to the inverting input of the A-NOT-B gate. If the bias to the sampler is too high, the sampler may "spin" (generating a continuous stream of logic "1" outputs) that can disable the RQL scan register wrapper of FIG. 2A. The suppression logic 700 prevents such spins (repeated triggers). The A-NOT-B gate 704 passes the first logic "1" from the sampler, but does not pass subsequent "1"s from the sampler that generate a stream of reciprocal SFQ pulses due to defects or excessive bias. In some examples, the throttle logic 700 can be omitted. Excessive AC bias amplitude is limited by a lower limit (X ACmin ) is higher than the standard X AC The standard logic in the read register spins about 2 dB faster before the raised sampler spins. Furthermore, the suppression logic circuitry itself may become defective and start spinning, for example due to the use of the RQLA-NOT-B gate 704, which has a narrow operating margin.

[0043] Some examples may use multiple instances of sampler stage 600 arranged in series as a shift register to provide a bias level sensor. Because a single JTL receives a substantial portion of its operating flux from the cells that drive it and from the cells it drives, it may be necessary to arrange several sensing JTLs 600 (with similarly shifted bias margins) in series before the net effect of bias shift appears at the output of the shift register that constitutes the bias level sensor. As an example, four or more sensing JTLs in series may be sufficient for the sensing elements to operate independently from the JTLs before and after them.

[0044] 8 illustrates an example shift register 800 configured as a bias level sensor, including four instances 804, 806, 808, 810 of the example sampler stage 600 of FIG. 6. The shift register 800 may further include an input stage 802 and an output stage 812, each of which may be implemented as one or more JTLs and / or logic gates with a standard bias (e.g., without the self-inductance and / or mutual inductance correction of the sampler stage 600 of FIG. 6). FIG. 9 illustrates an example shift register 900 including three instances 904, 906, 908 of the example sampler stage 600 of FIG. 6. The shift register 900 may further include an input stage 902 and an output stage 912, each of which may be implemented as one or more JTLs and / or logic gates with a standard bias (e.g., without the self-inductance and / or mutual inductance correction of the sampler stage 600 of FIG. 6). 10 illustrates an example shift register 1000 that includes one instance 1004 of the example sampler stage 600 of FIG. 6. The shift register 1000 may further include an input stage 1002 and an output stage 1012, each of which may be implemented as one or more JTLs and / or logic gates with standard biases (e.g., without the self-inductance and / or mutual inductance corrections of the sampler stage 600 of FIG. 6). FIG. 11 illustrates an example shift register 1100 that includes one instance 1104 of the example sampler stage 600 of FIG. 6. The shift register 1100 may further include an input stage 1102, which may be implemented as one or more JTLs and / or logic gates with standard biases (e.g., without the self-inductance and / or mutual inductance corrections of the sampler stage 600 of FIG. 6). As an example, any of the shift registers 800, 900, 1000, or 1100 may be implemented as any of the bias level sensors 202, 204, 206, 208, 210, 212 of FIG. 2A, any of the bias level sensors 262, 264, 266, 268, 270, 272 of FIG. 2B, or any of the bias level sensors BLS of FIG. 2C.

[0045] FIG. 12 shows an exemplary specific phase bias level sensor 1200 for the Q clock. Thus, the specific phase Q sampler 1200 of FIG. 12 provides a sampler that responds to variations in the amplitude of the Q clock but not to variations in the amplitude of the I clock. FIG. 13 shows an exemplary specific phase bias level sampler 1300 for the I clock. Thus, the specific phase I sampler 1300 of FIG. 13 provides a sampler that responds to variations in the amplitude of the I clock but not to variations in the amplitude of the Q clock. Thus, the samplers 1200, 1300 allow independent adjustment of the I and Q clock AC amplitudes. FIG. 14 and FIG. 15 explain the sense symbols used in FIG. 12, FIG. 13, FIG. 16 and FIG. 18.

[0046] In the specific phase Q sampler 1200 of FIG. 12, four quad ("x4") sampler stages 1202, 1204, 1206, 1208 are arranged in series with each other, and each of the four quad sampler stages 1202, 1204, 1206, 1208 is biased by a different phase of the RQL clock signal. The first quad sampler stage 1202 comprises a configuration of four JTL and / or logic gates with standard biasing without the self-inductance and / or mutual inductance correction of the sampler stage 600 of FIG. 6. An extension of such a standard biased quad sampler stage is shown as a standard biased JTL and / or series gate 1400 in FIG. 14. The first quad sampler stage 1202 is biased by a 0° clock. The second quad sampler stage 1204 comprises a configuration of four JTLs and / or logic gates with modified AC bias with self-inductance and / or mutual inductance correction of the sampler stage 600 of FIG. 6. An extension of such a modified bias quad sampler stage is shown as modified bias JTLs and / or series gates 1500 in FIG. 15. The second quad sampler stage 1204 is biased by a 90° clock (a clock whose AC waveform is shifted by 90° with respect to the AC waveform of the 0° clock). The third quad sampler stage 1206 is a quad standard bias sampler stage 1400 biased by a 180° clock. The fourth quad sampler stage 1208 is a quad standard bias sampler stage 1400 biased by a 270° clock. As described above in Table 1, the 0° and 180° clocks may be provided from an I clock resonator, and the 90° and 270° clocks may be provided from a Q clock resonator. Although sampler stages 1202, 1204, 1206, 1208 are shown in the illustrated exemplary configuration 1200 as quad sampler stages each having four serial JTLs and / or logic gates, the number of JTLs and / or logic gates in each sampler stage may be greater or less in other examples. The number of JTLs and / or logic gates in each sampler stage may be determined as a design parameter.In one example (not shown), sampler stage 1204 has four or more series JTLs and / or logic gates to prevent current sharing effects from sampler stages 1202, 1206, and sampler stages 1202, 1206, 1208 are composed of fewer than four series JTLs and / or logic gates.

[0047] In the particular phase I sampler 1300 of FIG. 13, four quad sampler stages 1302, 1304, 1306, 1308 are arranged in series with each other, and each of the four quad sampler stages 1302, 1304, 1306, 1308 is biased by a different phase of the RQL clock signal. The first quad sampler stage 1302 is a quad standard bias sampler stage 1400 biased by a 0° clock. The second quad sampler stage configuration 1304 is a quad standard bias sampler stage 1400 biased by a 90° clock. The third quad sampler stage 1306 is a quad modified bias sampler stage 1500 biased by a 180° clock. The fourth quad sampler stage 1308 is a quad standard bias sampler stage 1400 biased by a 270° clock. Although the sampler stages 1302, 1304, 1306, 1308 are shown in the illustrated exemplary configuration 1300 as quad sampler stages each having four series JTLs and / or logic gates, the number of JTLs and / or logic gates in each sampler stage can be greater or less in other examples. The number of JTLs and / or logic gates in each sampler stage can be determined as a design parameter. In one example (not shown), the sampler stage 1306 has four or more series JTLs and / or logic gates to prevent current sharing effects from the sampler stages 1304, 1308, and the sampler stages 1302, 1304, 1308 are each composed of fewer than four series JTLs and / or logic gates.

[0048] In the quad standard bias sampler stage extension 1400 shown in FIG. 14, each individual component stage 1402, 1404, 1406, 1408 of each sampler stage 1202, 1206, 1208, 1302, 1304, 1308 has a standard value of bias tap self-inductance, i.e., the same value of bias tap self-inductance used to feed the JTLs and gates in the operational RQL circuit 102 (e.g., AC offset inductance L offsetAC The JTLs or gates of each individual component stage 1402, 1404, 1406, 1408 are biased with an AC clock signal that is in phase ("PHASE°").

[0049] In the quad-corrected bias sampler stage expansion 1500 shown in FIG. 15, each individual component stage 1502, 1504, 1506, 1508 of each sampler stage 1204, 1306 includes an AC offset inductor L inserted between the JTL or gate and its corresponding bias tap. offsetAC (or equivalently, the magnified bias tap inductor L 2 ) and an AC offset inductor L offsetAC provides a bias self-inductance that is greater than the bias self-inductance in the JTLs and gates in the operational RQL circuit 102. Thus, each individual component stage 1502, 1504, 1506, 1508 provides a bias self-inductance that is greater than the bias self-inductance in the JTLs and gates in the operational RQL circuit 102. DC -X AC With the margin shmoo plot elevated in space, the JTLs or gates of each individual component stage 1502, 1504, 1506, 1508 are biased with an AC clock signal of the same phase ("PHASE°").

[0050] Because of the tendency for flux to be shared between the driven JTL or driven logic gate and the driving JTL or driving logic gate, if a single JTL or logic gate is operated with a clock phase 90° behind the JTL or logic gate that drives it, and 90° ahead of the JTL or logic gate that it drives, an accurate measurement of the amplitude of the clock of the particular phase biasing the JTL or logic gate may not be obtained. However, by using four or more individual component stages (e.g., sampler stages 1502, 1504, 1506, 1508, or 1402, 1404, 1406, 1408) biased with a clock signal of the phase to be sampled, flux sharing can be effectively limited to the first and last JTL or logic gate, leaving the remaining JTLs and / or logic gates largely unaffected by flux sharing. In this way, the phase to be detected can be accurately measured. In the particular phase sampler 1200, 1300 shown in FIGS. 12 and 13, the serial arrangement 1204, 1306 of the individual component stages 1402, 1404, 1406, 1408 may be, for example, AC The AC offset inductor L exists to raise the lower limit of offsetAC 1506, while the series arrangement 1202, 1206, 1208, 1302, 1304, 1308 of the individual component stages 1502, 1504, 1506, 1506 have standard bias taps to form a support infrastructure. The individual component stages 1502, 1504, 1506, 1508 of the sensing sampler stage 1204 or 1306 respond independently to either the I or Q clock bias. When the I / Q phase angle is close to the nominal 90°, the phase sensitivity of the JTL or gate of the I and Q weakened taps have opposite slopes.

[0051] FIG. 16 shows an exemplary I-clocked (Q-clock independent) bias level sensor 1600. The standard biased quad sampler stages 1602, 1606, and 1610 are similar to those expanded in FIG. 14, and the modified biased quad sampler stages 1604 and 1608 are similar to those expanded in FIG. 15. Thus, the exemplary sampler 1600 includes 20 JTLs and / or gates in series with each other. In the exemplary I-clocked (Q-clock independent) bias level sensor 1600, the X of the sensing sampler stages (sensing JTLs and / or gates in quad configurations 1604, 1608) to which the 0° and 180° clocks are provided are AC The operating margin is, for example, an AC offset inductor L of 1.5 times the nominal tap self-inductance (e.g., 1.5 × 19.3 pH). offsetAC By inserting X DC -X AC Only at these sensed JTLs or gates is the AC amplitude of the I clock altered during a margin sweep optimization procedure that determines the optimal AC bias level for the I clock signal. In contrast, sampler stages 1602, 1606, and 1610 have an AC offset inductance L offsetAC is equal to 0 (AC offset inductor L offsetAC does not exist), so the X of the sampler stage JTL and / or gates in the sampler stages 1602, 1606, and 1610 AC The margin is the X of the JTL and the gate in the operation circuit 102. AC The amplitude of the Q clock supplied to the quad sampler stages 1602, 1606, and 1610 remains fixed during the margin sweep optimum procedure (while sweeping the AC amplitude of the I clock supplied to the sampling JTLs or gates in the quad sampler stages 1604 and 1608).

[0052] The graph in FIG. 17 shows an example AC and DC bias margin shmoo plot for a particular I-clock (Q-clock independent) bias level sensor 1600 of FIG. 16.AC When bias levels (nominal, 1 dB below nominal, 2 dB below nominal) are applied, the effect on the margin shmoo plot of a particular I sampler 1600 can be observed as different plot curves in Figure 17. The lower limit 1702 of the margin shmoo plot of the I sampler 1600 remains constant with variations in Q bias (it is not affected by the strength of the clock signal applied to the Q wrapper), confirming that the I bias level can be measured independently of variations in the Q bias level.

[0053] 18 shows another exemplary I-clocked (Q-clock independent) bias level sensor. The standard biased quad sampler stages 1802, 1806 are similar to those expanded in FIG. 14, and the modified biased quad sampler stage 1804 is similar to those expanded in FIG. 15. In the exemplary I-clocked (Q-clock independent) bias level sensor 1800, the margin shmoo plot for the sampler stage provided with a 180° clock (sampler stage in quad configuration 1804) shows that the AC offset inductor L has a value of, for example, 1.5 times the nominal tap self inductance (e.g., 1.5×19.3 pH). offsetAC By inserting X DC -X AC The inputs are shifted upwards in space. No AC offset inductors are used in the standard biased sampler stages 1802 and 1806 (as are the JTLs and gates in operational circuit 102). Sampler 1800 achieves the architectural simplification of sampler 1600 without incurring any loss in performance. Sampler 1800 has a margin shmoo plot similar to sampler 1600 shown in FIG. 17. In contrast to sampler 1600, sampler 1800 has a margin shmoo plot similar to that of sampler 1600 shown in FIG. AC Only the 180° phase clock is used, and no 0° phase clock is used, to define the lower limit 1702 of I sampler 1800. The lower limit 1702 of the margin shmoo plot of I sampler 1800 remains constant with variations in Q bias, confirming that the I bias level can be measured independently of variations in the Q bias level.

[0054] A challenge with the RQL circuit is that the I and Q clock signals 112, 114, which are generated to be 90° apart and in quadrature when measured at the signal generator 110 in the warm space, may not be 90° apart from each other at the level of the RQL IC 106 in the cold space due to components in the clock resonator network 104 that introduce undesirable phase shifts. An offset from 90° in the phase difference between the I and Q clock signals at the level of the RQL IC 106 can cause operational problems in the operational RQL circuit 102, including reduced operating margins. The circuit described herein can provide an indirect measurement of the phase error by measuring the effect on the operation of the sampler for different clock phase differences, by effectively converting the phase variation into an amplitude variation.

[0055] In addition to being sensitive to the I and Q clock amplitudes, the specific phase samplers 1200, 1300, 1600, and 1800 of Figures 12, 13, 16, and 18 are also sensitive to the phase difference between the I and Q clocks. When the phase difference between the I and Q clocks in the RQL IC 106 is 90°, the minimum X AC Therefore, the I and Q specific phase samplers 1200, 1300, 1600, and 1800 can be used to determine the optimum phase difference between the I and Q clocks, as generated by source 110, required to obtain a phase difference of exactly 90° between the I and Q clocks in the RQL IC 106. The graph in FIG. 19 shows the deviation of the Q clock phase from 90° (X at the lower limit of the margin shmoo plot for the I and Q specific samplers). AC 19 shows an example minimum operational AC bias for a particular I-clock and a particular Q-clock bias level sensor as a function of the AC offset inductance L of the I- and Q-sensing JTLs or gates for the sampler used to generate the graph of FIG. offsetACis 1.5 times the nominal tap self-inductance (the tap self-inductance used for the JTL or gate in the operational RQL circuit 102). The phase difference between the I and Q clocks varies ±45° around a nominal value of 90°. The horizontal axis of the graph in FIG. 19 is the deviation of the inter-clock phase difference from 90°. ACmin is equal at 1902 for both I and Q sensing JTLs or gates when the I / Q phase difference is 90°.

[0056] FIG. 20 is a graph showing the X phase 20 shows a 45° shift register 2000 with JTL or logic gates clocked at 45°, 135°, 225°, and 315° that can be used as a phase sampler, also called a phase sampler. phase The sampler can indirectly detect the phase difference between two AC clocks (e.g., between an I clock and a Q clock). In the phase sampler 2000 of FIG. 20, four hex sampler stages 2002, 2004, 2006, 2008 are arranged in series with each other, and each of the four hex sampler stages 2002, 2004, 2006, 2008 is biased by a clock signal of a different phase, which may be generated, for example, as a combination of other clock signals (e.g., as shown in Table 1 above). FIG. 21 shows the extension of the hex sampler stage code used for each of the hex sampler stages 2002, 2004, 2006, 2008 of FIG. 20. The first hex sampler stage 2002 is biased by a 45° clock. The second hex sampler stage 2004 is biased by a 135° clock. The third hex sampler stage 2006 is biased by a 225° clock. The fourth hex sampler stage 2008 is biased by a 315° clock. A combined clock waveform providing a 45°, 135°, 225°, or 315° phase clock can be provided by transformer coupling to both the I (0° or 180°) and Q (90° or 270°) clock resonators (as shown in Table 1 above). X in FIG. phaseUsing sampler 2000 to directly measure the phase error between the I and Q clock signals may involve first equalizing the amplitudes of the I and Q clock signals using separate sensors (e.g., an I-independent clock amplitude sensor such as the specific-phase I sampler 1300 of FIG. 13, and a Q-independent clock amplitude sensor such as the specific-phase Q sampler 1200 of FIG. 12).

[0057] In the expansion 2100 of each of the hex sampler stages 2002, 2004, 2006, 2008 of FIG. 21, each individual component stage 2102, 2104, 2106, 2108, 2110, 2112 of each sampler stage 2002, 2004, 2006, 2008 includes an AC offset inductor L inserted between the JTL or gate and its corresponding bias tap. offsetAC (or equivalently, the magnified bias tap inductor L 2 ) and an AC offset inductor L offsetAC provides a bias self-inductance that is greater than the bias self-inductance of the JTLs and gates in the operational RQL circuit 102. Thus, each sampler stage 2102, 2104, 2106, 2108, 2110, 2112 provides a bias self-inductance that is greater than the bias self-inductance of the JTLs and gates in the operational RQL circuit 102. DC -X ACWith a margin shmoo plot elevated in space. The JTLs or gates of each sampler stage 2102, 2104, 2106, 2108, 2110, 2112 are biased with an AC clock signal of the same phase ("Phase°"). As described above, concatenating several sampler stages all biased with the same AC clock phase mitigates the effects of current (or, alternatively, magnetic flux) sharing between adjacent JTLs biased by clock signals of different clock phases. The particular number of sensing JTLs required to provide this insensitivity depends on the details of the JTLs and / or gates and their individual bias taps. In some examples, concatenating between four sampler stages and six sampler stages may be sufficient to provide the desired flux sharing mitigation. While FIG. 20 shows an example of a phase sampler 2000 having six sampler stages driven by the same clock phases per set 2002, 2004, 2006, 2008, i.e., each sampler stage 2002, 2004, 2006, 2008 includes a set of six sampler stages driven by the same clock phases directly coupled in series to each other, other examples may have more or fewer sampler stages driven by the same clock phases directly coupled in series to each other, for example, four, five, or seven JTLs or gates driven by the same clock phases directly coupled in series to each other in each set, or various numbers of JTLs or gates driven by the same clock phases directly coupled in series to each other in different sets.

[0058] min x ACThe clock amplitude, i.e. the amplitude of the AC flux provided by the transformer for the 45° and 135° combined clocks, is plotted in FIG. 22 as a function of phase error (phase difference between the I and Q clocks). The sampler stage responds to these differences in clock amplitude. Thus, the phase error can be calibrated based on information about the operating margin observed at the sampler stage while varying the I / Q phase. In the 45° shift register 2000 of FIG. 20, the clock amplitude of the 45° and 225° converters decreases and the clock amplitude of the 135° and 315° converters increases as the inter-clock phase difference (phase error) increases relative to 90°. The graph of clock amplitude vs. phase error in FIG. 22 illustrates this relationship for the exemplary phase sampler 2000 of FIG. 20. The AC amplitude graph of the minimum operating bias signal in FIG. 23 shows how this characteristic is applied to the phase-sensitive X-phase sampler 2000. phase A phase sampler for forming a shift register having sampler stages of 45°, 135°, 225°, and 315° is shown in the form of a phase sampler 2000 in FIG. 20. As shown in FIG. 23, the lower limit (X ACmin ) is the minimum X when the phase difference (phase error) between the I clock and Q clock measured on the RQL IC106 is 90°. AC FIG. 20 shows an example with six sampler stages, each with a specific phase sampler stage 2002, 2004, 2006, 2008, but with X phase Other exemplary shift registers configured as samplers may have more or fewer sampler stages per configuration 2102, 2104, 2106, 2108. A method 3000 for calibrating a clock signal phase using a phase-sensitive sampler such as the phase sampler 2000 shown in Figure 20 is shown in Figure 30 and described in more detail below.

[0059] Figure 24 illustrates a representative portion of a phase mode logic (PML) bias level sensing configuration 2400 that can sense and read out bias amplitudes using flip-flops (e.g., flip-flops 2402, 2404, 2406) and phase mode shift registers (e.g., shift registers 2408, 2410, 2412, 2414, 2416, 2418, 2420, 2422, 2424). Thus, the PML bias level sensing configuration 2400 of Figure 24 can provide similar functionality to the ladder wrapper configuration of Figure 2A, where the PML bias level sensing configuration 2400 provides sensors that are individually testable for their operating range under variable RQL bias conditions and can be placed in multiple locations on the RQL IC 106, but have a different structure and method of use than the configuration of Figure 2A. Testing and adjusting bias levels using configuration 2400 of Figure 24 involves changing the AC levels in the resonator under test, in different examples, the I resonator (as shown) or the Q resonator (not shown). Similar to the RQL scan register or JTL testbed of Figure 2A, multiple sensors are activated and their responses are read out using a shift register circuit structure.

[0060] The structure 2400 of Figure 24 forms a shift register such that each time a logic clock assertion signal (e.g., provided as a reciprocal pair of SFQ pulses, or in some cases as the first positive SFQ pulse of such a pulse pair) travels through the logic clock path 2426 (right to left in the orientation of Figure 24) and is provided to the clocking inputs of the D flip-flops (e.g., D flip-flops 2402, 2404, 2406), a pattern signal provided on the data path 2428 travels one shift register element through the shift register 2400 (left to right in the orientation of Figure 24). A single element of the shift register 2400 is enclosed by a dashed box 2430, which has one D flip-flop 2416 and JTL-based shift registers 2410, 2416, 2422. Register 2400 can include any desired number of elements such as element 2430 arranged in series with one another, with each element located at a location on RQL IC 106 such that it is connected to a clock resonator in that portion of IC 106. Thus, each element sees a different physical connection (tap) 120 to AC clock network 104 within RQL IC 106. In Figure 24, each small triangle represents a buffer, e.g., a JTL-based buffer. The flip-flops (e.g., flip-flops 2402, 2404, 2406) of the shift register 2400 may be implemented, for example, as PML flip-flops, examples of which are described in U.S. Pat. No. 10,615,783, entitled "RQL D Flip-Flops," and U.S. Pat. No. 10,756,712, entitled "RQL Phase-Mode Flip-Flop," both of which are incorporated herein by reference. The number (in degrees) above each flip-flop or buffer represents the phase of the clock provided to the flip-flop or buffer below it. Clocks of different phases may be provided by connecting different clock resonators 104 on the RQL IC 106 through different transformers, or in some cases by connecting different combinations of transformers.

[0061] In some examples of shift register 2400, the elements of the shift register may be designed and manufactured to each have different operating margin offsets from one another, and these offsets may be linearly or in some other manner stepped, similar to how the bias level sensors 202-212 of the ladder wrapper configuration 200 of FIG. 2A may be purposely configured with stepped operating margin offsets, as described above. In some examples, the bias transformers connecting the AC clock network to the D flip-flops in shift register 2400 may be altered from their normal values, such that the D flip-flops of shift register 2400 are all under-biased or over-biased with the same amount of under-biasing or over-biasing, or with different degrees of under-biasing or over-biasing. Thus, a D flip-flop can be expected to fail (cry out because the AC bias point is outside the D flip-flop's AC operating margin) with a fluctuating AC bias at a larger AC bias amplitude (at a higher AC bias point) than the AC amplitude at which a JTL-based buffer would fail with the same fluctuating AC bias. Because D flip-flops are not as robust as JTLs with respect to their operating margins, even if the D flip-flop is not intentionally under-biased, it may fail at a higher AC bias point than the AC bias point at which a JTL-based buffer would fail for the same fluctuating AC bias.

[0062] The PML flip-flop-based bias sampler in the shift register configuration 2400 of FIG. 24 is responsive to variations in the clock resonator, the bias coupling transformer, and all other circuit parameters. Thus, the use of the PML flip-flop-based bias sampler in the shift register configuration 2400 of FIG. 24 can help identify the bias levels required for an operational RQL circuit 102 that can be expected to be affected by variations in all process parameters. In particular, the PML flip-flop-based bias sampler is sensitive to the self-inductance of the bias coupling transformer, the mutual inductance between the bias coupling transformer and the corresponding clock resonator, the magnitude of the current in the clock line, the inductance of the coupling transformer, the inductance in the JTL and gate, and the critical current of the Josephson junction (JJ).

[0063] In the example 2400 illustrated in FIG. 24, the Q clock resonator may be driven at a nominal bias level to ensure that logic clock signals are provided to all of the flip-flops (e.g., flip-flops 2402, 2404, 2406) in the shift register 2400, while the I resonator may be driven with varying AC amplitudes to test whether the shift operation is successful over a range of different AC amplitudes. For example, the operating range of each of the flip-flops may be determined independently for each flip-flop by performing the method 2900 illustrated in the flow diagram of FIG. 29. With the AC amplitudes of the Q and I clocks set to nominal values ​​(2902) and the logic clock running, a bit pattern of test data may be shifted in (2904) into the data path 2428. The logic clock may be performed by inputting a continuous stream of reciprocal pulse pairs into the logic clock path 2426. Thus, the shifting in of the initial data (2904) is performed while driving the I resonator at the nominal AC bias amplitude level. After the test data bit pattern is shifted into the PML shift register 2400, with the logic clock subsequently stopped (2906), the I resonator AC bias amplitude may be changed (2908) to test for AC bias amplitude levels greater than or less than nominal. A single logic clock assertion (e.g., a single positive SFQ pulse or reciprocal pulse pair) may then be input (2910) into the logic clock path 2426. The I resonator AC bias amplitude may then be returned to the nominal value (2912) and the logic clock restarted to shift out the output data bit pattern on the data path 2428 (2914). The output data bit pattern may be observed (2916), for example, following output of the data bit pattern via the input / output circuitry of the RQL IC 106. Observation may be performed, for example, by conventional semiconductor circuitry (e.g., CMOS circuitry) outside the cooling space of the RQL IC 106.

[0064] If the output data bit pattern does not match the input data bit pattern, it can be determined that at least one of the elements 2430 of the PML shift register 2400 is outside of its operating margin under the conditions of the altered I resonator AC bias amplitude, and precisely which element 2430 is outside of its operating margin can be identified by the point in the output data bit pattern where the output data bit pattern no longer matches the input data bit pattern (e.g., by a single bit error found in the output data bit stream). In some examples, multiple shift errors in the data bit pattern (e.g., multiple single bit errors between the input and output data bit streams) can be used to identify multiple shift register elements operating outside their respective margins.

[0065] By observing the data output when one of the elements of the shift register 2400 has failed (e.g., due to the provided 2908 bias point being outside the operating margin of that element), and, for example, comparing the output data bit pattern to the input data bit pattern, it may become apparent which bit failed to progress through the shift register 2400 in the bit data stream at some point in the output bit data stream. For example, if the input data bit pattern consists of alternating pairs of "0"s and "1"s, the output data bit pattern may contain, somewhere in the bit stream, three "0"s in a row followed by a "1" ("0001"), or three "1"s in a row followed by a "0" ("1110"). The location of the extra bit may indicate the identity of the element of the shift register 2400 that was outside its operating margin during the progression of a single clock. An exemplary input data bit pattern may consist of a series of alternating pairs, triplets, etc. of logical "1's" and "0's" depending on the length of the PML shift register 2400, such as "0011001100110011" for a 16-bit shift register. The method 2900, or portions thereof, may be repeated in some examples with a bit pattern offset to ensure that transitions arrive at different flip-flops of the shift register 2400, providing complete data probing of the shift register 2400. For example, a "0011001100110011" or "1100110011001100" bit pattern may be capable of detecting only errors caused by odd numbered elements of shift register 2400, while a "1001100110011001" or "0110011001100110" bit pattern may be capable of detecting only errors caused by even numbered elements of shift register 2400. Other input data bit patterns may also be used.A conventional semiconductor circuit (e.g., a CMOS circuit) outside the cooling space of the RQL IC 106 can perform a comparison between the input data bit pattern and the output data bit pattern or otherwise detect anomalies in the output data bit pattern that indicate a failure of the flip-flop due to variations in the bias parameters.

[0066] 29, after the output data bit pattern provided on data path 2428 of shift register 2400 of FIG. 24 is observed 2916 for differences from the input data bit pattern, it may be evaluated 2918 whether the AC bias amplitude parameter has been optimized. For example, if a number of different AC bias amplitudes are provided to shift register 2400, data may be compiled that indicates which AC bias amplitude is the furthest from a value that would cause an error in the output data bit pattern, from which a conclusion may be drawn as to which AC bias amplitude is optimal. As an example, an AC bias amplitude that is between two extreme values ​​of the AC bias amplitude that are within the operating margin (e.g., an average value) may be selected as the optimal AC bias amplitude. As another example, if the bias tap values ​​of the D flip-flops are set in stages to provide different amounts of AC bias per flip-flop, the output data bit stream can be analyzed to determine which D flip-flops have failed AC bias adjustment and which have not, and the optimal AC bias can be determined based on the respective operating margins of the working and failed flip-flops during the test. If insufficient data is collected to draw a conclusion regarding the optimality of the bias parameters, the test can be repeated by resetting the AC bias amplitude to the nominal value (2902), restarting the logic clock (2904), and shifting in the same or a different input data bit pattern (2904) and repeating portions of the test process 2902-2918. This portion of the test process can be repeated iteratively as many times as necessary to be confident that the AC bias amplitude has been optimized (2920) for the AC clock resonator under test (e.g., the I resonator in the example as shown in FIG. 24). In some instances, the AC bias amplitude is not optimized, but is, for example, improved from a starting or nominal value.

[0067] 29 is outlined with respect to AC bias adjustment or optimization, a similar method may be used for DC bias adjustment or optimization, or for phase error adjustment or optimization. In DC bias adjustment or optimization, the DC bias value of the bias signal supplied to the D flip-flop may be changed (2908) rather than the AC amplitude value, and in some examples, the transformer coupling strength to the DC bias line of the D flip-flop of the phase mode shift register under test may be stepped so that multiple flip-flops are aligned X-axis relative to each other, each with a different strength of DC bias coupling, as shown in FIG. DC 22 shows different operating margin shmoo plots shifted in the X dimension. In addition to the AC amplitude values, in phase error adjustment or optimization, the phase difference between the I and Q clock signals fed to the D flip-flop can be changed (2908) to produce a two-dimensional X-axis shmoo plot as shown in FIG. AC -X phase A search can be performed, with each D flip-flop biased by an AC bias signal that is a mixture of the I and Q clock signals. In some examples, the transformer coupling strength to the AC bias lines of the D flip-flops of the phase-mode shift register under test is stepped so that each D flip-flop has a different strength of AC bias coupling to the mixed resonator clock signal, causing the flip-flops to be biased X relative to each other, as shown in FIG. 5A. AC 4 shows different operating margin shmoo plots shifted in dimension.

[0068] While a conventional RQL shift register may travel with at least four phases (e.g., 0°, 90°, 180°, 270°) in all paths, the PML shift register 2400 is configured such that the logical clock path 2426 is coupled to the clock resonator 104 to receive only two phases (in the illustrated example, 90° and 270°) in the trunks 2420, 2422, 2424 of the logical clock path, and the data path 2428 is coupled to the clock resonator 104 to receive only the other two phases (in the illustrated example, 0° and 180°). Thus, the trunks of the logical clock path 2426 are powered by only one clock resonator (in the illustrated example, the Q resonator) and the data path 2428 is powered by only the other clock resonator (in the illustrated example, the I resonator). This configuration ensures that even if the data path 2428 is stressed and fails by changing the bias parameters for one or more shift register elements outside the data path's operating margins, the logic clock path 2426 remains functional, thus ensuring that the logic clock signal reaches all flip-flops in the shift register 2400, even those that have failed due to bias parameter adjustments. Thus, the phase assignment isolates the operation of the flip-flops to one AC clock resonator, and the logic clocks that drive the flip-flops to different AC clock resonators. The 0° buffers in the branches 2414, 2416, 2418 in the logic clock path can be considered as part of the corresponding flip-flop circuits 2406, 2404, 2402 in the above description. In the illustrated example 2400, the buffers driving the clock pins of individual flip-flops may be required to be on the same clock phase as the flip-flops.

[0069] Buffers shown in dashed lines in Fig. 24, such as buffers 2432, 2434 in logical clock path 2426 and buffer 2436 in data path 2428, may be of a different design than the buffers shown in solid lines in Fig. 24. Each of the buffers shown in dashed lines in Fig. 24 may include an additional Josephson junction grounded at the input of the respective JTL, allowing them to reliably operate at a 180° phase delta from the previous cell. Without this additional Josephson junction, there may be ambiguity as to whether an SFQ pulse waiting at a boundary will propagate in the forward or reverse direction when the AC bias signal supplied to the corresponding buffer rises.

[0070] In another exemplary PML shift register similar to shift register 2400, but not shown, a 90° AC clock phase can be added to all phase values ​​shown in FIG. 24 to provide a bias level sensing configuration that tests the Q clock resonator instead of the I clock resonator. In such an example, the trunk of the logic clock path is driven by the I resonator and the data path is driven by the Q resonator. In such an example, the "resonator under test" in method 2900 of FIG. 29, and the resonator whose AC amplitude is changed (2908) as part of method 2900, is the Q resonator instead of the I resonator. In another exemplary modification of PML shift register 2400, the JTL-based buffer in the logic clock path can include an offset bias transformer as shown in and described above with respect to FIG. 6. Such a modification can effectively shift the operating margin of the clock supply, which can allow samples to be taken when the operating logic is closer to the nominal AC bias.

[0071] In other exemplary PML shift registers similar to shift register 2400, but not shown, an AC clock phase of 45° or 135° can be added to all phase values ​​shown in FIG. 24 to provide a bias level sensing configuration in which the trunks of the data and logic clock paths receive bias signals that are a mix of an I clock at 0° and a Q clock at 90°. For example, the data paths can be driven by AC signals of 45° and 225° phase, and the trunks of the logic clock paths can be driven by 135° and 315° signals. As another example, the data paths can be driven by AC signals of 135° and 315° phase, and the trunks of the logic clock paths can be driven by 45° and 225° signals. Such an example can be useful to determine the phase error between the I and Q clock signals and to improve or optimize the phase of the I and Q clocks to true quadrature. In another example modification of PML shift register 2400, the JTL-based buffers in the logic clock path can include an offset bias transformer as shown in and described above with respect to Figure 6. Such a modification can effectively shift the operating margin of the clock supply, which can allow samples to be taken when the operating logic is closer to the nominal AC bias.

[0072] FIG. 25 shows an example proximal portion of a configuration 2500 in which pulse generators 2502, 2508 are connected to RQL gates (AND gates 2504, 2510 in the illustrated example) to form a bias level sensor (sampler). A portion of a wrapper for a pulse generator based bias level sensor is shown in FIG. 25, which resembles the ladder configuration shown in FIG. 2A and has a repeating circuit pattern of runs (e.g., the first two runs 2512, 2514) and rails (2516, 2518) between a proximal input / output end (shown at the bottom of FIG. 25) and a distal end (not shown in FIG. 25), with the runs located between the input rail 2516 and the output rail 2518 of the wrapper ladder. The rails 2516, 2518 may extend the entire length of the clock resonators connected by the wrapper, for example. As an example, the wrapper has about 2,000 stages, each stage having a pulse generator-based sampler that individually samples the clock resonator at a different position along the clock resonator. The JTL, represented as a triangle in FIG. 25, provides the timing delay. The sample signal input 2506 provides the wrapper ladder with an SFQ pulse as a sample signal, which propagates along the input rail 2516 (upward in the orientation of FIG. 25), branches and replicates along each stage, and either returns or does not return to the output OUT along the output rail 2518 (downward in the orientation of FIG. 25) depending on whether the individual samplers embedded in the stages of the wrapper ladder are within their operating margins. Thus, in the wrapper shown in FIG. 25, a single sample SFQ pulse provided at the input 2506 results in a series of output SFQ pulses separated in time at the output OUT.

[0073] Each of the pulse generators (e.g., pulse generators 2502, 2508) in configuration 2500 comprises a Josephson junction having a first end grounded via an inductor and a second end inductively coupled to an AC bias transformer (e.g., via a coupling transformer). The second end substantially provides the output of the pulse generator. Each pulse generator outputs an SFQ pulse to its corresponding ladder stage for each cycle of an AC clock driving the pulse generator, provided that the pulse generator is driven within its operating range, e.g., provided that the amplitude of the AC clock driving the pulse generator is within the AC operating margin of the pulse generator. To help reduce the variation of the Josephson junctions of the pulse generators, the Josephson junctions of the pulse generators can be sized larger, and therefore have a larger critical current, than the Josephson junctions used in the JTLs and gates of the operating RQL circuit 102. The output of each pulse generator is gated by a sample signal via a corresponding gate (e.g., gates 2504, 2510 in FIG. 25). Thus, each pulse generator operates continuously to provide repeated SFQ outputs to its corresponding stage as long as the provided AC bias is within the operating margins of the pulse generator, but only the SFQ outputs generated substantially simultaneously with the arrival of a sample signal pulse on the same stage (e.g., within the same AC clock cycle or half clock cycle) propagate down the output rail 2518 to the output OUT.

[0074] The operating range of each pulse generator in the sensing system of FIG. 25 can be individually set, for example, by configuring each pulse generator to have stronger or weaker coupling strength to one or more AC clock resonators and / or DC bias lines that provide bias (drive) the pulse generator. For example, the X ACShifting (offsetting) the margins allows the pulse generator to start and stop operating in response to varying levels of AC bias provided (varying amplitude of the driving AC clock), and bias point variations that allow sensing can determine those operating levels even while still allowing the operating RQL circuit 102 to remain within its operating margins.

[0075] X AC The margin shift may be implemented in some examples by increasing the critical current of the JJ in the pulse generator. Increasing the critical current of the JJ in the pulse generator in a pulse generator-based sampler is similar to the X DC -X AC In the plot, this has the effect of shifting the margin shmoo plot of the corresponding sampler up and to the right because a higher DC and AC bias amplitude is required to flip the pulse generator's JJ due to the increased critical current. The JJ critical current occurs when the AC and DC bias generated by the pulse generator's bias coupling transformer falls within the margin shmoo plot (operating region) of the operational JTL circuit 102. DC -X AC The bias point may be selected to be a threshold that triggers the pulse generator's JJ every AC clock cycle. For example, the margin shmoo plot (operating region) of the pulse generator-based sampler may be located within the margin shmoo plot of the operational JTL circuit 102, so that the pulse generator-based sampler may be driven into and out of the operating region that generates pulses by varying the bias delivered to both the pulse generator-based sampler and the operational RQL circuit 102, but the bias delivered remains within the operating region of the operational RQL circuit 102 so that the operational RQL circuit 102 continues to function. As with the example of FIG. 2A, the pulse generator-based samplers of FIG. 25 are driven into and out of the operating region that generates pulses by varying the bias delivered to both the pulse generator-based sampler and the operational RQL circuit 102, so that the operational RQL circuit 102 continues to function. AC and / or X DCThe operating margin offsets may be stepped, for example, linearly arranged along a ladder from the lowest AC margin to the highest AC margin, or from the highest AC margin to the lowest AC margin, or any other arrangement that may be taken into account when evaluating the output. DC The stepwise setting of, for example, the length of the DC part of the coupling transformer is changed in the pulse generator-based sampler of FIG. 25 to obtain the respective margin shmoo plots of the pulse generator-based sampler as shown in FIG. 5A. DC -X AC This may be provided by a substantial shift in space to the left or right.

[0076] The pulse generator-based sampler of Figure 25 may be disposed on the RQL IC 106 to connect to the clock resonator 104 at various points along the resonator. Although not shown in Figure 25, an input sample SFQ pulse may be provided to the input 2506 using an input transformer coupled to the input 2506 similar to the input transformer 252 shown in Figure 2A, and the output SFQ pulse may be converted to a voltage pulse using an output amplifier coupled to the output OUT similar to the output amplifier 254 shown in Figure 2A.

[0077] The pulse generators in configuration 2500 (e.g., pulse generators 2502, 2508) are sensitive to manufacturing variations in the JJs that compose them, as well as variations in the clock resonators and coupling transformers, and are relatively less sensitive to other circuit parameters compared to JTL or gate-based samplers that have large self-inductances as discussed above with respect to Figures 6, 8A, 9A, 10A, 11A, 12, 13, 16, and 18. For example, the pulse generator-based sampler of Figure 25 is not particularly sensitive to variations in the inductance of the circuit side of the ground plane in the RQL IC 106. Thus, configuration 2500 is particularly well suited to assess the performance of clock resonators and coupling transformers, and is useful, for example, in assessing the self-inductance of coupling transformers, the mutual inductance between coupling transformers and the clock resonators to which they are coupled, and the magnitude of currents in the clock resonators.

[0078] The pulse generators in configuration 2500 may be configured to measure a specific I (Q independent) or a specific Q (I independent) reading by coupling the sampler to an appropriate clock bias resonator, as described above with respect to Figures 12, 13, 16, and 18, and listed in Table 1. The pulse generators in configuration 2500 may also be configured to measure the phase difference between the I and Q clocks (in some examples, with the AC bias amplitudes first calibrated for both the I and Q clock bias signals), which may be measured by driving multiple pairs of pulse generators in a single wrapper, or by driving multiple pulse generators in different wrappers with a mixed clock signal separated by 90°, for example, a first pulse generator (or a first pair in a first wrapper of a pulse generator-based bias level sensor). This can be achieved by driving the first pulse generator (or the first set of pulse generators in the first wrapper of the pulse generator-based bias level sensor) with a 45° clock and the second pulse generator (or the second set of pulse generators in the second wrapper of the pulse generator-based bias level sensor) with a 135° clock, or by driving the first pulse generator (or the first set of pulse generators in the first wrapper of the pulse generator-based bias level sensor) with a 225° clock and the second pulse generator (or the second set of pulse generators in the second wrapper of the pulse generator-based bias level sensor) with a 315° clock. The outputs of the pulse generators driven at 45° and 135° (or the pulse generators driven at 225° and 315°, etc.) are equal only if the phase difference between the two driving clocks is 90° and the AC amplitudes of the AC signals provided by the I and Q clock resonators are equal. This mixed clock setup can therefore be used to determine the true quadrature phase between the I and Q clock signals and can be used to inform or indicate adjustments to the I and Q clock phases, or adjustments to the phase difference between the I and Q clock phases, to improve or optimize the orthogonality for a 90 degree phase difference between the I and Q clocks.As an example, the process described with reference to FIG. 30 can be used in configuration 2500 to determine the optimal phase difference between the I and Q clocks at which to drive the I and Q clocks in the warm space to achieve true quadrature (90° phase separation) between the clocks in the operating RQL circuit 102 on the RQL IC 106 in the cooled space.

[0079] FIG. 26A illustrates an exemplary configuration of samplers 2602-2610 arranged in a DC SQUID-based bias level sensor 2600. The samplers 2602-2610 may be based on JTL or RQL gates, as described above with respect to FIG. 6, and may comprise one or more sampler stages in series with each other, as described above with respect to FIGS. 15 and 21. The samplers 2602-2610 act as triggers for the DC SQUIDs 2612-2620. Each sampler 2602-2610 adjusts its parameter (X AC Or X DC2A-2C )。 Thus, the voltage level of the output pulse generated by the stack of DC SQUIDs 2612-2620 varies depending on the bias level applied. Thus, the configuration 2600 can be considered as a single bias level sensor with a voltage output that varies with the number of individual samplers 2602-2610 biased in the operating region when a sample signal pulse is applied to the sample signal input. The output voltage may be indicative of the sensed bias parameter (AC bias amplitude or DC bias value) that the sensor 2602 is configured to measure, given the appropriate graduated setting of the bias coupling strengths of the sensors 2600-2610, for example, as described above with respect to Figures 4A and 5A. Because the sensor 2600 can measure the outputs of the individual sensors 2602-2610 in parallel and simultaneously, the sensor 2600 may have a higher output throughput than the configurations of Figures 2A-2C. The sensor 2600 generates an output voltage pulse each time an input SFQ pulse is applied to the sample signal input, which may be as frequent as once per AC clock cycle.

[0080] Each DC SQUID 2612-2620 in the DC SQUID stack of sensor 2600 receives input from a respective sampler 2602-2610 via a respective transformer coupling to the DC SQUID. Each respective transformer coupling is shown in FIG. 26A as a dashed line between each sampler 2602-2610 and the respective DC SQUID 2612-2620 that is transformer coupled to the sampler. Each sampler can be, for example, a JTL. The JTL determines the desired X from the nominal AC A separate AC offset inductor L is added to provide both the offset (as shown in FIG. 3) and the desired stepwise setting (sampler-to-sampler variation). offsetACThe sizes of the samplers 2602-2610 are adjusted. In the example of FIG. 26A, the DC SQUID stack is shown as including multiple stages (five samplers 2602-2610 and five corresponding DC SQUIDs 2612-2620), but in other examples, the stack can include more or fewer stages (more or fewer samplers and corresponding DC SQUIDs), with more stages providing finer resolution of the output voltage signal or allowing multiple bias parameters to be sensed. For example, some of the samplers 2602-2610 can be configured to sense AC bias amplitude and other samplers can be configured to sense DC bias values, or some of the samplers 2602-2610 can be configured to sense AC bias amplitude of one clock resonator, I or Q, or some combination of clock signals, and other samplers can be configured to sense AC bias amplitude of a different clock resonator, or some different combination of clock signals. In different examples, the structure of the sensor 2600 of FIG. 26A can have 5-10 stages.

[0081] A sample signal input may be provided to each of the samplers 2602-2610, for example, via a binary vine tree (not shown) of a JTL, in some examples, such that the sample signal arrives at each of the samplers 2602-2610 substantially simultaneously. Similar to the examples described above (e.g., the examples of FIGS. 2A and 25), the samplers may use the variation in mutual inductance for individual AC resonators or DC bias lines measured by the individual samplers to calculate the X AC Shift and / or X AC Staged setting and / or X DC It is possible to set it stepwise. The DC bias current I, which is insufficient by itself to trigger any of the SQUIDs 2612-2620, BIASOUT is provided between OUTP and OUTN to bias the SQUID stack so that the current provided by the input sample pulse distributed through samplers 2602-2610 to SQUIDs 2612-2620 is sufficient to trigger the individual SQUIDs. BIASOUTcan be supplied external to the RQL IC 106 in which the sensor 2600 is implemented, and the voltage signal between OUTP and OUTN is made available at a pad on the RQL IC 106, so that the signal from the sensor of FIG. 26A can be made available for direct measurement by external test equipment, for example, and no logic is required to process or interpret the output.

[0082] In the example shown in FIG. 26A, the five samplers 2602-2610 are represented by values ​​X AC1 ~X ACN The AC amplitude margin variation given by X AC For example, a resonator clock network can be fabricated on the RQL IC106 to operate under the samplers 2602-2610, with different AC offset inductors L offsetAC can be provided for each sampler 2602-2610 to cross-couple power to the individual samplers based on the I and Q bias signals required for the clock phase desired to be provided to the sampler. AC The value indicates the nominal bias level of the sampler, and X AC The variation in value represents a greater or lesser AC bias level coupled to the sampler. AC Values ​​are shown as an example of a linearly stepped configuration of a five sampler configuration as shown in Figure 26 A. In operation, when a sample signal input pulse is provided to the sensor 2600, the magnitude of the bias level provided to all of the samplers 2602-2610 can be externally varied, with different strengths of bias to each of the samplers 2602-2610 resulting in different numbers of SQUIDs 2612-2620 contributing to the potential difference between the output voltage terminals OUTP and OUTN depending on how many samplers are operating under the bias conditions provided.

[0083] For example, the sampler 2610 may select an AC offset inductor LoffsetAC The 125% X AC The sampler 2610 having a value of 1000 requires a higher AC bias level to transfer the input sampler pulse to its corresponding DC SQUID 2620, while the sampler 2602 has a smaller AC offset inductor L offsetAC 75% of the X AC The sampler 2602 with a 75% X value requires a relatively low AC bias level to operate. AC The sampler 2602 with the value 125% of X AC Even if the sampler 2610 with the value cannot continue to operate (because the AC bias level is below and therefore outside its operating region), it can continue to operate at a higher bias current (because a higher supply bias current is within its operating region).

[0084] For example, in the configuration 2600 of Figure 26A, if each SQUID 2612-2620 generates a potential difference of approximately 0.5 mV when activated by a corresponding operating sampler 2602-2610, then the voltage output between OUTP and OUTN is approximately 2.5 mV when the supplied bias levels are within the individual operating regions of all samplers 2602-2610. This output voltage decreases when fewer than all of the samplers 2602-2610 are supplied with bias within their individual operating regions. For example, the output voltage of the configuration 2600 may be approximately 2 mV if only four samplers 2602-2610 are operating with the bias level applied, approximately 1.5 mV if only three samplers 2602-2610 are operating with the bias level applied, approximately 1 mV if only two samplers 2602-2610 are operating with the bias level applied, approximately 0.5 mV if only one of the samplers 2602-2610 is operating with the bias level applied, and approximately 0 mV if none of the samplers 2602-2610 are operating with the bias level applied. In the five stage example of FIG. 26A, the AC bias amplitude may be considered calibrated if the amplitude is changed to obtain approximately three-fifths of the maximum output voltage pulse height. In the five stage example of FIG. 26A, the AC bias amplitude can be considered calibrated if samplers 2602 and 2604 are within their operating range and therefore provide a split input sample signal to their corresponding SQUIDs 2612, 2614, samplers 2608 and 2610 are outside their operating range and therefore do not provide a split input sample signal to their corresponding SQUIDs 2618, 2620, and sampler 2606 is exactly within its operating range and therefore provides a split input sample signal to its corresponding SQUID 2616.

[0085] The operational RQL circuit 102 of FIG. 1 provides an appropriate current level for the output bias current I BIASOUT26A , which may require biasing at a current level that may vary with variations in circuit fabrication process and / or system setup. BIASOUT The applied level of the output bias current I BIASOUT The output bias current I can be used to sense how well it meets the requirements of the output amplifier to which it is applied. BIASOUT 26B illustrates an exemplary DC SQUID-based output amplifier 2650 configured as a level sensor. The configuration 2650 of FIG. 26B is similar to the configuration 2600 of FIG. 26A, but with the addition of AC offset inductors L of the corresponding samplers 2602-2610. offsetAC The inductance values ​​of the standard bias samplers 2652 to 2660 are not set in stages, but rather there is no difference between the self-inductances of the standard bias samplers 2652 to 2660 (for example, the AC offset inductor L offsetAC 26B), instead, the critical currents Ic of the JJs of the corresponding DC SQUIDs 2662-2670 are stepped to individual offsets relative to a nominal value. C3 = 100%), while other SQUIDs in the stack have lower critical currents (e.g., SQUIDs 2662 and 2664 each have a critical current I C1 =75% and I C2 = 87.5% JJ) or higher critical current (e.g., SQUID 2668, 2670 have critical current I C4 =112.5% ​​and I CN = 125% JJ) As with the example shown in Figure 26A, the example of Figure 26B can have more or fewer DC SQUIDs in its DC SQUID stack, with more stages providing finer output voltage signal resolution.

[0086] In the example 2650 of FIG. 26B, an output bias current I BIASOUTcan be varied to determine the optimum DC bias on the bias line of the output amplifier, i.e., the optimum bias current for SQUIDs 2662, 2664, 2666, 2668, and 2670. For example, if a five SQUID stack is used as shown in FIG. 26B, the output bias current I of the output amplifier can be adjusted to obtain approximately three-fifths of the full output voltage pulse height with each sample SQUID pulse presented to the sample signal input. BIASOUT 26B does not separate the respective effects of AC and DC bias on the samplers 2652-2660 that trigger the SQUIDs 2662-2670 or other JTLs in the circuit. The example configuration 2650 may, for example, vary the output bias current I BIASOUT can be used to calibrate X AC and X DC is first independently adjusted, improved, or optimized, and the output bias current I BIASOUT can then be adjusted, improved, or optimized.

[0087] Because the output amplifier-based configurations 2600, 2650 of Figs. 26A and 26B instantaneously indicate the number of samplers in the configuration that are operational for each sample signal provided, these configurations improve the output throughput of bias level sensing compared to the RQL scan register configurations as in Figs. 2A or 25, the ring oscillator configurations as in Fig. 2C, or the PML shift register configurations as in Fig. 24, each of which may take longer than the output amplifier-based configuration to provide a complete output indicative of the bias parameter being sensed. In some examples (not shown), different amounts of time delay can be added to each branch of the output amplifier-based configurations 2600, 2650 of Figs. 26A and 26B to allow for time division multiplexing (e.g., by adding different numbers of additional standard bias JTLs to the samplers in each branch of the output amplifier-based configurations 2600, 2650 of Figs. 26A and 26B). For example, phase shifts can be added in 90° increments or 45° increments. In one example, each branch of the output amplifier structure 2600 or 2650 of FIG. 26A, FIG. 26B has a time delay (e.g., from top to bottom) to assign a phase of 0°, 45°, 90°, 135°, 180°, etc. This exemplary configuration provides a time-based step function signal at the output, where the output signal increases or does not increase by 0.5 mV increments for each time step depending on whether the SQUID of the corresponding stage of the output amplifier configuration was induced to operate, which in the example of FIG. 26A depends on whether the corresponding JTL-based sampler 2602-2610 is within its operating range. The time-shifted outputs can then be used to identify which of the samplers 2602-2610 delivered a signal to and triggered the corresponding SQUID 2612-2620.

[0088] A serial output ladder wrapper (RQL scan register) structure such as that of FIG. 2A may also be used to calibrate the output bias current of an output amplifier by implementing its bias level sensors 202-212 as output amplifier emulators. A JTL-based bias level sensor configured as an output amplifier emulator may have the following characteristic properties. First, each bias level sensor configured as an output amplifier emulator may ensure that the AC bias transformer(s) of the corresponding JTL(s) can be coupled to the clock resonator via a lower than standard mutual inductance. Second, each bias level sensor configured as an output amplifier emulator may ensure that the DC bias transformer(s) of the corresponding JTL(s) can be coupled to the output amplifier's output bias current (I in FIG. 26B) instead of a separate DC bias line. BIASOUT ) to the output bias line of the output amplifier of the RQL IC 106. Each output amplifier emulator thus derives its DC bias from the output bias line of the output amplifier of the RQL IC 106. Third, the sensitivity of the JTL in each output amplifier emulator to the output bias current of the output amplifier can be set to be similar to the sensitivity of the SQUID in the output amplifier that the output amplifier emulator is configured to emulate. For example, the JJ in the JTL of the output amplifier emulator can be sized to have a critical current that approximates the critical current of the JJ in the DC SQUID of the output amplifier that the output amplifier emulator is configured to emulate. When the bias level sensors 202-212 of the series output ladder configuration 200 of FIG. 2A are configured as output amplifier emulators having the three characteristics described above, the pulse count provided at the output of the ladder configuration 200 configured with the output amplifier emulator as the bias level sensors 202-212 indicates how well the output amplifier output bias current is tuned to the SQUID in the output amplifier that the output amplifier emulator is configured to emulate.

[0089] As described above with respect to the bias level sensing configurations configured to calibrate the AC bias amplitude or DC bias value, the mutual inductance of each bias level sensor configured as an output amplifier emulator to the output bias line of the output amplifier is adjusted so that each output amplifier emulator has a desired X OA 2A, if each bias level sensor 202-212 is implemented as an output amplifier emulator, the output amplifier emulator 202 may have a smaller mutual inductance to the output bias line of the output amplifier than the output amplifier emulator 204, which may have a smaller mutual inductance to the output bias line of the output amplifier than the output amplifier emulator 206, and so on for each stage of the wrapper ladder configuration 200. Thus, changing the output bias of the output amplifier will cause more or fewer output amplifier emulators 202-212 to generate pulses, changing the pulse count of the serial output of the wrapper.

[0090] With respect to the example of the output amplifier emulator described above, the output amplifier output bias current can be adjusted, improved, or optimized by direct observation of the output amplifier output without the use of the output amplifier emulator. Such variation of the output amplifier output bias current upon direct observation of the output amplifier output may require varying the output amplifier output bias current over a range that includes disabling the observed output amplifier. After the optimal bias is determined by such a method, pulse counts from the serial output wrapper ladder sensor with bias level sensors 202-212 configured as the output amplifier emulator can be recorded and used to maintain an optimal output amplifier output bias current even while the output amplifier is continuously operating. This is possible because the output amplifier output bias current is kept within the operating range of the output amplifier being emulated. In such a case, the output amplifier emulator does not need to emulate the critical current characteristics of the JJ of the SQUID of the output amplifier being emulated, i.e., the output amplifier emulator does not need to be configured to meet the third characteristic described above.

[0091] Figures 27A and 27B show example feedback systems 2700, 2750 that may be used to sense and tune the AC amplitude (Figure 27A) and phase (Figure 27B) of the I-clock and Q-clock. In each of Figures 27A and 27B, two RQL bias level sensors 2702, 2704, 2708, 2710 may be implemented as shown in Figures 26A or 26B. The sensors 2702, 2704, 2708, 2710 may be implemented as all or part of the sensor 118 on the RQL IC 106 in the cooling space.

[0092] In the example shown in FIG. 27A, the first sensor 2702 is powered with a 90° clock (Q clock). The second sensor 2704 is powered with a 0° clock (I clock). The AC bias amplitudes provided to the I and Q clocks can be sensed simultaneously by the two sensors 2702, 2704. The outputs OUTPQ, OUTPI of the sensors 2702, 2704 have the form of a voltage pulse train with a time-varying voltage height. The pulses of the pulse train can be configured to be generated, for example, once every AC clock cycle. The individual output signals OUTPQ, OUTPI provided by the sensors 2702, 2704 are each of sufficiently large voltage amplitude so that they can be analyzed by an AC amplitude adjustment logic 2706, which can be provided, for example, as part of a feedback loop 122 to the bias signal generator(s) 110 outside the cooling space. The AC amplitude adjustment logic 2706 can be implemented, for example, in a conventional semiconductor circuit (e.g., a CMOS circuit). A third input to the AC amplitude adjustment logic 2706, labeled AMPREF, provides an AC or DC signal representing the desired ideal nominal level that should be provided from the two sensors 2702, 2704. An output QOUT at the top of the logic 2706 directs a change in the output of the clock source for the Q clock (the 90° clock source), an output IOUT at the bottom of the logic 2706 directs a change in the output of the clock source for the I clock (the 0° clock source), and an amplitude reference signal AMPREF describes or represents the level to which the clock sources should be regulated. The reference signal AMPREF may represent, for example, the height of the pulses generated by the sensors 2702 and 2704.

[0093] The AC amplitude adjustment logic 2706 may be configured to perform a voltage comparison of the provided bias sense signals OUTPQ, OUTPI and generate one or more control signals based on a comparison of the OUTPQ and OUTPI signals. For example, if the AC amplitudes of the 0° I-clock and 90° Q-clock sensed on the RQL IC 106 by the sensors 2702, 2704 are close to or match the optimal AC bias point 306, then the outputs OUTPQ, OUTPI of the sensors 2704, 2702 will be equal and the outputs QOUT, IOUT of the logic 2706 will not direct a change in the AC amplitude of either of the clocks 112, 114. However, if the AC amplitudes of the 0° I-clock and the 90° Q-clock sensed on the RQL IC 106 by sensors 2702, 2704 are different, or if either of them does not match the optimal AC bias setting for the corresponding clock, then the outputs OUTPQ, OUTPI of sensors 2704, 2702 will not be equal and one or both of the outputs QOUT, IOUT of logic circuit 2706 will indicate a change in the AC amplitude of either of the clocks 112, 114.

[0094] Following the AC amplitude calibration of the I and Q clocks performed by the configuration of FIG. 27A, the configuration of FIG. 27B can be used to sense and calibrate the relative phase of the I and Q clocks to ensure that the phase difference between the I and Q clocks provided to the operational RQL circuit 102 on the RQL IC 106 in the cooling space is 90°. The bias level sensor configuration of FIG. 27B is structurally identical to the configuration of FIG. 27A, except that the first sensor 2708 of FIG. 27B is provided with a 45° clock formed by connecting both the I and Q resonators, rather than a 90° clock formed by connecting only the Q resonator as in sensor 2702 of FIG. 27A, and the second sensor 2710 of FIG. 27B is provided with a −45° (315°) clock formed by connecting both the Q and I resonators, rather than a 0° clock formed by connecting only the I resonator. The clock signal generated by the 45° transformer or 135° transformer on the RQL IC 106 depends on both the phase difference and the amplitude of the I and Q clocks. Phase mismatch between the I and Q clocks at the level of the RQL IC 106 in the cooling space can cause AC amplitude variations in the 45° and 135° signals. As shown in FIG. 27B, by powering the sampler in the sensor 2708 with the 45° clock, the output voltage mismatch between the output OUTPIQ of the 45° sensor 2708 and the output OUTPQI of the -45° sensor 2710 shows a phase difference between the I and Q clocks that is different from 90°. The reason for this is that after the AC amplitudes of the I and Q clocks become equal, the only factor that can cause an output voltage difference of such a sensor is the phase error between the clocks.

[0095] Thus, the AC phase adjust logic 2712 may be configured to perform a voltage comparison of the provided bias sense signals OUTPIQ, OUTPQI and generate one or more control signals based on a comparison of the OUTPIQ and OUTPQI signals. For example, if the phase error between the 0° I-clock and the 90° Q-clock sensed on the RQL IC 106 by the sensors 2708, 2704 indicates true quadrature (exactly 90° phase difference), then the outputs OUTPIQ, OUTPQI of the sensors 2708, 2710 will be equal and the outputs QOUT, IOUT of the logic 2712 will not indicate a change in the AC phase of either of the clocks 112, 114. However, if the phase error between the 0° I-clock and the 90° Q-clock sensed on the RQL IC 106 by sensors 2708, 2702 is different, the outputs OUTPIQ, OUTPQI of the sensors 2708, 2710 will not be equal and one or both of the outputs QOUT, IOUT of the AC phase adjustment logic 2712 will indicate a change in the phase of either of the clocks 112, 114.

[0096] The power amplifier-based structures of Figures 26A and 26B have the advantage that they can generate relatively large output voltages at relatively high throughputs, which can be used to adjust AC amplitude and phase and tune the resonator clock, as shown in Figures 27A and 27B.

[0097] 28 illustrates an example optimization method 2800 that may be used to calibrate a bias signal, for example, to or near an ideal calibration, using one or more configurations of bias level sensors. AC The signal is input to a sampler wrapper having a sampler (2802). By way of example, the wrapper can be a serial output RQL scan register as shown in FIG. 2A or FIG. 25, a parallel output configuration as shown in FIG. 2B, a ring oscillator as shown in FIG. 2C, a DC SQUID-based configuration as shown in FIG. 26A or FIG. 26B, or a PML shift register configuration as shown in FIG. 24. ACThe sampler may be, by way of example, a JTL-based or RQL-gate based sampler as shown in FIG. 6, a shift register based sampler as shown in any of FIGs. 8, 9, 10, 11, 12, 13, 16, or 18, a PML flip-flop based sampler as shown in FIG. 24, or a pulse generator based sampler as shown in FIG. AC The sampler output may be observed (2804), for example, by a circuit that counts pulses in an output pulse train generated by the sampler wrapper, such as the pulses shown in FIGS. 4A-4D, in the case of a serial pulse output by a wrapper as shown in FIG. 2A, by a circuit that compares an input pulse stream to an output pulse stream, in the case of a PML shift register configuration as shown in FIG. 24, or by a voltage comparison circuit, in the case of a DC SQUID-based configuration as shown in FIG. 26A or FIG. 26B, which outputs voltage pulses having values ​​on the order of millivolts. The circuit that observes the bias level sensor output may be a conventional semiconductor circuit (e.g., a CMOS circuit) that operates in the warm space of the system 100, and need not be implemented on the RQL IC 106 or otherwise in the cooled space. Observation (2804) may, in some examples, be performed by a human user using a human-in-the-loop feedback technique, where the human user may provide feedback to the X AC The sampler output is observed (2804), optimization decisions are made (2806), and the AC clock amplitude is manually varied (2808).

[0098] As an example, X AC Two or more of the samplers (AC bias samplers) include at least one JTL or pulse generator with a weakened AC clock resonator bias tap to the AC clock resonator of the RQL IC compared to the AC clock resonator bias tap of the JTL in the operational RQL circuit 102. The weakened AC clock resonator bias tap means that a larger amplitude AC bias signal is required to drive the JTL or pulse generator within their respective AC operating margins, and therefore the X of the AC bias sampler.DC -X AC The margin shmoo plot is shifted upwards relative to the margin shmoo plot of the operational RQL circuit 102, for example as shown in FIG. AC Two or more of the samplers include a pulse generator having a Josephson junction having a greater critical current than the Josephson junction in the operational RQL circuit.

[0099] X AC Based on the observation of the sampler output (2804), it may be evaluated whether the AC bias amplitude parameter has been optimized (2806). For example, if a number of different AC bias amplitudes were provided to the sampler wrapper, data may be compiled that indicates which AC bias amplitude produced optimal or near optimal output results. For example, an X AC For the serial output wrapper of FIG. 2A with a bias level sensor, a moderate number of X AC When the sampler is operational, optimal results are produced. If not enough data has been collected to draw such a conclusion, the AC clock amplitude of the AC clock resonator under test may be changed to a different value (2808) and a new sample signal may be input (2802). Portions of this process 2802-2808 may be repeated iteratively as many times as necessary to provide confidence that the AC bias amplitude has been optimized (2810) for the AC clock resonator under test (e.g., I resonator or Q resonator). In some exemplary methods similar to method 2800, the AC bias amplitude is not optimized at 2810, but is improved. The improvement in AC bias amplitude may be indicated by a positive integer value X indicating results consistent with the AC clock amplitude provided at 2808 approaching the optimal bias point 306 of the operational RQL circuit 102. AC This can be determined by observing (2804) the sampler output.

[0100] After the AC bias signal is calibrated at 2098, the process 2800 may continue to calibrate the DC bias. DCThe sampler is input to a sampler wrapper having a sampler (2812). The wrapper can be the same wrapper or a different wrapper than the wrapper used to calibrate the AC bias amplitude in the AC bias calibration portion of method 2800. DC The sampler may similarly be of the types listed and described above. DC The sampler output may be observed (2814), for example, by a circuit that counts pulses in the output pulse train generated by the sampler wrapper, such as the pulses shown in FIGS. 4A-4D, in the case of a serial pulse output by a wrapper such as that shown in FIG. 2A, or by a circuit that compares the input pulse stream to the output pulse stream, in the case of a PML shift register configuration such as that shown in FIG. 24, or by a voltage comparison circuit, in the case of a DC SQUID-based configuration such as that shown in FIG. 26A or FIG. 26B, which outputs voltage pulses having values ​​on the order of millivolts. The circuit that observes the bias level sensor output may be a conventional semiconductor circuit (e.g., a CMOS circuit) that operates in the warm space of the system 100, and need not be implemented on the RQL IC 106 or otherwise in the cooled space. Observation 2814 may also be performed by a human user, using a human-in-the-loop feedback technique, where the human user may provide feedback to the X DC The sampler output is observed (2814), optimization decisions are made (2816), and the DC bias value is manually varied (2818).

[0101] X DC Based on the observation of the sampler output (2814), it may be evaluated whether the DC bias value parameters have been optimized (2816). For example, if a number of different DC bias values ​​are provided to the sampler wrapper, data may be compiled that indicates which DC bias values ​​produce optimal or near-optimal output results. DC For the serial output wrapper of FIG. 2A with a bias level sensor, for example, the mid-offset range X DCOptimal results are produced when only the sampler is operating. If insufficient data has been collected to draw such a conclusion, the DC bias value provided to the DC bias line under test may be changed to a different value (2818) and a new sample signal may be input (2812). Portions of this process 2812-2818 may be repeated iteratively as many times as necessary to provide confidence that the DC bias value has been optimized (2820) for the DC bias line under test. Thus, both the AC and DC bias signals are calibrated (2820). The calibration method 2800, or any portion thereof, may be performed while the operational RQL circuit 102 is continuously operating, in some examples, even while its bias parameters are being adjusted, improved, or optimized. In some example methods similar to method 2800, the DC bias value is improved even though it is not optimized at 2820. The improvement in the DC bias value may be indicated by an X-axis shift register (X ) indicating results consistent with the DC bias value provided at 2818 approaching the optimal bias point 306 of the operational RQL circuit 102. DC This can be determined by observing the sampler output (2814).

[0102] The PML-based optimization method 2900 of Figure 29 is described above in conjunction with the description of the PML shift register structure shown in part in Figure 24. Although the method 2900 shown and described relates to calibrating the AC bias amplitude, the method 2900 may be modified to provide for calibration of the DC bias value, i.e., by using flip-flops of various PML shift register elements with graduated respective DC bias operating margin offsets (e.g., by fabricating the flip-flop bias transformers to have different, e.g., graduated, DC bias line-coupled transformer lengths), stopping the logic clock (2906), changing the DC bias value rather than the AC amplitude (2908), advancing a single clock cycle (or half cycle) (2910), and restarting the logic clock (2914), and observing the output data bit pattern (2916), after which the X AC X, not optimization DC This is fixed by checking optimization (2918).

[0103] 30 shows an example optimization method 3000 that may be used to calibrate the phase difference between different AC clock bias signals, e.g., between the I clock and the Q clock. In some examples, the AC amplitudes of the I and Q clocks are first calibrated 3002, 3004 independently of each other, which may be done using either method 2900 or 2900, e.g., by using a bias level sensor that is I clock independent or Q clock independent, as shown in FIG. 12, 13, 16, 18, or 24. In method 3000, a sample signal, e.g., an SFQ pulse or a reciprocal pulse pair, is calibrated 3002, 3004, independently of each other ... phase Sampler or multiple X phase The inputs are input to a sampler wrapper having a sampler (3002). The wrapper can be a serial output RQL scan register as shown in FIG. 2A or FIG. 25, a parallel output configuration as shown in FIG. 2B, a ring oscillator as shown in FIG. 2C, or an output amplifier based configuration as shown in FIG. 26A or FIG. 26B (e.g., configured as shown in FIG. 27B). phase The sampler or samplers can be, for example, JTL-based samplers as shown in FIG. 21, with four mixed-resonator clock inputs that are 90° out of phase with each other. phase The most weakly biased JTL or gate in the sampler is X phase The minimum AC operating point at which the sampler operates (X ACmin ) is defined as X. phase The sampler output may be observed, for example, by circuitry that counts the pulses in the output pulse train generated by the sampler wrapper (3004). Such circuitry may be conventional semiconductor circuitry (e.g., CMOS circuitry) that operates within the warm space of the system 100 and need not be implemented on the RQL IC 106 or otherwise within the cooled space.

[0104] X phaseBased on the observation of the sampler output (3004), it may be evaluated whether the clock phase difference parameter has been optimized (3006). For example, multiple clock phase difference values ​​over multiple AC bias amplitudes in a two-dimensional search may be searched for in one or more X phase Data may be compiled that indicates which clock phase difference values, when provided to the sampler, would produce optimal or near optimal output results. For example, phase When the sampler 2000 is used, as shown at point 2402 in FIG. phase The lower limit of the operating margin of the Sampler 2000 is X ACmin (X phase The lowest AC bias amplitude at which the Sampler 2000 continues to operate is ACmin Optimal results are produced when the phase error is lowest over a range that depends on the phase error of the point. As another example, X at a particular I or a particular Q as shown in FIG. 12, FIG. 13, FIG. 16, or FIG. 18 is AC When a sampler is used, the X of a particular I sampler is ACmin The phase error dependence plot of X for a particular Q sampler ACmin Optimal results are produced when the phase error is such that it intersects the phase error dependence plot of . As another example, an X 2000 with mixed resonator clocks separated by 90°, such as a 45° clock sampler and a 135° sampler, AC If a sampler is used, the X of the first mixing resonator sampler is ACmin The phase error dependence plot of X for a second mixed resonator sampler is fed with an AC bias signal that is 90° out of phase with the AC bias signal fed to the first mixed resonator sampler. ACmin Optimal results are produced when the phase error is such that it intersects the phase error dependence plot of

[0105] X phase If insufficient data was collected to draw a conclusion that the value was optimized, X AC and X phaseMore data can be collected by performing a two-dimensional search of the values ​​of X. phase For the value, X AC Vary the X of the phase sampler(s) ACmin X AC If the sweep is not complete for the current X phase value (3008), a different X AC To provide an input value to the phase sampler(s), the AC amplitude of the bias provided (whether the I clock resonator, the Q clock resonator, or both) is changed (3010) and a new input sample signal is provided to the sampler wrapper (3002). The AC sweep portion of the process 3002-3010 is phase X for the phase sampler(s) relative to the value ACmin This can be repeated until the X for the phase sampler is determined for the current phase difference between the I and Q clocks. ACmin Once X is found, the phase difference between the I and Q clocks can be changed to a different value (3012) and a new sample signal can be input (3002). phase The process portion of the sweep 3002-3012 is the X of the phase sampler(s). ACmin The number of times required to find X needed to provide confidence that the clock phase difference has been optimized for the AC clock resonator under test (3014) is phase It can be repeated iteratively for as many values ​​of X AC Sweep and X phase The sweep does not have to be a linear sweep, for example, a binary search process can be used to search through each X phase X in value ACmin And, X phase X as a function of ACmin X where is the smallest phase This allows the user to more quickly approach both the X and ACmin 20, such as point 2302 in FIG. 23 using phase sampler 2000 in FIG. 20), or the X ACThe phase offset where the plots intersect (such as points 1902 or 2202 in Figures 19 and 22, respectively) indicates the optimum phase offset between the I and Q clocks in the warm space at which the clocks should be driven to obtain true quadrature (90° separation) in the operational RQL circuit 102 on the RQL IC 106 in the cold space. DC Level: X ACmin Therefore, X AC Similarly, X DC By searching for the value of X AC Once the minimum of is found, X DC The optimal value of will also be found.

[0106] FIG. 31 illustrates an exemplary optimization method 3100 that can be used to calibrate I and Q clock AC amplitude parameters and I and Q clock phase parameters to optimize the clock bias signal delivered to the RQL IC 106, for example, using the output amplifier based sensor 2600 or 2650 shown in FIG. 26A and FIG. 26B and the two sensor feedback system shown in FIG. 27A and FIG. 27B. A first and a second sensor are driven with I and Q clock signals, respectively (3102). Each of the sensors can be provided with a sample signal, e.g., a SFQ pulse, at a corresponding input, and each can provide an output voltage signal at a corresponding output. The outputs of the first and second sensors can be compared (3104). The comparison 3104 can be performed, for example, outside the cooled space in which the RQL IC 106 resides, for example, by a conventional semiconductor circuit (e.g., a CMOS circuit) configured to receive the output voltage signals of the first and second sensors and perform the comparison 3104. Based on the comparison of the outputs of the first and second sensors (3104), and in some examples further based on the reference signal, it may be evaluated whether the AC clock amplitude parameters of the I and Q clocks have been optimized (3106). For example, if the comparison (3104) indicates that there is no difference between the sensor outputs of the first and second sensors (e.g., OUTPQ and OUTPI in FIG. 27A) and both outputs are within an acceptable range of values ​​indicated by the reference signal, the AC amplitude parameters may be determined to be calibrated (3110) and the method 3100 may proceed to calibrating the phase error between the I and Q clocks. However, if the comparison (3104) indicates a difference between the sensor outputs, one or both of the AC clock amplitudes for the I and Q clocks may be changed (3108), e.g., based on the output of the comparison circuit in the room temperature space, and the outputs of the first and second sensors may be re-compared (3104). Portions 3102-3108 of this process may be repeated iteratively as many times as necessary to provide confidence that the AC clock amplitudes of the I and Q clock signals have been optimized (3110).

[0107] Once the AC clock amplitudes of the I and Q clock signals have been optimized (3110), the first and second sensors may be biased with a 90° phase separated clock signal formed from a mix of the I and Q resonator signals. For example, the first sensor may be driven with a 45° AC clock signal and the second sensor may be driven with a -45° (315°) AC clock signal. The mixed resonator AC clock signal may be formed according to Table 1 above. The first and second sensors driven with the 90° phase separated mixed resonator clock signal (3112) may be the same sensors as the sensors driven with the I and Q clock signals (in which case mechanisms are provided for switchably coupling them to different resonators or combinations of resonators), or one or both of them may be different from the sensors driven with the I and Q clock signals (3102). As an example, a first sensor (e.g., sensor 2710 of FIG. 27B) may be driven 3112 with a nominal -45° clock signal (e.g., by transformer coupling the first sensor to both the Q and I clock resonators) and a second sensor (e.g., sensor 2708 of FIG. 27B) may be driven 3112 with a nominal 45° clock signal (e.g., by transformer coupling the second sensor to both the I and Q clock resonators). In another example, the 90° phase separated clock signals biasing the first and second sensors may be pure I and Q clock signals, respectively (e.g., 0° and 90°, 90° and 180°, or 180° and 270°). A method for detecting phase by comparing the outputs of a pair of bias parameter sensors in which the clock signal is formed from a combination of I and Q clock signals (e.g., ±45°, or 45° and 135°, 135° and 225°, etc.) has the advantage of being more sensitive to phase matching than a configuration consisting of a pair of bias parameter sensors operating with pure I and Q clock signals (e.g., at 0° and 90°, 90° and 180°, or 180° and 270°).

[0108] The outputs of the first and second sensors may be compared (3114). The comparison (3114) may be performed, for example, outside the cooling space in which the RQL IC 106 resides, for example, by a conventional semiconductor circuit (e.g., a CMOS circuit) configured to receive the output voltage signals of the first and second sensors and perform the comparison 3114. The comparison circuit may be the same or different circuit as the circuit used to perform the comparison of the AC amplitude indication outputs (3104) in the first portion of the method 3100. Based on the comparison of the outputs of the first and second sensors (3114), and in some examples further based on the reference signal, it may be evaluated (3116) whether the phase error of the AC clock is optimized to provide true quadrature between the I clock phase and the Q clock phase, i.e., whether there is a 90° separation of the Q clock phase from the I clock phase as observed on the RQL integrated circuit 106. For example, if the comparison (3114) indicates that there is no difference between the sensor outputs of the first and second sensors (e.g., OUTPIQ and OUTPI in FIG. 27B), it may be determined that the AC phase error parameters are calibrated (3120). However, if the comparison (3114) indicates a difference between the sensor outputs of the first and second sensors, then one or both of the AC clock phases for the I and Q clocks may be changed (3118), e.g., based on the output of the comparison circuit in room temperature space, and the outputs of the first and second sensors may be recompared (3114). Portions 3112-3118 of this process may be repeated iteratively as many times as necessary to provide confidence that the AC clock phase error of the I and Q clock signals has been optimized (3120).

[0109] In the exemplary circuit structures and methods described above, the operating region of the test circuits may be established by electronic testing where bias levels are varied to determine the individual operating ranges of the test circuits. The operating range of the test circuits may be made to differ from that of the operating RQL circuit due to manufacturing variations such as differences in mutual inductance values ​​of the AC clock resonators or DC bias line coupling transformers, and due to the addition of self-inductance between the taps and the individual JTLs or gates driven by the taps. In each of the different examples described, the electronic testing involves applying stimuli in the form of logic signals and observing the presence or absence of expected logic outputs indicative of operation of the test circuits. The boundaries of the operating region may be determined by verifying that each test circuit operates correctly or fails at various applied bias levels.

[0110] In some examples, the bias level sensor and associated methods of the present application can advantageously determine how close the operating point of an operational RQL circuit is to an optimal operating point while the operational RQL circuit continues to operate, i.e., without causing bias-related failures in the operational RQL circuit. By placing a sampler in the RQL IC 106 having an operating range configured to vary systematically relative to the operating ranges of the other samplers, it is possible to numerically ascertain the currently applied bias level of the RQL IC 106 as observed on the RQL IC 106. If the sampler is placed in a wrapper having a ladder configuration as shown in FIG. 2A or FIG. 25, a numerical determination of the current bias level can be made, for example, by counting the number of pulses provided at the output of the sampler wrapper each time a sampler pulse is provided to the input of the sampler wrapper. Thus, the bias level sensor and associated methods of the present application can evaluate the bias condition on the RQL IC 106 without interfering with the operation of the operational RQL circuit 102 on the IC 106. The bias level sensor and associated method of the present application are particularly useful in calibrating the bias operating points of an RQL system having multiple RQL ICs. The bias level sensor and associated method of the present application can function as a process control monitor, i.e., an on-chip instrument for evaluating the performance of a circuit as affected by variations in circuit (wafer) processing. The bias level sensor and associated method of the present application can be implemented in a human-in-the-loop feedback control or in a fully automated feedback control using a combination of RQL circuitry inside the cooling space and non-RQL circuitry (e.g., CMOS or other semiconductor circuitry) outside the cooling space to make continuous or periodic measurements of bias signal parameters and direct adjustments to the bias signal parameters.

[0111] The above description is an example of the present invention. Of course, it is not possible to describe every combination of elements or methods conceivable for describing the invention, but one skilled in the art will recognize that many further combinations and permutations of the invention are possible. Therefore, the invention is intended to encompass all such changes, modifications, and variations that are within the scope of this application, including the appended claims. In addition, when the disclosure or claims recite "a," "an," "a first," or "another" element, or the equivalent thereof, it should be construed as including one or more such elements, and does not require or exclude two or more such elements. As used herein, the term "includes" means including but not limited to, and the term "including" means including but not limited to. The term "based on" means based at least in part on.

Claims

1. A reciprocal quantum logic (RQL) integrated circuit (IC), a phase-mode shift register, the phase-mode shift register comprising: a first plurality of Josephson transmission lines (hereinafter referred to as JTLs) arranged in series as a data path; a second plurality of JTLs arranged in series as a logical clock path trunk; a plurality of phase-mode D flip-flops, each phase-mode D flip-flop having a data input coupled to the data path and configured to receive an input from the data path, a data output coupled to the data path and configured to provide an output to the data path, and a logic clock input coupled to a respective logic clock path branch coupled to the logic clock path trunk; the first plurality of JTLs and the plurality of phase-mode D flip-flops in the data path are transformer-coupled to one or more AC clock resonators of the RQL IC to receive AC clock bias signals of first two AC clock phases that are approximately 180° apart in phase from each other; the second plurality of JTLs in the logical clock path trunks are transformer coupled to one or more AC clock resonators of the RQL IC to receive AC clock bias signals of second two AC clock phases that are approximately 180° apart in phase from each other; The first two AC clock phases are different from the second two AC clock phases.

2. a first of the first two AC clock phases is approximately 90 degrees apart from a first of the second two AC clock phases; 2. The system of claim 1, wherein a second of the first two AC clock phases is approximately 90 degrees apart from a second of the second two AC clock phases.

3. a first of the first two AC clock phases is approximately 0°; a first of the second two AC clock phases is approximately 90 degrees; a second of the first two AC clock phases is approximately 180 degrees; 3. The system of claim 2, wherein a second of the second two AC clock phases is approximately 270 degrees.

4. a first of the second two AC clock phases is approximately 0°; a first of the first two AC clock phases is approximately 90 degrees; a second of the second two AC clock phases is approximately 180 degrees; 3. The system of claim 2, wherein a second of the first two AC clock phases is approximately 270 degrees.

5. a first of the first two AC clock phases is approximately 45 degrees; a first of the second two AC clock phases is approximately 135°; a second of the first two AC clock phases is approximately 225°; 3. The system of claim 2, wherein a second of the second two AC clock phases is approximately 315 degrees.

6. a first of the second two AC clock phases is approximately 45 degrees; a first of the first two AC clock phases is approximately 135°; a second of the second two AC clock phases is approximately 225°; 3. The system of claim 2, wherein a second of the first two AC clock phases is approximately 315 degrees.

7. 2. The system of claim 1, wherein each of the plurality of phase-mode D flip-flops is transformer coupled to the one or more AC clock resonators at a different point along the one or more AC clock resonators.

8. 2. The system of claim 1, wherein each of the plurality of phase-mode D flip-flops is transformer-coupled to an AC bias signal source or a DC bias signal source weaker or stronger than a JTL of an operational RQL circuit on the RQL IC that is not part of the phase-mode shift register.

9. 9. The system of claim 8, wherein the individual transformer couplings of each of the plurality of phase-mode D flip-flops are graduated such that the strengths of the individual transformer couplings of each phase-mode D flip-flop vary relative to one another.

10. 9. The system of claim 8, wherein a lower limit of an AC operating range of at least one of said plurality of phase-mode D flip-flops is at approximately the center of gravity of an operating range of said operating RQL circuit.

11. 2. The system of claim 1, wherein each of the second plurality of JTLs in the logical clock path trunk is biased by an AC bias signal source weaker than a JTL of an operational RQL circuit on the RQL IC that is not part of the phase-mode shift register.

12. 12. The system of claim 11, wherein a lower limit of an AC operating range of each of the second plurality of JTLs in the logical clock path trunk is at approximately a center of gravity of an operating range of the operational RQL circuit.

13. 1. A method comprising: setting at least one bias signal parameter of a bias signal provided to a reciprocal quantum logic (RQL) integrated circuit (IC) to a nominal value; initiating a logic clock signal provided to a logic clock path of a phase-mode RQL shift register to shift in an input data bit pattern into a data path of said phase-mode RQL shift register; stopping the logic clock; Varying the value of the at least one bias signal parameter provided to the data path of the phase-mode RQL shift register; inputting an assertion SFQ pulse pair or a single SFQ pulse into the logical clock path; returning the value of the at least one bias signal parameter to the nominal value; resuming the logic clock signal provided to the logic clock path of the phase-mode RQL shift register to shift out an output data bit pattern into the data path of the phase-mode RQL shift register; observing the output data bit pattern of the phase-mode RQL shift register; and determining, based on observing the output data bit pattern, that by varying a value of the at least one bias signal parameter, a value of the at least one bias signal parameter approaches an optimal value for the at least one bias signal parameter.

14. The method of claim 13 , wherein the at least one bias signal parameter comprises an AC amplitude of an AC bias signal provided to the data path of the phase-mode RQL shift register.

15. The method of claim 13 , wherein the at least one bias signal parameter comprises a DC bias value of a DC bias signal provided to the data path of the phase-mode RQL shift register.

16. 14. The method of claim 13, wherein the at least one bias signal parameter comprises a phase difference between an I clock signal and a Q clock signal provided to the RQL IC.

17. observing the output data bit pattern includes identifying, in the output data bit pattern, one or more differences between the output data bit pattern and the input data bit pattern; 14. The method of claim 13, wherein the determining step is based on ascertaining which element of the phase-mode RQL shift register is biased outside its operating region or which elements of the phase-mode RQL shift register are biased outside their respective operating regions while inputting an assertion SFQ pulse pair or a single SFQ pulse into the logical clock path when the value of the at least one bias signal parameter is changed.

18. A reciprocal quantum logic (hereinafter referred to as RQL) superconducting bias level detection circuit for detecting a bias level supplied to an RQL circuit in an operating RQL circuit, the bias level detection circuit comprising a phase mode logic (hereinafter referred to as PML) shift register including a plurality of PML shift register elements coupled in series with each other, each PML shift register element having: a PML D flip-flop having a data input, a data output, and a logic clock input, the data input being configured to be coupled to either a data output of a previous element in the PML shift register or an input data bit stream source; a data output path section having an input coupled to the data output of the PML D flip-flop and an output configured to be coupled to either a data input of a next element in the PML shift register or to a circuit configured to receive an output data bit stream from the PML shift register, the data output path section comprising first, second and third Josephson transmission line (hereinafter JTL) based buffers coupled in series with each other between the input and the output of the data output path section; a logic clock path trunk portion having an input configured to be coupled to either a logic clock path output of a next element in the PML shift register or a logic clock source, and an output configured to be coupled to either a logic clock path input of a previous element in the PML shift register and / or a branch of a logic clock path of the PML shift register element, the logic clock path trunk portion comprising fourth, fifth, sixth, seventh and eighth JTL based buffers coupled in series with each other between the input and the output of the logic clock path trunk portion; a branch of the logic clock path having an input coupled to the output of the logic clock path trunk portion of the PML shift register element and having an output coupled to the logic clock input of the PML D flip-flop, the branch of the logic clock path comprising ninth and tenth JTL based buffers coupled in series with each other between the input and the output of the branch of the logic clock path.

19. the PML D flip-flop and the first and tenth JTL-based buffers are driven by an AC bias signal having a first phase value; the fifth and sixth JTL-based buffers are driven by a second AC bias signal having a second phase value that is approximately 90 degrees greater than the first phase value; the second and third JTL-based buffers are driven by a third AC bias signal having a third phase value that is approximately 90 degrees greater than the second phase value; 20. The bias level sensing circuit of claim 18, wherein the fourth, seventh, eighth, and ninth JTL-based buffers are driven by a fourth AC bias signal having a fourth phase value that is approximately 90 degrees greater than the third phase value.

20. 20. The bias level sensing circuit of claim 19, wherein the second, fifth, and seventh JTL-based buffers include at least one additional Josephson junction at their respective inputs compared to the first, third, fourth, sixth, eighth, ninth, and tenth JTL-based buffers, respectively.

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