Method for forming a dielectric material-based layer on an etched III-V material-based layer - Patents.com

Abstract

The present invention relates to a method for forming a layer based on a dielectric material on an etched layer based on a III-V material, the method comprising at least the following steps: - providing at least one layer based on a III-V material, preferably III-N, called III-V layer (100), having a top surface (101); - etching at least a portion of the III-V layer (100) from the top surface (101) so as to expose a surface of the III-V layer, called the etching surface (103), - exposing at least the etching surface (103) to a plasma treatment of O2 or N2, which step comprises: treatment Temperature T < 100 °C treatment and depositing, at least on the etching surface, a layer based on a dielectric material, called the dielectric layer (200); The present invention relates to a method comprising the steps of:

Description

[Technical field]

[0001] The present invention relates to the formation of a layer based on a dielectric material on an etched layer based on a III-V material, such as etched GaN. The invention is therefore applicable to the manufacture of devices comprising an interface between a III-N material and a dielectric material. For example, the invention finds particular advantageous application in the field of power electronics, such as transistors integrating one or more layers of III-N materials. [Background technology]

[0002] Due to increasing needs and avoidance of energy waste, manufacturers of microelectronic devices are under pressure to improve the yield and performance of their electrical energy conversion systems. Currently, conversion circuits are fabricated on a silicon basis and further research is being carried out to develop architectures with the aim of improving yield and conductivity. However, these known devices are reaching the theoretical limits of silicon and novel solutions are being considered. These solutions are based on the use of III-V materials such as GaN, for example for High Electron Mobility Transistors (HEMTs).

[0003] To manufacture these types of devices, it is necessary to carry out many steps, such as etching the III-V material and subsequently depositing a dielectric layer on the etched zone. However, the etching step can severely degrade the chemical and electrical properties of the etched material. As a result, the interfaces provided between the III-V material and the dielectric often have degraded electrical properties. For example, plasma etching induces structural defects that alter the quality of the interfaces between the etched layer and the dielectric layer. The electrical properties of these interfaces and therefore of the electronic components are degraded.

[0004] It is known in the prior art to resort to etching methods that are essentially non-damaging with respect to the quality of the etched layers. In particular cyclic etching techniques, such as the technique known as "atomic layer etching" or ALE, make it possible to obtain etched layers with minimal damage and good electrical properties. However, current ALE techniques are very time-consuming and have a significant impact on productivity. In addition, ALE techniques are often difficult to implement, since they often require being within a narrow energy range that allows both selective and complete removal of the layer sought to be etched. Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, there exists a need to provide a solution for improving the productivity of the formation of dielectric layers on etched III-V material layers without affecting the quality of the interfaces produced. [Means for solving the problem]

[0006] To this end, according to one embodiment, a method is provided for forming a layer based on a dielectric material on an etched layer based on a III-V material, the method comprising at least the following steps: - providing at least one layer based on a III-V material, preferably III-N, called III-V layer, having a top surface; - etching at least a portion of the III-V layer from the top surface so as to expose a surface of the III-V layer, referred to as the etching surface; - At least the etched surface is O 2 Plasma treatment of N 2 Plasma treatment of O 2 and N 2 and exposing the mixture to a plasma treatment, the plasma treatment comprising exposing the mixture to a plasma treatment of T treatment Temperature T < 100 °C treatmentand depositing, at least on the etching surface, a layer based on a dielectric material, called the dielectric layer; Includes.

[0007] The plasma treatment carried out in the method according to the invention makes it possible to significantly improve the quality of the III-V material layers, typically etched GaN. In particular, low temperature operation makes it possible to obtain highly stable etched GaN layers and therefore facilitates and accelerates the handling of the samples, which leads to an increase in productivity. The samples can be easily transported from one reactor to another, for example from the reactor where the plasma treatment is carried out, to the reactor where the Al 2 O 3 The layer must actually be moved into the reactor where the deposition of the dielectric layer takes place. It is noted within the scope of the developments of the invention that at higher temperatures the III-N material layer becomes less stable, which creates problems in terms of the robustness of the method. Furthermore, within the scope of the developments of the invention, it has been unexpectedly observed that this reduction in temperature leads to a better interface quality between the etched III-N material and the dielectric material than would have been predictable. In contrast, this situation would have prompted the skilled person to apply a higher temperature to recrystallize the III-V material that is located on the surface and that is altered by etching.

[0008] The improved quality of the etched GaN layer itself leads to a greatly improved quality of the etched GaN / dielectric interface, especially in terms of its electrical properties.

[0009] The method according to the invention therefore makes it possible to improve considerably the productivity with respect to ALE type solutions while providing a very satisfactory interface quality, however the method according to the invention can be used together with ALE type etches.

[0010] It must be noted that the treatments following the step of depositing the non-etched epitaxially grown GaN are not adapted to the treatment of the etched GaN layer, or at least are much less effective. In fact, the surface of the non-etched epitaxially grown GaN layer is generally relatively stable, since the layer has spent a considerable amount of time in air, often from hours to months. The stoichiometry of the epitaxially grown GaN layer is stabilized, which minimizes the reactivity of the surface of the layer, in contrast to the surface of the etched GaN layer. Therefore, the strategy of applying a plasma treatment proposed in this application to chemically alter the surface of the GaN and thus improve the quality of the interface with the dielectric will have a minimal effect on the epitaxially grown GaN surface. On the non-etched epitaxially grown surface, the plasma treatment constitutes rather a cleaning strategy and does not allow the structural reconstruction that the method according to the invention used on the etched GaN layer allows.

[0011] Further provided is a method for making a microelectronic device comprising forming a dielectric material based layer on the etched III-V material based layer by performing the formation method described above, the microelectronic device being taken from among a transistor and an LED.

[0012] Additionally, there is provided a method for making a microelectronic device according to the above-mentioned manufacturing method, the method comprising: - The microelectronic device is a transistor, an etch of the III-V layer is performed to create a trench in the etched III-V material; a deposition of a layer based on a dielectric material is carried out on at least a portion of the etched surface of the trench so as to form a gate dielectric, after the formation of the dielectric layer the following steps are carried out: - filling the trench to define at least one gate of a transistor; Includes.

[0013] By microelectronic device is meant any type of device created by microelectronic means. These devices include in particular devices of purely electrical purpose as well as micromechanical or electromechanical devices (MEMS, NEMS, etc.), as well as optical or optoelectronic devices (LEDs, MOEMS, etc.). It may be a device intended to ensure the performance of an electrical, optical, mechanical function, etc. It may also be an intermediate product that is only intended to create another microelectronic device.

[0014] Also provided is a method for making a transistor, the method comprising the steps of: - forming a layer based on dielectric material on the etched layer based on III-V material by implementing the formation method as described above, where an etch of the III-V layer is performed to create a trench in the etched III-V material, and a deposition of a layer based on dielectric material is performed on at least a portion of the etched surface of the trench to form a gate dielectric. - filling the trench to define at least one gate of a transistor; Includes.

[0015] Also, the following steps: - providing at least one layer based on a III-V material, preferably III-N, called III-V layer, having a top surface; - etching at least one trench in the III-V layer from the top side through the mask so as to expose a surface of the III-V layer, referred to as the etching surface; - At least the etched surface is O 2 Plasma treatment or N 2 a step of exposing the substrate to a plasma treatment of T treatment Temperature T < 100 °C treatmentand - depositing, on at least a portion of the etched surface of the trench, a layer based on a dielectric material, called the dielectric layer, so as to form a gate dielectric; - filling the trench to define at least one gate of a transistor; A method is provided for making a transistor including:

[0016] This type of transistor has an improved interface between the III-V layer and the dielectric layer, and therefore the method allows the transistor to reach high performance while improving manufacturability.

[0017] The aims, objects, features and advantages of the present invention will best appear from the following detailed description of the embodiments, as illustrated by the accompanying drawings, in which: [Brief description of the drawings]

[0018] [Figure 1A] 1A-1D illustrate steps of a method according to one of the embodiments of the present invention, the preparation of a layer based on III-V materials, called III-V layer. [Figure 1B] FIG. 2 illustrates a step of a method according to one of the embodiments of the present invention, depositing an optional mask layer on top of the III-V layer. [Figure 1C] 4A-4D illustrate a method step according to one of the embodiments of the present invention, the formation of an opening in a mask layer to form an etching mask on a III-V layer. [Figure 1D] FIG. 2 illustrates a step of the method according to one of the embodiments of the invention, etching a III-V layer, making it possible to renew a surface, called the etching surface, of the III-V layer. [Figure 1E]FIG. 2 illustrates a method step according to one of the embodiments of the present invention, the step of exposing an etching surface to a plasma treatment, characterized by a set of arrows directed towards the etching surface. [Figure 1F] 3A-3C are diagrams illustrating steps of a method according to one of the embodiments of the present invention, depicting the deposition of a dielectric layer on an etching surface. [Figure 1G] FIG. 4 illustrates a step of a method according to one of the embodiments of the present invention, the optional removal of a mask. [Figure 2A] FIG. 1 illustrates the capacitance-voltage characteristic (also CV characteristic or CV profiling) of a MOS (metal oxide semiconductor) capacitor fabricated according to known prior art methods. [Figure 2B] FIG. 4 illustrates the CV characteristics of a MOS capacitor manufactured according to an embodiment of the method according to the present invention. [Diagram 3] 3 summarizes the different steps of an example of a forming method according to the invention; [Figure 4] 4 is a graph illustrating CV characteristics of a MOS capacitor made in accordance with an embodiment of the present invention, with processing temperatures of one at 40° C. and another at 60° C.; [Figure 5A] 1 is a graph illustrating flat band voltage values ​​of MOS capacitors made in accordance with an embodiment of the present invention, at processing temperatures of 40° C. for one and 60° C. for another. [Figure 5B] 1 is a graph showing values ​​of hysteresis of MOS capacitance at processing temperatures of 40° C. for one and 60° C. for another, made in accordance with an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The figures are given as examples and do not limit the invention. They constitute schematic representations of principles intended to facilitate understanding of the invention and are not necessarily drawn to scale in real applications. In particular, the thicknesses of the different layers do not represent reality.

[0020] Before commencing a detailed discussion of embodiments of the present invention, reference is made below to optional features, which may be used optionally, in conjunction with or instead.

[0021] According to one embodiment, the etching step and the plasma treatment step are carried out in one and the same reactor.

[0022] According to one example, T treatment >40°C.

[0023] According to one example, T treatment <80°C.

[0024] According to one example, the plasma treatment step is treatment < 5 minutes, i.e., t treatment <300 sec, preferably t treatment <2 minutes, i.e., t treatment Duration t < 120 seconds treatment has.

[0025] According to one embodiment, the method comprises a wet cleaning step prior to the step of depositing the dielectric layer.

[0026] According to one embodiment, the step of depositing the dielectric layer is carried out under vacuum.

[0027] According to one example, the etching step includes a chlorine plasma etch.

[0028] According to one example, the etching step includes at least one ALE type etching cycle.

[0029] According to one example, the etching is performed at 100 nm (10 -9 meter), preferably greater than 500 nm, preferably greater than 1 μm (10 -6 The etching is performed to etch a thickness of III-V material greater than 1 meter, preferably greater than 3 μm.

[0030] According to one example, the plasma treatment step is performed at a zero bias voltage V bias It is executed below.

[0031] According to one example, the plasma treatment step is performed with a mass flow rate D between 50 sccm and 1000 sccm, preferably between 100 sccm and 500 sccm. flow O 2 Flow of N 2 Flow of, or, O 2 and N 2 The method is carried out by injecting a stream of a mixture of

[0032] According to one example, the plasma treatment step is carried out with a power source P of between 100 W and 4000 W, preferably between 300 W and 1000 W. source Generated by O 2 Flow of N 2 Flow of, or, O 2 and N 2 The method is carried out by injecting a stream of a mixture of

[0033] According to one example, the III-V material is one of GaN and AlGaN.

[0034] According to one example, the dielectric material is AlN, Al 2 O 3 , and HfO 2 It is one of the following.

[0035] In the scope of the present invention, it is provided that "on", "surmount", "cover", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, depositing, transferring, bonding, assembling or attaching a first layer onto a second layer does not necessarily mean that the two layers are in direct contact with each other, but rather means that the first layer at least partially covers the second layer, either by direct contact or by being separated by at least one other layer or at least one other element.

[0036] Furthermore, a layer may consist of several sublayers of one and the same material or of different materials.

[0037] By substrate, layer, or device "based" on material M, we mean a substrate, layer, or device that includes only this material M, or that material M and optionally other materials, e.g., alloying elements, impurities, or doping elements. Thus, a material based on III-N materials can include III-N materials with the addition of dopants. Similarly, a GaN-based layer typically includes GaN and AlGaN or InGaN alloys.

[0038] The term "III-V material" refers to semiconductors composed of one or more elements from columns III and V of Mendeleev's periodic table. Among the elements in column III are boron, gallium, aluminum, or indium. Column V includes, for example, nitrogen, arsenic, antimony, and phosphorus.

[0039] By the terms "selective etch against" or "etch with selectivity against" is meant an etch configured to remove material A or layer A against material B or layer B, and having an etch rate of material A that is faster than the etch rate of material B. Selectivity is the ratio between the etch rate of material A and the etch rate of material B. The selectivity between A and B is referred to as SA:B.

[0040] A preferably orthonormal system with x, y and z axes is shown in Figure 1 A. This system can be extended and applied to other figures.

[0041] In this patent application, reference is made to a preferred thickness for a layer and to a preferred height for a structure or device. The thickness is taken along a direction perpendicular to the principal extension plane of the layer, and the height is taken perpendicular to the principal plane XY. Thus, a layer typically has a thickness along z when it extends primarily along the plane XY, and protruding elements, such as isolation trenches, have a height along z. Relative terms such as "on", "under" and "underlying" preferably refer to positions taken along the z direction.

[0042] The steps of the methods as claimed may be understood broadly and may optionally be performed in several sub-steps.

[0043] An example of a fabrication method will now be described with reference to Figures 1A to 1G and Figure 3. This method makes it possible to obtain the structure shown in Figure 1G, comprising an interface 1000 between an etched III-V material layer 100 and a dielectric layer 200.

[0044] As illustrated in FIG. 1A, the first step consists of providing a layer 100, preferably based on at least one III-N material and at least one III-V material. Typically, this material is GaN-based. This layer is called III-V layer 100. The III-V layer 100 has an upper surface 101 and a lower surface 102, both extending mainly in a plane XY of an orthogonal system XYZ. The III-V layer 100 extends along the z direction with a thickness e 100 has.

[0045] The III-V layers 100 may typically be formed from a homogenous layer of a single material. Alternatively, the III-V layers 100 may be formed from a stack of III-N material layers, at least consisting of these layers having different compositions. For example, the III-V layers 100 may be formed from one or more GaN layers and one or more P-, AlGaN-, AlN-, and / or InGaN-doped GaN layers. Typically, the III-V layers 100 may be formed from an assembly of one or more GaN layers and an AlGaN layer on top of this assembly. This is the case, for example, in certain HEMT type transistors.

[0046] The III-V layer 100 may rest on a substrate, typically a support or growth substrate. Such a substrate is not shown in Figures 1A-1G. One or more intermediate layers may be disposed between the substrate and the lower surface 102 of the III-V layer 100. This may in particular be a nucleation layer.

[0047] The second step is to remove at least a portion of the III-V layer 100 from its upper surface 101 to a thickness e etching This step is represented by block 31 in FIG. 3. The etching removes the III-V layer 100 to a depth of 100 nm (10 -9 meter), preferably deeper than 500 nm, preferably deeper than 1 μm (10 -6 meter), preferably deeper than 3 μm in thickness e etching1C. In order to etch only certain zones of the III-V layer 100, it is possible to provide for the formation of a mask 310 on top of the III-V layer 100, as illustrated in FIG. 1C. However, the presence of this mask 310 is not essential to carry out the etching method described below. According to an example, the mask 310 is arranged directly on the top surface 101 of the III-V layer 100. The mask 310 is formed, for example, by lithography of a mask layer 300 deposited or transferred onto the III-V layer 100, as illustrated in FIG. 1B. Preferably, the mask 310 is a hard mask. Preferably, the mask 310 is based on a polymer, for example a resin or a dielectric. For example, the mask 310 is made of SiO 2 or Si x N y where x and y are non-zero integers. The hard mask 310 is made of, for example, the following materials: SiN, Si 3 N 4 , SiOCN, SiCBN, or one of the following materials: SiN, Si 3 N 4 , SiOCN, SiCBN, etc. The mask 310 has at least one opening 311, as shown in FIG. 1C, through which etching of the III-V layer 100 is performed.

[0048] The etching may be a dry or wet etching. For example, it may be a chlorine or fluorocarbon chemistry plasma etching step. This etching step may be carried out in a reactive ion etching (RIE) reactor, preferably an inductively coupled plasma (ICP) reactor. Separately or complementary to the conventional plasma etching, it is also possible to carry out self-limiting cyclic etching methods, such as ALE (Atomic Layer Etching). Such methods generally comprise the following steps: - modifying a part of the layer to be etched, which is preferably located on the surface of this layer, e.g. by modifying the surface of the layer to be etched with Cl2 / BCl 3 self-limiting chlorination by exposure to plasma of - etching a portion of the layer to be etched, thus selectively modifying it with respect to the remainder of the layer to be etched, for example using an Ar-based plasma under a non-zero bias voltage. It consists of one or more periods including

[0049] A self-limiting cyclic etching method makes it possible to significantly limit damage to the etched layers. In synergy with the plasma treatment step described below, etching the III-V layer 100 with such a method makes it possible to obtain a further improved quality of the interface 1000. However, it is quite possible that etching the III-V layer 100 is limited to conventional plasma etching.

[0050] The etching techniques mentioned above are given by way of example and in no way constitute an exhaustive list of possible techniques.

[0051] The etching step just described makes it possible to expose a surface of the III-V layer 100, called the etched surface 103, as represented in Figure 1D. According to one example, this etching makes it possible, for example, to form trenches in the III-V layer 100.

[0052] The third step consists of exposing the etching surface 103 to a treatment, as represented in FIG. 1E. The treatment is characterized in this figure by a vertical arrow pointing towards the etching surface 103. This treatment is carried out by subjecting the etching surface 103 to a treatment using dioxygen (O 2 ) and / or dinitrogen (N 2) based plasma. This step is represented by block 32 in FIG. 3. This step is advantageously carried out in the same chamber as the step of etching the III-V layer 100. This is preferably an ICP reactor. By carrying out the plasma treatment step in situ, it is possible to limit contamination due to ventilation of the sample and improve the productivity. This also has advantages commensurate with the structural defects induced by the etching step. Indeed, from the etching step onwards, the etching surface 103 constitutes a reactive surface, which reacts with air during ventilation and forms defects. For example, the gaps caused by the etching at the etching surface 103 can be filled with contaminants present in the air, such as carbon or oxygen-based contaminants. The contaminants therefore constitute traps capable of hindering the step of depositing the dielectric detailed above and / or modifying the electrical properties of the device obtained after further subsequent steps. By subjecting the etching surface 103 to a plasma treatment in situ and prior to ventilation of the sample, it is possible to fill these gaps with beneficial elements provided by the plasma, thus limiting the filling of these gaps with elements present in the air. For example, the nitrogen gaps of the GaN-based etching surface 103 can be filled with N 2 This can be filled with nitrogen atoms provided by the base plasma treatment.

[0053] However, it is possible to perform the plasma treatment in a chamber different from the one used to etch the III-V layer 100 .

[0054] O source in the processing chamber 2 or N 2A flow of is generated, the power of which is between 100 W and 4000 W, preferably between 300 W and 1000 W. The power of the flow is a parameter that directly influences the reactivity of the plasma formed. Within the scope of the invention, it is sought to obtain a highly chemically reactive plasma in order to ensure a good reconstruction of the etching surface 103 with short processing times. This is characterized in particular by a high concentration of reactive radicals and a limited amount of ions. Increasing the power of the flow makes it possible to increase the amount of reactive radicals, but also has the effect of increasing the density of ions. The preferred values ​​mentioned therefore represent a good compromise. The flow can be pure or it can be mixed with small amounts of other gases. For example, it can be N 2 and O 2 A flow consisting of N 2 and Ar, or O 2 and Ar. The flow rate of the species is advantageously between 50 and 1000 sccm (standard cubic centimetres per minute), preferably between 100 and 500 sccm. The duration of this plasma treatment step is advantageously between a few seconds, preferably between 30 s and a few hundred seconds. The bias voltage is preferably zero. In fact, by choosing a non-zero bias voltage in combination with the fact that the plasma contains ions, the risk of degradation increases.

[0055] The plasma treatment step is carried out at a temperature below 100° C. and not at high temperatures, as is the case in current techniques for recrystallizing etched layers. These treatment conditions make it possible to improve the quality of the interface 1000 by an unexpected ratio. This low temperature level makes it possible in particular to obtain a stable interface 1000 after the plasma treatment step. This makes it possible to improve the robustness of the method and therefore the quality of the interface, while improving the productivity. In addition, O 2 In the case of the base plasma treatment, low temperature work makes it possible to avoid unwanted oxidation on the etching surface 103 .

[0056] Preferably, the processing temperature, i.e. the temperature of the substrate carrier on which the III-V layer 100 rests in the plasma processing chamber, is greater than or equal to 20° C. Preferably, the processing temperature is less than 90° C. Advantageously, the processing temperature is between 40° C. and 80° C., preferably between 60° C. and 80° C. An increased temperature makes it possible in particular to improve the reactivity of the etching surface 103 and therefore to optimize the structural reconstruction of the III-V layer 100.

[0057] Advantageously but optionally, after the step of exposure to the plasma treatment, a wet cleaning of the etched surface 103 of the III-V layer 100 is provided. This cleaning is advantageously based on HCl, HF or a mixture of HCl and HF. This step makes it possible to clean the etched surface prior to the deposition of the dielectric layer 200, and is complementary to the plasma treatment. It also makes it possible to improve the electrical properties of the interface between the etched III-V layer 100 and the dielectric layer 200. These electrical properties are surprisingly improved. This cleaning step is carried out outside the reactor that allows etching of the III-V layer 100. This optional step is represented by the block 33 depicted in dotted lines in FIG. 3.

[0058] The fourth step, represented in Figure 1F and indicated by block 34 in Figure 3, consists of the deposition, at least on the etched surface 103 of the III-V layer 100, of a layer based on a dielectric material. This layer is called dielectric layer 200. Preferably, the following materials are used: AlN, Al 2 O 3 , HfO 2 or a mixture thereof. Preferably, the deposition of the dielectric layer 200 is carried out by ALD (Atomic Layer Deposition). This may be a thermal ALD or a plasma ALD method. If the dielectric layer 200 is Al 2 O 3 In the particular case of a deposition carried out by thermal ALD, the oxygen-based precursor is water (H 2 O) or ozone (O 3), and the aluminum-based precursor may be trimethylaluminum (TMA). If the deposition is performed by plasma-assisted ALD, the oxygen-based precursor may be dioxygen (O 2 ) based plasma. The deposition of the dielectric layer 200 is preferably carried out under vacuum to avoid contamination.

[0059] The contact zone between the lower surface 202 of the dielectric layer 200 and the etched surface 103 of the group III-V layer 100 defines the interface 1000 between the group III-V layer 100 and the dielectric layer 200 .

[0060] FIG. 1G illustrates an optional step of removing the mask 310 and some parts of the dielectric layer 200. This removal can be performed before or after the step of exposing the etching surface 103 to a plasma treatment, and before or after the step of depositing the dielectric layer 200. This removal can, for example, be simultaneous with a cleaning step. In this case, preferably HF-based or HCl and HF-based solvents are used. Advantageously, the mask 310 is stored until the step of exposing to a plasma treatment, during which the mask 310 can function as a mask. The mask 310 may also be stored until the step of depositing the dielectric layer 200, as illustrated in FIG. 1F.

[0061] 2A and 2B illustrate one of the advantages provided by the method according to the present invention. The graph presented in FIG. 2A shows the relationship between the etched GaN layer and the Al 2 O 3 2A and 2B are CV (capacitance-voltage) characteristics of a MOS capacitor obtained by a method that does not include a plasma treatment after etching of the GaN layer, with an interface between the layers. The graph presented in Fig. 2B is the CV characteristics of a MOS capacitor designed by the same material by the same method according to one of the embodiments of the present invention, but whose etched GaN layer is subjected to a plasma treatment in an ICP reactor and an HCl-based wet cleaning. In each of the two Figs. 2A and 2B, the CV characteristics are identified for different frequencies of the AC signal applied to the studied MOS capacitor.

[0062] It should be noted that at low frequencies (see especially the 5 kHz feature) and at high frequencies (see especially the 500 kHz feature), the MOS capacitor characterized in Figure 2A has lower performance than the MOS capacitor characterized in Figure 2B. The slopes of the features for each of the studied frequencies are in fact lower than their counterparts in Figure 2B, representing a slower passage of the accumulation region relative to the inversion region in response to a voltage variation. Thus, a comparison of Figures 2A and 2B highlights the clear improvement in the performance of electronic components with etched III-V material / dielectric interfaces, thanks to the method according to the invention.

[0063] Figures 4, 5A and 5B illustrate that, as mentioned above, the choice of the processing temperature makes it possible to optimize the performance of the devices made according to the invention. The graph presented in Figure 4 is the CV characteristics of a MOS capacitor with an interface between a dielectric and a III-V material for two distinct processing temperatures, namely 40°C and 60°C, obtained by carrying out an embodiment of the method according to the invention. Figures 5A and 5B illustrate the values ​​of the flat band voltage Vfb and the hysteresis ΔVfb for each of these two samples. It is observed that the MOS capacitor subjected to processing at a temperature of 60°C has better electrical characteristics than the one whose processing temperature was 40°C. In particular, its flat band voltage is higher (T treatment = 1.35V at 40°C, approx. 1.61V), while the hysteresis is obviously smaller (T treatment = 0.65 V at 40° C.) Thus, in one measurement, increasing the treatment temperature during the plasma treatment step allows a clear improvement in the device performance, which is explained by a better resorption of the surface defects.

[0064] However, it was noted that, surprisingly, at temperatures above 80° C., the performance of the MOS capacitors was significantly and rapidly degraded. This explains why it is not always useful to treat samples at high, or even very high, temperatures, as is commonly achieved, in the hope of achieving better recrystallization. Too rapid recrystallization can, on the contrary, solidify structural defects, especially on the surface, and thus lead to a degradation of the device's performance.

[0065] These results therefore illustrate the optimization of the structural restructuring of III-V layers in the range of 60°C to 80°C.

[0066] An advantage of the solution proposed by the invention is that the steps of exposing the etched III-V layer 100 to a plasma treatment and of depositing the dielectric layer 200 can be carried out for any III-V material after any type of etching. The method according to the invention therefore constitutes a solution that can be considered universal for the problem of the quality of the interface between the etched III-V material and the dielectric. In addition, such adaptability allows a certain standardization of the methods for manufacturing electronic components in which the method according to the invention can be incorporated.

[0067] Another advantage of the proposed solution is, in addition, that the plasma treatment step is a rapid step that can be carried out immediately after the etching step in the same reactor, thus allowing the method according to the invention to be integrated into a method for manufacturing microelectronic devices without altering the productivity.

[0068] Through the different embodiments described above, it becomes clearly evident that the present invention proposes an effective solution to improve the productivity of the formation of an interface between an etched III-V layer and a dielectric layer, while ensuring a good quality of this interface.

[0069] The proposed method is particularly advantageous for power applications, such as power transistors, or for LEDs or μLEDs, where the thickness of the etched III-V material, such as GaN, may be from 100 nanometers to several microns.

[0070] The present invention is not limited to the embodiments described above, but extends to all embodiments covered by its spirit. [Explanation of symbols]

[0071] 100 III-V material layers 101 Top surface 102 Bottom surface 103 Etched surface 200 Dielectric layer, dielectric material 202 Bottom surface 300 Mask Layers 310 Mask 311 Aperture 1000 Boundary Surface

Claims

1. 1. A method for forming a layer based on a dielectric material on an etched layer based on a III-V material, comprising at least the following steps: Providing at least one layer based on a III-V material, preferably III-N, called III-V layer (100), having a top surface (101); Etching at least a portion of the III-V layer (100) from the top surface (101) so as to expose a surface of the III-V layer, referred to as the etching surface (103); At least the etched surface (103) is O ２ Plasma treatment of N ２ or O ２ and N ２ and exposing the mixture to a plasma treatment at a temperature T between 60° C. and 80° C. ｔｒｅａｔｍｅｎｔ and depositing a layer based on a dielectric material, called the dielectric layer (200), at least on said etching surface; A method comprising:

2. The method of claim 1 , wherein said etching step and said plasma treating step are performed in one and the same reactor.

3. The plasma treatment step is ｔｒｅａｔｍｅｎｔ <5 minutes, preferably t ｔｒｅａｔｍｅｎｔ Duration t < 2 minutes ｔｒｅａｔｍｅｎｔ The method according to claim 1 or 2, comprising:

4. The method of claim 1 , further comprising a wet cleaning step prior to the step of depositing the dielectric layer.

5. The method of claim 1 , wherein the step of depositing the dielectric layer is carried out under vacuum.

6. The method of claim 1 , wherein the etching step comprises a chlorine plasma etch.

7. 7. The method of claim 1, wherein the etching step comprises at least one ALE type etching cycle.

8. The plasma treatment step is performed at a zero bias voltage V ｂｉａｓ The method according to any one of claims 1 to 7, wherein the method is carried out under

9. The etching is 100 nm (10 －９ meter), preferably greater than 500 nm, preferably greater than 1 μm (10 －６ The method according to any one of claims 1 to 8, carried out to etch a thickness of III-V material greater than 1000 Å (meter), preferably greater than 3 μm.

10. The plasma treatment step has a mass flow rate D between 50 sccm and 1000 sccm, preferably between 100 sccm and 500 sccm. ｆｌｏｗ O ２ The flow of N ２ Flow of, or O ２ and N ２ 10. The method according to claim 1 , wherein the method is carried out by injecting a stream of a mixture of

11. The plasma treatment step is carried out with a power source P of between 100 W and 4000 W, preferably between 300 W and 1000 W. ｓｏｕｒｃｅ Generated by O ２ The flow of N ２ Flow of, or O ２ and N ２ 11. The method according to claim 1, wherein the method is carried out by injecting a stream of a mixture of

12. The method according to any one of claims 1 to 11, wherein the III-V material is one of GaN and AlGaN.

13. The dielectric material is AlN, Al ２ O ３ , and HfO ２ The method according to any one of claims 1 to 12, wherein the method is one of:

14. A method for making a microelectronic device comprising forming a layer based on a dielectric material (200) on an etched layer based on a III-V material (100) by implementing the method according to any one of claims 1 to 13, said microelectronic device being taken from among transistors and LEDs.

15. the microelectronic device is a transistor; said etching of said III-V layer (100) is performed to create trenches in said etched III-V material; said deposition of said layer based on a dielectric material (200) is carried out on at least a portion of said etched surface of said trench to form a gate dielectric; After said formation of said dielectric layer (200), the following steps are performed: filling the trench to define at least one gate of the transistor.

15. A method for making the microelectronic device of claim 14, comprising:

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