Autonomous Frequency Search from a Plasma Output Source

Abstract

The embodiments disclosed in this specification include processing tools. In an embodiment, the processing tool includes a transmission line sensor and an analog / digital (A / D) converter. In an embodiment, the processing tool may further include a digital down converter (DDC) and a frequency digital phase-locked loop (dPLL). In an embodiment, the processing tool may further include a transmission line scaling module.

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims priority to U.S. Patent Application No. 17 / 737,665, filed on May 5, 2022, the entire content of which is incorporated herein by reference.

[0002] Embodiments relate to the field of semiconductor manufacturing, and more particularly, to a semiconductor processing tool configured to provide frequency search from a plasma output source.

Background Art

[0003] In a plasma processing tool, plasma is ignited by a cathode coupled to a processing gas in a chamber. In most tools, the power supply is coupled to the cathode through an impedance matching network (sometimes simply referred to as a "matcher"). The matcher makes it possible to adjust the impedance of the system for matching with the impedance of the load to which the cathode is coupled. The load has a wide range of impedances defined by parameters such as processing conditions and chamber structure. Impedance matching is important for efficient power transfer from the power supply to the load.

[0004] In addition to impedance matching, it is also important to know the exact frequency of the power supplied from the power supply. Therefore, a frequency detection system may be included in the power supply network. In existing frequency identification methods, in order to determine the frequency, the passing of messaging or other information from various systems or subsystems is required. Optimal messaging or information passing requires a network connection between two points, and a significant group delay occurs between actuator control and feedback across various elements of a dynamic system. Therefore, a delay occurs in the required frequency feedback.

Summary of the Invention

[0005] The embodiments disclosed in this specification include processing tools. In an embodiment, the processing tool comprises a transmission line sensor and an analog / digital (A / D) converter. In an embodiment, the processing tool may further comprise a digital down converter (DDC) and a frequency digital phase-locked loop (dPLL). In an embodiment, the processing tool may further comprise a transmission line scaling module.

[0006] Further embodiments disclosed in this specification may further include a processing tool. In an embodiment, the processing tool comprises a transmission line sensor and an analog / digital (A / D) converter. In an embodiment, the processing tool may further comprise a digital down converter (DDC) and a transmission line scaling module.

[0007] Further embodiments may include a semiconductor processing tool. In an embodiment, the semiconductor processing tool may include a chamber, a plasma source connected to the chamber, and a signal processing module for determining the frequency of the plasma generated by the plasma source. In an embodiment, the signal processing module includes a transmission line sensor, an analog / digital (A / D) converter, a digital down converter (DDC), a frequency digital phase-locked loop (dPLL), and a transmission line scaling module.

Brief Description of the Drawings

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Mode for Carrying Out the Invention

[0009] The systems described herein include a power supply architecture configured to provide frequency search from a plasma output source. In the following description, numerous specific details are presented in order to provide a comprehensive understanding of the embodiments. It will be apparent to those skilled in the art that the embodiments can be practiced without these specific details. In other instances, well-known aspects are not described in detail so as not to unnecessarily obscure the embodiments. Further, it should be understood that the various embodiments shown in the accompanying figures are exemplary representations and are not necessarily drawn to scale.

[0010] As described above, knowledge of the frequency of the processing power is important in real-time processing control and monitoring. Therefore, the embodiments disclosed herein include detection and search processes with high accuracy, minimum group delay, and optimal control. Further, the methods described herein are autonomous and do not require messaging and / or information transfer from other systems or subsystems.

[0011] Referring now to FIG. 1, a more detailed schematic view of a plasma processing tool 100 according to an embodiment is shown. In one embodiment, the plasma processing tool 100 includes a plasma chamber 120. The plasma chamber 120 includes a cathode 122 for coupling the received power to one or more gases flowing into the plasma chamber 120. In one embodiment, the plasma chamber 120 may be suitable for any plasma processing typical in a semiconductor manufacturing environment. For example, the plasma chamber 120 may be a plasma etching chamber, a plasma deposition chamber, a plasma treatment chamber, etc. In a particular embodiment, the plasma chamber 120 may be a plasma enhanced chemical vapor deposition (PECVD) chamber, a physical vapor deposition (PVD) chamber, or a plasma enhanced atomic layer deposition (PEALD) chamber.

[0012] In one embodiment, the plasma chamber 120 may be coupled to a power supply architecture. For example, the power supply architecture may include one or more power supplies 132 1 -132 n as shown. In the illustrated embodiment, a plurality of power supplies 132 are shown. However, it should be understood that in some embodiments, a single power supply 132 may be used. In one embodiment, the power supply 132 may include any type of power supply. For example, the power supply 132 may be an RF power supply, a microwave power supply, a direct current (DC) power supply, a pulsed DC power supply, etc.

[0013] In one embodiment, the power supply 132 may be coupled to the cathode 122 via an impedance matching network 130. The impedance matching network 130 changes the impedance of the power supply architecture to match the load within the chamber 120. The impedance of the load may vary due to changes in processing conditions (e.g., gas flow rate, pressure, temperature, etc.). Thus, the impedance matching network 130 is used to match the varying impedance to provide an efficient (i.e., with no or minimal reflected power) power supply within the chamber.

[0014] In one embodiment, sensors 151 and 152 may be provided on both sides of impedance matching network 130. For example, sensor 151 1 -151 n may be on the upstream side of impedance matching network 130, and sensor 152 may be on the downstream side of impedance matching network 130. The "upstream" side may refer to the input side of matching network 130, and the "downstream" side may refer to the output side of matching network 130. As shown in the figure, a plurality of sensors 151 1 -151 n are provided on the upstream side of impedance matching network 130. The number of sensors 151 may be equal to the number of power supplies 132. That is, each power supply 132 has a dedicated sensor 151. The downstream side of impedance matching network 130 may have a single sensor 152. However, it should be understood that additional sensors 152 may exist if there is more than one output from matching network 130. For example, if there are two outputs (for example, for the center of chamber 120 and the end of chamber 120), there may be two sensors 152.

[0015] When there are a plurality of sensors 151, the plurality of sensors 151 1ーn can be manufactured on a single PCB. That is, a single module can include a plurality of sensors. Generally, the embodiments described herein include electrical shielding techniques that limit the mutual coupling between sensors on a single PCB.

[0016] In FIG. 1, sensors 151 and 152 are generally shown as blocks. However, it should be understood that sensors 151 and 152 may be similar to any of the sensor architectures described in more detail below. For example, each sensor 151 and / or 152 may be a voltage and current (i.e., V / I) sensor. The voltage may be detected by an embedded voltage ring, and the current may be detected by a current loop. The sensor may have an aperture through which a cable (e.g., an RF cable) passes.

[0017] In one embodiment, sensors 151 and 152 may be communicatively coupled to the processing power control module 134. For example, in FIG. 1, an RF processing power control module 134 may be provided. However, it should be understood that the processing module may be a microwave processing power control module 134, a DC processing power control module, etc., depending on the type of power supply 132 included in the tool 100. In one embodiment, sensors 151 and 152 supply voltage and / or current to the processing power control module. In one embodiment, the processing power control module may have external connections such as ENET and ECAT connections.

[0018] In one embodiment, the processing power control module 134 may be coupled to the impedance matching network by an analog / digital link. Through the analog / digital link, the processing power control module 134 may be able to transmit a control signal to the impedance matching network 130. For example, the control signal may be used to adjust the capacitance of a variable capacitor in the impedance matching network 130. Further, the processing power control module 134 may be coupled to the power supply 132 by an analog / digital link. Thus, the processing power control module 134 enables cooperative impedance adjustment.

[0019] Referring now to FIG. 2, a plan view of a sensor 250 according to an embodiment is shown. As shown, the sensor 250 is fabricated on a PCB 253. The sensor 250 may include a current loop 254 and a voltage loop 265 within the current loop 254. The current loop 254 and the voltage loop 265 may surround the aperture 260 through the PCB 253.

[0020] In one embodiment, the current loop 254 may include inner vias 255 B and outer vias 255 A The vias 255 may be connected to each other by a trace 256 on the top surface of the PCB 253 and a trace 257 on the bottom surface of the PCB 253. In the illustrated embodiment, the current loop 254 includes a pair of windings around the aperture 260.

[0021] In one embodiment, the voltage ring 265 may include an inner conductive ring 266 and an outer conductive ring 268. The insulating ring 267 may be provided between the inner ring 266 and the outer ring 268. The inner ring 266 may be a voltage pickup surface, and the outer ring 268 may be grounded. In one embodiment, the inner ring 266 may define the outer periphery of the aperture 260.

[0022] In one embodiment, the sensor 250 may further include a protective ring 270 surrounding the outer periphery of the current loop 254. In one embodiment, the protective ring 270 may be grounded. The protective ring 270 may include vias (not shown). These vias connect the protective ring 270 to a ring on the bottom surface of the PCB 253 having a similar size and shape. Accordingly, an electrical shielding barrier is provided around the pickup components of the sensor 250. For this reason, the sensor performance can be improved.

[0023] In one embodiment, the voltage ring 265 may be connected to a pickup circuit 281 on the PCB 253. The pickup circuit 281 in FIG. 2 is schematically shown as a dashed box. However, it should be understood that the pickup circuit 281 may include features such as filters and amplifiers. In one embodiment, pads 283 are provided. The pads 283 may be suitable for the attachment of a connector (not shown) in order to feedback voltage information to a processing module (for example, the processing module described in more detail above).

[0024] In one embodiment, the current loop 254 can be coupled to a pickup circuit 282 on the PCB 253. The pickup circuit 282 in FIG. 2 is schematically shown as a dashed box. However, it should be understood that the pickup circuit 282 may include features such as filters and amplifiers. In one embodiment, a pad 284 is provided. The pad 284 may be suitable for attachment of a connector (not shown) to feedback current information to a processing module (e.g., the processing module described in more detail above).

[0025] In one embodiment, the pickup circuit 281 is electrically isolated from the pickup circuit 282. The two sets of pickup circuits 281 and 282 enable reduction of the mutual coupling between the two circuits. Thus, the performance of the sensor 250 can be improved. In one embodiment, electrical insulation can be achieved by a conductive strip 285 provided between the two sets of pickup circuits 281 and 282. In one embodiment, the conductive strip 285 can be grounded. In some embodiments, the conductive strip 285 is electrically coupled to the protection ring 270. The conductive strip 285 may be provided on the top surface of the PCB 253. In other embodiments, vias may be provided below the strip 285 to extend the electrical insulation through the thickness of the PCB 253.

[0026] Referring now to FIG. 7, a more detailed schematic diagram of a processing power control module 790 according to an embodiment is shown. As described above, the processing power control module 790 may include an impedance matching network and functional blocks for controlling one or more power supplies. As described above, knowing the actual frequency of the power supply is beneficial for processing control. Thus, the embodiments disclosed herein include a processing power control module 790 configured to implement a frequency detection process.

[0027] In an embodiment, the processing power control module 790 may include a dual analog / digital (A / D) converter 741. The dual A / D converter 741 may receive a first input from a voltage sensor and a second input from a current sensor such as the transmission line sensor 750. For example, an analog voltage signal and an analog current signal may be provided to the dual A / D converter 741. The analog voltage signal and the analog current signal can be picked up by sensors such as the sensors described in more detail above. For example, the sensors may be current sensors and voltage sensors. In an embodiment, the dual A / D converter 741 may have a sample rate of about 250 megasamples per second (MSPS) or more. However, it should be understood that in some embodiments, a lower sample rate is also possible.

[0028] In an embodiment, the converted digital signal may then be processed by a digital down converter (DDC) 742. The digital down converter may take in the input signal and apply a low-pass filter to obtain a desired signal. For example, in FIG. 3, the first graph on the left shows the input digital signal. As can be seen from the figure, the desired signal 314 (frequency f) may be surrounded by other signals of various intensities. The function of the low-pass filter may result in the graph on the right. The graph on the right shows that the desired signal 315 (frequency f) has been frequency-shifted and passed through the DDC, while the other signals have been significantly attenuated. This results in a better signal-to-noise ratio in a system with multiple frequency impairments.

[0029] In an embodiment, the output of the digital conversion may be provided in Cartesian coordinates. Further, the output may be split into two branches. The first branch may be passed directly to the transmission line scaling matrix 764, and the second branch may pass through the digital phase lock loop dPLL 766. The first branch may remain in Cartesian coordinates and propagate the signal at a first rate R. The second branch may start in Cartesian coordinates and propagate the signal at a second rate nR. In an embodiment, the second rate nR may be greater than the first rate R. For example, the second rate nR may be four times or more the first rate R.

[0030] In an embodiment, the second branch provides the Cartesian coordinates to a Polar Phase converter block. Then, to improve the measurement accuracy of the system, the frequency can be supplied to a scaling matrix 764 and / or fed back to a DDC742 to provide feedback to the digital down-conversion process.

[0031] In the description of FIG. 7, for simplicity, one iteration of the frequency detector is described. However, it should be understood that in some embodiments, additional frequency detectors may be used. For example, if there are two or more power supplies, dedicated frequency detectors may be provided for each power supply. A more detailed description of the additional frequency detectors is provided in the description of FIG. 7 below.

[0032] Referring now to FIG. 4, a process 480 for detecting the frequency of a signal from a power supply according to an embodiment is described. In an embodiment, frequency detection can be used as part of a system control architecture to provide an efficient power supply from the power supply to a load (e.g., a plasma load). In an embodiment, process 480 can be utilized by a power supply architecture such as the architecture described in more detail above, although a similar process 480 may be utilized in other power supply architectures.

[0033] In an embodiment, process 480 can be initiated at operation 481. Operation 481 includes picking up an analog voltage signal and an analog current signal with a transmission line sensor. In an embodiment, the analog voltage signal and the analog current signal can be detected by a sensor including a voltage loop and a current loop, as in the embodiments described in more detail above. In an embodiment, a single sensor can be placed before or after an impedance matching network. In other embodiments, multiple sensors (e.g., before and / or after the impedance matching network) can be used.

[0034] In an embodiment, process 480 may subsequently proceed to operation 482. Operation 482 includes digitizing an analog voltage signal and an analog current signal into a digital voltage signal and a digital current signal. For example, the digitization process may be implemented by an A / D converter. In some embodiments, a dual A / D converter may be used to digitize both signals. In certain embodiments, the A / D converter may have a sample rate of about 250 MSPS or higher.

[0035] In an embodiment, process 480 may subsequently proceed to operation 483. Operation 483 includes down-converting a digital signal to provide a first signal having a first rate and a second signal having a second rate. In an embodiment, the first rate (i.e., the first signal rate) is less than the second rate (i.e., the second signal rate). In certain embodiments, the second rate may be about 4 times the first signal rate. In other embodiments, the second rate may be approximately any integer multiple of the first signal rate. The down-conversion can be implemented using a DDC such as the DDC342 described in more detail above.

[0036] In an embodiment, process 480 may subsequently proceed to operation 484. Operation 484 includes extracting phase V(θ V ) and phase I(θ I ) from the second signal. For example, the second signal can be supplied to a frequency detector described in more detail above. In such an embodiment, the desired signal can be represented in Cartesian form and converted to polar form to derive a time-varying phasor.

[0037] In an embodiment, process 480 may subsequently proceed to operation 485. Operation 485 multiplies the derivative of the phase by 2π to convert the rotational phase unit to the number of rotations. The multiplication operation can be performed by a functional block configured to perform frequency conversion.

[0038] In an embodiment, the detected frequency of a desired signal is sent to a scaling matrix. The first signal may also be sent to the scaling matrix. In other embodiments, optionally, to improve the accuracy of frequency detection, it is also possible to return the detected frequency to the DDC as a feedback input.

[0039] Accordingly, the embodiments described herein enable real-time processing control and monitoring that utilize knowledge of the frequency of the processing power. The detection and search methods described herein achieve high accuracy with minimal group delay and enable optimal control. Furthermore, the methods described herein are autonomous and do not require messaging and / or information transfer from other systems or subsystems.

[0040] Referring now to FIG. 5, a schematic diagram of a processing system used to identify the frequency of a signal according to an embodiment is shown. In the embodiment, graph A 1 , A 2 provides an illustration of the received signal and interference. The frequency ω c is the frequency of the desired signal, and the frequencies of other signals need to be substantially filtered because they cause interference that degrades the performance of the controller.

[0041] In an embodiment, a pair of transmission line sensors (TL sensor port 1 and TL sensor port 2) supply signals to the processing system. The signal from TL sensor port 1 is A 1 sin(ω c nTs + φ 1 ), and the signal from TL sensor port 2 is A 2 sin(ω c nTs + φ 2 ). The signals are routed to dual A / D converters 561 A and 561 B . Dual A / D converters 561 A and 561 Bis part of the digital down-conversion process. Further, the signal is dual A / D converters 561 which are part of a frequency digital phase-locked loop (dPLL) block C and 561 D can be routed to.

[0042] In an embodiment, dual A / D converters 561 A and 561 B can each supply the imaginary part (Q) of the signal and the real part (I) of the signal to a digital down-converter (DDC) 562 1 . DDC 562 1 can have a sample rate R. DDC 562 1 can combine the imaginary Q signal and the real I signal into a complex signal. For example, the first complex signal may take the form of a 1 e j(ωRTs+φ1) , and the second complex signal may take the form of a 2 e j(ωRTs+φ2) . In an embodiment, scaling factors (e.g., K 21 , K 11 , K 12 , and K 22 ) are multiplied against the complex signal by multiplier 563. The result of the multiplication can then be sent to transmission line scaling module 564. Transmission line scaling module 564 is a linear combination that takes two complex signals and outputs a set of four outputs. For example, the four outputs can include voltage V L , forward power P F , reflected power P R , and current I L .

[0043] In an embodiment, the frequency dPLL block begins with dual A / D converters 561 C and 561 D . Similar to dual A / D converters 561 A and 561 B , dual A / D converters 561 C and 561 D supply a real signal (I) and an imaginary signal (Q). Signals I and Q are then sent to DDC 5622 can be processed by DDC562 2 has a sample rate different from that of DDC562 1 For example, in some embodiments, the sample rate can be 2 -1 R. The DDC outputs a signal that is combined with the complex signal. The complex signal can be in the form of a 11 e j(ωn2^(-k)RTs) and a 22 e j(ωn2^(-k)RTs) In an embodiment, the complex signal is then converted to polar form by Cartesian to polar converters 565. The output polar signal can be in the form of θ 1 (n2 -k RTs) and θ 2 (n2 -k RTs). The polar signal can then be processed by the frequency dPLL module 566. The frequency dPLL module 566 can output a frequency ω

[0044] In an embodiment, the output from the frequency dPLL module 566 can be directly supplied to the direct digital synthesis (DDS) block 567. In an embodiment, the DDS block 567 outputs a conjugate modifier e j(ωnTs) or e -j(ωnTs) that is fed back to the dual A / D converter 561. In the lower dPLL block, the modifiers can be a conjugate pair. Using a conjugate pair can prevent the dPLL from locking incorrectly to an in-band frequency

[0045] Referring now to FIG. 6, a schematic diagram of a signal processing module when there is no interference according to an embodiment is shown. Graph A 1 ,A 2 As shown in, the only frequency is at ω C . A pair of TL sensor ports can then be supplied to the dual A / D converters 661 A and 661 B . The dual A / D converters 661 A and 661 Brespectively output the real I part and the imaginary Q part of the signal, and supply these signals to DDC662 1 and 662 2 can supply. DDC662 combines the real and imaginary components of the signal into a complex signal in the form of a 1 e j(ωRTs+φ1) and a 2 e j(ωRTs+φ2) form.

[0046] In an embodiment, the complex signal can be converted to polar form by a Cartesian - polar converter 665. The converted signal can take the form of θ 1 (nRTs) and θ 2 (nRTs). The polar - form signal can then be used to extract the frequency values ω 1 and ω 2 . Then, the frequency values can be supplied to DDS667 to provide an output modifier e j(ωnTs) that is supplied to the dual A / D converter 661.

[0047] In an embodiment, the complex signal can further be directed to pass through a filter 668. The filter 668 may be a finite impulse response (FIR) filter. In a particular embodiment, the filter 668 can be an equalization FIR filter. The output of the filter 668 can be supplied to a transmission line scaling module 664. The transmission line scaling module 664 includes a linear combination that takes two complex signals and outputs a set of four outputs. For example, the four outputs can include the load voltage V L , the forward power P F , the reflected power P R , and the load current I L . Further, the scaling matrix can generate a direct transfer from the raw DDC complex quantities to the incident voltage V i , the incident current I i , the reflected voltage V r , and the reflected current I r .

[0048] Referring now to FIG. 7, a schematic diagram of a signal processing architecture according to an embodiment is shown. In an embodiment, the signal processing architecture may include one or more transmission line sensors 750. For example, in FIG. 7, three transmission line sensors are shown. In an embodiment, each transmission line sensor may be coupled to a dual A / D converter 741. The dual A / D converter 741 may be coupled to a system-on-chip 790. In particular, the dual A / D converter is coupled to programmable logic 794 on the system-on-chip 790. In an embodiment, the programmable logic 794 may include threads for each transmission line sensor 750. In an embodiment, each thread may include a DDC 742, a transmission line scaling module 764, and a frequency dPLL 766. In each thread, the DDC 742, the transmission line scaling module 764, and the frequency dPLL 766 may be communicatively coupled to each other in the same manner as the embodiments described in more detail above.

[0049] In some embodiments, the frequency dPLL 766 may be shared among the threads. For example, the frequency dPLL 766 for the second transmission line sensor 750 may be shared by the third transmission line sensor 750. That is, a single frequency dPLL 766 may be coupled to a pair of DDCs 742 and a pair of transmission line scaling modules 764.

[0050] In an embodiment, the transmission line scaling module 764 may be communicatively coupled to a real-time processor 791. The real-time processor 791 may be communicatively coupled to a memory (e.g., DRAM 793) and a messaging controller 792.

[0051] Referring now to FIG. 8, a block diagram of an exemplary computer system 800 of a processing tool is shown in accordance with an embodiment. In one embodiment, the computer system 800 is coupled to the processing tool and controls processing within the processing tool. The computer system 800 may be connected (e.g., networked) to other machines in a local area network (LAN), intranet, extranet, or the Internet. The computer system 800 may operate in the role of a server or client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The computer system 800 may be any machine capable of executing a set of (sequential or otherwise) instructions to specify actions to be taken by that machine, such as a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, web appliance, server, network router, switch or bridge, or the like. Further, although only a single machine is shown as the computer system 800, the term "machine" should be further construed to include any collection of machines (e.g., computers) that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods described herein.

[0052] The computer system 800 may include a computer program product or software 822 having a non-transitory machine-readable medium storing instructions, which may be used to program the computer system 800 (or other electronic device) to perform the processing according to the embodiments. The machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium (e.g., read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium (in the form of electrical, optical, acoustic, or other propagated signals (e.g., infrared signals, digital signals, etc.)), etc.

[0053] In one embodiment, the computer system 800 includes a system processor 802, a main memory 804 (e.g., dynamic random access memory (DRAM) such as read-only memory (ROM), flash memory, synchronous DRAM (SDRAM), or Rambus DRAM (RDRAM)), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory 818 (e.g., a data storage device), which communicate with each other via a bus 830.

[0054] The system processor 802 represents one or more general-purpose processing devices such as a micro-system processor or a central processing unit. More specifically, the system processor can be a complex instruction set computing (CISC) micro-system processor, a reduced instruction set computing (RISC) micro-system processor, a very long instruction word (VLIW) micro-system processor, a system processor that executes other instruction sets, or a system processor that executes a combination of instruction sets. The system processor 802 can also be one or more special-purpose processing devices such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal system processor (DSP), or a network system processor. The system processor 802 is configured to execute processing logic 826 for performing the operations described herein.

[0055] The computer system 800 may further include a system network interface device 808 for communicating with other devices or machines. The computer system 800 may further include a video display unit 810 (e.g., a liquid crystal display (LCD), a light-emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 812 (e.g., a keyboard), a cursor control device 814 (e.g., a mouse), and a signal generation device 816 (e.g., a speaker).

[0056] The secondary memory 818 may include a machine-accessible storage medium 832 (or more specifically a computer-readable storage medium) in which one or more sets of instructions (e.g., software 822) that implement any one or more of the methods or functions described herein are stored. The software 822 may also reside, in whole or at least in part, within the main memory 804 and / or the system processor 802 while being executed by the computer system 800, and the main memory 804 and the system processor 802 may also constitute a machine-readable storage medium. The software 822 may be further transmitted and received over the network 820 via the system network interface device 808. In one embodiment, the network interface device 808 may operate using RF coupling, optical coupling, acoustic coupling, or inductive coupling.

[0057] In the exemplary embodiments, the machine-accessible storage medium 832 is shown as a single medium, but the term "machine-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized database or a distributed database, and / or associated caches and servers) that store one or more sets of instructions. Further, the term "machine-readable storage medium" should be interpreted to include any medium that is capable of storing or encoding a set of instructions executable by a machine and that causes a machine to execute any one or more of the methods. Thus, the term "machine-readable storage medium" should be interpreted to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0058] In the foregoing specification, specific exemplary embodiments have been described. It will be apparent that various modifications may be made to the specific exemplary embodiments without departing from the scope of the following claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a limiting sense.

Claims

1. A transmission line sensor, an analog / digital (A / D) converter, a digital down converter (DDC), a frequency digital phase-locked loop (dPLL), and a transmission line scaling module A processing tool comprising.

2. The processing tool according to claim 1, wherein the A / D converter is configured to receive an analog signal from the transmission line sensor and supply a digital signal to the DDC.

3. The processing tool according to claim 2, wherein the frequency dPLL, the transmission line scaling module, and the DDC are communicably coupled to each other.

4. The processing tool according to claim 1, wherein the transmission line sensor comprises a voltage sensor and a current sensor.

5. The processing tool according to claim 4, wherein the A / D converter is a dual A / D converter.

6. A second transmission line sensor, a second A / D converter, a second DDC, a second transmission line scaling module, and a second frequency dPLL The processing tool according to claim 1, further comprising.

7. A third transmission line sensor, a third A / D converter, a third DDC, and a third transmission line scaling module The processing tool according to claim 6, further comprising.

8. The processing tool according to claim 7, wherein the second frequency dPLL is communicably coupled to the third DDC and the third transmission line scaling module.

9. The processing tool according to claim 1, wherein the DDC is configured to process a real component of a signal from the transmission line sensor and an imaginary component of the signal from the transmission line sensor, and the DDC is configured to combine the real component and the imaginary component into a complex signal.

10. The processing tool according to claim 9, wherein the transmission line scaling module includes a plurality of scaling factors, and each of the plurality of scaling factors is configured to be multiplied by the complex signal.

11. The processing tool according to claim 1, wherein the dPLL feeds back a frequency to the DDC via a direct digital synthesis (DDS) module.

12. The processing tool according to claim 1, wherein the transmission line scaling module outputs voltage, forward power, reflected power, and current.

13. The processing tool according to claim 1, wherein the dPLL includes a feedback loop, and the feedback loop includes multiplying a conjugate pair by a signal.

14. A transmission line sensor, an analog / digital (A / D) converter, a digital down converter (DDC), and a transmission line scaling module A processing tool comprising.

15. The processing tool according to claim 14, wherein a filter is provided in front of the transmission line scaling module, and a complex signal passes through the filter.

16. The processing tool according to claim 15, wherein the filter is a finite impulse response (FIR) filter.

17. The processing tool according to claim 14, wherein the transmission line scaling module outputs voltage, forward power, reflected power, and current.

18. A chamber, a plasma source connected to the chamber, and a signal processing module for determining the frequency of the plasma generated by the plasma source, a transmission line sensor; an analog / digital (A / D) converter; a digital down converter (DDC); a frequency digital phase-locked loop (dPLL); a transmission line scaling module A signal processing module comprising A semiconductor processing tool comprising.

19. The semiconductor processing tool according to claim 18, wherein the A / D converter is configured to receive an analog signal from the transmission line sensor and supply a digital signal to the DDC.

20. The processing tool according to claim 18, wherein the frequency dPLL, the transmission line scaling module, and the DDC are communicably connected to each other.

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