Level shifter, semiconductor device, and method of manufacturing the same

Abstract

The present invention provides a level shifter, a semiconductor device, and a method for manufacturing the same. In the level shifter, by forming a non-doped region and / or an inverted-doped region in at least one isolation doped region, the overall ion amount in the isolation doped region is reduced, the difficulty of lateral depletion of the isolation doped region is decreased, which helps to improve the overall breakdown voltage performance of the level shifter, raise the breakdown voltage of the level shifter, and also realize that the isolation performance of the isolation region can be guaranteed, ensuring that there is no leakage phenomenon between the high-voltage side circuit and the drain terminal.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductors, and particularly to a level shifter and a manufacturing method thereof, a semiconductor device, and a manufacturing method thereof.

Background Art

[0002] A high-voltage power gate drive chip is usually realized by a process that enables both a high-voltage circuit and a low-voltage circuit. Between the high-voltage side circuit and the low-voltage side circuit, in order to control the high-voltage side circuit, a control signal from the low-voltage side circuit is converted into a control signal for the high-voltage side circuit by a level shifter and transmitted to the high-voltage side circuit, thereby realizing level conversion between the high-voltage side circuit and the low-voltage side circuit.

[0003] Here, a separation region is provided on the outer periphery of the level shifter to separate the high-voltage side circuit from the level shifter and prevent the influence on the function between devices caused by leakage. Currently, as separation forms in the separation region, for example, dielectric separation (separating the device structure in the substrate by an insulating medium such as an oxide), self-separation (realizing separation between devices by the breakdown voltage of the depletion layer of the device itself), junction separation (separating using the principle of PN reverse bias), etc. are included. When designing the separation region, it is necessary to ensure that the separation region itself has sufficient breakdown voltage to ensure the separation performance between the high-voltage side circuit and the level shifter, and usually, it is also necessary to achieve the breakdown voltage performance of the level shifter.

[0004] Therefore, how to ensure the breakdown voltage performance of the separation region and increase the breakdown voltage of the level shifter has always been an important research topic in this field.

Summary of the Invention

[0005] An object of the present invention is to provide a level shifter and a manufacturing method thereof that can effectively increase the breakdown voltage of the level shifter and optimize the breakdown voltage performance of the device.

[0006] Therefore, the present invention provides a level shifter including a substrate, a drain region of a first doping type and a source region of a first doping type formed in the substrate, and a gate structure formed on the substrate and located between the source region and the drain region, and at least one isolation doping region of a second doping type extending along the outer periphery of the field effect transistor and provided around the field effect transistor, wherein a non-doped region and / or an inverted doping region is formed in at least one isolation doping region.

[0007] The present invention further provides a semiconductor device including the level shifter as described above and a high-voltage side circuit located on a side away from the field effect transistor of the isolation doping region.

[0008] The present invention further provides a method for manufacturing a level shifter, which includes a step of forming a field effect transistor on a substrate, wherein the field effect transistor includes a drain region of a first doping type, a source region of a first doping type, and a gate structure, the drain region and the source region are formed in the substrate, the gate structure is formed on the substrate, and the gate structure is located between the source region and the drain region. The method for manufacturing the level shifter further includes a step of forming at least one isolation doping region of a second doping type around the field effect transistor, and a non-doped region and / or an inverted doping region is further formed in at least one isolation doping region.

[0009] The present invention further provides a method for manufacturing a semiconductor device, which includes the step of manufacturing the level shifter as described above or the step of manufacturing the semiconductor device by processing on a substrate having the level shifter as described above.

[0010] In the level shifter provided by the present invention, in order to reduce the overall ion amount in the isolation doped region, an undoped region or an inverted doped region is further provided in at least one isolation doped region, which helps to reduce the difficulty of lateral depletion in the isolation doped region and improve the overall breakdown voltage performance of the level shifter, realizes increasing the breakdown voltage of the level shifter and guaranteeing the isolation performance and breakdown voltage performance of the isolation region, and guarantees that there is no leakage phenomenon between the high-voltage side circuit and the drain terminal.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0012] Hereinafter, the level shifter, semiconductor device, and manufacturing method thereof according to the present invention will be described in more detail with reference to the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the drawings are all in a very simplified form and non-precise proportions, and are merely for assisting in easily and clearly explaining the embodiments of the present invention. The relative terms such as "upper", "lower", "uppermost", "bottom", "above", and "below" shown in the drawings should be recognized as being used to explain the relationships between various elements among each other. These relative terms are intended to include different orientations of elements other than the orientations shown in the figures. When the device is arranged oppositely to the drawing, for example, an element described as being "above" another element is now below the other element.

[0013] FIG. 1 is a schematic structural diagram of a semiconductor device having a level shifter according to an embodiment of the present invention, FIG. 2 is a schematic cross-sectional diagram of the semiconductor device shown in FIG. 1, and FIGS. 3 to 5 are schematic structural diagrams of three other types of semiconductor devices having a level shifter according to an embodiment of the present invention. FIGS. 17 to 18 are schematic structural diagrams of two types of semiconductor devices having a level shifter according to another embodiment of the present invention.

[0014] As shown in FIGS. 1 to 5 / FIGS. 17 to 18, the level shifter provided by this embodiment includes a substrate 100, a field effect transistor 200 formed on the substrate 100, and at least one isolation doping region (for example, in this embodiment, including three isolation doping regions: a first buried region PBL1, a first deep well region DPW1, and a first shallow well region PW1) formed outside the field effect transistor 200.

[0015] Here, the substrate 100 has a doping layer of a first doping type (i.e., an epitaxial layer 120N). In a specific example, the substrate 100 includes, for example, a base 110P and an epitaxial layer 120N formed on the base 110P. Specifically, the base 110P is a base of a second doping type, and the epitaxial layer 120N is an epitaxial layer of a first doping type. Therefore, the epitaxial layer 120N becomes the doping layer of the first doping type of the substrate 100.

[0016] It should be noted that the first doping type and the second doping type are opposite doping types. For example, if the first doping type is N-type, the second doping type is P-type, or if the first doping type is P-type, the second doping type is N-type. In this embodiment, the case where the first doping type is N-type and the second doping type is P-type is taken as an example for explanation.

[0017] Furthermore, specifically, the field effect transistor 200 includes a drain region 200D of a first doping type, a source region 200S of the first doping type, and a gate structure 200G. The drain region 200D and the source region 200S are specifically formed within a doping layer of the first doping type (i.e., the epitaxial layer 120N) of the substrate 100. The gate structure 200G is formed on the substrate 100 and is located between the source region 200S and the drain region 200D. In this embodiment, the field effect transistor 200 is, for example, an LDMOS transistor, and the epitaxial layer 120N located within the transistor region can be used to form the drift region of the LDMOS transistor.

[0018] Continuing to refer to FIGS. 1 to 5 / FIGS. 17 to 18, outside the field effect transistor 200, a separation region is provided to separate the field effect transistor 200 from the high-voltage side circuit and prevent the influence on the functions between devices caused by leakage. Here, at least one separation doping region of a second doping type (for example, a P-type separation region) is provided within the separation region, and the separation doping region extends along the outer periphery of the field effect transistor. In one example, the separation doping region can surround the transistor region from the high-voltage side (i.e., the side close to the drain region 200D) of the transistor region and reach the low-voltage side (i.e., the side close to the source region 200S) of the transistor region. Specifically, by forming at least one separation doping region within the doping layer of the first doping type of the substrate 100, device separation is realized by using the PN junction separation technology. By applying a PN reverse bias to the PN junction separation, depletion layer expansion can be generated in the PN junction separation structure, the breakdown strength of the device can be improved, and the leakage between the field effect transistor 200 and the high-voltage side circuit can be reduced.

[0019] Furthermore, at least two separated doped regions sequentially connected from top to bottom may be provided in the separation region. Among them, the separated doped region located at the lowermost layer extends upward from the base 110P to within the epitaxial layer 120N, and the separated doped region located at the upper layer is formed within the epitaxial layer 120N. That is, by sequentially connecting at least two separated doped regions from top to bottom, the epitaxial layer 120N is penetrated in the height direction to reach the base 110P.

[0020] In this embodiment, three separated doped regions are provided in the separation region, and include a first embedded region PBL1 of a second dopant type, a first deep well region DPW1 of a second dopant type, and a first shallow well region PW1 of a second dopant type, which are sequentially provided from bottom to top and connected to each other. Here, the first shallow well region PW1 is a well region with a dopant depth shallower than that of the first deep well region DPW1, and the first deep well region DPW1 is a well region with a dopant depth deeper than that of the first shallow well region PW1. Specifically, the first shallow well region PW1 extends inward from the upper surface of the substrate 100 and partially overlaps with the first deep well region DPW1 below in the height direction. The first deep well region DPW1 partially overlaps with the first embedded region PBL1 below it in the height direction. The first embedded region PBL1 straddles the interface between the epitaxial layer 120N and the base 110P. Thus, the first shallow well region PW1, the first deep well region DPW1, and the first embedded region PBL1 are connected up and down to penetrate the epitaxial layer 120N.

[0021] In this embodiment, three separated doped regions are provided. However, in other examples, as long as the separated doped regions are sequentially connected to penetrate the epitaxial layer 120N, it should be recognized that two separated doped regions (for example, only including the first shallow well region PW1 and the first embedded region PBL1 connected up and down) or three or more separated doped regions may be included.

[0022] Further, a first isolation oxide layer 400 formed on the upper surface of the substrate 100 and located above the isolation dope region may be further provided in the topmost isolation dope region. Here, the first isolation oxide layer 400 may be formed, for example, by a selective oxidation isolation process (Local Oxidation of Silicon, LOCOS). When the substrate 100 is a silicon substrate, the first isolation oxide layer 400 may correspondingly be a silicon oxide layer.

[0023] At least one non-doped region and / or a reverse-doped region of a first dope type are further provided in the isolation dope region. For example, in at least the topmost isolation dope region, the non-doped region and / or the reverse-doped region for adjusting the overall ion doping amount of the isolation dope region and reducing the overall ion amount of the isolation dope region may be provided. Thereby, it helps to reduce the difficulty of lateral depletion of the isolation dope region and increase the breakdown voltage of the level shifter.

[0024] In one embodiment of the present invention, referring to FIGS. 1 to 5, when a non-doped region is provided, the non-doped region can continuously extend along the isolation dope region. Thereby, the non-doped region correspondingly surrounds the outside of the field effect transistor 200. Also, when a reverse-doped region is provided, the reverse-doped region can also continuously extend along the isolation dope region. Thereby, the reverse-doped region correspondingly surrounds the outside of the field effect transistor 200. The non-doped region and / or the reverse-doped region provided by the present invention are provided in the isolation dope region so as to continuously extend along the extending direction of the isolation dope region. Therefore, the manufacturing difficulty of the non-doped region and the reverse-doped region is reduced, the process can be more easily controlled, which helps to improve the product yield and can be applied to large-scale production.

[0025] In another embodiment of the present invention, referring to FIGS. 17 to 18, a plurality of undoped regions and / or a plurality of inverted doped regions may be provided in the separation doped region, and the plurality of undoped regions and / or the plurality of inverted doped regions may be sequentially arranged at intervals in the separation doped region along the extending direction of the separation doped region. For example, referring to FIG. 17, the plurality of undoped regions and / or the plurality of inverted doped regions are arranged in two columns, and the undoped regions and / or the inverted doped regions in each column are all sequentially arranged at intervals along the extending direction of the separation doped region, that is, arranged in an array. Or, as shown in FIG. 18, the plurality of undoped regions and / or the plurality of inverted doped regions are arranged in one column along the extending direction of the separation doped region. Of course, in other examples, the plurality of undoped regions and / or the plurality of inverted doped regions may be arranged in other forms, which are not limited here.

[0026] For convenience of explanation, hereinafter, both the undoped region and the inverted doped region are defined and described as the adjustment region 300. Therefore, the undoped region and the inverted doped region in this embodiment may refer to the adjustment region 300 shown in FIGS. 1 to 5 / FIGS. 17 to 18.

[0027] Regarding the adjustment region 300 of the inverted doping region, since the doping type of the inverted doping region is opposite to that of the separated doping region, it corresponds to a reduction in the overall ion amount of the second doping type within the separated doping region. Here, specifically, the inverted doping region may be formed by an ion implantation process, that is, ion implantation of the first doping type is performed on the separated doping region to form the inverted doping region. Or, the inverted doping region may be formed by a filled material of the first doping type, that is, the inverted doping region may include a concave groove formed within the separated doping region and a material of the first doping type filled within the concave groove. Specifically, the concave groove is, for example, at least one concave groove formed by etching a part of the separated doping region after forming the separated doping region by ion implantation with respect to the substrate 100. At this time, the P-doped region within the separated doping region is partially removed correspondingly, and the overall doping amount within the separated doping region is reduced (that is, the amount of P-type ions within the separated doping region is reduced). Also, filling the material of the first doping type within the concave groove to form the inverted doping region corresponds to further reducing the overall amount of P-type ions within the separated doping region.

[0028] Furthermore, the depth of the inverted doping region can be adjusted as needed and includes the following. The inverted doping region may be formed only in the first shallow well region PW1 (for example, in the case of the depth of the adjustment region 300 in the examples of FIGS. 1, 2, 3, and 4), or the inverted doping region may extend downward from the first shallow well region PW1 further into the first deep well region DPW1 (for example, in the case of the depth of the adjustment region 300 in the example of FIG. 5), and furthermore, the inverted doping region may be formed within the first shallow well region PW1 and the first deep well region DPW1 and may extend downward further into the first buried region PBL1.

[0029] Regarding the adjustment region 300 of the non-doped region, in a selective solution, the non-doped region is, for example, a region in the separated doped region where ion implantation is not performed in the ion implantation process (i.e., when performing ion implantation in the separated doped region, a part of the separation region can be shielded by a mask layer to avoid ion implantation and form the non-doped region). At this time, the overall doping amount in the separated doped region can be reduced similarly (i.e., the amount of P-type ions in the separated doped region is reduced). In this embodiment, in at least one ion implantation process of the first shallow well region PW1, the first deep well region DPW1, and the first buried region PBL1, a part can be shielded to form a non-doped region. In another selectable solution, the non-doped region includes, for example, a concave groove formed in the separated doped region and a non-doped material filled in the concave groove. The concave groove for accommodating the non-doped material in this solution and the concave groove for accommodating the material of the first doping type in the above solution can be set with similar manufacturing processes and groove depths, and detailed description is omitted here. In still another selectable solution, the non-doped region may only include a concave groove formed in the separated doped region.

[0030] Similarly, the depth of the non-doped region in this example can also be adjusted as needed, including the following. The non-doped region may be formed only in the first shallow well region PW1 (for example, in the case of the depth of the adjustment region 300 in the examples of FIGS. 1, 2, 3, and 4), or the non-doped region may extend downward from the first shallow well region PW1 to further into the first deep well region DPW1 (for example, in the case of the depth of the adjustment region 300 in the example of FIG. 5), or further, the non-doped region may be formed in the first shallow well region PW1 and the first deep well region DPW1 and further extend downward into the first buried region PBL1.

[0031] In a further solution, for example, as shown in FIG. 4, at least two adjustment regions 300 may be provided in the separation dope region. That is, in the separation dope region, at least two undoped regions sequentially arranged from the side closer to the field effect transistor 200 to the side farther away may be provided, or at least two inverted dope regions sequentially arranged from the side closer to the field effect transistor 200 to the side farther away may be provided in the separation dope region. The two adjustment regions 300 shown in FIG. 4 both continuously extend along the separation dope region and sequentially surround the outside of the field effect transistor. Or, at least one inverted dope region and at least one undoped region sequentially arranged from the side closer to the field effect transistor 200 to the side farther away are provided in the separation dope region (not shown).

[0032] That is, in the example of FIG. 4, at least two adjustment regions 300 are provided in the separation dope region, and each adjustment region 300 continuously extends along the separation dope region, and at least two adjustment regions 300 sequentially surround the periphery of the field effect transistor 200 in the order of proximity. In the examples of FIGS. 17 and 18, a plurality of adjustment regions 300 are provided in the separation dope region, and the plurality of adjustment regions 300 are arranged at intervals in one row or multiple rows along the extending direction of the separation dope region.

[0033] Also, in the examples of FIGS. 17 and 18, the parameter settings of the adjustment region 300 may specifically refer to FIG. 20. In FIG. 20, the D1 direction is the extending direction of the separation dope region, and the D2 direction is the cross-sectional direction perpendicular to the extending direction of the separation dope region. Here, the distance S1 from the adjustment region 300 to the side boundary of the adjacent separation dope region is 1 μm or more, and the distance between adjacent adjustment regions 300 may also be 1 μm or more (for example, the distance S3 between adjacent adjustment regions 300 in the D1 direction is 1 μm or more, and the distance S2 between adjacent adjustment regions 300 in the D2 direction may also be 1 μm or more). Also, the cross-sectional shape of the adjustment region 300 parallel to the surface of the substrate may be circular, elliptical, rhombic, rectangular, etc., and the maximum lateral dimension S4 of the adjustment region 300 is, for example, 2 μm to 5 μm. The shape, dimensions of the adjustment region 300, and the distance from the adjustment region 300 to the side boundary of the adjacent separation dope region are not limited to these, and it should be recognized that in specific applications, for example, they can be adjusted according to the actual dope concentration and dimensions of the separation dope region, etc.

[0034] Continuing to refer to FIGS. 1 to 5 / FIGS. 17 to 18, a second shallow well region PW2 of a second dope type is further formed in the substrate 100. The second shallow well region PW2 extends downward from the upper surface of the substrate 100 to the inside of the substrate and is formed on the low-voltage side of the transistor region (that is, on the side close to the source region 200S of the gate structure 200G), and the source region 200S can be formed within the second shallow well region PW2. Also, the portion of the gate structure 200G close to the source region 200S further shields the second shallow well region PW2. When an on voltage is applied to the gate structure 200G of the field-effect transistor 200, an inversion-induced conductive channel is formed within the second shallow well region PW2 shielded by the gate structure 200G. Thereby, current flow from the source region 200S, through the conductive channel, the drift region to the drain region 200D is realized. That is, the second shallow well region PW2 is for constituting the body region of the inversion channel of the field-effect transistor 200.

[0035] Here, in the second shallow well region PW2, a first contact region 200B of the second doping type (specifically, a body contact region Bulk) is further formed. In order to electrically extract the second shallow well region PW2 by the first contact region 200B, the ion doping concentration of the first contact region 200B is greater than the ion doping concentration of the second shallow well region PW2. In this embodiment, the first contact region 200B is formed on the side away from the gate structure 200G of the source region 200S, and a second isolation oxide layer 210 is further provided between the first contact region 200B and the source region 200S.

[0036] In a specific example, the second shallow well region PW2 and the first shallow well region PW1 may be formed simultaneously in the same ion implantation process. Thereby, the second shallow well region PW2 and the first shallow well region PW1 have the same parameters, that is, the second shallow well region PW2 and the first shallow well region PW1 may have substantially the same doping depth and doping concentration. In particular, the first shallow well region PW1 surrounds the field effect transistor 200 from the outside of the drain region 200D and extends horizontally to the low voltage side of the transistor region, so that the first shallow well region PW1 is connected to the second shallow well region PW2 in the horizontal direction. Furthermore, the first shallow well region PW1 and the second shallow well region PW2 connected to each other can surround the field effect transistor 200.

[0037] It should be noted that the second shallow well region PW2 and the first shallow well region PW1 are formed simultaneously in the same ion implantation process. In order to ensure the performance of the field effect transistor 200, it is necessary to meet the requirements for the doping concentration and doping depth of the second shallow well region PW2. Therefore, it is difficult to directly adjust the doping concentration and doping depth of the first shallow well region PW1 in the ion implantation process. Based on this, in this embodiment, by providing the adjustment region 300 (i.e., the undoped region or the inverted doping region), the overall ion doping amount in the first shallow well region PW1 can be significantly reduced without affecting the second shallow well region PW2, which helps to reduce the difficulty of lateral depletion of the separated doping region.

[0038] In this embodiment, a second deep well region DPW2 of a second doping type and a second buried region PBL2 of the second doping type are further formed in the substrate 100. The second deep well region DPW2 and the second buried region PBL2 are sequentially formed below the second shallow well region PW2 and are connected to each other. The second deep well region DPW2 may have the same doping depth and doping concentration as the first deep well region DPW1, and the second buried region PBL2 may have the same doping depth and doping concentration as the first buried region PBL1. Specifically, the second deep well region DPW2 and the first deep well region DPW1 may be formed simultaneously in the same ion implantation process, and the second buried region PBL2 and the first buried region PBL1 may also be formed simultaneously in the same ion implantation process. That is, the second shallow well region PW2 extends inward from the upper surface of the substrate 100 and partially overlaps with the second deep well region DPW2 below in the height direction. The second deep well region DPW2 partially overlaps with the second buried region PBL2 below it in the height direction. The second buried region PBL2 extends downward from the epitaxial layer 120N to the base 110P. Thereby, the second shallow well region PW2, the second deep well region DPW2, and the second buried region PBL2 are connected vertically and penetrate the epitaxial layer 120N. Similarly, both the first buried region PBL1 and the first deep well region DPW1 extend horizontally from the outside of the drain region 200D to surround the field effect transistor 200 to the low voltage side of the transistor region (i.e., the side close to the source region 200S), so that the first deep well region DPW1 is connected to the second deep well region DPW2 in the horizontal direction, and the first buried region PBL1 is connected to the second buried region PBL2 in the horizontal direction. Furthermore, the mutually connected first deep well region DPW1 and second deep well region DPW2, and the mutually connected first buried region PBL1 and second buried region PBL2 can both surround the field effect transistor 200.

[0039] On the low-voltage side of the transistor region (i.e., the side close to the source region 200S), the vertically connected second shallow well region PW2, second deep well region DPW2, and second buried region PBL2 are also used to achieve the separation effect. They are horizontally connected one-to-one with the first shallow well region PW1, first deep well region DPW1, and first buried region PBL1 in the separation region to separate the field-effect transistor 200 therein. It is considered that a separation ring surrounding the field-effect transistor 200 is formed.

[0040] That is, the separation doping region in this embodiment can be adjusted according to the doping situation on the low-voltage side. For example, on the low-voltage side (i.e., the side close to the source region 200S), the second shallow well region PW2 designed to meet the performance requirements of the field-effect transistor 200 has a small depth. At this time, by adding and providing the second deep well region DPW2, the vertically connected second shallow well region PW2, second deep well region DPW2, and second buried region PBL2 can reach the base 110P to achieve separation. At this time, in the separation region, the first shallow well region PW1, first deep well region DPW1, and first buried region PBL1 may be correspondingly provided. Conversely, if the designed second shallow well region PW2 has a large depth and can be vertically connected to the lower second buried region PBL2, the second deep well region DPW2 may be omitted. At this time, in the separation region, the first deep well region DPW1 may be correspondingly omitted, and only the first shallow well region PW1 and the first buried region PBL1 may be provided.

[0041] Continuing to refer to FIGS. 1 to 5 / FIGS. 17 to 18, a third well region NW1 of a first doping type is further formed in the substrate 100. The third well region NW1 is located on the high-voltage side of the transistor region (i.e., the side close to the drain region 200D of the gate structure 200G), and the drain region 200D is formed in the third well region NW1. Here, the ion doping concentration of the third well region NW1 may be between the ion doping concentration of the drain region 200D and the ion doping concentration of the epitaxial layer 120N, whereby a buffer is formed by the third well region NW1, and a large change in the ion doping concentration from the drain region 200D directly to the epitaxial layer 120N can be avoided. As described above, in one selectable solution, the inverted doping region of the first doping type can be formed by an ion implantation process. At this time, in order to facilitate the simplification of the process, the inverted doping region and the third well region NW1 can be simultaneously formed by the same ion implantation process. In this way, the depth of the formed inverted doping region can be made substantially the same as the depth of the third well region NW1. For example, the depth of the adjustment region 300 in FIGS. 1, 2, 3, and 4 is substantially the same as the depth of the third well region NW1.

[0042] Continuing to refer to FIGS. 1 to 5, in one example, a third embedded region NBL1 of the first doping type is further provided in the substrate 100. The third embedded region NBL1 is located below the third well region NW1, and the third embedded region NBL1 and the third well region NW1 at least partially spatially overlap. In this embodiment, a part of the third embedded region NBL1 further extends laterally toward the separated doping region so that a part thereof exceeds the projection range of the third well region NW1. That is, the third embedded region NBL1 partially spatially overlaps with the third well region NW1 and also has a part exceeding the overlapping region. By providing the third embedded region NBL1 for adjusting the electric field distribution at the drain end, the electric field lines in the drain end region become gentler, and further the breakdown voltage at the drain end is improved. Furthermore, the breakdown voltage at the drain end may be made larger than the breakdown voltage of the high-voltage side circuit. Thereby, an electrostatic protection structure can be formed between the high-voltage side circuit and the low-voltage side circuit to discharge current. Further, the third embedded region NBL1 is partially formed in the base 110P and extends upward from the base 110P into the epitaxial layer 120N.

[0043] It should be noted that, in a specific example, the third embedded region NBL1 may or may not be provided. Also, the third embedded region NBL1 may be a continuous doping region as in the examples of FIGS. 1, 2, 4, and 5, or in other examples, the third embedded region NBL1 may be a plurality of intermittently arranged doping regions as in the example of FIG. 3. In the example shown in FIG. 3, by cutting a continuous large-area doping region into a plurality of intermittently arranged small-area doping regions, the ion amount of the first doping type ions in the third embedded region NBL1 can be reduced, and the breakdown voltage performance can be further optimized.

[0044] In an alternative solution, a field oxide layer 220 is also formed on the surface of the substrate 100. The field oxide layer 220 is located between the second shallow well region PW2 and the drain region 200D. Also, the gate structure 200G further extends to cover the field oxide layer 220 to form a field plate structure. Here, the field oxide layer 220 may be formed, for example, by a selective oxidation isolation process (Local Oxidation of Silicon, LOCOS). When the substrate 100 is a silicon substrate, the field oxide layer 220 may correspondingly be a silicon oxide layer. In this embodiment, the drain region 200D is formed between the field oxide layer 220 and the first isolation oxide layer 400. Also, the field oxide layer 220, the first isolation oxide layer 400, and the second isolation oxide layer 210 can be simultaneously formed by a selective oxidation isolation process in the same process step.

[0045] Continuing to refer to FIGS. 1 to 5 / FIGS. 17 to 18, in one example, a plurality of fifth embedded regions PBL3 are also formed in parallel in the substrate 100. The plurality of fifth embedded regions PBL3 are arranged within the transistor region, specifically arranged between the source region 200S and the drain region 200D. More specifically, they may be arranged below the gate structure 200G and the field oxide layer 220. Also, the fifth embedded region PBL3 extends downward from the epitaxial layer 120N to within the base 110P (or it may be considered that the fifth embedded region PBL3 extends upward from the base 110P to within the epitaxial layer 120N). By providing the fifth embedded region PBL3, the depletion degree of the drift region of the field effect transistor 200 below the field oxide layer 220 (in the epitaxial layer 120N) is further increased. Also, since a plurality of fifth embedded regions PBL3 with small dimensions are provided in parallel (the width dimension of the fifth embedded region PBL3 may be smaller than the width dimension of the first embedded region PBL1, for example), it is possible to effectively avoid the ion concentration of the second doping type in this region from being too high.

[0046] Further, this embodiment further provides a semiconductor device having a level shifter as described above, and the semiconductor device further includes a high-voltage side circuit. Referring to FIGS. 1 to 5 / FIGS. 17 to 18, the high-voltage side circuit is provided on the high-voltage side of the level shifter (i.e., the side close to the drain region 200D), and is located on the side away from the field effect transistor 200 of the isolation doped region. The high-voltage side circuit includes a fourth well region NW2 of a first doping type, and a second contact region of the first doping type for realizing electrical connection with the outside is further formed in the fourth well region NW2. Further, the high-voltage side circuit further includes a fourth buried region NBL2 of the first doping type, and the fourth buried region NBL2 extends upward from the base 110P to within the epitaxial layer 120N.

[0047] In this embodiment, the third buried region NBL1 and the fourth buried region NBL2 can be simultaneously formed on both sides of the isolation doped region by the same ion implantation process. Thus, the third buried region NBL1 and the fourth buried region NBL2 have the same doping parameters (for example, the doping depth and the doping concentration are substantially the same). In an alternative solution, for example, as shown in FIG. 3, by adjusting the pattern of the corresponding mask when performing the ion implantation process, the third buried region NBL1 can be formed as a small-area doped region arranged at intervals, and the fourth buried region NBL2 can be formed as a large-area doped region extending continuously. In this way, in the same ion implantation process, the amount of ions in the formed third buried region NBL1 can be smaller than the amount of ions in the fourth buried region NBL2. Further, the spatial overlapping area between the third buried region NBL1 and the third well region NW1 is smaller than the spatial overlapping area between the fourth buried region NBL2 and the fourth well region NW2, so that the breakdown voltage performance at the drain end can be made higher than the breakdown voltage performance on the high-voltage side, which is useful for forming an electrostatic protection structure between the high-voltage side circuit and the low-voltage side circuit.

[0048] During the operation of the semiconductor device, the body contact region Bulk (i.e., the first contact region 200B) and the source region 200S can be connected to the low-potential port, an operating voltage (e.g., 25V) can be applied to the gate structure 200G, and the drain region 200D and the high-voltage side circuit (e.g., the second contact region in the fourth well region NW2) can be connected to the high-potential port. (Here, for example, 600V is applied to the drain region 200D and 615V is applied to the high-voltage side circuit.) In this process, the mutual separation between the drain region 200D and the high-voltage side circuit can be realized by the separation region.

[0049] As described above, by adjusting the overall ion doping amount of the separation doping region and providing the adjustment region 300 in the separation doping region to reduce the overall ion amount of the separation doping region, it is helpful to reduce the difficulty of lateral depletion of the separation doping region and further increase the breakdown voltage of the level shifter.

[0050] Referring to the set of simulation results shown in FIG. 21, it is a comparison diagram (i.e., a comparison of the overall breakdown voltage performance of the level shifter) that simulates the breakdown voltage BV_D when the drain end of the device and the high-voltage side circuit are short-circuited when the adjustment region 300 is provided in the separation doping region and when the adjustment region 300 is not provided. As shown in FIG. 21, the breakdown voltage BV_D1 when the adjustment region 300 is not provided is only 173.7V, but the breakdown voltage BV_D2 after the adjustment region 300 is provided can rise to 674.5V, and the breakdown voltage performance of the device has been greatly improved.

[0051] Next, referring to another simulation result shown in FIG. 22, which simulates the breakdown voltage BV_H between the high-voltage side circuit and the drain terminal when in the operating state when the adjustment region 300 is provided, the breakdown voltage BV_H is obtained as follows. For example, while maintaining that the drain region 200D is connected to the 600V potential, a scanning voltage that gradually increases from 600V is applied to the high-voltage side circuit until breakdown appears (specifically, the scanning voltage is continuously increased from 600V with respect to the second contact region of the fourth well region NW4). As shown in FIG. 22, after the adjustment region 300 is provided, the breakdown voltage BV_H between the high-voltage side circuit and the drain terminal can rise to 20V, satisfying the breakdown voltage requirement (greater than 15V) of the isolation structure 310 and ensuring that there is no leakage phenomenon between the high-voltage side circuit and the drain terminal.

[0052] For the level shifter and the semiconductor device as described above, the manufacturing method thereof will be described in detail below. As shown in FIGS. 1 to 5 / FIGS. 17 to 18, the manufacturing method of the level shifter in this embodiment specifically includes a step of forming a field effect transistor 200 on a substrate 100, where the field effect transistor 200 includes a drain region 200D of a first doping type, a source region 200S of the first doping type, and a gate structure 200G. The drain region 200D and the source region 200S are formed in the substrate 100, and the gate structure 200G is formed on the substrate 100, and the step of being located between the source region 200S and the drain region 200D. Further, the manufacturing method of the level shifter further includes a step of forming at least one isolation doping region of a second doping type in an isolation region, and at least one non-doped region and / or at least one inverted doping region are further formed in at least one isolation doping region. Here, at least one non-doped region and / or at least one inverted doping region may continuously extend along the isolation doping region, or may be arranged at intervals along the extending direction of the isolation doping region in the isolation doping region. Of course, it is also possible that a part of the non-doped region and / or the inverted doping region continuously extends along the isolation doping region and a part of the non-doped region and / or the inverted doping region are sequentially arranged at intervals along the extending direction of the isolation doping region at the same time. Further, for the semiconductor device, the manufacturing method thereof includes manufacturing a level shifter by the method as described above.

[0053] A method of forming at least one isolation doped region within an isolation region may include performing an ion implantation process of a second dopant type to form a first shallow well region PW1. Here, during the execution of the ion implantation process, a second shallow well region PW2 is further formed by implantation. The second shallow well region PW2 is located on the side closer to the source region 200S of the gate structure 200G, and the source region 200S is formed within the second shallow well region PW2. The first shallow well region PW1 surrounds the field effect transistor 200 from the outside of the drain region 200D and extends to the second shallow well region PW2 and is connected to the second shallow well region PW2. As described above, an undoped region and / or an inverted doped region are formed in at least one isolation doped region.

[0054] Here, a method of forming an inverted doped region in the isolation doped region may include, for example, the following. Perform an ion implantation process of a first dopant type on a part of the isolation region to form the inverted doped region, and also perform an ion implantation process of a second dopant type on another part of the isolation region to form an isolation doped region (including the first shallow well region PW1) surrounding the inverted doped region.

[0055] Alternatively, the method of forming an inverted doped region in the isolation doped region may further be as follows. Form a mask layer that completely exposes the isolation region on the substrate 100, then perform an ion implantation process of a second dopant type to form at least one isolation doped region (including the first shallow well region PW1), then etch a part of the region within at least the uppermost isolation doped region to form a concave groove within at least the uppermost isolation doped region, and then fill the concave groove with a material of the first dopant type to form the inverted doped region.

[0056] The method of forming a non-doped region in the isolation doped region includes, for example, the following. A mask layer is formed on the substrate 100, and a shielding pattern is formed in a part of the isolation region of the mask layer such that a part of the isolation region is shielded and the other part is exposed. Then, an ion implantation process of the second doping type is performed to form an isolation doped region (including the first shallow well region PW1) in the exposed isolation region, and ions are not implanted into the shielded part of the isolation region, and the non-doped region is formed.

[0057] Alternatively, the method of forming a non-doped region in the isolation doped region may further be as follows. A mask layer that completely exposes the isolation region is formed on the substrate 100. Then, an ion implantation process of the second doping type is performed to form at least one isolation doped region (including the first shallow well region PW1). Subsequently, a part of the region in at least the uppermost isolation doped region is etched to form a concave groove in at least the uppermost isolation doped region, and the concave groove portion can constitute a non-doped region. In a further solution, the concave groove may further be filled with a material of the first doping type. At this time, it can be considered that the concave groove and the material of the first doping type filled in the concave groove constitute a non-doped region.

[0058] In a specific example, the uppermost isolation doped region is the first shallow well region PW1. And while the first shallow well region PW1 is formed by implantation, a second shallow well region PW2 is further formed by implantation. Thus, the doping depth and the doping concentration of the first shallow well region PW1 and the second shallow well region PW2 are the same or approximately the same. By forming an inverted doped region or a non-doped region in the first shallow well region PW1, the total amount of P-type ions in the isolation region is reduced. It should be recognized that with the subsequent high-temperature process, the ions may diffuse into each other and reduce the ion concentration of the first shallow well region PW1.

[0059] In a further solution, the substrate 100 has a doped layer of a first doping type. In this embodiment, the substrate 100 includes a base 110P and an epitaxial layer 120N formed on the base 110P. Specifically, the base 110P is a base of a second doping type, and the epitaxial layer 120N is an epitaxial layer of a first doping type. Therefore, the epitaxial layer 120N becomes the doped layer of the first doping type of the substrate 100.

[0060] Also, at least two separation doped regions of the second doping type (for example, P-type separation doped regions) may be formed in the separation region. The at least two separation doped regions are sequentially provided from bottom to top and connected to each other. The separation doped region located at the lowermost layer extends downward from the epitaxial layer 120N into the base 110P (it may be considered that the separation doped region at the lowermost layer extends upward from the base 110P into the epitaxial layer 120N). In a specific example, the separation doped region can further extend from the high-voltage side of the transistor region to surround the transistor region and reach the low-voltage side of the transistor region. In this embodiment, three separation doped regions, namely, a second-doping-type first embedded region PBL1, a second-doping-type first deep well region DPW1, and a second-doping-type first shallow well region PW1, which are sequentially connected to each other from bottom to top, are formed in the separation region.

[0061] In an alternative solution, the method of forming at least one isolation doped region in the isolation region may be referred to FIGS. 7 to 10 and FIG. 12. First, referring to FIG. 7, a base 110P is prepared, and before forming the epitaxial layer 120N, a patterned mask layer 520 is formed on the base 110P, and a second doping type ion implantation process (for example, a P-type ion implantation process) is performed on the base 110P under the mask of the mask layer 520 to form a first buried region PBL1. Next, referring to FIG. 8, an epitaxial process is performed to form an epitaxial layer 120N on the base 110P. During the process of epitaxially forming the epitaxial layer 120N, the ions in the first buried region PBL1 can be further diffused upward into the epitaxial layer 120N. Subsequently, referring to FIG. 9, in this example, ion implantation of the first doping type is performed on a part of the isolation region to form an inverted doped region (i.e., the adjustment region 300 shown in FIG. 9). Subsequently, referring to FIG. 10, a patterned mask layer 540 is formed on the epitaxial layer 120N, and a second doping type ion implantation process (for example, a P-type ion implantation process) is performed on the epitaxial layer 120N under the mask of the mask layer 540 to form a first deep well region DPW1. Subsequently, referring to FIG. 12, a patterned mask layer 560 is formed on the epitaxial layer 120N, and then a second doping type ion implantation process (for example, a P-type ion implantation process) is performed under the mask of the mask layer 560 to form a first shallow well region PW1.

[0062] In another alternative solution, for a method of forming at least one separated doped region within a separation region, reference may further be made to FIGS. 23 to 26. First, referring to FIG. 23, a base 110P is provided, and a second dopant type ion implantation process (for example, a P-type ion implantation process) is performed on the base 110P to form a first buried region PBL1. Next, an epitaxial process is performed to form an epitaxial layer 120N on the base 110P. During the process of epitaxially forming the epitaxial layer 120N, the ions in the first buried region PBL1 can be diffused upward into the epitaxial layer 120N. Subsequently, referring to FIG. 24, a patterned mask layer 540 is formed on the epitaxial layer 120N, and a second dopant type ion implantation process (for example, a P-type ion implantation process) is performed on the epitaxial layer 120N under the mask of the mask layer 540 to form a first deep well region DPW1. Subsequently, referring to FIG. 26, a patterned mask layer 560 is formed on the epitaxial layer 120N. In this example, in the mask layer 560, a shielding pattern 561 is formed within the adjustment region 320 of the separation structure, so that only a part of the region of the separation structure is exposed. Then, a second dopant type ion implantation process (for example, a P-type ion implantation process) is performed under the mask of the mask layer 560 to form a first shallow well region PW1, and ions are not implanted into the region covered by the shielding pattern 561 within the first shallow well region PW1, and an undoped region is formed.

[0063] Also, simultaneously with manufacturing the first buried region PBL1, the first deep well region DPW1, and the first shallow well region PW1 within the separation region, a second buried region PBL2, a second deep well region DPW2, and a second shallow well region PW2 are correspondingly formed on the low voltage side. Here, the first buried region PBL1 and the second buried region PBL2 are connected to each other to form an annular structure, the first deep well region DPW1 and the second deep well region DPW2 are connected to each other to form an annular structure, and the first shallow well region PW1 and the second shallow well region PW2 are connected to each other to form an annular structure. Thereby, an annular separation ring can be formed.

[0064] In one example, the manufacturing method of the level shifter further includes a step of manufacturing the first isolation oxide layer 400. Specifically, reference may be made to FIG. 11 / FIG. 25, and the first isolation oxide layer 400 may be formed by a selective oxidation isolation process (LOCOS). In this embodiment, when manufacturing the first isolation oxide layer 400, the second isolation oxide layer 210 and the field oxide layer 220 are also formed at the same time.

[0065] Hereinafter, with reference to FIGS. 6 to 14, a specific manufacturing method of a semiconductor device having a level shifter will be described in detail. The specific manufacturing method includes a manufacturing process of the level shifter and a manufacturing process of other circuits (for example, a high-voltage side circuit).

[0066] First, referring to FIG. 6, a base 110P which is a base of the second doping type is prepared. In this embodiment, the base 110P is a P-type base. Specifically, it may be doped with boron ions (B), and the ion concentration is, for example, 1E13 cm -3 ~1.5E15 cm -3 . Then, a mask layer 510 is formed on the base 110P, and an ion implantation process of the first doping type (for example, an N-type ion implantation process) is performed under the mask of the mask layer 510 to form a third embedded region NBL1 in the high-voltage side of the level shifter (that is, the drain end region of the field effect transistor). In this embodiment, at the same time, a fourth embedded region NBL2 is further formed in the region of the high-voltage side circuit. Then, the mask layer 510 may be removed.

[0067] Next, referring to FIG. 7, a mask layer 520 is formed on the base 110P. In the mask layer 520, a pattern of the first embedded region PBL1 located in the isolation region and a pattern of the second embedded region PBL2 located on the low-voltage side of the transistor region are defined. Here, the first embedded region PBL1 surrounds the periphery of the transistor region and is connected to the second embedded region PBL2. Thereafter, a second-dopant-type ion implantation process (for example, a P-type ion implantation process) is performed under the mask of the mask layer 520, so that the first embedded region PBL1 and the second embedded region PBL2 can be formed in the base 110P. In this embodiment, since a pattern of the fifth embedded region PBL3 located in the transistor region is also defined in the mask layer 520, when the second-dopant-type ion implantation process (for example, a P-type ion implantation process) is performed, the fifth embedded region PBL3 can be simultaneously formed in the transistor region.

[0068] In a specific example, the first embedded region PBL1, the second embedded region PBL2, and the fifth embedded region PBL3 may be boron-doped, the implantation energy thereof is, for example, 20 Kev to 100 Kev, and the ion doping concentration thereof is, for example, 6E10 cm -3 ~6E14 cm -3 -3.

[0069] Next, referring to FIG. 8, an epitaxial layer 120N is epitaxially formed on the base 110P. In the process of epitaxially forming the epitaxial layer 120N, ions in the first embedded region PBL1, the second embedded region PBL2, the third embedded region NBL1, the fourth embedded region NBL2, and the fifth embedded region PBL3 can be diffused upward from the base 110P into the epitaxial layer 120N. Here, the epitaxial layer 120N is specifically an epitaxial layer of the first dopant type, the thickness thereof is, for example, 4 μm to 9 μm, and the epitaxial layer 120N is, for example, phosphorus-doped, and the doping concentration thereof is, for example, 1E14 cm -3 ~1.6E16 cm -3 -3.

[0070] Subsequently, referring to FIG. 9, a mask layer 530 is formed on the epitaxial layer 120N. A pattern of a third well region is defined in the mask layer 530, and an ion implantation process of a first doping type (for example, an N-type ion implantation process) is performed under the mask of the mask layer 530, so that a third well region NW1 can be formed in the epitaxial layer 120N. In this embodiment, since a pattern of a fourth well region NW2 located in the region of the high-voltage side circuit is also defined in the mask layer 530, by performing an ion implantation process of the first doping type (for example, an N-type ion implantation process), the fourth well region NW2 can be simultaneously formed in the region of the high-voltage side circuit. In a further solution, since the mask layer 530 also defines a pattern of an inverted doping region in the isolation region, by performing an ion implantation process of the first doping type (for example, an N-type ion implantation process), an inverted doping region (that is, an adjustment region 300 shown in FIG. 9) can be simultaneously formed in the isolation region. Here, the doping depth of the inverted doping region may be close to or the same as the depth of the third well region NW1. Then, the mask layer 530 may be removed.

[0071] Subsequently, referring to FIG. 10, a mask layer 540 is formed on the epitaxial layer 120N. Patterns of a first deep well region DPW1 and a second deep well region DPW2 are defined in the mask layer 540. Here, the first deep well region DPW1 surrounds the periphery of the transistor region and is connected to the second deep well region DPW2. Then, an ion implantation process of a second doping type (for example, a P-type ion implantation process) is performed under the mask of the mask layer 540, so that the first deep well region DPW1 and the second deep well region DPW2 can be formed in the epitaxial layer 120N. Here, the bottom of the first deep well region DPW1 is connected to a first buried region PBL1 below it, and the bottom of the second deep well region DPW2 is connected to a second buried region PBL2 below it.

[0072] Next, referring to FIG. 11, a first isolation oxide layer 400 is formed on the surface of the epitaxial layer 120N. The first isolation oxide layer 400 is formed above the isolation doped region and is used to enhance the isolation performance of the isolation region. Here, the first isolation oxide layer 400 may be formed, for example, by a selective oxidation isolation process (Local Oxidation of Silicon, LOCOS). Specifically, a mask layer 550 is formed on the epitaxial layer 120N, and then an oxidation process is performed to form the first isolation oxide layer 400, and thereafter, the mask layer 550 may be removed. In this embodiment, when the first isolation oxide layer 400 is formed, a field oxide layer 220 and a second isolation oxide layer 210 are also formed.

[0073] Next, referring to FIG. 12, a mask layer 560 is formed on the epitaxial layer 120N. Patterns of a first shallow well region PW1 and a second shallow well region PW2 are defined in the mask layer 560. Here, the first shallow well region PW1 surrounds the periphery of the transistor region and is connected to the second shallow well region PW2. Thereafter, a second-doped type ion implantation process (for example, a P-type ion implantation process) is performed under the mask of the mask layer 560 to form the first shallow well region PW1 and the second shallow well region PW2 in the epitaxial layer 120N. Also, the bottom of the first shallow well region PW1 is connected to the first deep well region DPW1 therebelow, the first shallow well region PW1 further surrounds the inverted doped region, and the bottom of the second shallow well region PW2 is connected to the second deep well region DPW2 therebelow. In this way, an isolation ring can be formed in the isolation region around the transistor region, and the second shallow well region PW2 is further used to form the body region of the inversion channel of the field effect transistor.

[0074] Next, referring to FIG. 13, an oxidation process is performed to form a gate oxide layer on the epitaxial layer 120N. Thereafter, a gate structure 200G that covers a part of the second shallow well region PW2 is formed on the epitaxial layer 120N. In this embodiment, the gate structure 200G further extends to cover the field oxide layer 220 to form a field plate structure, thereby improving the breakdown voltage performance of the device.

[0075] In a further solution, a sidewall all (not shown) can also be formed on the sidewall of the gate structure 200G. Specifically, the manufacturing method of the sidewall all includes depositing a sidewall all material that covers the upper surface and the sidewall of the gate structure 200G and covers the substrate surface other than the gate structure, and then performing an etch-back process to remove the sidewall all material on the upper surface of the gate structure and the sidewall all material on the upper surface of the substrate, and retaining the sidewall all material on the sidewall of the gate structure 200G to form the sidewall all.

[0076] Next, referring to FIG. 14, a first doping type ion implantation process (for example, an N-type ion implantation process) is performed to form a source region 200S formed in the second shallow well region PW2 and a drain region 200D formed in the third well region NW1. In this embodiment, in this step, a second contact region of the first doping type can also be simultaneously formed in the fourth well region NW2.

[0077] Continuing to refer to FIG. 14, a second doping type ion implantation process (for example, a P-type ion implantation process) is performed to form a first contact region 200B formed in the second shallow well region PW2, and the ion doping concentration of the first contact region 200B is higher than the ion doping concentration of the second shallow well region PW2.

[0078] Figures 6 to 14 schematically show a method of forming an inverted doped region of a first doping type in a separated doped region by an ion implantation process. In the above example, the formation of the inverted doped region by the ion implantation process is prioritized, and further doping is performed to form the separated doped region. However, in other examples, the formation of the separated doped region may be prioritized, and the inverted doped region may be formed by implantation. In addition, a method of forming an undoped region in the separated doped region will be described below with reference to FIGS. 15 and 16 by way of example.

[0079] Specifically, referring to FIG. 15, a mask layer 570 is formed on a substrate 100. The mask layer 570 is provided with a shielding pattern in a part of the separation region such that a part of the separation region is shielded and the other part is exposed. Further, an ion implantation process of a second doping type is performed under the mask of the mask layer 570 to form a first deep well region DPW1. At this time, ions are not implanted into the shielded part of the separation region, and an undoped region is formed. Then, the mask layer 570 may be removed.

[0080] Subsequently, referring to FIG. 16, a mask layer 580 is formed on the substrate 100. Similarly, the mask layer 580 is provided with a shielding pattern in a part of the separation region such that a part of the separation region is shielded and the other part is exposed. An ion implantation process of a second doping type is performed under the mask of the mask layer 580 to form a first shallow well region PW1. At this time, ions are not implanted into the shielded part of the separation region, and an undoped region is formed. In this embodiment, the first deep well region DPW1 and the first shallow well region PW1 are arranged vertically aligned, and the undoped regions in the first deep well region DPW1 and the first shallow well region PW1 may be arranged aligned to form an undoped region. Then, the mask layer 580 may be removed.

[0081] That is, in the examples shown in FIGS. 15 to 16, the undoped region is formed in the first shallow well region PW1 and the first deep well region DPW1. However, in other examples, it may be formed only in the first shallow well region PW1.

[0082] It should be noted that in the method for manufacturing a semiconductor device shown in FIGS. 6 to 14 and FIGS. 15 to 16, specifically, it includes a manufacturing process of a level shifter and a manufacturing process of a high-voltage side circuit. However, in other examples, when manufacturing a semiconductor device, regarding the manufacturing process of the level shifter, as long as the structure of the level shifter as described above can be manufactured, it is not limited to the above method (that is, it does not have to be formed by adopting the above method), and based on this, the manufacturing processes of other circuits (for example, high-voltage side circuits) are combined. That is, in other examples, the method for manufacturing a semiconductor device includes manufacturing the semiconductor device by processing on the substrate of the level shifter as described above, which still belongs to the protection scope of the technical solution of the present invention.

[0083] It should be noted that each embodiment in this specification is described step by step. The description of each embodiment focuses on the different parts from other embodiments. For the same or similar parts between each embodiment, reference may be made to each other. A person skilled in the art can make a very large number of possible changes and modifications to the technical solution of the present invention or modify it into equivalent embodiments with equivalent changes without departing from the scope of the technical solution of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention all still belong to the protection scope of the technical solution of the present invention.

[0084] Unless otherwise specified or noted, the descriptions in the specification using terms such as "first", "second", "third", etc. are merely for distinguishing each component, element, step, etc. in the specification, and it should also be understood that they do not indicate the logical relationship or order relationship, etc. between each component, element, step. Also, it should be recognized that the singular forms "one" and "a" used herein and in the appended claims include plural referents unless the context clearly dictates otherwise. For example, a description that refers to "one step" or "one device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices.

Description of Reference Numerals

[0085] 100 Substrate 110P Base 120N Epitaxial Layer 200 Field-Effect Transistor 200S Source Region 200D Drain Region 200G Gate Structure 200B First Contact Region 210 Second Isolation Oxide Layer 220 Field Oxide Layer 300 Adjustment Region 310 Isolation Structure 400 First Isolation Oxide Layer 510 / 520 / 530 / 540 / 550 / 560 / 570 / 580 Mask Layer PBL1 First Implanted Region PBL2 Second Implanted Region NBL1 Third Implanted Region NBL2 Fourth Implanted Region PBL3 Fifth Implanted Region DPW1 First Deep Well Region DPW2 Second Deep Well Region PW1 First Shallow Well Region PW2 Second Shallow Well Region NW1 Third Well Region NW2 Fourth Well Region

Claims

1. A substrate; a field effect transistor including a drain region of a first doping type and a source region of a first doping type formed in the substrate, and a gate structure formed on the substrate and positioned between the source region and the drain region; and at least one isolated doped region of a second doping type extending around the periphery of the field effect transistor, wherein undoped and / or inverted doped regions are formed within the at least one isolated doped region.

2. 2. The level shifter according to claim 1, wherein the undoped region is a region of the isolated doped region that is not implanted with ions in an ion implantation process.

3. 2. The level shifter of claim 1, wherein the undoped region comprises a recess formed in the isolated doped region.

4. 4. The level shifter of claim 3, wherein the undoped region further comprises an undoped material filled in the groove.

5. 2. The level shifter according to claim 1, wherein the inverse doped region is a region formed by implanting ions of a first doping type through an ion implantation process, or the inverse doped region includes a groove formed in the isolated doped region and a material of the first doping type filled in the groove.

6. 2. A level shifter as claimed in claim 1, characterized in that the undoped region extends continuously along the isolated doped region and / or the inversely doped region is of a first doping type and extends continuously along the isolated doped region.

7. At least two undoped regions are provided within the separate doped region, the undoped regions being arranged in sequence from closer to the field effect transistor, or At least two inversion doped regions are provided within the isolated doped region, arranged sequentially from closer to the field effect transistor, or 7. The level shifter according to claim 6, wherein the isolated doped region includes at least one inversion doped region and at least one undoped region arranged in sequence from closer to the field effect transistor.

8. 2. The level shifter according to claim 1, further comprising a plurality of undoped regions and / or a plurality of inversion doped regions arranged in sequence within the isolated doped region along an extension direction of the isolated doped region.

9. The level shifter according to claim 8 , wherein the arrangement of the plurality of undoped regions and / or the plurality of inversion doped regions in the isolated doped region includes an arrangement in which the undoped regions and / or the inversion doped regions are arranged at intervals in an array arrangement.

10. the substrate includes a base of a second doping type and an epitaxial layer of a first doping type, the field effect transistor being formed in the epitaxial layer; 2. The level shifter of claim 1, wherein the level shifter includes at least two of the isolated doped regions arranged in sequence from bottom to top and connected to each other, the lowest isolated doped region of which extends upward from the base into the epitaxial layer.

11. the at least two isolated doped regions include a first shallow well region of a second doping type extending inwardly into the epitaxial layer from a top surface of the epitaxial layer; and 11. The level shifter of claim 10, further comprising a second shallow well region of a second doping type extending inwardly from an upper surface of the epitaxial layer into the epitaxial layer, the second shallow well region being located on a side of the gate structure closer to a source region, the source region being formed in the second shallow well region, and the first shallow well region extending from outside the drain region to surround the field effect transistor and connect to the second shallow well region.

12. The at least two separated doped regions further include a first deep well region of a second doping type and a first buried region of a second doping type, which are located below the first shallow well region and connected in sequence from top to bottom; and 12. The level shifter of claim 11, further comprising a second deep well region of a second doping type and a second buried region of a second doping type, which are located below the second shallow well region and connected sequentially from top to bottom, the first deep well region extending from outside the drain region to surround the field effect transistor and connected to the second deep well region, and the first buried region extending from outside the drain region to surround the field effect transistor and connected to the second buried region.

13. the inversion doped region is formed only in the first shallow well region, or extends downward from the first shallow well region into the first deep well region, or extends downward from the first shallow well region sequentially into the first deep well region and the first buried region; and 13. The level shifter of claim 12, wherein the undoped region is formed only in the first shallow well region, or extends downward from the first shallow well region into the first deep well region, or extends downward from the first shallow well region sequentially into the first deep well region and the first buried region.

14. 2. The level shifter of claim 1, further comprising a third well region of a first doping type, the third well region being located on a side of the gate structure proximate to a drain region, the drain region being formed within the third well region.

15. 15. The level shifter of claim 14, further comprising a third buried region of the first doping type, said third buried region being disposed below said third well region.

16. 16. The level shifter of claim 15, wherein the third buried region is a continuously extending doped region or comprises a plurality of spaced apart doped regions.

17. 17. A semiconductor device comprising a level shifter according to any one of claims 1 to 16 and a high-side circuit located on a side remote from the field effect transistor of the isolated doped region.

18. 20. The semiconductor device of claim 17, wherein the high side circuit includes a fourth well region of a first doping type and a fourth buried region, the fourth buried region below the fourth well region and extending upwardly from the base into the epitaxial layer.

19. the level shifter further includes a third well region of a first doping type and a third buried region of a first doping type, the third well region being located on a side of a gate structure proximate to a drain region, the drain region being formed within the third well region, the third buried region being disposed below the third well region, and 20. The semiconductor device of claim 18, wherein a spatial overlap area between the third buried region and the third well region is smaller than a spatial overlap area between the fourth buried region and the fourth well region.

20. forming a field effect transistor on a substrate, the field effect transistor including a drain region of a first doping type, a source region of a first doping type, and a gate structure, the drain region and the source region being formed in the substrate, the gate structure being formed on the substrate and located between the source region and the drain region; and 2. A method for manufacturing a level shifter, comprising the further step of forming at least one isolated doped region of a second doping type around the field effect transistor, wherein undoped regions and / or inversion doped regions are further formed within the at least one isolated doped region.

21. The method for producing at least one of the isolated doped regions comprises the steps of: forming a mask layer on the substrate that completely exposes an isolation region; performing an ion implantation process of a second doping type to form at least one isolated doped region; 21. The method of claim 20, further comprising the step of: etching a portion of at least the top-layer isolation doped region to form a recessed groove in at least the top-layer isolation doped region.

22. 22. The method for manufacturing a level shifter according to claim 21, further comprising, after forming the groove, filling the groove with an undoped material to form the undoped region, or filling the groove with a material of a first doping type to form the reverse doped region.

23. The method for producing at least one of the isolated doped regions comprises the steps of: forming a mask layer on the substrate, the mask layer having a shielding pattern formed on a portion of the isolation region such that a portion of the isolation region is shielded and another portion is exposed; 21. The method of claim 20, further comprising: performing an ion implantation process of a second doping type to form an isolated doped region, the ions being not implanted in a shielded portion of the isolated region to form the undoped region.

24. 21. A method for manufacturing a level shifter according to claim 20, characterized in that the undoped region extends continuously along the isolated doped region and / or the inverse doped region is of a first doping type and extends continuously along the isolated doped region.

25. At least two undoped regions are formed in the isolated doped region and are arranged in sequence from a closer region to a farther region from the field effect transistor; or At least two inversion doped regions are formed within the isolated doped region and arranged in sequence from the closest to the field effect transistor to the furthest from the field effect transistor, or 25. The method of claim 24, wherein at least one inversion doped region and at least one undoped region are formed in the isolated doped region, the inversion doped region and the undoped region being sequentially arranged from closer to the field effect transistor.

26. 21. The method for manufacturing a level shifter according to claim 20, characterized in that a plurality of undoped regions and / or a plurality of inversion doped regions are formed within the isolated doped region, and the plurality of undoped regions and / or a plurality of inversion doped regions are sequentially arranged within the isolated doped region along the extension direction of the isolated doped region.

27. 27. The method of claim 26, wherein the arrangement of the plurality of undoped regions and / or the plurality of inversion doped regions in the isolated doped region includes an arrangement at intervals called an array arrangement.

28. 21. The method of claim 20, wherein the method of forming the inverse doped region comprises the step of implanting ions of a first doping type by an ion implantation process to form the inverse doped region.

29. At least one method of fabricating the isolated doped region includes performing an ion implantation process of a second doping type to form a first shallow well region; and 21. The method for manufacturing a level shifter according to claim 20, further comprising the step of forming a second shallow well region by implantation during the ion implantation process, the second shallow well region being located on a side closer to the source region of the gate structure, the source region being formed within the second shallow well region, and the first shallow well region extending from outside the drain region to surround the field effect transistor and connected to the second shallow well region.

30. The substrate includes a base of a second doping type and an epitaxial layer of a first doping type, which are disposed in this order from bottom to top, and the method for producing at least one of the isolated doped regions includes: performing an ion implantation process of a second doping type on the base prior to forming the epitaxial layer to form a first buried region of a second doping type in the base; 21. The method for manufacturing a level shifter according to claim 20, further comprising the steps of: performing an epitaxial process to form the epitaxial layer on the base, in which ions of the first buried region diffuse upward into the epitaxial layer; and performing two second doping type ion implantation processes on the epitaxial layer sequentially to form a first deep well region and a first shallow well region, in which a bottom of the first deep well region is connected to the first buried region and a bottom of the first shallow well region is connected to the first deep well region.

31. When the first buried region is manufactured, a second buried region is further formed on the low-voltage side of the transistor region, and the first buried region extends from the high-voltage side of the transistor region to surround the transistor region and to the low-voltage side of the transistor region and is connected to the second buried region; When fabricating the first deep well region, a second deep well region is further formed on the low voltage side of the transistor region, the first deep well region extends from the high voltage side of the transistor region to surround the transistor region and to the low voltage side of the transistor region and is connected to the second deep well region; and 31. The method for manufacturing a level shifter according to claim 30, wherein when the first shallow well region is manufactured, a second shallow well region is further formed on the low voltage side of the transistor region, and the first shallow well region extends from the high voltage side of the transistor region to surround the transistor region and to the low voltage side of the transistor region, and is connected to the second shallow well region.

32. Before forming the epitaxial layer, the method further includes the step of performing an ion implantation process of a first doping type on the base to form a third buried region of a first doping type in the base, the third buried region being located in a drain end region of the level shifter; and 31. The method of claim 30, wherein ions of the third buried region diffuse upward into the epitaxial layer during the step of performing an epitaxial process to form the epitaxial layer on the base.

33. The method includes the steps of a method for manufacturing a level shifter according to any one of claims 20 to 32, A method for manufacturing a semiconductor device, comprising the step of manufacturing the semiconductor device by processing the level shifter according to any one of claims 1 to 16 on a substrate.

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