Method and apparatus for non-contact inspection of substrates

Abstract

A device (201) for inspecting a conductive pattern (202) on a substrate (200) includes a plurality of sensor plates (204), a table configured and arranged to support the substrate, a voltage source (208) configured to generate an electric field between the sensor plate and the conductive pattern on the substrate, an actuator (206) configured to move the sensor plate relative to the substrate, and a controller (210) configured and arranged to identify areas having defects based on changes in capacitance between the sensor plate and the substrate as the sensor plate moves relative to the substrate.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to European Patent Application No. 22190849.4, filed August 17, 2022, the entire contents of which are incorporated herein by reference.

[0002] This description relates generally to systems and methods for inspecting structures on a substrate. More particularly, this description relates to using an electric field to identify areas where defects may be present. [Background technology]

[0003] Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). A patterning device (e.g., a mask) can contain or provide a device pattern (a "design layout") corresponding to an individual layer of the IC. This pattern can be transferred onto a target portion (e.g., one or more dies) on a substrate (e.g., a silicon wafer) that is coated with a layer of radiation-sensitive material (resist), e.g., by irradiating the target portion with the patterning device pattern. Typically, a single substrate contains several adjacent target portions, onto which the lithographic apparatus successively transfers the pattern, one target portion at a time. In one type of lithographic apparatus, the pattern of the entire patterning device is transferred onto one target portion at a time; such an apparatus is commonly referred to as a stepper. In another type of apparatus, commonly referred to as a step-and-scan apparatus, a projection beam scans over the patterning device in a given reference direction (the "scan" direction) while the substrate is moved parallel or anti-parallel to this direction. Different portions of the patterning device pattern are gradually transferred onto one target portion. In general, the lithographic apparatus will have a magnification factor M (generally <1), so the speed F at which the substrate moves will be a factor M times faster than the speed at which the projection beam scans the patterning device.

[0004] Before transferring the pattern from the patterning device to the substrate, the substrate may undergo various procedures, such as priming, resist coating, and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake, and measurement / inspection of the transferred pattern. This sequence of procedures is used as a basis for fabricating individual layers of a device, such as an IC. The substrate may then undergo various processes, such as etching, ion implantation (doping), metallization, oxidation, and chemical-mechanical polishing, all to complete the individual layers of the device. If several layers are required for a device, the entire procedure, or a variation thereof, is repeated for each layer. Eventually, devices will be present in each target portion on the substrate. The devices are then separated from each other by techniques such as dicing or sawing, so that the individual devices can be attached to a carrier or connected to pins.

[0005]

[0005] Thus, fabricating devices such as semiconductor devices typically involves processing a substrate (e.g., a semiconductor wafer) using a number of fabrication processes to form various features and multiple layers of the device. Such layers and features are typically fabricated and processed using deposition, lithography, etching, chemical-mechanical polishing, and ion implantation. Multiple devices are fabricated on multiple dies on the substrate, which may then be separated into individual devices. This device fabrication process can be considered a patterning process. The patterning process includes a patterning step in which a pattern in the patterning device is transferred to the substrate by optical lithography and / or nanoimprint lithography using a patterning device in a lithography apparatus, and typically further includes one or more associated pattern processing steps, such as (optionally) developing the resist in a developer, baking the substrate using a bake tool, etching using an etcher, ...

[0006] These manufacturing processes are subject to a variety of errors at any one of several steps. As a result, it is useful to be able to inspect the structures after fabrication to determine whether there are any defects that may affect the operation of the finished product. Such inspections may occur at any of several steps within the process. A method for characterizing defects prior to the final electrical test stage may help reduce the cycle time between identifying a problem and making appropriate corrections to the processing steps. Summary of the Invention

[0007]

[0007] In one embodiment, a device for inspecting a conductive pattern on a substrate includes a plurality of sensor plates, a table configured and arranged to support the substrate, a voltage source configured to generate an electric field between the sensor plates and the conductive pattern on the substrate, an actuator configured to move the sensor plate relative to the substrate, and a controller configured and arranged to identify areas having defects based on a change in capacitance between the sensor plate and the substrate as the sensor plate moves relative to the substrate.

[0008]

[0008] In one embodiment, a method for inspecting a conductive pattern on a substrate includes applying a voltage to a plurality of sensor plates and applying an opposite voltage to the conductive pattern to generate an electric field between the plurality of sensor plates and the conductive pattern, scanning the plurality of sensor plates relative to the substrate, measuring a change in capacitance between the sensor plates and the substrate during the relative scanning, and identifying areas of the conductive pattern having defects based on the measured change in capacitance.

[0009]

[0009] In one embodiment, there is provided a computer system including a processor and memory, the computer system including a non-transitory machine-readable medium containing instructions for performing the above-described method.

[0010] In one embodiment, a computer program product is provided that includes a non-transitory computer-readable medium having instructions recorded thereon that, when executed by a computer, perform the method described above. [Brief explanation of the drawings]

[0011] [Figure 1]

[0011] A schematic diagram of a lithographic apparatus is shown. [Figure 2]

[0012] 1 illustrates an embodiment of a lithography cell or cluster. [Figure 3a]

[0013] 1 illustrates a prior art design / inspect / make cycle for lithographic manufacturing of a device. [Figure 3b] 1 illustrates an alternative design / test / manufacture cycle according to one embodiment. [Figure 4]

[0014] 1 is a schematic diagram of an embodiment of a testing device according to one embodiment. [Figure 5]

[0015] FIG. 2 is a diagram of a scan pattern for an array of sensors according to one embodiment. [Figure 6]

[0016] 1 is a flowchart illustrating a process according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012]

[0017] Figure 1 schematically depicts a lithographic apparatus LA in which the techniques described herein can be employed. The lithographic apparatus includes an illumination optical system (illuminator) IL configured to condition a radiation beam B (e.g., ultraviolet or DUV radiation), a patterning device support or support structure (e.g., mask table) MT constructed to support a patterning device (e.g., mask) MA and coupled to a first positioner PM configured to accurately position the patterning device according to particular parameters, one or more substrate tables (e.g., wafer tables) WTa, WTb constructed to hold a substrate (e.g., a resist-coated wafer) W and coupled to a second positioner PW configured to accurately position the substrate according to particular parameters, and a projection optical system (e.g., a refractive, reflective, or catadioptric optical system) PS configured to project a pattern imparted to the radiation beam B by the patterning device MA onto a target portion C (e.g., comprising one or more dies) of the substrate W.

[0013]

[0018] The illumination optical system may include various types of optical components, such as refractive, reflective, magnetic, electromagnetic, electrostatic or other types of optical components, or any combination thereof, to direct, shape or control the radiation. In this particular case, the illumination system also includes a radiation source SO.

[0014]

[0019] The patterning device support holds the patterning device in a manner that depends on the orientation of the patterning device, the design of the lithographic apparatus, and other conditions, such as whether or not the patterning device is held in a vacuum environment. The patterning device support may use mechanical, vacuum, electrostatic or other clamping techniques to hold the patterning device. The patterning device support may, for example, be a frame or a table, which may be fixed or movable as required. The patterning device support may ensure that the patterning device is at a desired position, for example with respect to the projection system. Any use of the terms "reticle" or "mask" herein may be considered as synonymous with the more general term "patterning device".

[0015]

[0020] The term "patterning device", as used herein, should be interpreted broadly to refer to any device that can be used to impart a radiation beam with a pattern in its cross-section so as to create a pattern in a target portion of a substrate. It should be noted that the pattern imparted to the radiation beam may not exactly correspond to the desired pattern in the target portion of the substrate, for example if the pattern includes phase-shifting features or so-called assist features. Typically, the pattern imparted to the radiation beam will correspond to a particular functional layer in a device being created in the target portion, such as an integrated circuit.

[0016]

[0021] A patterning device may be transmissive or reflective. Examples of patterning devices include masks, programmable mirror arrays, and programmable LCD panels. Masks are well known in lithography, and include mask types such as binary, alternating phase-shift, and attenuated phase-shift, as well as various hybrid mask types. An example of a programmable mirror array employs a matrix arrangement of small mirrors, each of which can be individually tilted so as to reflect an incoming radiation beam in different directions. The tilted mirrors impart a pattern to the radiation beam that is reflected by the mirror matrix.

[0017]

[0022] As depicted herein, the lithographic apparatus is of a transmissive type (e.g. employing a transmissive patterning device). However, the lithographic apparatus may also be of a reflective type (e.g. employing a programmable mirror array as referred to above, or employing a reflective mask). Lithographic apparatus may also employ other types of patterning device than a conventional mask; examples include a programmable mirror array or an LCD matrix.

[0018]

[0023] The lithographic apparatus may be of a type in which at least a portion of the substrate is covered by a liquid having a relatively high refractive index, e.g., water, so as to fill a space between the projection system and the substrate. Immersion liquid may also be applied to other spaces in the lithographic apparatus, for example, between the mask and the projection system. Immersion techniques are well known in the art for increasing the numerical aperture of projection systems. As used herein, the term "immersion" does not imply that a structure such as a substrate must be submerged in liquid, but simply that a liquid is present between the projection system and the substrate during exposure.

[0019]

[0024] Referring to Figure 1, the illuminator IL receives radiation from a radiation source SO (e.g. a mercury lamp or excimer laser, an LPP (laser produced plasma) EUV source). The source and the lithographic apparatus may be separate entities, for example if the source is an excimer laser. In such cases, the source is not considered to form part of the lithographic apparatus and radiation is delivered from the source SO to the illuminator IL using a beam delivery system BD, which may comprise, for example, suitable directing mirrors and / or beam expanders. In other cases, the source may be an integral part of the lithographic apparatus, for example when the source is a mercury lamp. The source SO and the illuminator IL, together with the beam delivery system BD if required, may be referred to as a radiation system.

[0020]

[0025] The illuminator IL may include an adjuster AD for adjusting the spatial and / or angular intensity distribution of the radiation beam. Generally, at least the outer and / or inner radial extent (commonly referred to as σ-outer and σ-inner, respectively) of the intensity distribution in a pupil plane of the illuminator may be adjusted. In addition, the illuminator IL may include various other components, such as an integrator IN and a condenser CO. The illuminator can be used to condition the radiation beam so that it has a desired uniformity and intensity distribution in its cross-section.

[0021]

[0026] The radiation beam B is incident on a patterning device (e.g., mask) MA, which is held on a patterning device support (e.g., mask table) MT, and is patterned by the patterning device. After passing through the patterning device (e.g., mask) MA, the radiation beam B passes through a projection optical system PS, which focuses the beam onto a target portion C of a substrate W, thereby projecting an image of the pattern onto the target portion C. The substrate table WT can be accurately moved using a second positioner PW and a position sensor IF (e.g., an interferometric device, a linear encoder, or a capacitive sensor), for example, to position different target portions C in the path of the radiation beam B. Similarly, the first positioner PM and another position sensor (not explicitly shown in Figure 1) can be used to accurately position the patterning device (e.g., mask) MA with respect to the path of the radiation beam B, for example after mechanical retrieval from a mask library or during a scan.

[0022]

[0027] The patterning device (e.g., mask) MA and substrate W may be aligned using patterning device alignment marks M1 and M2 and substrate alignment marks P1 and P2. Although the substrate alignment marks as illustrated occupy dedicated target portions, the substrate alignment marks may be located in spaces between the target portions (these are known as scribe-lane alignment marks). Similarly, in situations in which more than one die is provided on the patterning device (e.g., mask) MA, the patterning device alignment marks may be located between the dies. Device features may also include small alignment marks within the dies; in such cases, it is desirable for the marker to be as small as possible and not require any different imaging or process conditions than adjacent features. Alignment systems for detecting alignment marks are described in more detail below.

[0023]

[0028] The lithographic apparatus LA in this example is a so-called dual-stage type having two substrate tables WTa, WTb and two stations, namely, an exposure station and a measurement station, and the substrate tables can be swapped between the exposure station and the measurement station. While one substrate on one substrate table is being exposed at the exposure station, another substrate can be loaded onto the other substrate table at the measurement station, and various preliminary steps can be performed. Preliminary steps can include mapping the surface of the substrate using a level sensor LS, measuring the position of an alignment mark on the substrate using an alignment sensor AS, or performing any other type of metrology or inspection. This can significantly increase the throughput of the apparatus. More generally, the lithographic apparatus can be of a type having two or more tables (e.g., two or more substrate tables, one substrate table and one measurement table, two or more patterning device tables, etc.). In such a "multi-stage" device, several of the multiple tables can be used in parallel, or preliminary steps can be performed on one or more tables while another table or tables are used for exposure. A twin stage lithographic apparatus is described, for example, in US Pat. No. 5,969,441, which is incorporated herein by reference in its entirety.

[0024]

[0029] Although the level sensor LS and alignment sensor AS are shown adjacent to the substrate table WTb, it will be appreciated that in addition to or instead, the level sensor LS and alignment sensor AS may be provided adjacent to the projection system PS and perform measurements relative to the substrate table WTa.

[0025]

[0030] The depicted apparatus can be used in various modes, including, for example, a step mode or a scan mode. The construction and operation of lithographic apparatus are well known to those skilled in the art and need not be described further for an understanding of embodiments of the present invention.

[0026]

[0031] As shown in FIG. 2, the lithography apparatus LA forms part of a lithography system called a lithography cell LC, lithocell, or cluster. The lithography cell LC may also include devices for performing pre-exposure and post-exposure processes on the substrate. Conventionally, these devices include a spin coater SC for depositing a resist layer, a developer DE for developing the exposed resist, a chill plate CH, and a bake plate BK. A substrate handler (or robot) RO retrieves substrates from input / output ports I / O1 and I / O2, moves them between different process tools, and then transfers them to the loading bay LB of the lithography apparatus. These devices, often collectively referred to as the track, are under the control of a track control unit TCU, which itself is controlled by a supervisory control system SCS, which also controls the lithography apparatus via a lithography control unit LACU. Thus, the various devices can be operated to maximize throughput and processing efficiency.

[0027]

[0032] The patterning device described above can include or form one or more design layouts or patterns (hereinafter referred to as "design patterns" for convenience). Design patterns can be generated using a CAD (computer-aided design) program, a process often referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules to produce functional design patterns / patterning devices. These rules are set by processing and design constraints. For example, design rules define the space tolerance between circuit devices (gates, capacitors, etc.) or interconnect lines to ensure that these circuit devices or lines do not interact with each other in an undesirable manner. One or more design rule constraints can be referred to as a "critical dimension (CD)." A critical dimension of a circuit can be defined as the smallest width of a line or hole, or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit. Of course, one of the goals of integrated circuit fabrication is to faithfully reproduce the original circuit design (via a patterning device) on a substrate.

[0028]

[0033] An illumination system provides illumination (i.e., radiation) to the patterning device in the form of an illumination mode, and a projection system directs and shapes this illumination through the patterning device onto the substrate as an aerial image (AI). The illumination mode defines illumination characteristics such as the angular or spatial intensity distribution (e.g., normal, dipole, annular, quadrupole, etc.) and the illumination sigma (σ) setting. The aerial image (AI) is the radiation intensity distribution at substrate level. A resist layer on the substrate is exposed, and the aerial image is transferred to the resist layer as a latent image, the "resist image" (RI). The resist image (RI) can be defined as the spatial distribution of resist solubility in the resist layer.

[0029]

[0034] A set of conditions for imaging can be considered, and of the total set of possible conditions, the process window of a pattern is the space under which the processing parameters for generating the pattern are such that satisfactory imaging of the pattern is achieved. That is, for a given pattern, there may be a set of values for depth of focus, illumination intensity, illumination pattern, numerical aperture, and other controllable variables that produce an image with sufficiently good imaging of lines or features, including linewidth, pitch, or other aspects of the imaged pattern, defined as meeting the required imaging specifications. The process window indicates the sensitivity of the process to variations in input parameters, such as radiation dose.

[0030]

[0035] Process parameters are parameters of the patterning process. The patterning process can include processes upstream and downstream of the actual lithographic transfer of the pattern. Process parameters can belong to a number of categories. The first category can be parameters of the lithographic apparatus or any other apparatus used in the patterning process. Examples of this category include parameters of the illumination system, projection system, substrate stage, etc. of the lithographic apparatus. The second category can be parameters of any step performed in the patterning process. Examples of this category can include focus, dose, bandwidth, exposure duration, development temperature, chemical composition used in development, etc. The third category can be parameters of the design pattern. Examples of this category can include optical proximity correction adjustments, such as resolution enhancement techniques (RET) or the shape and / or position of assist features. The fourth category can be parameters of the substrate. Examples of this can include features of structures beneath the resist layer, the chemical composition of the resist layer, and / or the physical dimensions of the resist layer. The fifth category can be parameters that characterize the temporal variation of one or more parameters of the patterning process. Examples of this category can include high frequency stage movement features (e.g., frequency, amplitude, etc.), high frequency laser bandwidth changes (e.g., frequency, amplitude, etc.), and / or high frequency laser wavelength changes. These high frequency changes or movements exceed the response time of the mechanisms for adjusting the underlying parameters (e.g., stage position, laser intensity, etc.). A sixth category can be features upstream or downstream of exposure, such as post-exposure bake (PEB), development, etching, deposition, resist coating, doping, and / or mounting.

[0031]

[0036] FIG. 3a illustrates a workflow 100 for a chip manufacturing process. In particular, FIG. 3a depicts the design / inspect / make cycle for a particular process or recipe. The lithography process 102, as described above, involves printing a pattern on a substrate. This process includes a metrology aspect 104 in that alignment sensors AS and level sensors LS (shown in FIG. 1) provide feedback to the imaging process. This metrology 104 can provide information back to an advanced process control (APC) module 106, which can adjust the recipe on the fly to improve imaging performance. Because the APC 106 can react during the printing of a batch of wafers or between batches, the cycle time for improving processing is on the order of minutes or less.

[0032]

[0037] Once the image is formed, a metrology tool performs an inspection step 108. For example, this may be an inspection after develop (AID) tool. One such tool is an optical metrology tool such as Yieldstar, which may be integrated into the lithography cluster. Feedback from this inspection step 108 to the APC 106 occurs on the order of minutes or hours.

[0033]

[0038] The developed image can then be etched 110 and subjected to another optical metrology step 112. As above, this optical metrology step 112 can be, for example, a YieldStar post-etch inspection. The feedback timeframe for this step is on the order of a few hours or a day.

[0034]

[0039] The next step inspection can be, for example, electron beam inspection 114. Because electron beam inspection is relatively time consuming, it may be applied only to certain critical areas of the wafer. Furthermore, electron beam inspection 114 is typically not integrated with APC 106, but rather feeds back into an overall fabrication monitoring system 116. This feedback process proceeds in a similar timeframe as the second optical metrology step 112, i.e., a few hours to a day.

[0035]

[0040] Next, the steps of fill 118 and chemical-mechanical processing 120 are performed. After this, inspection 122 using e-beam or similar techniques can be performed. Manufacturers would prefer to be able to identify electrical defects and characterize the transistors at this post-CMP stage, as this gives the manufacturer a relatively early indication of what the final yield will be. However, e-beam techniques are very time-consuming, and extensive e-beam testing at this stage is generally not acceptable in workflows. To maximize the impact on throughput, only low-density measurements are typically performed at this stage. The cycle time for this metrology step is on the order of days to weeks, but typically does not identify all electrical defects due to the requirement to only include low-density measurements.

[0036]

[0041] One or more metallization steps 124 are performed, after which a full electrical test (e-test) 126 can be performed. This test can completely identify electrical defects, but has the drawback of having a cycle length of several weeks. Finally, a yield test 128 is performed. As shown by the dotted lines in FIG. 3a, there may be additional intermediate steps between the steps shown. The yield test 128 has a cycle time on the order of several months. Of course, it would be useful to develop an inspection process that can identify electrical defects in cycle times shorter than weeks or months, and if such an inspection process had a higher throughput than electron beam inspection.

[0037]

[0042] FIG. 3b illustrates a workflow 150 for a chip manufacturing process similar to the workflow 100 of FIG. 3a, but including a novel inspection step. The lithography step 102 described above involves printing a pattern on a substrate. This step includes a metrology aspect 104, in that alignment sensors AS and level sensors LS (shown in FIG. 1) provide feedback to the imaging process. This metrology 104 can provide information back to an advanced process control (APC) module 106, which can adjust the recipe on the fly to improve imaging performance. Because the APC 106 can react during the printing of a batch of wafers or between batches, the cycle time for improving processing is on the order of minutes or less.

[0038]

[0043] Once the image is formed, a metrology tool performs an inspection step 108. For example, this may be an inspection after develop (AID) tool. One such tool is an optical metrology tool such as Yieldstar, which may be integrated into the lithography cluster. Feedback from this inspection step 108 to the APC 106 occurs on the order of minutes or hours.

[0039]

[0044] The developed image can then be etched 110 and subjected to another optical metrology step 112. As above, this optical metrology step 112 can be, for example, a YieldStar post-etch inspection. The feedback timeframe for this step is on the order of a few hours or a day.

[0040]

[0045] The next step inspection can be, for example, electron beam inspection 114. Because electron beam inspection is relatively time consuming, it may be applied only to certain critical areas of the wafer. Furthermore, electron beam inspection 114 is typically not integrated with APC 106, but rather feeds back into an overall fabrication monitoring system 116. This feedback process proceeds in a similar timeframe as the second optical metrology step 112, i.e., a few hours to a day.

[0041]

[0046] Next, the steps of filling 118 and chemical mechanical processing 120 are performed, after which electrical testing 152 is performed using the device according to one embodiment, which is described in more detail below.

[0042]

[0047] One or more metallization steps 124 are performed, after which a full electrical test (e-test) 126 can be performed. Finally, a yield test 128 is performed. There may be additional intermediate steps between the steps shown, as indicated by the dotted lines in Figure 3b. The yield test 128 has a cycle time on the order of several months.

[0043]

[0048] 4, a substrate 200 to be inspected using an apparatus 201 according to one embodiment includes an array of conductive features 202. This substrate 200 may be, for example, a wafer with several dies, a single die on a wafer, or a die diced from a wafer.

[0044]

[0049] Above the substrate 200 is an array of sensor plates 204. While in principle a single sensor plate could be used, as described more specifically below, the use of an array as shown in FIG. 4 allows for increased throughput in the inspection device. The substrate 200 is clamped to a fixed table (not shown). While a fixed table would suffice, the table need not be fixed; indeed, any system capable of scanning the sensor plates 204 and substrate 200 relative to one another can be used, including systems in which the substrate 200 is held on a movable stay. The sensor plates 204 are mechanically linked so that they can be actuated as a unit in the x, y, and z directions by actuators 206, so that all of the sensor plates move in unison in three axes. Embodiments may further include a six-degree-of-freedom actuator allowing rotation about three axes. The actuators 206 may be of any suitable type, such as, for example, a linear motor array. In one embodiment, the sensor plates 204 are mounted on a movable stage (not shown). The movable stage may also be operatively coupled to an interferometer or other device for determining the precise position of the movable stage as it is scanned over the substrate 200. The relative scanning may be stepwise, continuous, or a combination of stepwise and continuous relative motion.

[0045]

[0050] Additionally, in one embodiment, the individual plates may be tilted or moved relative to one another to account for wafer topography. This approach can include a topography measurement process, where the individual plates can be manipulated in up to six degrees of freedom to track height variations on the substrate surface.

[0046]

[0051] In use, the controller 210 receives the measurement signals and performs an appropriate comparison to identify the location of the defect. Alternately, the controller 210 can transmit the measured signals for remote processing to localize the defect.

[0047]

[0052] In one embodiment, the substrate includes a large number of conductive features 202, such as metallic vias, on its surface. The sensor plate 204 is a conductive plate that can receive a voltage via a voltage source 208. In one example, the smallest via dimension on the substrate is approximately 20 nm, with a typical pitch of approximately 40 nm in the x and y directions. The sensor plate dimensions can be, for example, approximately 40 μm by 40 μm. In this particular configuration, 1000 conductive features 202 will fit within the footprint of each sensor plate. In another embodiment, the area may be such that 100 vias will fit within the footprint of the sensor plate. Of course, if the entire wafer is to be inspected, the plate may be sized accordingly, or the scan time may be increased to ensure complete coverage.

[0048]

[0053] In operation, the sensor plate 204 and the substrate 200 are separated by an air gap, which may be, for example, less than about 100 μm. A voltage source supplies an opposite charge to the conductive features 202 as compared to the sensor plate, thereby creating a charge buildup in the features and the plate, respectively.

[0049]

[0054] The controller 210 may be further configured to control the actuation of the sensor plate 204. By actuating the sensor plate 204 in the z-direction, the distance between the sensor plate 204 and the substrate 200 can be maintained at less than 100 μm, which allows the electric fields from the conductive features 202 to interact with the plate 204 individually. The capacitance between the sensor plate and the substrate will capture the aligned positions of the metallic vias.

[0050]

[0055] If there are more or fewer conductive features (or if these features have an inaccurate area), the capacitance will differ from what is expected. In this regard, prior to measurement, the capacitance can be modeled to determine the expected capacitance value for each sensor plate. Deviation of the measured capacitance from the expected capacitance is a proxy for non-contact vias and can be an early indicator of wear. The voltage of the power supply can be DC with a magnitude of 1000V or less.

[0051]

[0056] In one embodiment, the controller maintains a constant voltage across the circuit, and deviations in measured current from expected current are taken as a proxy for non-contacting vias and therefore an early indication of yield.

[0052]

[0057] The use of an array of plates 204, each providing an independent capacitance measurement, allows for relatively rapid measurement of large areas. The sensor plates 204 can be scanned across the substrate 200 in the pattern shown in Figure 5. Each plate 204 has an extent in the y-direction equal to the extent of the substrate 200 in the y-direction divided by twice the number of plates. This means that within two strokes (one in the positive x-direction and one in the negative x-direction), the footprint of the sensor plate will completely cover the entire substrate.

[0053]

[0058] In one embodiment, the apparatus 201 may further include a vacuum chamber 212 to reduce the risk of breakdown due to voltage between the plate and the substrate. The vacuum chamber may include a load lock 214.

[0054]

[0059] In embodiments where the array of plates 204 includes gaps between plates, step-and-scan type inspection may be performed. As shown in FIG. 5, a typical plate starts at the starting zone 220 and scans across the substrate 200 in the x-direction until it reaches the first landing zone 222. After displacing its own width in the y-direction, the plate scans across the substrate 200 in the negative x-direction toward the second landing zone 224. That is, the plate moves in a first direction, then displaces in a second direction perpendicular to and coplanar with the first direction, and then moves in a third direction opposite the first direction, so that the entire area of the die to be inspected on the substrate is covered by the scans in the first and third directions. In embodiments where the plates are dimensioned as described above, two passes will completely scan the substrate 200. In principle, a single plate could cover the same area by multiple scans, at the expense of throughput.

[0055]

[0060] The capacitance of the sensor plate 204 is measured as a function of sensor plate position and compared by a controller or processor to an expected value. The expected value can be determined, for example, by modeling or by comparison to a reference die. If a reference die is used, it can be useful to perform multiple measurements and utilize an average value. These measurements can provide information about whether and where there are defects in the conductive features, such as misalignment, misplacement, improper formation (e.g., size), and / or poor connection of vias to a voltage source on the backside of the substrate 200.

[0056]

[0061] In one embodiment, the tool may include two sets of sensor plates 204. The first set of plates is larger than the second set of plates (not shown). The larger plates provide a coarse measurement in which specific areas of the substrate 202 may be identified as requiring further inspection. The smaller plates are then used to more precisely locate defects, i.e., localize defects within sub-regions of the identified areas. In this approach, the smaller plates may be one to two orders of magnitude smaller in area than the larger plates.

[0057]

[0062] The inspection method 300 is shown in the flowchart of FIG. 6. First, in step 302, a voltage is applied to multiple sensor plates and an opposite voltage is applied to the conductive pattern to generate an electric field between the sensor plates and the conductive pattern. Next, in step 304, the sensor plates are scanned relatively above the substrate while the voltage is maintained. During this scanning, changes in capacitance between the sensor plates and the conductive pattern are measured in step 306. This measurement may be continuous monitoring or may include sampling at selected timing or distance intervals. Finally, in step 308, areas of the conductive pattern having defects are identified based on the measured changes in capacitance.

[0058]

[0063] Embodiments may include a computer-readable medium programmed with instructions that, when executed, perform any of the methods described herein. Furthermore, aspects of the present application may take the form of a computer program product embodied in any one or more physical computer-readable media having computer-usable program code embodied therein.

[0059]

[0064] Any combination of one or more computer-readable media may be utilized. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable media may include: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (e.g., EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CDROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the context of this specification, a computer-readable storage medium may be any tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device.

[0060]

[0065] The computer program instructions may also be loaded into a computer, other programmable data processing apparatus, or other device to cause the computer, other programmable apparatus, or other device to perform a series of operational steps to create a computer-implemented process such that the instructions executing on the computer or other programmable apparatus provide a process for performing the functions / operations identified in one or more blocks in the flowcharts and / or block diagrams.

[0061]

[0066] A data processing system suitable for storing and / or executing program code will include at least one processor coupled directly or indirectly to memory elements via a system bus. The memory elements may include local memory employed during the actual execution of the program code, mass storage devices, and cache memory that provides temporary storage of at least some of the program code to reduce the number of times the code must be retrieved from mass storage devices during execution.

[0062]

[0067] Input / output devices, or I / O devices (including but not limited to keyboards, displays, pointing devices, etc.) may be coupled to the system either directly or through intervening I / O controllers. Network adapters may also be coupled to the system to enable the data processing system to couple to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems, and Ethernet cards are just a few of the network type adapters currently available.

[0063]

[0068] The description in this application has been presented for purposes of illustration and description and is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations will be apparent to those skilled in the art. The embodiments have been chosen and described in order to best explain the principles and practical applications of the invention and to enable those skilled in the art to understand the invention in a variety of embodiments with various modifications suitable for the particular uses intended.

[0064]

[0069] While specific reference is made herein to IC fabrication, it should be expressly understood that the description herein has many other possible applications, such as in the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid crystal display panels, thin film magnetic heads, etc. Those skilled in the art will appreciate that in such other applications, any references to "reticle," "wafer," or "die" as used herein may be considered interchangeable with the more general terms "mask," "substrate," or "target portion," respectively.

[0065]

[0070] As used herein, the terms "radiation" and "beam" are used to encompass all types of electromagnetic radiation, including ultraviolet radiation (e.g., having a wavelength of 365 nm, 248 nm, 193 nm, 157 nm, or 126 nm) or EUV (e.g., extreme ultraviolet radiation having a wavelength in the range of about 5 to 100 nm).

[0066]

[0071] Embodiments also include the following numbered clauses:

[0067]

[0072] Clause 1: An apparatus for inspecting conductive patterns on a substrate, comprising: at least one sensor plate; a table constructed and arranged to support a substrate; a voltage source configured to generate an electric field between the at least one sensor plate and a conductive pattern on the substrate; an actuator configured for relative movement between the at least one sensor plate and the substrate; a controller constructed and arranged to identify regions having defects based on a change in capacitance between the at least one sensor plate and the substrate during relative movement between the at least one sensor plate and the substrate; 1. An apparatus comprising:

[0068]

[0073] Clause 2: An apparatus as described in clause 1, wherein each sensor plate has an area greater than 100 times the area of a representative feature in the conductive pattern to be inspected.

[0069]

[0074] Clause 3: An apparatus described in either clause 1 or 2, further comprising at least one precision measurement sensor plate having an area smaller than the area of the at least one sensor plate, and the at least one precision measurement sensor plate is operable to identify sub-areas within each of the defect-containing areas, and to locate the defect in the sub-area based on a change in capacitance between the at least one precision measurement sensor plate and the substrate during relative movement between the at least one precision measurement sensor plate and the substrate.

[0070]

[0075] Clause 4: An apparatus described in any one of clauses 1 to 3, wherein the actuator is configured to move the sensor plate in a first direction relative to the substrate, displace the sensor plate in a second direction perpendicular to and coplanar with the first direction, and then move the sensor plate in a third direction opposite to the first direction relative to the substrate, so that scanning in the first and third directions covers the entire area of the die to be inspected on the substrate.

[0071]

[0076] Clause 5: An apparatus described in any one of clauses 1 to 4, wherein the apparatus is configured to measure capacitance substantially continuously during relative movement between the sensor plate and the substrate.

[0072]

[0077] Clause 6: An apparatus according to any one of clauses 1 to 5, wherein the table comprises a clamp constructed and arranged to hold the substrate during measurement.

[0073]

[0078] Clause 7: An apparatus described in any one of clauses 1 to 6, wherein the actuator enables relative movement between the plurality of sensor plates and the substrate in three mutually perpendicular dimensions.

[0074]

[0079] Clause 8: The apparatus of clause 7, wherein the actuator further enables relative rotation about three mutually perpendicular dimensions.

[0075]

[0080] Clause 9: An apparatus described in any one of clauses 1 to 8, wherein the at least one sensor plate includes a plurality of sensor plates, each sensor plate being held in a fixed relationship with each of the other sensor plates of the plurality of sensor plates.

[0076]

[0081] Clause 10: An apparatus according to any one of clauses 1 to 9, wherein the defective area is determined by comparing the measured capacitance with an expected capacitance.

[0077]

[0082] Clause 11: The apparatus of clause 10, wherein the expected capacitance is derived from measurements of a reference substrate or from a model.

[0078]

[0083] Clause 12: An apparatus according to any one of clauses 1 to 11, wherein the relative movement between at least one sensor plate and the substrate comprises moving in a continuous manner.

[0079]

[0084] Clause 13: An apparatus according to any one of clauses 1 to 11, wherein the relative movement between at least one sensor plate and the substrate comprises moving in a stepwise manner.

[0080]

[0085] Clause 14: An apparatus described in any one of clauses 1 to 11, wherein the relative movement between at least one sensor plate and the substrate includes movement in a combination of a stepwise manner and a continuous manner.

[0081]

[0086] Clause 15: A method for inspecting a conductive pattern on a substrate, comprising: applying a voltage to the plurality of sensor plates and an opposite voltage to the conductive pattern to generate an electric field between the plurality of sensor plates and the conductive pattern; scanning a plurality of sensor plates relative to a substrate; measuring a change in capacitance between the sensor plate and the substrate during the relative scan; identifying areas of the conductive pattern having defects based on the changes in measured capacitance; A method comprising:

[0082]

[0087] Clause 16: The method described in Clause 15, wherein relatively scanning the multiple sensor plates includes moving the sensor plates in a first direction relative to the substrate, displacing the sensor plates in a second direction perpendicular to and coplanar with the first direction, and then moving the sensor plates in a third direction opposite to the first direction relative to the substrate, so that scanning in the first and third directions covers the entire area of the die to be inspected on the substrate.

[0083]

[0088] Clause 17: The method of any one of clauses 15-16, wherein the capacitance is measured continuously during relative movement between the sensor plate and the substrate.

[0084]

[0089] Clause 18: The method of any one of clauses 15 to 17, wherein identifying areas of the conductive pattern having defects includes comparing changes in measured capacitance with respective expected capacitances.

[0085]

[0090] Clause 19: The method of clause 18, further comprising deriving the expected capacitance from measurements on a reference substrate.

[0086]

[0091] As used herein, terms such as "optimizing" and "optimization" represent or refer to adjusting a patterning apparatus (e.g., a lithography apparatus), a patterning process, etc., so that the result and / or process has more desirable characteristics, such as greater accuracy in the projection of a design pattern on a substrate, a larger process window, etc. Accordingly, as used herein, terms such as "optimizing" and "optimization" represent or refer to a process of identifying one or more values for one or more parameters that result in an improvement (e.g., a local optimum in at least one relevant metric compared to an original set of one or more values for those one or more parameters). "Optimum" and other related terms should be interpreted accordingly. In one embodiment, the optimization process may be applied iteratively to result in further improvement in one or more metrics.

[0087]

[0092] The above description is intended to be illustrative rather than limiting. Thus, it will be apparent to one skilled in the art that modifications may be made to the invention as described without departing from the scope of the claims set forth below.

Claims

1. 1. An apparatus for inspecting a conductive pattern on a substrate, comprising: at least one sensor plate; a table constructed and arranged to support the substrate; a voltage source configured to generate an electric field between the at least one sensor plate and the conductive pattern on the substrate; an actuator configured for relative movement between the at least one sensor plate and the substrate; a controller constructed and arranged to identify regions having defects based on a change in capacitance between the at least one sensor plate and the substrate during the relative movement between the at least one sensor plate and the substrate; and 1. An apparatus comprising:

2. 10. The apparatus of claim 1, wherein each sensor plate has an area that is greater than 100 times the area of a representative feature in the conductive pattern under test.

3. 2. The apparatus of claim 1, further comprising at least one precision measurement sensor plate having an area smaller than an area of the at least one sensor plate, the at least one precision measurement sensor plate operable to identify sub-areas within each of the defect-containing areas, and to locate the defect in the sub-areas based on a change in capacitance between the at least one precision measurement sensor plate and the substrate during the relative movement between the at least one precision measurement sensor plate and the substrate.

4. 2. The apparatus of claim 1, wherein the actuator is configured to move the sensor plate in a first direction relative to the substrate, displace the sensor plate in a second direction perpendicular to and coplanar with the first direction, and then move the sensor plate in a third direction opposite to the first direction relative to the substrate, such that scanning in the first and third directions covers an entire area of a die to be tested on the substrate.

5. The apparatus of claim 1 , wherein the apparatus is configured to measure the capacitance substantially continuously during relative movement between the sensor plate and the substrate.

6. The apparatus of claim 1 , wherein the table includes a clamp constructed and arranged to hold the substrate during measurement.

7. The apparatus of claim 1 , wherein the actuator enables relative movement between the plurality of sensor plates and the substrate in three mutually perpendicular dimensions.

8. The device of claim 7 , wherein the actuator further allows relative rotation about the three mutually perpendicular dimensions.

9. The apparatus of claim 1 , wherein the at least one sensor plate comprises a plurality of sensor plates, each sensor plate being held in a fixed relationship with each other sensor plate of the plurality of sensor plates.

10. The apparatus of claim 1 , wherein the defective area is determined by comparing the measured capacitance to an expected capacitance.

11. The apparatus of claim 10 , wherein the expected capacitance is derived from measurements of a reference substrate or from a model.

12. The apparatus of claim 1 , wherein the relative movement between the at least one sensor plate and the substrate comprises moving in a continuous manner.

13. The apparatus of claim 1 , wherein the relative movement between the at least one sensor plate and the substrate comprises moving in a stepwise manner.

14. The apparatus of claim 1 , wherein the relative movement between the at least one sensor plate and the substrate comprises moving in a combination of a stepwise manner and a continuous manner.

15. 1. A method for inspecting a conductive pattern on a substrate, comprising: applying a voltage to a plurality of sensor plates and an opposite voltage to the conductive pattern to generate an electric field between the plurality of sensor plates and the conductive pattern; scanning the plurality of sensor plates relative to the substrate; measuring a change in capacitance between the sensor plate and the substrate during the relative scanning; identifying areas of the conductive pattern having defects based on the changes in the measured capacitance; and A method comprising:

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