Method for etching features in a stack - Patents.com

Abstract

A method is provided for etching a feature in a stack comprising a silicon oxide layer beneath a mask. A substrate support for supporting the stack in an etching chamber is cooled to a temperature below 0° C. An etching gas is provided that includes a halogen-containing component and a phosphorus-containing component. A plasma is generated from the etching gas. A bias is provided to accelerate ions from the plasma into the stack. The feature is selectively etched in the stack relative to the mask.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS: This application claims the benefit of priority to U.S. Patent Application No. 63 / 406,183, filed September 13, 2022, which is incorporated herein by reference for all purposes. [Background technology]

[0002] FIELD OF THE DISCLOSURE The present disclosure relates to methods of forming semiconductor devices on semiconductor wafers, and more particularly to etching stacks in the formation of memory or other semiconductor devices.

[0003] In the formation of semiconductor devices, etching layers can be used to form memory holes or lines. Some semiconductor devices can be formed by etching a stack of bilayers of silicon oxide and silicon nitride (ONON). Such stacks can be used in memory applications such as forming dynamic random access memory (DRAM) and three-dimensional "negative AND" gates (3D NAND).

[0004] The background description provided herein is intended to generally present the contents of the present disclosure. The information described in this Background section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure. Summary of the Invention

[0005] To achieve the above, and in accordance with the objectives of the present disclosure, a method is provided for etching a feature in a stack comprising a silicon oxide layer beneath a mask. A substrate support for supporting the stack in an etching chamber is cooled to a temperature below 0° C. An etching gas is provided that includes a halogen-containing component and a phosphorus-containing component. A plasma is generated from the etching gas. A bias is provided to accelerate ions from the plasma into the stack. The feature is selectively etched in the stack relative to the mask.

[0006] In another aspect, an apparatus is provided for processing a stack on a substrate having at least one of a silicon oxide layer and a silicon nitride layer under a mask. An etching chamber is provided. A substrate support supports the substrate within the etching chamber. A temperature controller controls the temperature of the substrate support. An electrode supplies RF power within the etching chamber. An RF power source supplies RF power to the electrode. A gas source supplies an etching gas to the etching chamber, the gas source including a halogen-containing component source and an HF gas source.

[0007] These and other features of the present disclosure are described in more detail in the following detailed description taken in conjunction with the following figures. [Brief explanation of the drawings]

[0008] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which like reference numerals refer to similar elements and in which:

[0009] [Figure 1] FIG. 1 is a high-level flow chart of one embodiment.

[0010] [Figure 2A] FIG. 2A is a schematic cross-sectional view of a stack processed according to one embodiment. [Figure 2B] FIG. 2B is a schematic cross-sectional view of a stack processed according to one embodiment.

[0011] [Figure 3] FIG. 3 is a schematic diagram of an etching chamber that may be used in one embodiment.

[0012] [Figure 4] FIG. 4 is a schematic diagram of a computer system that can be used to practice one embodiment.

[0013] In the drawings, like reference numerals may be used to denote like structural elements. It should also be understood that the depictions in the figures are schematic and not to scale. DETAILED DESCRIPTION OF THE INVENTION

[0014] The present disclosure will be described in detail below with reference to several preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without some or all of these specific details. In other instances, well-known process steps and / or structures have not been described in detail in order to avoid unnecessarily obscuring the present disclosure.

[0015] Profile control presents a significant challenge in very high aspect ratio contact dielectric etching, specifically cryogenic etching of 3D NAND pillar structures, where large bow CDs and small bottom CDs exist. This is believed to be due to increased by-product accumulation near the etch front, which reduces the SiO2 reactive ion etching (RIE) rate. The most common method to increase etch rate (ER) for high aspect ratios is to increase ion energy and ion flux, which results in poor bow CD control (larger bow). Another common practice to increase bottom CD and ER is to modify plasma chemistry. This approach introduces other tradeoffs, such as bow expansion, capping, or excessive contact twist.

[0016] In some embodiments, etching of silicon oxide (SiO2, also known as SiO) and silicon nitride (Si3N4, also known as SiN) is improved by modifying the etch front. In some embodiments, a phosphorus (P)-containing precursor is added to the plasma. The P-containing precursor is believed to cause P-doping of the SiO2 and Si3N4 materials. Doped SiO2 materials have a reduced activation energy for RIE. Therefore, even low-energy ions from the plasma can contribute to etching. Phosphine (PH3) and phosphorus trifluoride (PF3) are two primary compounds that can be used as P-containing precursors in some embodiments. In some embodiments, other compounds, such as phosphorus trichloride (PCl3), phosphorus tribromide (PBr3), phosphorus oxyfluoride (POF3), or phosphorus triiodide (PI3), which are more difficult to produce because they are liquids or solids at room temperature, or phosphorus pentafluoride (PF5) can also be used.

[0017] Reducing the etch activation energy of SiO2 and Si3N4 by phosphorus doping in RIE helps maintain high ON-ON pillar ER, even at high aspect ratios. This allows for more efficient utilization of reactive ions delivered to the etch front. Reducing the ER dependence on high-energy ions to control pillar profile (especially necessary for etch front control and twisting) may enable new operating process power regimes that rely more on high ion flux with reduced ion energy, i.e., increased radio frequency (RF) average power with reduced peak power in pulsed capacitively coupled plasma (CCP) etchers. Hardware power limitations allow for either increased ion energy or ion flux. In some embodiments, the silicon oxide etch chemistry becomes more similar to silicon nitride etch, providing a more uniform ON-ON etch.

[0018] For ease of understanding, FIG. 1 is a high-level flowchart that may be used in some embodiments. In some embodiments, a stack is placed in an etch chamber on a substrate support (step 104). In some embodiments, the stack is disposed beneath a carbon-containing patterned mask. In some embodiments, the carbon-containing mask is an amorphous carbon mask. FIG. 2A is a schematic cross-sectional view of a stack 200 used in one embodiment. In some embodiments, the stack comprises a substrate 208 beneath a plurality of bilayers 212 disposed beneath a carbon-containing patterned mask 216. One or more layers may be disposed between the substrate 208 and the plurality of bilayers 212, or between the plurality of bilayers 212 and the carbon-containing patterned mask 216. However, in some embodiments, no silicon-containing mask is provided over the plurality of bilayers 212 or over the carbon-containing patterned mask 216. The carbon-containing patterned mask 216 may be amorphous carbon. In some embodiments, the patterned mask pattern provides mask features 220 for high aspect ratio contacts. In some embodiments, the mask features are formed before the substrate is placed in the etch chamber. In other embodiments, the mask features 220 are formed while the substrate is in the etch chamber. In some embodiments, the plurality of bilayers 212 is a bilayer of a silicon oxide layer 224 and a silicon nitride layer 228.

[0019] After the stack 200 is placed in the etching chamber, the stack is cooled to a temperature below 0° C. (Step 108). In some embodiments, the stack is cooled to a temperature below −40° C.

[0020] An etching gas including a halogen-containing component and a phosphorus-containing component is flowed into the etching chamber (step 112). In some embodiments, the etching gas includes a halogen-containing component, a phosphorus-containing component, a hydrogen-containing component, a hydrocarbon-containing component, and a fluorocarbon-containing component. In some embodiments, the halogen-containing component is a chlorohydrocarbon C x H y Cl zThe etching gas may include at least one of silicon tetrachloride (SiCl), bromine trichloride (BCl), nitrogen trifluoride (NF), C4F8, octafluoropropane (C3F8), hexafluoro-1,3-butadiene (C4F6), sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), chlorine (Cl2), hydrogen bromide (HBr), trifluoroiodomethane (CF3I), fluoromethane (CH3F), difluoromethane (CH2F2), hydrochloric acid (HCl), and trifluoromethane (CHF3). In some embodiments, the etching gas further includes an inert gas, such as argon (Ar), helium (He), krypton (Kr), neon (Ne), xenon (Xe), or nitrogen (N2). In some embodiments, the inert gas may be an inert bombardment gas to provide ions for ion bombardment to facilitate etching. In some embodiments, the etching gas is oxygen-free and free of both octafluorocyclobutane (CF) and hexafluorocyclobutene (CF). In some embodiments, the etching gas further includes at least one of methane (CH) and hydrogen gas (H). In some embodiments, the phosphorus-containing component is at least one of PH, PF, PCl, PBr, POF, and PI. In some embodiments, an example etching gas is 5-120 sccm NF, 50-400 sccm H, 0-100 sccm CHF, 1-100 sccm PH, 0-100 sccm Cl, 0-100 sccm HBr, and 20-200 sccm CHF. In this example, a pressure of 5-60 mTorr is provided. In some embodiments, the halogen-containing component may include a fluorine-, chlorine-, or bromine-containing component.

[0021] The etching gas is formed into an etching plasma (step 116). This can be accomplished by supplying excitation RF power having a frequency of 60 megahertz (MHz) at 200 to 15,000 watts. In some embodiments, the RF power ranges from 0 to 25,000 watts at a frequency of 60 MHz. The stack 200 is exposed to the plasma (step 120). A bias is supplied (step 124) with a magnitude ranging from 200 volts to 15,000 volts. In some embodiments, RF power, either continuous or pulsed RF power with a peak power ranging from 3 kW to 150 kW, can be used for both the excitation RF power, which uses a higher frequency, and the bias RF power, which uses a lower frequency. The bias accelerates ions into the stack 200, selectively etching high-aspect-ratio etch features in the stack 200 relative to the carbon-containing patterned mask (step 128). The plasma is maintained for 180 to 3,600 seconds. The etch can etch both silicon oxide and silicon nitride layers. After etching is completed, the substrate is removed from the etching chamber (step 132).

[0022] 2B is a cross-sectional view of stack 200 after contact 232 has been etched. The contact is a high aspect ratio contact. Preferably, the contact has an etch depth to feature CD width aspect ratio of greater than 30:1. More preferably, the high aspect ratio contact has a height to CD width ratio of greater than 40:1. More preferably, the high aspect ratio contact has a height to CD width ratio of greater than 100:1.

[0023] The etching process can selectively etch silicon oxide and silicon nitride layers relative to amorphous carbon with a selectivity of greater than 3:1 while etching high aspect ratio features. The resulting features also have reduced bowing, striations, distortion, capping, and tapering. Additionally, this embodiment allows for the use of carbon-containing patterned masks, such as amorphous carbon, without the need for silicon-containing masks, such as polysilicon, reducing costs and defects.

[0024] Previous processes using etching where the stack is processed at temperatures above 0°C relied on fluorocarbon chemistries to provide etching and sidewall protection. Such processes resulted in etch selectivities of less than 3:1 between the mask and silicon oxide and silicon nitride. Sidewall protection was provided by polymer deposition, which was controlled by carbon concentration; higher carbon concentrations increased sidewall deposition, and oxygen consumed the deposited polymer; higher oxygen concentrations also increased mask consumption. Some previous processes used silicon-containing masks.

[0025] In some embodiments, the etch rate is increased and the contact geometry / stripe is improved compared to conventional approaches. Without being bound by theory, it is believed that adding a phosphorus-containing component to the etching gas deposits phosphorus dopants in silicon oxide and silicon nitride-containing layers. The phosphorus dopant lowers the activation energy required to etch silicon oxide-containing layers, allowing silicon oxide to be etched more easily and requiring lower-energy ions. Providing lower-energy ions for etching reduces curvature and other etching complications caused by high-energy ions. The phosphorus dopant can also lower the activation energy required to etch silicon nitride. However, phosphorus dopants lower the activation energy for silicon oxide more than phosphorus does for silicon nitride. In conventional techniques, silicon oxide is more difficult to etch than silicon nitride, leading to non-uniform etching of ON-ON stacks. Providing a phosphorus dopant allows for more uniform etching of ON-ON stacks.

[0026] In some embodiments, the electrostatic chuck is cooled to a temperature below 0° C. In some embodiments, the chuck is cooled to a temperature below −10° C. In some embodiments, the chuck is cooled to a temperature below −20° C. In some embodiments, the chuck is cooled to a temperature between −80° C. and 0° C. to provide improved processing. In some embodiments, the stack is cooled to a temperature between −60° C. and −20° C.

[0027] In some embodiments, the stack comprises one or more layers of at least one of silicon oxide and silicon nitride. In some embodiments, the stack is a single layer of silicon oxide or silicon nitride. In some embodiments, the stack comprises alternating layers of silicon oxide and polysilicon (OPOP).

[0028] In some embodiments, an ONON stack can be etched to form contact holes, channel holes, or trenches when fabricating 3D NAND memory devices. In other embodiments, an OPOP (alternating layers of SiO2 and polysilicon) stack can be etched to form contact holes, channel holes, or trenches when fabricating 3D NAND memory devices. Other embodiments can be used to etch DRAM capacitors. The capacitor etch can have a depth of 1.5 microns with a tight CD providing high aspect ratio features in silicon oxide. In some embodiments, etch features with height-to-width ratios greater than 10:1 are provided. In some embodiments, CDs of less than 50 nm are achieved with etch depths greater than 20 microns, providing features with depth-to-width aspect ratios of at least 4000:1. In some embodiments, the etch depth is greater than 3 microns. In some embodiments, a single amorphous carbon mask less than 1 micron thick allows etching of at least 48 layers of silicon oxide and silicon nitride in a single etch step.

[0029] In some embodiments, the etching gas may further include a hydrofluorocarbon-containing component, such as difluoromethane (CHF), which can be used to enhance etching of silicon nitride by providing passivation at cryogenic temperatures to control CD.

[0030] In some embodiments, the supply of etching gas and the ion etching may be performed as successive steps in a cyclic process. Supplying the etching gas simultaneously with the ion etching provides a faster process than a continuous cyclic process.

[0031] FIG. 3 is a schematic diagram of an etching reactor that can be used in one embodiment. In one or more embodiments, the etching reactor 300 includes a gas distribution plate 306 providing a gas inlet and an electrostatic chuck (ESC) 308 within an etching chamber 349 surrounded by chamber walls 352. Within the etching chamber 349, the stack 200 is positioned on top of the ESC 308, which acts as a substrate support. The ESC 308 can be biased by an ESC source 348. An etching gas source 310 is connected to the etching chamber 349 through the gas distribution plate 306. In some embodiments, the etching gas source 310 includes a phosphorus-containing component source 312, a halogen-containing component source, and other gas sources 318, such as a hydrogen-containing component source and a fluorocarbon-containing component source. An ESC temperature controller 350 is connected to a chiller 314. The chiller 314 can cool the ESC 308 to a temperature below 0° C. In this embodiment, chiller 314 supplies coolant to channels 392 in or near ESC 308. A radio frequency (RF) power supply 330 supplies RF power to the lower electrode and / or upper electrode (ESC 308 and gas distribution plate 306 in this embodiment). In some embodiments, a non-RF power source, such as a pulsed DC power supply, can replace or be used in conjunction with RF power supply 330 to control the plasma. In an exemplary embodiment, 400 kilohertz (kHz), 60 megahertz (MHz), and optionally 2 MHz and 27 MHz power supplies make up RF power supply 330 and ESC source 348. In this embodiment, the upper electrode is grounded. In this embodiment, one generator is provided for each frequency. In other embodiments, the generators may be on separate RF sources, or separate RF generators may be connected to different electrodes. For example, the upper electrode may have an inner electrode and an outer electrode connected to different RF sources. In other embodiments, other arrangements of RF sources and electrodes may be used. RF power may be continuous or pulsed. A controller 335 is controllably connected to the RF power source 330 , the ESC source 348 , the exhaust pump 320 , and the etching gas source 310 .An example of such an etch chamber is the Exelan Flex® Dielectric Etch System or the Vantex® Dielectric Etch System manufactured by Lam Research, Inc. of Fremont, Calif. The etch chamber may be a CCP (Capacitively Coupled Plasma) reactor or an ICP (Inductively Coupled Plasma) reactor, and the electrode may be a coil.

[0032] FIG. 4 is a high-level block diagram illustrating a computer system 400 suitable for implementing the controller 335 used in the embodiments. Computer systems can have many physical forms, ranging from integrated circuits, printed circuit boards, and small handheld devices to massive supercomputers. The computer system 400 includes one or more processors 402 and may further include an electronic display device 404 (for displaying graphics, text, and other data), a main memory 406 (e.g., random access memory (RAM)), a storage device 408 (e.g., a hard disk drive), a removable storage device 410 (e.g., an optical disk drive), a user interface device 412 (e.g., a keyboard, touchscreen, keypad, mouse, or other pointing device, etc.), and a communication interface 414 (e.g., a wireless network interface). The communication interface 414 allows software and data to be transferred between the computer system 400 and external devices via a link. The system may also include a communication infrastructure 416 (e.g., a communication bus, crossover bar, or network) to which the aforementioned devices / modules are connected.

[0033] Information transferred via communications interface 414 may be in the form of signals, such as electronic, electromagnetic, optical, or other signals receivable by communications interface 414, and transmitted over a communications link that transmits signals, which may be implemented using wire or cable, fiber optics, telephone lines, cellular phone links, radio frequency links, and / or other communications channels. Such communications interfaces may enable one or more processors 402 to receive information from a network or output information to a network in the course of performing the method steps described above. Furthermore, method embodiments may be performed solely on a processor or over a network, such as the Internet, in conjunction with a remote processor that shares some of the processing.

[0034] The term "non-transitory computer-readable medium" is generally used to refer to media such as main memory, secondary memory, removable storage, and storage devices such as hard disks, flash memory, disk drive memory, CD-ROMs, and other forms of persistent memory, and should not be interpreted as covering transitory content such as carrier waves or signals. Examples of computer-readable code include machine code, such as produced by a compiler, and files containing high-level code that are executed by a computer using an interpreter. The computer-readable medium may also be computer code embodied in a carrier wave and transmitted by a computer data signal representing a sequence of instructions executable by a processor.

[0035] In some embodiments, liquid nitrogen is used as the coolant that flows through the ESC 308 to provide cooling. In other embodiments, Vertel Sinera™ liquid, manufactured by DuPont of Wilmington, Delaware, can be used as the coolant.

[0036] While the present disclosure has been described based on several preferred embodiments, there are alterations, modifications, substitutions, and various substitute equivalents that fall within the scope of the present disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. Therefore, it is intended that the following appended claims be interpreted as including all such alterations, modifications, substitutions, and various substitute equivalents that fall within the true spirit and scope of the present disclosure. As used herein, the phrase "A, B, or C" should be interpreted in the sense of a logic using a non-exclusive logical "OR" ("A or B or C"), and not in the sense of "only one of A or B or C." Each step within a process may be optional and not required. Different embodiments may omit one or more steps or provide steps in a different order. Additionally, various embodiments may provide different steps simultaneously rather than sequentially.

Claims

1. 1. A method for etching a feature in a stack comprising a silicon oxide layer under a mask, the method comprising: cooling a substrate support for supporting the stack in an etching chamber to a temperature below 0°C; providing an etching gas including a halogen-containing component and a phosphorus-containing component; generating a plasma from the etching gas; providing a bias to accelerate ions from the plasma into the stack; selectively etching features in the stack relative to the mask; A method comprising:

2. 10. The method of claim 1, The method, wherein the etching gas further comprises a hydrogen-containing component, a hydrocarbon-containing component, and a fluorocarbon-containing component.

3. 10. The method of claim 1, The method, wherein the mask is a carbon-containing mask.

4. 4. The method of claim 3, The method wherein the carbon-containing mask is amorphous carbon.

5. 10. The method of claim 1, The etching gas does not contain oxygen and 4 F 8 and C 4 F 6 A method that does not include both.

6. 10. The method of claim 1, The halogen-containing component is a chlorohydrocarbon, SiCl 4 , BCl 3 , N.F. 3 , C 4 F 8 , C 3 F 8 , C 4 F 6 , S.F. 6 , C.F. 4 , Cl 2 , HBr, CF 3 I, CH 3 F, CH 2 F 2 , CHF 3 and HCl.

7. 10. The method of claim 1, The etching gas is H 2 , O 2 , and C.H. 4 The method further comprising at least one of:

8. 10. The method of claim 1, The method, wherein said cooling the substrate support for supporting the stack in an etching chamber to a temperature below 0°C further comprises cooling the substrate support to a temperature below -10°C.

9. 10. The method of claim 1, The method, wherein the mask is a carbon-containing mask and the stack comprises a plurality of alternating silicon oxide or silicon nitride layers.

10. 10. The method of claim 1, The method further comprising supplying RF power having a peak power in the range of 3 kW to 150 kW.

11. 10. The method of claim 1, The phosphorus-containing component is 3 , P.F. 3 , PCl 3 , PBr 3 , POF 3 , and P.I. 3 The method includes at least one of the following:

12. 10. The method of claim 1, The phosphorus-containing component is 3 and P.F. 3 The method includes at least one of the following:

13. 10. The method of claim 1, The etching gas is He, Ne, Ar, Kr, Xe, and N 2 The method further comprising an inert gas comprising at least one of:

14. 10. The method of claim 1, The method, wherein the mask is a carbon-containing mask and the stack includes a plurality of alternating silicon oxide and polysilicon layers.

15. 10. The method of claim 1, The method wherein the features have a height to width ratio greater than 10:

1.

16. 1. An apparatus for processing a stack on a substrate having at least one silicon oxide layer, comprising: an etching chamber; a substrate support for supporting a substrate within the etching chamber; a temperature controller for controlling the temperature of the substrate support; an electrode for supplying RF power into the etching chamber; an RF power source for supplying RF power to the electrode; a gas source for supplying an etching gas to the etching chamber, the gas source comprising: a source of halogen-containing components, and Source of phosphorus-containing ingredients a gas source comprising: An apparatus comprising:

17. 17. The apparatus of claim 16, a controller controllably connected to the gas source, the RF power source, and the temperature controller, a processor; 1. A computer readable medium having computer readable code thereon, the computer readable code comprising: computer readable code for cooling the substrate support to a temperature below 0° C.; computer readable code for supplying an etching gas comprising a halogen-containing component from the halogen-containing component source and a phosphorus-containing component from the phosphorus-containing component source; computer readable code for supplying RF power to generate a plasma from the etching gas; and Computer readable code for generating a bias a computer-readable medium including: The apparatus further comprises a controller comprising:

18. 18. The apparatus of claim 17, The gas source a source of hydrogen-containing components; a source of fluorocarbon-containing ingredients; The apparatus further comprises:

19. 19. The apparatus of claim 18, The apparatus, wherein the computer readable code for supplying the etching gas further comprises computer readable code for supplying a hydrogen-containing component from the hydrogen-containing component source and a fluorocarbon-containing component from the fluorocarbon-containing component source.

20. 17. The apparatus of claim 16, The apparatus further comprising a non-RF power source for controlling a plasma in the etching chamber.

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