Epitaxial chip structure

Abstract

The present application discloses an epitaxial chip structure, which includes a substrate, a preparation layer, a buffer layer, a base layer, and an application layer, which are sequentially stacked on the substrate, among which the buffer layer is a multi-layer In x Ga y Al z N(0

Description

[Technical Field]

[0001] This application claims priority to a Chinese patent application filed with the China Patent Office on September 15, 2022, bearing application number 202211124726.7 and entitled "Epitaxial Chip Structure," the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the technical field of semiconductors, and in particular to epitaxial chip structures applicable to semiconductor devices such as semiconductor optoelectronic devices (LED / LD laser / PV photovoltaic), power devices and radio frequency microwave devices. [Background technology]

[0003] Currently, third-generation semiconductor devices may include semiconductor optoelectronic devices, power devices, radio-frequency microwave devices, etc. In conventional manufacturing processes, sapphire or Si is typically used as a substrate, and a material layer containing InGaN is used as the application layer of the corresponding semiconductor device. For example, in the manufacturing process of semiconductor optoelectronic devices, a sapphire substrate is typically used, and an MQW (multiple quantum well) layer comprising an active region is grown on the sapphire substrate. The MQW layer is a multilayer structure formed by alternately growing thin layers of two different semiconductor materials, one of which is a quantum well layer and the other is a quantum barrier layer. However, due to the large lattice mismatch between the application layer of the In-containing semiconductor device and the sapphire substrate, it is difficult to grow a high-quality, high-In-content application layer on the substrate in the semiconductor device. Summary of the Invention

[0004] The present invention provides a substrate, a buffer layer, and an application layer that are sequentially stacked on the substrate, wherein the buffer layer is a multi-layer In x Ga y Al zComposed of a gradually changing growth structure of the In component of the N(0 < x ≤ 100%, x + y + z = 1) compound material, and the lattice constants of the buffer layer and the application layer materials provide the same or similar epitaxial chip structures.

[0005] Preferably, the buffer layer includes at least two In composition buffer layers with gradually or stepwise changing growth temperatures.

[0006] Preferably, the epitaxial chip structure further includes a preparation layer provided between the substrate and the buffer layer.

[0007] Preferably, the preparation layer includes at least one of aluminum nitride, graphene, gallium oxide, aluminum oxide, silicon carbide, or diamond.

[0008] Preferably, the buffer layer is one of an InGaN material, an InGaAlN material, or an InN material, that is, In x Ga y Al z N(0 < x ≤ 100%, x + y + z = 1), or a mixture of at least two materials, that is, the above-mentioned buffer layer is a composite buffer layer.

[0009] Preferably, the epitaxial chip structure further includes a base layer composed of at least one layer of In x Ga y Al z N(0 < x ≤ 100%, x + y + z = 1) compound material. The base layer is close to the application layer, and the growth temperature is higher than the growth temperature of the buffer layer.

[0010] Preferably, the growth temperature of the buffer layer is 300°C to 600°C, and the growth temperature of the base layer is 400°C to 1000°C.

[0011] Preferably, In within the buffer layer and / or the base layer x Ga y Al zIn the content of the In component in the Group III element in the N(0 < x ≤ 100%, x + y + z = 1) compound material, it gradually increases or decreases along the direction from the buffer layer to the application layer.

[0012] Preferably, In in the buffer layer and / or the base layer x Ga y Al z The molar percentage of the In component in the Group III element in the N(0 < x ≤ 100%, x + y + z = 1) compound material is greater than 0% and less than or equal to 100%.

[0013] Preferably, the buffer layer includes at least two sub-buffer layers provided in a stacked manner, and In in different sub-buffer layers x Ga y Al z In the content of the In component in the Group III element in the N(0 < x ≤ 100%, x + y + z = 1) compound material, it gradually increases or decreases along the direction from the buffer layer to the application layer.

[0014] Preferably, the base layer includes at least two sub-base layers provided in a stacked manner, and In in different sub-base layers x Ga y Al z In the content of the In component in the Group III element in the N(0 < x ≤ 100%, x + y + z = 1) compound material, it gradually increases or decreases along the direction from the buffer layer to the application layer.

[0015] Preferably, the thickness of the buffer layer is 10 nm to 100 nm, the thickness of the base layer is 1 μm to 20 μm, and the thickness of the preparation layer is 1 nm to 100 nm.

[0016] Preferably, the base layer is n-type doped, or both the buffer layer and the base layer are n-type doped.

[0017] Preferably, Si is doped in at least one sub-base layer close to the application layer.

[0018] Preferably, the substrate has a roughened surface on one side thereof that is closer to the buffer layer.

[0019] Preferably, the roughened structure is a regular step or porous structure, which is formed by electrochemical corrosion or photolithography.

[0020] Preferably, the porous structure is provided on one surface of the substrate close to the buffer layer, and the duty ratio is greater than 5% and less than 80%.

[0021] Preferably, the preparation layer has a porous structure on one surface thereof close to the buffer layer, and the duty ratio is greater than 5% and less than 80%; and / or the buffer layer has a porous structure on one surface thereof close to the base layer, and the duty ratio is greater than 5% and less than 80%; And / or, a porous structure is provided on one surface of the base layer close to the application layer, and the duty ratio is greater than 5% and less than 80%.

[0022] Preferably, the preparation layer comprises a graded n-doped multilayer structure.

[0023] Preferably, the substrate comprises at least one of a silicon, silicon carbide, aluminum nitride, gallium nitride, gallium oxide, indium oxide, diamond, germanium or sapphire substrate.

[0024] Preferably, the buffer layer includes an InN material, the base layer includes an InGaN material or an InN material, and the buffer layer, the base layer and the application layer are stacked in this order.

[0025] Preferably, the buffer layer comprises at least two sub-buffer layers stacked one on the other, and the growth temperatures of the sub-buffer layers are gradually or stepwise changed; The base layer comprises at least two sub-base layers provided in a stack, and the growth temperatures of the sub-base layers change gradually or stepwise.

[0026] Preferably, the preparation layer comprises at least one layer of AlN material.

[0027] Preferably, the In content in the different sub-buffer layers gradually increases or decreases along the direction from the buffer layer to the application layer; The In content in the different sub-basic layers gradually increases or decreases along the direction from the buffer layer to the application layer.

[0028] Preferably, the buffer layer comprises at least two sub-buffer layers stacked one on top of the other, and the growth temperatures of the sub-buffer layers change gradually or stepwise, and the In contents of the sub-buffer layers have a stepwise change structure along the direction from the buffer layer to the application layer.

[0029] Compared to the prior art, the present application grows a buffer layer on a substrate that has a multi-layer In component gradual change growth structure, so as to further grow an application layer that is high quality and matches the lattice constant of the substrate. This solves the problem that, when a sapphire substrate is used in the prior art, the lattice mismatch between the application layer (which is a semiconductor element) and the sapphire substrate is too large, making it difficult to grow an application layer with a high In component.

[0030] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the present application. [Brief explanation of the drawings]

[0031] In order to more clearly explain the technical aspects of the embodiments of the present application, the drawings necessary to be used in the description of the embodiments will be briefly introduced below. However, the drawings in the following description are only some embodiments of the present application, and it is obvious that a person skilled in the art can further obtain other drawings according to these drawings without paying any creative labor.

[0032] [Figure 1] 1 is a structural schematic diagram of a first embodiment of an epitaxial chip structure according to the present invention. [Figure 2]FIG. 2 is a structural schematic diagram of a second embodiment of the epitaxial chip structure of the present application. [Figure 3] FIG. 10 is a structural schematic diagram of a third embodiment of the epitaxial chip structure of the present invention. [Figure 4] FIG. 10 is a structural schematic diagram of a fourth embodiment of the epitaxial chip structure of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0033] In order to allow those skilled in the art to better understand the technical aspects of the present application, the epitaxial chip structure according to the present application will be described in more detail below with reference to the drawings and specific embodiments. It should be understood that the described embodiments are only some of the embodiments of the present application, and are not all of the embodiments. All other embodiments that can be obtained by those skilled in the art based on the embodiments herein without the need for creative work are all within the scope of protection of the present application.

[0034] The terms "first," "second," etc., used herein are not intended to describe a particular order but to distinguish between different objects. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to the steps or units already listed, but may optionally include steps or units not listed, or may further optionally include other steps or units that are inherent to the process, method, product, or apparatus.

[0035] The present application provides an epitaxial chip structure to solve the problem of the difficulty in growing application layers with high In content on sapphire substrates in the prior art.

[0036] Referring to Figure 1, Figure 1 is a structural schematic diagram of a first embodiment of the epitaxial chip structure of the present application. As shown in Figure 1, the epitaxial chip structure 10 includes a substrate 11, a buffer layer 12, and an application layer 13. The application layer 13 may be a corresponding functional layer of a different semiconductor device, such as an MQW layer in a semiconductor optoelectronic device, a doped conductive layer in a power device, or a signal transmitting or receiving layer in a radio frequency microwave device.

[0037] Specifically, the present application will specifically describe the epitaxial chip structure 10 of the present application by taking a semiconductor photoelectric device as an example. When the epitaxial chip structure 10 of the present application is applied to a semiconductor photoelectric device, the application layer 13 of the present application is specifically multiple quantum well The MQW layer includes a quantum barrier layer made of GaN and a quantum well layer made of InGaN, and the mole percentage of In in the quantum well layer can be adjusted according to the wavelength of the light to be modulated. For example, when the epitaxial chip structure 10 is used to generate red light, the mole percentage of In in the group III elements in the InGaAlN material of the quantum well layer is about 40%. When the epitaxial chip structure 10 is used to generate green light, the mole percentage of In in the group III elements in the InGaAlN material of the quantum well layer is about 25%. Preferably, a single quantum well layer and a single quantum barrier layer form one period, and the application layer 13 may have multiple periods stacked alternately, and the number of periods of the alternating quantum well layer and quantum barrier layer may be 2 to 1000.

[0038] Specifically, the buffer layer 12 and the application layer 13 are sequentially stacked on the substrate 11. The buffer layer 12 has a multi-layer In component gradual change growth structure, and the materials of the buffer layer 12 and the application layer 13 are lattice constant of The multi-layer In composition gradual change growth structure includes at least two In composition buffer layers whose growth temperature changes gradually or stepwise. The buffer layer 12 is a multi-layer In x Gay Al z It is composed of a stack of N(0 < x ≤ 100%, x + y + z = 1) compounds. Preferably, the In composition is at least one of an InGaN material, an InGaAlN material, or an InN material. When the In composition is a plurality of materials, the buffer layer 12 is a composite buffer layer. Preferably, the composite buffer layer described above may have a superlattice structure.

[0039] Preferably, in one embodiment, the buffer layer 12 may include one layer of InN material and at least one layer of InGaN material or InGaAlN material. Among them, the InN material layer grows on the substrate 11, and the InGaN material layer or InGaAlN material layer further grows on the InN material layer. In this embodiment, by growing an InN material layer on the substrate 11, an InGaN material layer or InGaAlN material layer having the same In component can also grow better on the InN material layer. Similarly, a MQW layer having the same In component can grow better on the InGaN material layer or InGaAlN material layer. Thereby, an epitaxial chip structure 10 with a high In component and a high-quality MQW layer grown thereon is obtained.

[0040] In the prior art, long-wavelength GaN-based LEDs usually use sapphire as the substrate material and low-temperature GaN / AlN as the buffer layer material. The lattice constant of the substrate is smaller than that of the buffer layer. At the same time, the lattice constant of the substrate is smaller than that of the quantum wells in the MQW layer When a large compressive stress from the substrate and the buffer layer is applied to a quantum well with a high In component, In precipitation and phase separation occur. Also, since the material of the buffer layer is different from that of the MQW layer, it is difficult for the MQW layer to grow on the buffer layer, which affects the light emission efficiency of the LED.

[0041] Therefore, in this embodiment, by growing a single buffer layer 12 having a multi-layer In-component gradually changing growth structure between the substrate 11 and the application layer 13 and having a lattice constant of the material the same as or similar to that of the material of the application layer 13, the application layer 13 having the same In component can grow on the buffer layer 12 with high quality. On the other hand, since the lattice constants of the materials of the buffer layer 12 and the application layer 13 are the same or similar, the buffer layer 12 is aligned with the lattice constant of the application layer 13, and it is easy to grow the application layer 13 on the buffer layer 12, effectively improving the growth quality of the application layer 13.

[0042] As shown in FIG. 1, the epitaxial chip structure 10 further includes a base layer 15. Among them, the buffer layer 12, the base layer 15, and the application layer 13 are sequentially stacked and grown on the substrate 11. That is, the buffer layer 12 is provided closer to the substrate 11, and the base layer 15 is provided closer to the application layer 13. Among them, the base layer 15 is composed of at least one layer of In x Ga y Al z N (0 <x ≤ 100%, x + y + z = 1) compound material.

[0043] Specifically, in this embodiment, the growth temperature of the buffer layer 12 is lower than that of the base layer 15. Among them, the growth temperature of the buffer layer 12 is 300°C to 600°C, and the growth temperature of the base layer 15 is 400°C to 1000°C. Since the corresponding growth stresses of InGaN grown at high and low temperatures are different, the growth stresses of the buffer layer 12 and the base layer 15 in this embodiment are also different.

[0044] Specifically, in this embodiment, the content of the In component in the III group elements in the In x Ga y Al z N (0 <x ≤ 100%, x + y + z = 1) compound material of the buffer layer 12 or / and the base layer 15 gradually increases or decreases along the direction from the buffer layer 12 to the application layer 13. Preferably, the In x Ga y Al zThe molar percentage of the In component in the Group III element in the N(0 < x ≤ 100%, x + y + z = 1) compound material is greater than 0% and less than or equal to 100%, and the In of the base layer 15 x Ga y Al z The molar percentage of the In component in the Group III element in the N(0 < x ≤ 100%, x + y + z = 1) compound material is greater than 0% and less than or equal to 100%. That is, the In of the buffer layer 12 x Ga y Al z The molar percentage of the In component in the Group III element in the N(0 < x ≤ 100%, x + y + z = 1) compound material changes from 0% to 100% or from 100% to 0% from the side close to the substrate 11 to the side close to the base layer 15, and the In of the base layer 15 x Ga y Al z The molar percentage of the In component in the Group III element in the N(0 < x ≤ 100%, x + y + z = 1) compound material changes from 0% to 100% or from 100% to 0% from the side close to the buffer layer 12 to the side close to the application layer 13.

[0045] Preferably, in this embodiment, the buffer layer 12 and the base layer 15 are at least one of an InGaN material, an InGaAlN material, or an InN material. That is, the buffer layer 12 and the base layer 15 may both contain an In component, a Ga component, and an Al component. Specifically, the In component, the Ga component, and the Al component are components of independent amounts, and their contents do not affect each other, and the contents of the Ga component and the Al component may both be greater than or equal to 0%.

[0046] Specifically, when the content of the Ga component is greater than 0% and the content of the Al component is greater than 0%, the buffer layer 12 and the base layer 15 are an InGaAlN material. When the content of the Ga component is greater than 0% and the content of the Al component is equal to 0%, the buffer layer 12 and the base layer 15 are an InGaN material. When the content of the Ga component is equal to 0% and the content of the Al component is equal to 0%, the buffer layer 12 and the base layer 15 are an InN material.

[0047] In this embodiment, a buffer layer 12 with a low growth temperature and a high In mole percentage is grown on a substrate 11 to relieve stress as much as possible from the buffer layer 12, and at the same time, a base layer 15 with the same doping composition as the buffer layer 12 is further grown. Because the base layer 15 has a high growth temperature and a low In mole percentage, the base layer 15 can be successfully grown on the buffer layer 12, and therefore the application layer 13 with the same doping composition and a similar In mole percentage can be successfully grown on the base layer 15. This embodiment improves the growth environment for the application layer 13, thereby reducing defects caused by the stress relief in the application layer 13 and improving the light conversion efficiency of the application layer 13.

[0048] Specifically, in this embodiment, the thickness of buffer layer 12 is 10 nm to 100 nm, and the thickness of base layer 15 is 1 μm to 20 μm. Because the thickness of base layer 15 is greater than the thickness of buffer layer 12, i.e., buffer layer 12, which has a relatively large number of lattice defects, is thinner than base layer 15, which has a relatively small number of lattice defects, it becomes easier to grow application layer 13 on base layer 15.

[0049] Preferably, in one embodiment, the buffer layer 12 may be an InN material, the base layer 15 may be an InGaN material or an InN material, and the buffer layer 12, the base layer 15 and the application layer 13 are stacked in sequence.

[0050] In this embodiment, a buffer layer 12 made of InN material is grown on a substrate 11. Since the lattice constant of InN material is slightly different from that of the substrate 11 and is easy to grow on the substrate 11, a base layer 15 having the same In content can also be grown well on the buffer layer 12. Similarly, an application layer 13 having an In content can also be grown well on the base layer 15. This results in an epitaxial chip structure 10 in which an application layer 13 with a high In content and high quality is grown.

[0051] 2 in conjunction with FIG. 1, which is a structural schematic diagram of a second embodiment of the epitaxial chip structure of the present application. As shown in FIG. 2, the buffer layer 12 of this embodiment includes at least two sub-buffer layers 121 stacked one on the other.

[0052] In this embodiment, the In content in the different sub-buffer layers 121 gradually increases or decreases along the direction from the buffer layer 12 to the application layer 13. Preferably, in another embodiment, the growth temperatures of the at least two stacked sub-buffer layers 121 change gradually or stepwise.

[0053] Specifically, the thickness of each sub-buffer layer 121 is the same and is equal to 1 / n of the thickness of the buffer layer 12, where n is the number of sub-buffer layers 121; that is, the total thickness of the at least two sub-buffer layers 121 remains unchanged and is equal to the thickness of the buffer layer 12.

[0054] The In content of each sub-buffer layer 121 is different, but the In content of the sub-buffer layers 121 in the same layer is the same. For example, the buffer layer 12 may have four stacked sub-buffer layers 121, where the first sub-buffer layer 121 has an In content of 5%, the second sub-buffer layer 121 has an In content of 35%, the third sub-buffer layer 121 has an In content of 65%, and the fourth sub-buffer layer 121 has an In content of 95%, and the first to fourth sub-buffer layers 121 may be stacked along the direction from the substrate 11 to the application layer 13, or may be stacked along the direction from the application layer 13 to the substrate 11.

[0055] 3 in conjunction with FIG. 1, which is a structural schematic diagram of a third embodiment of the epitaxial chip structure of the present application. As shown in FIG. 3, the base layer 15 of this embodiment includes at least two sub-base layers 151 stacked one on top of the other.

[0056] Among them, in this embodiment, the In content in different sub-base layers 151 gradually increases or decreases along the direction from the buffer layer 12 to the application layer 13. Preferably, in other embodiments, the growth temperatures of at least two sub-base layers 151 provided by stacking change gradually or stepwise. In the present invention, regarding the above-mentioned stepwise change, the growth parameters of each stacked layer, such as temperature or component doping, may not change linearly and gradually, but may change non-linearly and stepwise.

[0057] Specifically, the thickness of each sub-base layer 151 is the same and equal to 1 / n of the thickness of the base layer 15, where n is the number of sub-base layers 151, that is, the total thickness of at least two sub-base layers 151 does not change and is equal to the thickness of the base layer 15.

[0058] Among them, the In content of each sub-base layer 151 is different, and the In content of the sub-base layers 151 in the same layer is the same. For example, the sub-base layer 151 may include four sub-base layers 151 provided by stacking. The In content of the first sub-base layer 151 is 10%, the In content of the second sub-base layer 151 is 20%, the In content of the third sub-base layer 151 is 30%, and the In content of the fourth sub-base layer 151 is 40%. Moreover, the first to fourth sub-base layers 151 may be stacked along the direction from the substrate 11 to the application layer 13, or may be stacked along the direction from the application layer 13 to the substrate 11. Here, the In content refers to the content of the In component in the group III elements in the x Ga y Al z InN (0 < x ≤ 100%, x + y + z = 1) compound material.

[0059] 1, the basic layer 15 and the application layer 13 are stacked, so the basic layer 15 needs to have n-type functionality, i.e., be n-doped. Specifically, the basic layer 15 can achieve n-type functionality by being doped with Si. Preferably, the basic layer 15 can include multiple sub-basic layers 151, so that the basic layer 15 can achieve n-type functionality by doping at least one sub-basic layer 151 close to the application layer 13 with Si.

[0060] Preferably, in another embodiment, both the buffer layer 12 and the base layer 15 may have n-type functionality, i.e., both the buffer layer 12 and the base layer 15 are n-doped. Specifically, both the buffer layer 12 and the base layer 15 may be doped with Si to achieve n-type functionality.

[0061] Preferably, the epitaxial chip structure 10 of the present application is applicable to all substrates, and the substrate 11 of this embodiment may include at least one of a silicon substrate or a sapphire substrate, and may further include, for example, a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, a diamond substrate, a germanium (Ge) substrate, at least one of gallium nitride (GaN), gallium oxide (Ga2O3), indium oxide (In2O3), etc. Preferably, the epitaxial chip structure 10 of the present application is also applicable to a composite substrate, which may specifically be n-GaN grown on ordinary sapphire or other conductive, transparent (reflective) heat dissipation substrates.

[0062] Preferably, when the substrate 11 is a silicon substrate and the buffer layer 12 comprises at least one InN material layer, the silicon substrate is an opaque material, while the buffer layer 12 and the application layer 13 are transparent materials. Therefore, if a transparent epitaxial chip structure 10 is required, the substrate 11 of the epitaxial chip structure 10 must be separated. The growth temperature of InN is 400°C, the dissociation temperature of InN is 600°C, and the growth temperature of the buffer layer 12 is about 700°C. Therefore, by setting the growth temperature of the epitaxial chip structure 10 to be higher than 600°C, the InN can be decomposed and the substrate 11 can be separated from the buffer layer 12 and the application layer 13.

[0063] 1, the epitaxial chip structure 10 of this embodiment further includes a preparation layer 14 disposed between the substrate 11 and the buffer layer 12, which is configured as a multilayer In-graded growth structure. The preparation layer 14 of this embodiment functions to protect the substrate 11, repair and perfect the growth interface of the buffer layer 12, and meet the stress design target of the buffer layer 12. Preferably, if there is no need to protect the substrate, the preparation layer 14 may be omitted.

[0064] Preferably, the preparation layer 14 of this embodiment may specifically be at least one of aluminum nitride (AlN), graphene, gallium oxide (Ga2O3), aluminum oxide (Al2O3), silicon carbide (SiC) or diamond.

[0065] In this embodiment, the preparation layer 14 has a multi-layer structure with gradually changing n-type doping. Specifically, when the preparation layer 14 includes at least one layer of AlN material, the AlN material separates the buffer layer 12 (specifically, InN material) from the substrate 11, thereby preventing corrosion of the substrate 11 by the InN material, i.e., preventing chemical reactions between the InN material and the silicon substrate, and repairing and perfecting the growth interface, which also facilitates stress design of the buffer layer.

[0066] Preferably, in this embodiment, the preparation layer 14 is only an insulating thin film, so that the epitaxial chip structure 10 does not need to grow an excessively thick preparation layer 14, and the growth thickness of the preparation layer 14 may be 1 nm to 100 nm.

[0067] Furthermore, the epitaxial chip structure 10 of the present application may be provided with a roughened structure, which may be provided on one surface of the substrate 11 close to the buffer layer 12. Specifically, the roughened structure may be a regular step or porous structure, which is formed by electrochemical corrosion or photolithography.

[0068] The porous structure may be provided on at least one of the surface of the substrate 11 close to the buffer layer 12, the surface of the preparation layer 14 close to the buffer layer 12, the surface of the buffer layer 12 close to the base layer 15, and the surface of the base layer 15 close to the application layer 13.

[0069] Specifically, a porous structure is provided on one surface of the substrate 11 close to the buffer layer 12, and the duty ratio of the surface of the substrate 11 close to the buffer layer 12 is greater than 5% and less than 80%, where the duty ratio is the ratio of the area with holes to the total area, i.e., the ratio of the area with holes to the total area of ​​the substrate 11.

[0070] A porous structure is provided on one surface of the preparation layer 14 close to the buffer layer 12, so that the duty ratio of the surface of the preparation layer 14 close to the buffer layer 12, i.e., the ratio of the area with holes to the total area of ​​the preparation layer 14, is greater than 5% and less than 80%.

[0071] A porous structure is provided on one surface of the buffer layer 12 close to the base layer 15, so that the duty ratio of the surface of the buffer layer 12 close to the base layer 15, i.e., the ratio of the area with holes to the total area of ​​the buffer layer 12, is greater than 5% and less than 80%.

[0072] A porous structure is provided on one surface of the base layer 15 close to the application layer 13, so that the duty ratio of the surface of the base layer 15 close to the application layer 13, i.e., the ratio of the area with holes to the total area of ​​the base layer 15, is greater than 5% and less than 80%.

[0073] In the present invention, a porous structure is formed on one surface of substrate 11 near buffer layer 12, and buffer layer 12 is made of InN, a material with a lattice constant slightly different from that of substrate 11, making it easier for buffer layer 12 to grow on substrate 11. Based on this, buffer layer 12 and base layer 15, made of the same material but grown at different temperatures, are sequentially grown to form a high-quality InGaN or InGaAlN layer serving as a growth preparation layer for application layer 13. At the same time, because base layer 15 and application layer 13 are made of the same material, and the application layer 13 grown on high-quality base layer 15 matches the lattice constant of base layer 15, a high-quality application layer 13 with a high In content is obtained, thereby solving the problem of In precipitation and phase separation due to a large lattice mismatch between the MQW layer and substrate in long-wavelength LEDs.

[0074] The present application aims to provide an epitaxial chip structure 10 for growing a thick layer of high-quality indium-containing nitride compound with low stress. The epitaxial chip structure 10 provides a high-quality indium-containing nitride compound growth platform for the growth of the application layer 13, thereby solving the problem of In precipitation and phase separation due to large lattice mismatch. The material selection and structure design combinations may include several combinations, as specifically shown in the table below, in which the preparation layer 14 may be omitted. In the table, the growth temperature of the buffer layer 12 is lower than that of the base layer 15, and the temperature of the base layer 15 is higher than that of the buffer layer 12.

[0075] TIFF2025531215000007.tif147170

[0076] Specifically, further reference is made to Figure 4, which is a structural schematic diagram of a fourth embodiment of the epitaxial chip structure of the present application. As shown in Figure 4, the buffer layer 12 of the epitaxial chip structure 10 may include multiple sub-buffer layers 121, and the base layer 15 may include multiple sub-base layers 151. A three-dimensional structure formed on the surface of the substrate 11 or adjacent layers above each other is preferred. The multiple sub-buffer layers 121 and the multiple sub-base layers 151 have an In composition gradation structure and a temperature gradation structure, where the growth temperature of the sub-base layers 151 is higher than that of the sub-buffer layers 121.

[0077] Furthermore, the above-mentioned In component gradual change structure may be a step change structure, that is, the In component changes stepwise in each layer, and the In component is uniformly distributed in each layer.

[0078] The above are merely examples of the present application, and the scope of the patent of the present application is not limited thereby. Any equivalent structure or equivalent flow modification made using the contents of the specification and drawings of the present application, or any modification directly or indirectly operated in other related technical fields, is also included in the scope of patent protection of the present application.

Claims

1. The present invention comprises a substrate, a buffer layer and an application layer sequentially stacked on the substrate, and the buffer layer is a multi-layer In ｘ Ga ｙ Al ｚ The N (0<x≦100%, x+y+z=1) compound material is configured to have an In content gradation growth structure, and the lattice constants of the materials of the buffer layer and the application layer are the same or similar; An epitaxial chip structure characterized by:

2. The buffer layer comprises at least two In composition buffer layers whose growth temperature changes gradually or stepwise.

2. The epitaxial chip structure of claim 1.

3. further comprising a preparation layer disposed between the substrate and the buffer layer; 2. The epitaxial chip structure of claim 1.

4. the preparation layer includes at least one of aluminum nitride, graphene, gallium oxide, aluminum oxide, silicon carbide, and diamond; 4. The epitaxial chip structure of claim 3.

5. The buffer layer is one of an InGaN material, an InGaAlN material, or an InN material, or is configured as a composite buffer layer of at least two materials; 3. The epitaxial chip structure of claim 2.

6. At least one layer of In ｘ Ga ｙ Al ｚ The method further includes providing a base layer made of an N (0<x≦100%, x+y+z=1) compound material, the base layer being close to the application layer and having a growth temperature higher than that of the buffer layer.

5. The epitaxial chip structure of claim 4.

7. The growth temperature of the buffer layer is 300°C to 600°C, and the growth temperature of the base layer is 400°C to 1000°C.

7. The epitaxial chip structure of claim 6.

8. In in the buffer layer and / or the base layer ｘ Ga ｙ Al ｚ the content of In in the group III elements in the N (0<x≦100%, x+y+z=1) compound material gradually increases or decreases along a direction from the buffer layer to the application layer; 7. The epitaxial chip structure of claim 6.

9. In in the buffer layer and / or the base layer ｘ Ga ｙ Al ｚ The mole percentage of In component in the group III elements in the N (0<x≦100%, x+y+z=1) compound material is greater than 0% and less than or equal to 100%; 7. The epitaxial chip structure of claim 6.

10. The buffer layer includes at least two sub-buffer layers stacked one on the other, and the In in the different sub-buffer layers ｘ Ga ｙ Al ｚ the content of In in the group III elements in the N (0<x≦100%, x+y+z=1) compound material gradually increases or decreases along a direction from the buffer layer to the application layer; 9. The epitaxial chip structure of claim 8.

11. The base layer includes at least two sub-base layers stacked one on top of the other, and In ｘ Ga ｙ Al ｚ the content of In in the group III elements in the N (0<x≦100%, x+y+z=1) compound material gradually increases or decreases along a direction from the buffer layer to the application layer; 9. The epitaxial chip structure of claim 8.

12. the buffer layer has a thickness of 10 nm to 100 nm, the base layer has a thickness of 1 μm to 20 μm, and the preparation layer has a thickness of 1 nm to 100 nm; 9. The epitaxial chip structure of claim 8.

13. The base layer is n-doped, or the buffer layer and the base layer are both n-doped.

9. The epitaxial chip structure of claim 8.

14. The sub-basic layer close to at least one application layer is doped with Si.

14. The epitaxial chip structure of claim 13.

15. a surface of the substrate close to the buffer layer having a roughened structure; 7. The epitaxial chip structure of claim 6.

16. The roughened structure is a regular step or porous structure, which is formed by electrochemical corrosion or photolithography.

16. The epitaxial chip structure of claim 15.

17. the porous structure is provided on one surface of the substrate close to the buffer layer, and has a duty ratio greater than 5% and less than 80%; 17. The epitaxial chip structure of claim 16.

18. the porous structure is provided on one surface of the preparation layer close to the buffer layer, and the duty ratio is greater than 5% and less than 80%; and / or the porous structure is provided on one surface of the buffer layer close to the base layer, and the duty ratio is greater than 5% and less than 80%; and / or the porous structure is provided on one surface of the base layer close to the application layer, and the duty ratio is greater than 5% and less than 80%.

18. The epitaxial chip structure of claim 17.

19. the preparation layer comprises a graded n-type doped multilayer structure; 5. The epitaxial chip structure of claim 4.

20. The substrate comprises at least one of silicon, silicon carbide, aluminum nitride, gallium nitride, gallium oxide, indium oxide, diamond, germanium, or sapphire substrate; 6. The epitaxial chip structure according to claim 1, wherein:

21. the buffer layer includes an InN material, the base layer includes an InGaN material or an InN material, and the buffer layer, the base layer, and the application layer are stacked in sequence; 5. The epitaxial chip structure of claim 4.

22. The buffer layer includes at least two sub-buffer layers stacked one on the other, and the growth temperature of the sub-buffer layers is gradually or stepwise changed; The base layer comprises at least two sub-base layers stacked one on top of the other, and the growth temperature of the sub-base layers changes gradually or stepwise.

22. The epitaxial tip structure of claim 21.

23. the preparation layer includes at least one layer of AlN material; 22. The epitaxial tip structure of claim 21.

24. the In content in the different sub-buffer layers gradually increases or decreases along a direction from the buffer layer to the application layer; The In content in the different sub-basic layers gradually increases or decreases along the direction from the buffer layer to the application layer.

23. The epitaxial tip structure of claim 22.

25. the buffer layer includes at least two sub-buffer layers stacked one on the other, and the growth temperatures of the sub-buffer layers are gradually or stepwise changed, and the In content of the sub-buffer layers is a stepwise change structure along a direction from the buffer layer to the application layer; 22. The epitaxial tip structure of claim 21.

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