Semiconductor element manufacturing method

Abstract

The present invention relates to a method for manufacturing a semiconductor device. According to one embodiment, a method for manufacturing a semiconductor device may include forming an insulating layer, forming a barrier layer on the insulating layer, performing a nitridation process on the barrier layer, and forming a metal electrode on the barrier layer. In one embodiment, performing the nitridation process may include performing a high-pressure nitridation (HPN) process. According to this embodiment, improving the quality of the barrier layer during a semiconductor device manufacturing process may improve the electrical characteristics of the barrier layer and the metal electrode, thereby improving the electrical characteristics of the semiconductor device.

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Semiconductor devices are components primarily used in electronic circuits and similar devices that utilize the electrical conductivity properties of semiconductors. Semiconductors can be divided into memory semiconductors and non-memory semiconductors. Memory semiconductors can be divided into volatile memory such as DRAM and SRAM, and non-volatile memory such as Mask ROM, EP ROM, EEP ROM, and flash memory.

[0003] FIG. 1 shows the structure of a typical semiconductor device.

[0004] Referring to FIG. 1, a semiconductor device may include an insulating layer 12 formed on a substrate 11 having a predetermined structure formed thereon, and a metal electrode 14 formed on the insulating layer 12.

[0005] The metal electrode 14 may include a metal material such as Al, Cu, W, Mo, or Ru. Metal ions, oxygen, or moisture contained in the metal electrode 14 may diffuse into the insulating layer 12, contaminating the insulating layer 12 or causing problems such as spikes. To prevent such problems, a barrier layer 13 acting as a barrier may be formed between the insulating layer 12 and the metal electrode 14 during the manufacturing process of the semiconductor device. The barrier layer 13 may include a metal material (e.g., Ti, Ta, TiN, TaN, TiOx, TaOx, W, WN, WO, etc.).

[0006] However, if a metal electrode 14 is formed on the barrier layer 13 after the barrier layer 13 is formed, the conformality of the barrier layer 13 is reduced, and foreign matter (e.g., H2 or D2) may be present inside the barrier layer 13. The reduction in electrical characteristics due to the low quality of the barrier layer 13 may also reduce the electrical characteristics of the metal electrode 14, resulting in a problem of reduced electrical characteristics of the semiconductor device. Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present invention is to provide a method for manufacturing a semiconductor device that can improve the quality of a barrier layer during the manufacturing process of a semiconductor device, thereby improving the electrical properties of the barrier layer and metal electrodes.

[0008] The objects of the present specification are not limited to those mentioned above, and other objects and advantages of the present specification not mentioned above can be more clearly understood from the examples of the present specification described below. In addition, the objects and advantages of the present specification can be realized by the elements and combinations thereof described in the claims. [Means for solving the problem]

[0009] A method for manufacturing a semiconductor device according to an embodiment may include forming an insulating layer, forming a barrier layer on the insulating layer, performing a nitridation process on the barrier layer, and forming a metal electrode on the barrier layer.

[0010] In one embodiment, the nitriding process may include performing a high pressure nitridation (HPN) process.

[0011] In one embodiment, the HPN process can be performed in a chamber in which a reactive gas containing nitrogen is injected in an inert gas atmosphere.

[0012] In one embodiment, when the HPN process is performed, the concentration of the reactive gas in the chamber may be 5% or more.

[0013] In one embodiment, when the HPN process is performed, the internal pressure of the chamber may be maintained at 2 to 50 atmospheres.

[0014] In one embodiment, the internal temperature of the chamber may be maintained at 200 to 1000° C. when the HPN process is performed.

[0015] The method for manufacturing a semiconductor device according to an embodiment may further include performing a high pressure anneal (HPA) process on the barrier layer.

[0016] In one embodiment, the HPA process can be performed in a chamber where a reactive gas containing hydrogen is injected in an inert gas atmosphere.

[0017] In one embodiment, when the HPA process is performed, the concentration of the reactive gas in the chamber may be 5% or more.

[0018] In one embodiment, when the HPA process is performed, the internal pressure of the chamber may be maintained at 2 to 50 atmospheres.

[0019] In one embodiment, the internal temperature of the chamber may be maintained at 200 to 1000° C. when the HPA process is performed. [Effects of the Invention]

[0020] According to the embodiment, by improving the quality of the barrier layer during the manufacturing process of the semiconductor device, the electrical properties of the barrier layer and the metal electrode can be improved, and thus the electrical properties of the semiconductor device can also be improved. [Brief explanation of the drawings]

[0021] [Figure 1] 1 is a diagram showing the structure of a typical semiconductor element. [Figure 2] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Figure 3] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Figure 4] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to another embodiment. [Figure 5] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to another embodiment. [Figure 6] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to another embodiment. [Figure 7] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to another embodiment. [Figure 8] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to another embodiment. [Figure 9] 1 is a graph showing resistance values ​​of a barrier layer measured when a voltage is applied to a conventional semiconductor device and a semiconductor device according to an embodiment. [Figure 10] 1 is a graph showing resistance values ​​of metal electrodes measured when voltages are applied to a conventional semiconductor device and a semiconductor device according to an embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0022] The above-mentioned objects, features, and advantages will be described in detail below with reference to the accompanying drawings, so that those skilled in the art can easily implement the embodiments of the present specification. In describing the present specification, if a detailed description of known technologies related to the present specification is deemed to obscure the gist of the present specification, the detailed description will be omitted. Hereinafter, preferred embodiments of the present specification will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings indicate the same or similar components.

[0023] 2 and 3 show a process for manufacturing a semiconductor device according to one embodiment.

[0024] As shown in FIGS. 2 and 3, in the method for manufacturing a semiconductor device according to an embodiment, an insulating layer 22 is formed on a substrate 21, and a barrier layer 23 is formed on the insulating layer 22.

[0025] In one embodiment, the substrate 21 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0026] In one embodiment, the insulating layer 22 may be a silicon oxide film formed by a thermal oxidation process or a silicon oxide film formed using a deposition technique.

[0027] In one embodiment, the barrier layer 23 may include a metal material (e.g., Ti, Ta, TiN, TaN, TiOx, TaOx, W, WN, WO, etc.).

[0028] After the barrier layer 23 is formed, a nitridation process is performed on the barrier layer 23 24. By performing the nitridation process on the barrier layer 23, the content of nitrogen (N) components inside the barrier layer 23 can be increased and impurities inside the barrier layer 23 can be removed. In addition, by performing the nitridation process on the barrier layer 23, the conformality of the barrier layer 23 can be improved.

[0029] In one embodiment, the nitridation process performed on the barrier layer 23 may include a HPN (High Pressure Nitridation) process.

[0030] In one embodiment, the HPN process can be performed in a chamber in which a reactive gas containing nitrogen is injected in an inert gas atmosphere.

[0031] Examples of inert gases include N2, Ar, and He, but the type of inert gas is not limited to these.

[0032] Examples of reactive gases containing nitrogen include NH2 and NH3, but the types of reactive gases containing nitrogen are not limited to these.

[0033] In one embodiment, when the HPN process is performed, the concentration of the nitrogen-containing reactive gas in the chamber may be 5% or more, for example, when the HPN process is performed, the concentration of the nitrogen-containing reactive gas in the chamber may be 5% to 100%.

[0034] In one embodiment, when the HPN process is performed, the internal pressure of the chamber may be maintained at 2 to 50 atmospheres.

[0035] In one embodiment, the internal temperature of the chamber may be maintained at 200 to 1000° C. when the HPN process is performed.

[0036] When the nitridation process is performed on the barrier layer 23 as described above, the conformality of the barrier layer 23 is increased, which may improve the electrical properties of the barrier layer 23. Furthermore, when the barrier layer 23 has high conformality, the conformality of the metal electrode 25 formed on the barrier layer 23 is also increased, which may improve the electrical properties of the metal electrode 25.

[0037] After the nitridation step 24 is performed on the barrier layer 23, a metal electrode 25 may be formed on the nitrided barrier layer 23.

[0038] The metal electrode 25 may be formed by a PVD (Physical Vapor Deposition) process such as plasma sputtering or evaporation, but the method for forming the metal electrode 25 is not limited thereto. For example, the metal electrode 25 may include a metal material such as W, Al, Ti, Ta, Co, Mo, Ru, or Cu.

[0039] Meanwhile, according to another embodiment, a high pressure anneal (HPA) process may be performed on the barrier layer 23 .

[0040] In one embodiment, the HPA process can be performed in a chamber where a reactive gas containing hydrogen is injected in an inert gas atmosphere.

[0041] Examples of inert gases include N2, Ar, and He, but the type of inert gas is not limited to these.

[0042] Examples of reactive gases containing hydrogen include H2 and D2, but the types of reactive gases containing hydrogen are not limited to these.

[0043] In one embodiment, when the HPA process is performed, the concentration of the reactive gas containing hydrogen in the chamber may be 5% or more, for example, when the HPN process is performed, the concentration of the reactive gas containing hydrogen in the chamber may be 5% to 100%.

[0044] In one embodiment, when the HPA process is performed, the internal pressure of the chamber may be maintained at 2 to 50 atmospheres.

[0045] In one embodiment, the internal temperature of the chamber may be maintained at 200 to 1000° C. when the HPA process is performed.

[0046] In one embodiment, the HPA process may be performed on the barrier layer 23, followed by the HPN process on the barrier layer 23. In another embodiment, the HPN process may be performed on the barrier layer 23, followed by the HPA process on the barrier layer 23.

[0047] When the HPA and HPN processes are performed on the barrier layer 23 together, the conformality of the barrier layer 23 and the conformality of the metal electrode 25 are further improved compared to when only the HPN process is performed on the barrier layer 23. This can further improve the electrical properties of the barrier layer 23 and the metal electrode 25.

[0048] 4 to 8 show a manufacturing process of a semiconductor device according to another embodiment.

[0049] Referring to FIG. 4, sacrificial layers 112 and insulating layers 110 may be alternately and repeatedly deposited on a substrate 100 to form a thin film structure (TS).

[0050] In one embodiment, the substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0051] In one embodiment, the sacrificial layers 112 may be formed to have the same thickness, but in other embodiments, the bottom and top sacrificial layers 112 among the sacrificial layers 112 may be formed to be thicker than the sacrificial layers 112 located between them.

[0052] In one embodiment, the insulating layers 110 may have the same thickness. In another embodiment, some of the insulating layers 110 may have different thicknesses.

[0053] In one embodiment, the sacrificial layer 112 and the insulating layer 110 may be formed using a thermal chemical vapor deposition (thermal CVD), a plasma enhanced chemical vapor deposition (plasma enhanced CVD), a physical chemical vapor deposition (physical CVD), or an atomic layer deposition (ALD) process.

[0054] In one embodiment, the sacrificial layer 112 and the insulating layer 110 may include materials having different etching selectivities. For example, the sacrificial layer 112 may be at least one of a silicon film, a silicon oxide film, a silicon carbide film, a silicon oxynitride film, and a silicon nitride film. The insulating layer 110 may be at least one of a silicon film, a silicon oxide film, a silicon carbide film, a silicon oxynitride film, and a silicon nitride film, but may be a different material from the sacrificial layer 112. For example, the sacrificial layer 112 may be formed of a silicon nitride film, and the insulating layer 110 may be formed of a silicon oxide film. However, according to another embodiment, the sacrificial layer 112 may be formed of a conductive material, and the insulating layer 110 may be formed of an insulating material.

[0055] Through holes (H) may be formed through the thin film structure (TS) to expose the substrate 100. The through holes (H) may be formed two-dimensionally on the upper surface of the thin film structure (TS) from a planar perspective. According to one embodiment, the through holes (H) may be arranged along the first direction (D1). However, according to another embodiment, the through holes (H) may be arranged in a zigzag pattern along the first direction (D1).

[0056] Forming the through holes (H) may include forming a first mask pattern (not shown) having openings defining regions where the through holes (H) will be formed on the thin film structure (TS), and anisotropically etching the thin film structure (TS) using the first mask pattern as an etching mask. The first mask pattern may be formed of a material that is selective to the sacrificial layer 112 and the insulating layer 110. The etching process may over-etch the top surface of the substrate 100, resulting in a recess in the upper portion of the substrate 100.

[0057] Next, as shown in FIG. 5, a charge storage structure 150 and a first semiconductor pattern 160 may be formed to cover the inner walls of each of the through holes H and expose the substrate 100 .

[0058] Specifically, a charge storage structure film (not shown) and a first semiconductor film (not shown) may be sequentially formed to cover the inner walls of each through hole (H). The charge storage structure film and the first semiconductor film may be formed to fill a portion of each through hole (H). Each through hole (H) may not be completely filled with the charge storage structure film and the first semiconductor film.

[0059] A charge storage structure film can cover the top surface of the substrate 100 exposed by the through-holes (H). The charge storage structure film can be deposited using plasma enhanced chemical vapor deposition (CVD), physical chemical vapor deposition (physical CVD), or atomic layer deposition (ALD) techniques, in one example.

[0060] A first semiconductor film may be formed on the charge storage structure film. According to one embodiment, the first semiconductor film may be a semiconductor material formed using one of atomic layer deposition (ALD) or chemical vapor deposition (CVD) techniques. The first semiconductor film may be, for example, a polycrystalline silicon film. According to one embodiment, the first semiconductor film is amorphous when deposited, but may be crystallized using an annealing process or the like.

[0061] After the charge storage structure layer and the first semiconductor layer are sequentially formed, the charge storage structure layer and the first semiconductor layer may be anisotropically etched to expose the substrate 100. As a result, the first semiconductor pattern 160 and the charge storage structure 150 may be formed on the inner walls of each of the through holes (H). That is, the charge storage structure 150 and the first semiconductor pattern 160 may be formed in a cylindrical shape with open ends. Over-etching during the anisotropic etching of the first semiconductor layer and the charge storage structure layer may result in recessing of the upper surface of the substrate 100 exposed by the first semiconductor pattern 160 and the charge storage structure 150.

[0062] In one embodiment, the charge storage structure 150 may include a tunnel insulating layer, a charge storage layer, and a blocking insulating layer sequentially stacked between the first semiconductor pattern 160 and the thin film structure (TS). The blocking insulating layer, the charge storage layer, and the tunnel insulating layer may be sequentially deposited on the inner walls of the through holes (H) using plasma enhanced chemical vapor deposition (PCVD), physical chemical vapor deposition (PCVD), or atomic layer deposition (ALD) techniques.

[0063] Next, a second semiconductor pattern 165 and a buried insulating pattern 170 may be formed to fill the remaining portions of the through holes (H).

[0064] Specifically, a second semiconductor layer (not shown) and a buried insulating layer (not shown) may be sequentially formed on the substrate 100 on which the charge storage structure 150 and the first semiconductor pattern 160 are formed.

[0065] The second semiconductor film may be formed to a thickness that does not completely fill each of the through holes (H). The second semiconductor film may cover the inner walls of each of the through holes (H) and may cover the top surface of the substrate 100 exposed by the charge storage structure 150 and the first semiconductor pattern 160. The second semiconductor film may connect the substrate 100 and the first semiconductor pattern 160.

[0066] The second semiconductor film may be a semiconductor material formed using one of atomic layer deposition (ALD) and chemical vapor deposition (CVD) techniques. The second semiconductor film may be a polycrystalline silicon film, for example. According to one embodiment, the second semiconductor film is amorphous when deposited, but may be crystallized using an annealing process or the like. The buried insulating film may be formed to completely fill each of the through holes (H). The buried insulating film may be at least one of an insulating material formed using a silicon oxide (SOG) technique and a silicon dioxide film.

[0067] The buried insulating film and the second semiconductor film may be planarized to form a second semiconductor pattern 165 and a buried insulating pattern 170 in each through hole (H). The planarization process may allow the second semiconductor pattern 165 and the buried insulating pattern 170 to be formed locally in each through hole (H). The first and second semiconductor patterns 160 and 165 may be defined as semiconductor patterns (SP).

[0068] Next, as shown in FIG. 6, the thin film structure (TS) may be patterned to form trenches (T) exposing the substrate 100 between adjacent through holes (H).

[0069] Forming the trench (T) may include forming a second mask pattern (not shown) on the thin film structure (TS) that defines the planar position where the trench (T) is to be formed, and anisotropically etching the thin film structure (TS) using the second mask pattern as an etching mask.

[0070] The trenches (T) may be formed to be spaced apart from the semiconductor patterns (SP) and to expose sidewalls of the sacrificial layer 112 and the insulating layer 110. From a horizontal perspective, the trenches (T) may be formed in a line or a rectangle, and from a vertical depth, the trenches (T) may be formed to expose the top surface of the substrate 100. During the etching process, the top of the substrate 100 may be over-etched, resulting in a recess.

[0071] Unlike the illustration, the trench T may have a width that varies depending on the distance from the substrate 100 by an anisotropic etching process. That is, the width of the bottom of the trench T may be narrower than the width of the top of the trench T.

[0072] Next, the sacrificial layer 112 exposed by the trench (T) may be removed to form a recess region (R) between the insulating layers 110. The recess region (R) may be formed by isotropically etching the sacrificial layer 112 using etching conditions having etching selectivity with respect to the insulating layer 110, the charge storage structure 150, the semiconductor pattern (SP), the lower insulating film 105, and the substrate 100. The sacrificial layer 112 may be completely removed by the isotropic etching process. For example, when the sacrificial layer 112 is a silicon nitride film and the insulating layer 110 is a silicon oxide film, the etching process may be performed using an etching solution containing phosphoric acid.

[0073] A barrier layer 200 is then formed within each recess region (R), as shown in the enlarged view 300 of Figure 7. The barrier layer 200 may be formed over the insulating layer 110 and the charge storage structure 150.

[0074] In one embodiment, the barrier layer 200 may include a metallic material (e.g., Ti, Ta, TiN, TaN, TiOx, TaOx, W, WN, WO, etc.).

[0075] After the barrier layer 200 is formed, a nitridation process is performed on the barrier layer 200 202. By performing the nitridation process on the barrier layer 200, the content of nitrogen (N) components inside the barrier layer 200 can be increased and internal impurities of the barrier layer 200 can be removed. In addition, by performing the nitridation process on the barrier layer 200, the conformality of the barrier layer 200 can be increased.

[0076] In one embodiment, the nitridation process performed on the barrier layer 200 may include a HPN process.

[0077] In one embodiment, the HPN process can be performed in a chamber where a reactive gas containing nitrogen is injected in an inert gas atmosphere.

[0078] Examples of inert gases include N2, Ar, and He, but the type of inert gas is not limited to these.

[0079] Examples of reactive gases containing nitrogen include NH2 and NH3, but the types of reactive gases containing nitrogen are not limited to these.

[0080] In one embodiment, when the HPN process is performed, the concentration of the nitrogen-containing reactive gas in the chamber may be 5% or more, for example, when the HPN process is performed, the concentration of the nitrogen-containing reactive gas in the chamber may be 5% to 100%.

[0081] In one embodiment, when the HPN process is performed, the internal pressure of the chamber may be maintained at 2 to 50 atmospheres.

[0082] In one embodiment, the internal temperature of the chamber may be maintained at 200 to 1000° C. when the HPN process is performed.

[0083] The nitridation process for the barrier layer 200 as described above increases the conformality of the barrier layer 200, which may improve the electrical properties of the barrier layer 200. Furthermore, when the barrier layer 200 has high conformality, the conformality of the metal electrode 204 formed on the barrier layer 200 also increases, which may improve the electrical properties of the metal electrode 204.

[0084] After the nitridation step 24 is performed on the barrier layer 200 , a metal electrode 204 may be formed on the nitrided barrier layer 200 .

[0085] The metal electrode 204 may be formed by a PVD process such as plasma sputtering or evaporation, but the method for forming the metal electrode 204 is not limited thereto. For example, the metal electrode 204 may include a metal material such as W, Al, Ti, Ta, Co, Mo, Ru, or Cu.

[0086] Meanwhile, according to another embodiment, the barrier layer 200 may be subjected to an HPA process.

[0087] In one embodiment, the HPA process can be performed in a chamber where a reactive gas containing hydrogen is injected in an inert gas atmosphere.

[0088] Examples of inert gases include N2, Ar, and He, but the type of inert gas is not limited to these.

[0089] Examples of reactive gases containing hydrogen include H2 and D2, but the types of reactive gases containing hydrogen are not limited to these.

[0090] In one embodiment, when the HPA process is performed, the concentration of the reactive gas containing hydrogen in the chamber may be 5% or more, for example, when the HPA process is performed, the concentration of the reactive gas containing hydrogen in the chamber may be 5% to 100%.

[0091] In one embodiment, when the HPA process is performed, the internal pressure of the chamber may be maintained at 2 to 50 atmospheres.

[0092] In one embodiment, the internal temperature of the chamber may be maintained at 200 to 1000° C. when the HPA process is performed.

[0093] In one embodiment, the HPA process may be performed on the barrier layer 200, followed by the HPN process on the barrier layer 200. In another embodiment, the HPN process may be performed on the barrier layer 200, followed by the HPA process on the barrier layer 200.

[0094] When the barrier layer 200 is subjected to both the HPA and HPN processes, the conformality of the barrier layer 200 and the conformality of the metal electrode 204 are further improved compared to when only the HPN process is performed on the barrier layer 200. This can further improve the electrical properties of the barrier layer 200 and the metal electrode 204.

[0095] Through these processes, a semiconductor device as shown in FIG. 8 can be completed.

[0096] FIG. 9 is a graph showing the resistance values ​​of the barrier layers measured when a voltage is applied to a conventional semiconductor device and a semiconductor device according to an embodiment.

[0097] 9 is the normal semiconductor element shown in FIG. 1, that is, a semiconductor element in which the HPN process or the HPA process has not been performed on the barrier layer 13. M2 in FIG. 9 is a semiconductor element having the same structure as FIG. 3, in which the HPN process has been performed on the barrier layer 23. M3 in FIG. 9 is a semiconductor element having the same structure as FIG. 3, in which the HPA process and the HPN process have been performed on the barrier layer 23.

[0098] 9, the resistance of the barrier layer 13 when a voltage is applied to the semiconductor element M1 is greater than the resistance of the barrier layer 23 when a voltage is applied to the semiconductor element M2. These results show that when the HPN process is applied to the barrier layer, the conformality of the barrier layer is improved, thereby reducing the resistance of the barrier layer.

[0099] 9, the resistance of the barrier layer 23 when a voltage is applied to the semiconductor element M2 is greater than the resistance of the barrier layer 23 when a voltage is applied to the semiconductor element M3. These results show that when the HPA process and the HPN process are both applied to the barrier layer, the conformality of the barrier layer is improved compared to when only the HPN process is applied to the barrier layer, thereby further reducing the resistance of the barrier layer.

[0100] FIG. 10 is a graph showing the resistance values ​​of the metal electrodes measured when a voltage is applied to a conventional semiconductor device and a semiconductor device according to an embodiment.

[0101] M1 in Fig. 10 is the normal semiconductor element shown in Fig. 1, that is, a semiconductor element in which the HPN process or the HPA process has not been performed on the barrier layer 13. M2 in Fig. 10 is a semiconductor element having the same structure as Fig. 3, in which the HPN process has been performed on the barrier layer 23. M3 in Fig. 10 is a semiconductor element having the same structure as Fig. 3, in which the HPA process and the HPN process have been performed on the barrier layer 23.

[0102] 10, the resistance of metal electrode 14 when a voltage is applied to semiconductor element M1 is greater than the resistance of metal electrode 25 when a voltage is applied to semiconductor element M2. These results show that when the HPN process is applied to the barrier layer, the conformality of the metal electrode is improved, thereby reducing the resistance of the metal electrode.

[0103] 10, the resistance of the metal electrode 25 when a voltage is applied to the semiconductor element M2 is greater than the resistance of the metal electrode 25 when a voltage is applied to the semiconductor element M3. This result shows that when the HPA process and the HPN process are both applied to the barrier layer, the conformality of the metal electrode is improved compared to when only the HPN process is applied to the barrier layer, thereby further reducing the resistance of the metal electrode.

[0104] Although the present specification has been described with reference to exemplary drawings, the present invention is not limited to the embodiments and drawings disclosed in the specification, and various modifications can be made by those skilled in the art. Note that even if the effects of the configurations of the specification are not explicitly described in the above-described embodiments of the specification, the effects that can be predicted by the configurations should also be recognized.

Claims

1. forming an insulating layer; forming a barrier layer on the insulating layer; performing a nitridation process on the barrier layer; and forming a metal electrode on the barrier layer; The step of performing the nitriding process includes: The method includes performing a high pressure nitridation (HPN) process. A method for manufacturing semiconductor devices.

2. The HPN process is carried out in a chamber in which a reactive gas containing nitrogen is injected in an inert gas atmosphere. The method for manufacturing a semiconductor device according to claim 1 .

3. When the HPN process is performed, the concentration of the reactive gas in the chamber is 5% or more. The method for manufacturing a semiconductor device according to claim 2 .

4. When the HPN process is performed, the internal pressure of the chamber is maintained at 2 to 50 atmospheres. The method for manufacturing a semiconductor device according to claim 1 .

5. When the HPN process is performed, the internal temperature of the chamber is maintained at 200 to 1000°C. The method for manufacturing a semiconductor device according to claim 1 .

6. The method further includes performing a high pressure anneal (HPA) process on the barrier layer. The method for manufacturing a semiconductor device according to claim 1 .

7. The HPA process is carried out in a chamber into which reactive gases including hydrogen are injected in an inert gas atmosphere. The method for manufacturing a semiconductor device according to claim 6 .

8. When the HPA process is performed, the concentration of the reactive gas in the chamber is 5% or more. The method for manufacturing a semiconductor device according to claim 7 .

9. When the HPA process is performed, the internal pressure of the chamber is maintained at 2 to 50 atmospheres. The method for manufacturing a semiconductor device according to claim 6 .

10. When the HPA process is performed, the internal temperature of the chamber is maintained at 200 to 1000°C. The method for manufacturing a semiconductor device according to claim 6 .

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