Method for fabricating optical structures on a photonic glass layer substrate

Abstract

The embodiments described herein also relate to methods for fabricating electronic and photonic integrated circuits, and integrated interconnects between electrical, optoelectronic, and photonic devices. One or more optical silicon photonic devices described herein can be used in combination with one or more optoelectronic integrated circuits (optoelectronic chips) on a single package substrate to form co-packaged optical and electrical devices. The methods described herein enable the mass production of electrical, optoelectronic, and optical silicon photonic devices with multiple optical structures, such as waveguides, formed on or integrated with a photonic glass layer substrate.

Description

[Technical Field]

[0001]

[0001] Embodiments of the present disclosure generally relate to silicon photonic integrated circuits and co-packaged optical silicon photonic devices. More particularly, the present disclosure relates to an apparatus for co-packaged optical silicon photonic devices and a method for fabricating optical structures for optical silicon photonic devices. [Background technology]

[0002]

[0002] As demand for data traffic networks increases, networking companies that traditionally use copper cables for communication have sought more efficient solutions that can be deployed on a large scale. Today, optical fiber technology is the mainstream in the long-distance communication field. Networking companies have gradually transitioned to using optical fiber for transmitting data over long distances. With the use of optical fiber, data is transmitted at the speed of light at ultra-high frequencies, known as photonics, allowing for the transmission of larger amounts of data.

[0003]

[0003] As data traffic network demands increase, so too do demands for continually increasing data rates in electronic systems and communications. One area of ​​improvement that can help the semiconductor industry balance the ever-increasing operating speeds of integrated circuits with the challenge of providing chip solutions that can keep up with the growing demands of data traffic networks is increasing interconnect speeds. The typical electrical interconnect solution between transistors in conventional integrated circuits remains electrons through copper wiring. Generally, issues with using copper wiring for communications and data transmission include infrared heating and electrons traveling through such wiring interacting with other atoms, slowing the electrons and contributing to signal loss. Therefore, there is an incentive to reduce the use and length of copper interconnects and wiring in communications and data transfer technology solutions. One approach to minimizing the use of copper interconnects is copackaged multichip modules, in which multiple integrated circuit devices are closely assembled on a single package substrate. While such multichip modules have been explored, typical multichip module applications still rely heavily on copper wiring to transmit data to and from the multichip module's printed circuit board.

[0004] Another approach to minimizing the use of copper wiring in electronic communication systems is integration with optical communication system technology. This optical communication system technology has proven advantageous over copper wire for communication and data transmission due to its low signal loss, which depends on the length and data rate. Recently, optical components have been integrated onto silicon (Si) substrates to fabricate large-scale silicon photonics integrated circuits that coexist with microelectronic chips. Optical communication technology typically involves different materials and manufacturing processes from electronic communication technology. However, silicon photonics technology has merged optical communication technology with electronic technology based on a common material platform. Optical transceivers can convert received optical signals into electrical signals that can be processed by integrated circuits and convert the processed electrical signals into optical signals for transmission over optical fibers.

[0005] Therefore, what is needed in the art are improved co-packaged optical silicon photonic devices and methods for fabricating same. Summary of the Invention

[0006]

[0006] Embodiments described herein relate to methods for fabricating electronic and photonic integrated circuits, and integrated interconnects between electrical, optoelectronic, and photonic devices. In one embodiment, a method for fabricating electronic and photonic devices is provided. The method includes depositing a core material layer on a surface of a substrate including a photonic glass layer (PGL) having a first refractive index. The core material layer has a second refractive index different from the first refractive index. A patterned layer is then deposited over the core material layer, with openings formed in the patterned layer that expose portions of the surface of the core material layer. The method continues by removing portions of the core material exposed in the openings in the patterned layer to form a plurality of optical structures. Each of the plurality of optical structures includes a waveguide configured to transmit light between a first edge and a second edge of the substrate, and each of the waveguides of the plurality of optical structures extends in one or more directions between the first edge and the second edge.

[0007] In one embodiment, a method for fabricating electronic and photonic devices is provided. The method includes depositing a patterned layer over a surface of a substrate including a photonic glass layer, the photonic glass layer having a first refractive index, the patterned layer having openings formed therein that expose portions of the surface of the substrate. The portions of the substrate exposed in the openings in the patterned layer are then removed to form a plurality of structures in the substrate separated by a plurality of trenches. The method continues with removing the patterned layer and depositing a fill layer having a second refractive index different from the first refractive index within the plurality of trenches to cover the plurality of structures to form a plurality of optical structures. Each of the plurality of optical structures includes a waveguide configured to transmit light between a first edge and a second edge of the substrate, and each of the waveguides of the plurality of optical structures extends in one or more directions extending between the first edge and the second edge.

[0008] In another embodiment, a method for fabricating electronic and photonic devices is provided. The method includes depositing a patterned layer over a surface of a substrate including a photonic glass layer, the photonic glass layer having a first refractive index, the patterned layer having an opening formed therein through which a portion of the surface of the substrate is exposed. The method then continues by performing an ion implantation process on the exposed portion of the substrate to implant a plurality of doping ions into the surface of the exposed portion of the substrate. The exposed portion of the substrate including the plurality of doping ions defines a plurality of optical structures having a second refractive index different from the first refractive index. Each of the plurality of optical structures also includes a waveguide configured to transmit light between a first edge and a second edge of the substrate, and each of the waveguides of the plurality of optical structures extends in one or more directions extending between the first edge and the second edge.

[0009] In another embodiment, an electronic and photonic device assembly is provided having a substrate with a chip mounting area configured to receive a photonic transceiver chip (which provides, among other functions, electrical-to-optical and optical-to-electrical conversion) and a fiber connector area configured to be coupled to a fiber connector, the substrate further including a plurality of optical structures between the optical transceiver chip and the fiber connector, each of the plurality of optical structures operable to transmit light between a first end of each of the plurality of optical structures configured to receive light transmitted from or received by a plurality of waveguides of the optical transceiver chip and a second end of each of the plurality of optical structures configured to receive light transmitted from a plurality of optical fibers of the fiber connector or received by an optical fiber of the fiber connector connected to the substrate.

[0010] In another embodiment, a co-packaged electronic and photonic device is provided. The co-packaged electronic and photonic device includes a package substrate, one or more electrical or opto-electrical integrated circuits mounted on the package substrate, and one or more electronic and photonic devices mounted on the package substrate, each of the one or more electronic and photonic devices connected to one or more of the electrical or opto-electrical integrated circuits. Each of the one or more electronic and photonic devices also includes an optical transceiver chip mounting region configured to receive an optical transceiver chip and a fiber connector region configured to be coupled to a fiber connector. The support substrate of the one or more electronic and photonic devices also includes a plurality of optical structures formed within the support substrate and operable to transmit light between a first end and a second end of the support substrate.

[0011] In one embodiment, a method for fabricating electronic and photonic devices is provided. The method includes depositing a patterned layer over a surface of a substrate including a photonic glass layer, the photonic glass layer having a first refractive index, the patterned layer having openings formed therein that expose portions of the surface of the substrate. The portions of the substrate exposed in the openings in the patterned layer are then removed to form a plurality of structures in the substrate separated by a plurality of trenches. The method then continues with removing the patterned layer and depositing a fill layer having a second refractive index different from the first refractive index within the plurality of trenches to cover the plurality of structures to form a plurality of optical structures. Each of the plurality of optical structures includes a waveguide configured to transmit light between a first edge and a second edge of the substrate, and each of the waveguides of the plurality of optical structures extends in one or more directions extending between the first edge and the second edge.

[0012] In another embodiment, a method for fabricating electronic and photonic devices is provided. The method includes depositing a patterned layer over a surface of a substrate including a photonic glass layer, the photonic glass layer having a first refractive index, the patterned layer having an opening formed therein through which a portion of the surface of the substrate is exposed. The method then continues by performing an ion implantation process on the exposed portion of the substrate to implant a plurality of doping ions into the surface of the exposed portion of the substrate. The exposed portion of the substrate including the plurality of doping ions defines a plurality of optical structures having a second refractive index different from the first refractive index. Each of the plurality of optical structures also includes a waveguide configured to transmit light between a first edge and a second edge of the substrate, and each of the waveguides of the plurality of optical structures extends in one or more directions extending between the first edge and the second edge.

[0013]

[0013] So that the above-mentioned features of the present disclosure can be understood in detail, a more particular description of the present disclosure briefly summarized above can be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only exemplary embodiments and therefore should not be considered as limiting the scope of the present disclosure, which may also admit of other equally effective embodiments. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a perspective view of at least a portion of a package substrate having one or more optical silicon photonic devices formed thereon, according to an embodiment. [Figure 2A]

[0015] FIG. 1 illustrates a top view of a photon engine according to an embodiment. [Figure 2B] FIG. 1 illustrates a top view of a photon engine according to an embodiment. [Figure 3]

[0016] 1A-E are schematic cross-sectional views of portions of one or more optical silicon photonic devices, according to embodiments. [Figure 4]

[0017] AG are schematic cross-sectional views of portions of one or more optical silicon photonic devices, according to embodiments. [Figure 5]

[0018] 1A-E are schematic cross-sectional views of portions of one or more optical silicon photonic devices, according to embodiments. [Figure 6]

[0019] 1 is a flow diagram illustrating method steps for fabricating an optical device on a photonic glass layer substrate, according to an embodiment. [Figure 7]

[0020] 1 is a flow diagram illustrating method steps for fabricating an optical device on a photonic glass layer substrate, according to an embodiment. [Figure 8]

[0021] 1 is a flow diagram illustrating method steps for fabricating an optical device on a photonic glass layer substrate, according to an embodiment. [Figure 9]

[0022] 11 is a schematic cross-sectional view of a portion of a photon engine formed using cross-section line CC of FIG. 10, according to an embodiment. [Figure 10]

[0023] 2B is a schematic cross-sectional view of a portion of a photon engine formed using cross-section line BB of FIG. 2A, according to an embodiment. [Figure 11]

[0024] 2B is a schematic alternative cross-sectional view of a portion of a photon engine formed using cross-section line BB of FIG. 2A, according to an embodiment. [Figure 12]

[0025] 2B is a schematic cross-sectional view of a portion of a pluggable connector formed using section line BB of FIG. 2A, according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015]

[0026] For ease of understanding, wherever possible, like reference numerals have been used to designate like elements common to the figures. It is contemplated that components and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0016]

[0027]

[0003] Embodiments of the present disclosure provided herein relate to optical silicon photonic devices and methods for fabricating optical silicon photonic devices. The methods described herein enable mass production and manufacturing of optical silicon photonic devices having a plurality of optical structures formed on a photonic glass layer substrate. The optical silicon photonic device further includes a silicon photonic chip mounted on the photonic glass layer substrate and connected to the plurality of optical structures. The plurality of optical structures optically connect the silicon photonic chip to a fiber connector configured to connect to an external fiber and operate to propagate optical signals between the fiber connector and the silicon photonic chip.

[0017]

[0028] The embodiments described herein also relate to methods for fabricating electronic and photonic integrated circuits, and integrated interconnects between electrical, optoelectronic, and photonic devices. One or more optical silicon photonic devices described herein can be used in combination with one or more optoelectronic integrated circuits (optoelectronic chips) on a single package substrate to form co-packaged optical and electrical devices. The methods described herein enable the mass production of electrical, optoelectronic, and optical silicon photonic devices with multiple optical structures, such as waveguides, formed on or integrated with a photonic glass layer substrate.

[0018]

[0029] One embodiment of the copackaged optical and electrical device described herein includes a package substrate on which one or more optical silicon photonic devices and one or more opto-electrical chips are formed. The one or more optical silicon photonic devices are connected to the one or more opto-electrical chips, providing an interface that operably connects the opto-electrical chips to external network fiber connections plugged into the optical silicon photonic device. The methods described herein provide a scalable process for fabricating optical silicon photonic devices with optical structures of various sizes, materials, and characteristics that are on or integrated with the photonic glass layer substrate. Additionally, fabrication of the optical silicon photonic devices described herein can be configurable based on varying electro-optical photonic circuits and network fiber connection characteristics in which the optical silicon photonic devices may be used.

[0019]

[0030] As used herein, the term "about" refers to a ±10% variation from the nominal value. It is understood that such a variation can be included in any value provided herein.

[0020]

[0031] In various embodiments of the present disclosure, layers or other materials are referred to as being deposited. It is understood that deposition of these materials can be performed using any conventional method used in semiconductor manufacturing, such as, but not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, selective deposition of any of the above, combinations of the above, and any other suitable method. When a method step is described herein as depositing material at two or more separate locations, it is understood that the deposition can occur simultaneously or the materials can be deposited in separate substeps.

[0021]

[0032] In various embodiments of the present disclosure, layers or other materials are referred to as being etched. It is understood that etching of these materials can be performed using any conventional method used in semiconductor manufacturing, such as, but not limited to, reactive ion etching (RIE), dry etching, wet etching, or laser ablation, combinations of the above, and any other suitable method of removing material. When a method step is described herein as etching two or more materials, it is understood that the etching can be performed simultaneously using the same etching process or in separate substeps using different etching processes. For example, a step describing etching a metal and a dielectric includes a first etching substep using a first etching process to etch the metal, which further includes a second etching substep using a second etching process to etch the dielectric.

[0022]

[0033] FIG. 1 is a perspective view of a portion of an exemplary co-packaged optical and electrical device 100 including an electrical or opto-electrical chip 102 connected to a photonic integrated interconnect unit 103 by multiple optical waveguide or electrical trace interconnects 104, all formed on or disposed on a package substrate 101. In one embodiment, the electrical or opto-electrical chip 102 may include any high-density chip having a high I / O pin count. In one example, a high-density chip has between 100 and 2000 I / O pins, or up to 2000 I / O pins. Examples of electrical or opto-electrical chips 102 include, but are not limited to, data center switch chips, artificial intelligence (AI) chips, etc.

[0023]

[0034] The photonic integrated interconnect unit 103 includes a fiber connector region configured to be coupled to a fiber connector 112 for removably connecting a fiber cable 120 to the photonic integrated interconnect unit 103. In one embodiment, the fiber cable 120 may be plugged into the fiber connector 112 to operably connect the fiber cable 120 to the co-packaged optical and electrical device 100. In one embodiment, the photonic integrated interconnect unit 103 is configured to connect fiber cables 120, including, but not limited to, single-mode optical fiber cables having a fiber core diameter of 9 microns. The fiber connector 112 may further include a plurality of optical fibers 112A ( FIG. 10 ) for operably connecting fiber cables 120 having between 1 and 74 fiber cores, between 74 and 148 fiber cores, and up to 148 or more fiber cores to the photonic integrated interconnect unit 103.

[0024]

[0035] In one embodiment, the photonic integrated interconnect unit 103 in the set of co-packaged electrical and optical devices 100 is configured to transmit signals between the electrical or opto-electrical chip 102 and a fiber cable 120 connected to the photonic integrated interconnect unit 103. The photonic integrated interconnect unit 103 includes a photonic glass layer (PGL) substrate 106 and a plurality of optical structures 1101-110 integrated with or formed on the PGL substrate 106. N and a plurality of optical structures 1101 to 110 mounted on a PGL substrate 106 and connected to a first interface 107. N and a second interface 109 connecting the PGL substrate 106 and a plurality of optical structures 1101-110. N and a fiber connector 112 connected to both of the optical fiber 110 and the optical fiber 112 .

[0025]

[0036] In one embodiment, the SiPho chip 108 of the photonic integrated interconnect unit 103 operates to convert electrical signals into optical signals and vice versa. N operates to transmit optical signals between the SiPho chip 108 and the fiber connector 112, and the optical waveguide or electrical trace interconnect 104 operates to transmit electrical or optical signals between the photonic integrated interconnect unit 103 (specifically, the SiPho chip 108) and the electrical or opto-electrical chip 102. The optical waveguide or electrical trace interconnect 104 may include metal traces formed within the package substrate 101, which in some embodiments may include metal traces formed within a printed circuit board (PCB) or metal traces formed within multiple redistribution layers (e.g., dielectric-containing layers) formed on a solid core substrate (e.g., a silicon or glass core substrate).

[0026]

[0037] The photon engine 103 may optionally further include one or more electronic physical chips 111 coupled to the SiPho chip 108. The electronic physical chip 111 is generally used to support the processes performed by the optical chip. In one embodiment, the electronic physical chip 111 is operably connected to the SiPho chip 108 and supports various electrical functions of the SiPho chip 108. As shown, the electronic physical chip 111 may be mounted on top of the SiPho chip 108 and thereby directly connected to the SiPho chip 108. Alternatively, the electronic physical chip 111 may be embedded in the PGL substrate 106 and connected to the SiPho chip 108 through the PGL substrate 106 (often referred to herein simply as substrate 106). Additionally, the electronic physical chip 111 may be mounted on or embedded in the package substrate 101 and connected to the SiPho chip 108 through electrical interconnects 104.

[0027]

[0038] 2A and 2B are top views of a photon engine 103 according to embodiments. In some embodiments, as shown in FIG. 2A, the photon engine 103 includes a SiPho chip 108 mounted near one end of a PGL substrate 106, a fiber connector 112 connected to the end of the PGL substrate 106 opposite the SiPho chip 108, and a plurality of optical structures 1101-110 extending between the SiPho chip 108 and the fiber connector 112. N In one embodiment, the plurality of optical structures 1101-110 N Each of the optical structures 1101-110 includes an optical transmission region for transmitting light in either direction between the first interface 107 and the second interface 109. Light transmitted through the optical structures may be received either from one or more of the plurality of waveguides 108A (FIG. 2B) of the SiPho chip 108, or from one or more of the plurality of optical fibers in the fiber connector 112 with which the optical signal source communicates during use. The SiPho chip 108 typically includes optical structures 1101-110 for communicating with an external device connected through the optical fiber connector 112. Nand receiving (e.g., detecting) light transmitted through the optical structures 1101-110. N The SiPho chip 108 is configured to emit (e.g., transmit) light to the optical structures 1101-110 through the use of at least one light emitter integrated into the SiPho chip 108 or through the use of a light emitter external to the PGL substrate 106. N When the light emitters are external to the PGL substrate 106, the light is transmitted through the optical structures 1101-110. N , which is then modulated by the SiPho chip 108 and transmitted to the optical structures 1101-110. N creates a transmit signal that is fed to

[0028]

[0039] In some embodiments, which may be combined with other embodiments described herein, a plurality of optical structures 1101-110 N are formed (e.g., directly or indirectly) on or integrated with the PGL substrate 106. Multiple optical structures 1101-110 within the photon engine 103 N Each of may be formed by one of the various methods described herein.

[0029]

[0040] In one embodiment, which can be combined with other embodiments described herein, a plurality of optical structures 1101-110 N The light-transmitting regions within each of the optical structures 1101-110 may have the same cross-sectional dimensions, such as height and width. N The light-transmitting region within at least one of the optical structures 110 may differ in at least one cross-sectional dimension (such as one of height and width) from the dimensions of the other optical structures 110 within the PGL substrate 106. In one embodiment, which can be combined with other embodiments described herein, multiple optical structures 1101-110 N In another embodiment, which can be combined with other embodiments described herein, the optically transmitting regions within each of the optical structures 1101-110 may have the same refractive index.N At least one of the internal light transmitting regions is formed by a plurality of optical structures 1101-110 in the PGL substrate 106. N The first and second portions of the first and second layers may have a different refractive index or multiple different refractive indices, or a step change in refractive index or other refractive index variation structure, compared to the rest of the first and second layers.

[0030]

[0041] In one embodiment, optical structures 1101-110 formed in PGL substrate 106 N The number of interconnects 1101-110 in the photonic glass layer substrate 106 depends on the number of waveguides 108A in the SiPho chip 108 that need to be connected, which may also correspond to the number of fiber connections that need to be connected to the opto-electrical chip 102. In one embodiment, the opto-electrical chip 102 may include 72 fiber connections, such that 72 corresponding interconnects 104 extend from the opto-electrical chip 102 and connect to 72 corresponding fibers and waveguides 108A in the SiPho chip 108 of the photon engine 103. N To properly connect the SiPho chip 108 to the fiber connector 112 via the optical fiber 110, 72 corresponding optical structures 110 are formed on or integrated into the PGL substrate 106. In this example, N equals 72, as shown in FIGS. 2A and 2B, and therefore the optical structures 110 are spaced apart in the XY plane from one edge of the PGL substrate 106 to the other edge of the PGL substrate 106. In this example, optical structure 1101 is located near the top edge. And, optical structures 110 72 2A. As further described below, optical structures 1101-110 N Optical structure 1101-110 N The optical transmission section is separated from the optical transmission section by a material with different optical properties, such as a refractive index (n).

[0031]

[0042] Multiple optical structures 1101-110 Nis generally sized and configured to appropriately couple to the plurality of waveguides 108A within the SiPho chip 108. In one embodiment, the plurality of waveguides 108A (FIG. 2B) at the output of the SiPho chip 108, i.e., the portion that communicates with the optical structure, have a core including a height dimension with a cross-sectional size of approximately 1 micron (μm). In one configuration, the output of the SiPho chip 108 has a square or rectangular shaped cross-section with at least one dimension equal to approximately 1 μm, which is length. For example, the square cross-section of the waveguide 108A may have a core with a height and width of 1 μm. Thus, light transmitted to or from the SiPho chip 108 would be transmitted through the 1 micron waveguide 108A.

[0032]

[0043] In contrast, light transmitted to and from fiber cable 120 through fiber connector 112 may have a different form factor, such as having a core cross-sectional dimension of approximately 9 μm in size. For example, fiber connector 112 may have a square, rectangular, or circular cross-section with a core having a height dimension of approximately 9 μm in size. Thus, in some embodiments, multiple optical structures 1101-110 N Each of the optical structures 1101-110 between the SiPho chip 108 and the fiber cable 120 N In one embodiment, a plurality of optical structures 1101-110 extending from the second interface 109 adjacent to the 9 μm fiber in the fiber connector 112 are configured such that light propagating through the optical fiber is expanded or compressed as appropriate depending on the direction of propagation of the optical signal. N Each structure has transmission regions with different cross-sectional areas in different portions of the structure to facilitate coupling to multiple 1 micron waveguides 108A in the SiPho chip 108. In one embodiment, multiple optical structures 1101-110 NThe optical structure 110 tapers along at least a portion of its length from a 9 μm dimensional core size to approaching a 1 μm dimensional core size near the first interface 107. The varying dimensional core size is assumed to be related to the lateral dimensions of the square or rectangular cross-sectional shaped optical structure 110. In some embodiments, the tapered optical structure 110 has a ratio of cross-sectional area as measured at one end of the optical structure 110 to the cross-sectional area as measured at its opposite end that is greater than 1:1, less than about 1:100, or less than 1:81. In another embodiment, multiple optical structures 1101-110 extending from the second interface 109 adjacent the fiber connector 112 are N has a refractive index that varies along at least a portion of its length from the second interface 109 to the first interface 107 to facilitate coupling between optical elements within the SiPho chip 108 having different cross-sectional dimensions and the fiber connector 112.

[0033]

[0044] In another embodiment, the photon engine 103 is configured such that the transmission loss of the optical signal between the first interface 107 and the second interface 109 is reduced by a plurality of optical structures 1101-110. N In one embodiment, the transmission loss is approximately 3 dB or less, including the loss due to transmission of the optical signal through the SiPho chip 108 and the plurality of optical structures 1101-110. N 2B, in one embodiment, the SiPho chip 108 is mounted on the coupling surface 208 of the chip mounting area 204 of the PGL substrate 106. Once mounted on the chip mounting area 204, the plurality of waveguides 108A located on the side 108B of the SiPho chip 108 are coupled to the plurality of optical structures 1101-110 found at the first interface 107. N is aligned with.

[0034]

[0045] In some embodiments, which can be combined with other embodiments described herein, the PGL substrate 106 further includes one or more fiducial marks 206 to aid in the alignment and mounting of the SiPho chip 108 onto the chip mounting area 204. The one or more fiducial marks 206 operate to guide and assist in the positioning of the SiPho chip 108 along the XY plane of the PGL substrate 106, ensuring that the mounting of the SiPho chip 108 is properly aligned with one or more electrical contacts (e.g., via 1006 (FIG. 10)) and optical structures of the PGL substrate 106. Thus, in one embodiment, the SiPho chip 108 and the plurality of optical structures 1101-110 are mounted in a manner that allows for proper alignment of the SiPho chip 108 with the plurality of optical structures 1101-110. N The tolerance for error in coupling or hybrid coupling together at first interface 107, as discussed further below, can be in the range of 0.1 to 2 microns, such that the connection is optimized for minimal signal loss. In one embodiment, the waveguide 108A and the optical structures 1101-110 N The misalignment of the centers of the waveguides 108A and the optical structures 1101-110 is maintained such that the lateral misalignment in the Y direction (i.e., from top to bottom in FIG. 2B) is less than 1-2 microns. N The misalignment of the centers is also maintained such that the vertical misalignment in the Z direction (FIGS. 10 or 11) is less than 1-2 microns. In one embodiment, the variation in vertical misalignment may depend on the variation in compression of the plurality of solder balls 1010 or other electrical contacts used to electrically couple the SiPho chip 108 to the plurality of vias 1006 (FIGS. 10-11) formed in a portion of the PGL substrate 106.

[0035]

[0046] FIG. 6 shows optical structures 1101 to 110 N3A-3E , is a flow diagram illustrating steps in an exemplary method 600 for fabricating a portion 300 of a PGL substrate 106, such as a portion of a PGL substrate 106 shown in FIGS. 3A-3E . Method 600 includes steps 602-618. In one embodiment, method 600 is a single-substrate or batch process involving multiple substrates being fabricated simultaneously. In step 602, as shown in FIG. 3A , a cladding layer 303 is disposed on a surface of a support substrate 301. The cladding layer 303 can be disposed on the surface using a liquid material injection casting process, a spin-on coating process, a liquid spray coating process, a dry powder coating process, a screen printing process, a doctor blade process, a PVD process, a CVD process, a PECVD (plasma-enhanced chemical vapor deposition) process, an FCVD process, an ALD process, or an evaporation process. In one embodiment, the cladding layer 303 is made of a material having a relatively low refractive index compared to the refractive index of the core material layer 302, which will be formed in a subsequent step. In some embodiments, the cladding layer 303 has a refractive index between 1.3 and 1.5. In some embodiments, the cladding layer 303 employed in step 602 may be formed from one or more low refractive index materials, including Si3N4, SiO2, doped SiO2, low refractive index fluoropolymers, nanoparticle films, hydrogels, porous materials, and photoresist-containing materials.

[0036]

[0047] 3A, core material layer 302 is disposed on the surface of cladding layer 303 and supporting substrate 301. Core material layer 302 may be disposed on the surface of cladding layer 303 using a liquid material injection casting process, a spin-on coating process, a liquid spray coating process, a dry powder coating process, a screen printing process, a doctor blade process, a PVD process, a CVD process, a PECVD process, an FCVD process, an ALD process, or an evaporation process. In some embodiments, supporting substrate 301 comprises a material selected from the group consisting of silica (SiO), boron oxide (BO), and alumina (AlO).

[0037]

[0048] The core material layer 302 can be a low-index material or a high-index material, depending on the embodiment. The material used to form the core material layer 302 has a refractive index that is different from the refractive index of the material used to form the cladding layer 303. In some embodiments, the core material layer 302 has a refractive index between 1.4 and 1.5. In other embodiments, the material used to form the core material layer 302 has a higher refractive index than the material used to form the cladding layer 303. Generally, the refractive index of the core material layer 302 is different from the cladding layer 303 and also different from the encapsulation layer 314, which will be described further below. In one example, the core material layer 302 has a refractive index between 1.45 and 1.50, while the cladding layer 303 and encapsulation layer 314 have refractive indices between 1.40 and 1.44.

[0038]

[0049] In embodiments that can be combined with other embodiments described herein, the core material layer 302 can be made of a material such as, but not limited to, silicon carbide (SiC), silicon oxycarbide (SiOC), titanium dioxide (TiO), silicon dioxide (SiO), vanadium(IV) oxide (VO x ), aluminum oxide (Al2O3), aluminum doped zinc oxide (AZO), indium tin oxide (ITO), tin dioxide (SnO2), zinc oxide (ZnO), tantalum pentoxide (Ta2O5), silicon nitride (Si3N4), zirconium dioxide (ZrO2), niobium oxide (Nb2O5), cadmium stannate (Cd2SnO4), silicon mononitride (SiN), silicon oxynitride (SiON), barium titanate (BaTiO3), diamond-like carbon (DLC), hafnium(IV) oxide (HfO2), lithium niobate (LiNbO3), silicon carbonitride (SiCN), or one or more other materials suitable for forming optical structures.

[0039]

[0050] In step 606, a patterned layer 305 is disposed over the core material layer 302. The patterned layer 305 defines exposed negative portions of the core material layer 302 and, when removed, corresponds to a structural pattern that enables the formation of the optical structure 110 in a subsequent step.

[0040]

[0051] In an embodiment, as shown in FIGS. 3B and 3C and described in further detail in steps 608-612 below, disposing the patterned layer 305 on the core material layer 302 may include disposing a hard mask 304 on the core material layer 302; disposing a patterned photoresist 306 on the hard mask 304, where the patterned photoresist 306 defines exposed portions of the hard mask 304; and removing the exposed portions of the hard mask 304 to form a patterned hard mask 304 corresponding to the patterned photoresist 306.

[0041]

[0052] In another embodiment, disposing the patterned layer 305 on the core material layer 302 in step 606 may include forming a patterned photoresist on the core material layer 302 by disposing a photoresist layer on the core material layer 302 and performing a lithography process to pattern and develop the photoresist material. The patterned photoresist defines exposed negative portions of the core material layer 302. The patterned photoresist may enable selective etching of the core material layer 302 beneath the patterned photoresist to protect certain areas of the core material layer 302 from unwanted etching in subsequent processes. In such an embodiment, the method 600 continues with step 614 below to remove the negative structure portions 312 of the core material layer 302 defined by the patterned layer 305.

[0042]

[0053] 3B, a hard mask 304 is disposed on the core material layer 302. The hard mask 304 may be disposed on the core material layer 302 using a liquid material injection casting process, a spin-on coating process, a liquid spray coating process, a dry powder coating process, a screen printing process, a doctor blade process, a PVD process, a CVD process, a PECVD process, an FCVD process, an ALD process, or an evaporation process. The hard mask 304 may comprise a material selected from a group of materials including, but not limited to, chromium (Cr), silver (Ag), Si3N4, SiO2, TiN, and carbon (C).

[0043]

[0054] In step 610, as shown in FIG. 3B , a patterned photoresist 306 is disposed on the core material layer 302 and, if present, on the hard mask 304. The patterned photoresist 306 allows for selective etching of the material below the patterned photoresist 306 to protect certain areas from unwanted etching in subsequent processes. In one example, the patterned photoresist 306 is formed by disposing a photoresist material on the hard mask 304 and performing a lithography process to pattern and develop the photoresist material. The patterned photoresist 306 defines exposed portions 310 of the hard mask 304 (i.e., openings in the hard mask 304). The exposed portions 310 correspond to the pattern 308 used to form the optical structure 110. The patterned photoresist 306 can be disposed on the hard mask 304 or on the core material layer 302 using a spin-on coating process. The photoresist material 306 may include, but is not limited to, a photosensitive polymer-containing material.

[0044]

[0055] 3C, the exposed portions 310 of the hard mask 304 are removed. Removal of the hard mask portions 310 exposes the negative structure portions 312 of the core material layer 302. The negative structure portions 312 correspond to the structure pattern 308 that will enable the formation of the optical structures 110 in a subsequent step. In one embodiment, the exposed portions 310 are removed by an ion etching, RIE, or selective wet chemical etching process to form a plurality of openings in the hard mask 304.

[0045]

[0056] 3C , the negative structure portions 312 of the core material layer 302 are removed to form a plurality of optical structures 110. In one embodiment, which may be combined with other embodiments described herein, the negative structure portions 312 are removed by an ion etching, RIE, or selective wet chemical etching process to form a plurality of trenches 316 in the core material layer 302. In one embodiment, the removal of the exposed portions 310 in step 612 and the etching of the negative structure portions 312 in step 614 may be performed simultaneously or sequentially. In one aspect, the hard mask 304 has a lower etch rate than the material of the core material layer 302.

[0046]

[0057] In step 616, the patterned layer 305 is removed. Removing the patterned layer 305 includes removing the hard mask and / or photoresist layer. In the example shown in FIG. 3D , removing the patterned layer 305 includes removing the hard mask 304 and the patterned photoresist 306. Removing the hard mask 304 may include ion etching, RIE, or selective wet chemical etching. Removing the patterned photoresist 306 may include using an ashing process or an etching process described herein.

[0047]

[0058] In step 618, an encapsulation layer is disposed over the cladding layer 303 and the plurality of optical structures 110, as shown in FIG. 3E. The encapsulation layer 314 may be formed using one or more of PVD, CVD, FCVD, and spin-on coating processes. In one embodiment, the encapsulation layer 314 is made of a material having a relatively low refractive index compared to the refractive index of the core material layer 302. In some embodiments, the encapsulation layer 314 has a refractive index between 1.3 and 1.5 (e.g., between 1.40 and 1.44). In some embodiments, multiple encapsulation layers having multiple refractive indices may be used.

[0048]

[0059] In embodiments that can be combined with other embodiments herein, the encapsulation layer 314 may be formed from one or more low refractive index materials, including Si3N4, SiO2, doped SiO2, low refractive index fluoropolymers, nanoparticle films, hydrogels, porous materials, and photoresist-containing materials. The materials used to form the encapsulation layer 314 have a refractive index that is different from the refractive index of the materials used to form the core material layer 302. In one embodiment, the materials used to form the encapsulation layer 314 have a refractive index that is lower than the refractive index of the materials used to form the core material layer 302. Low refractive index materials are discussed herein in contrast to "high" refractive index materials, such as amorphous and crystalline silicon, silicon nitride, titanium dioxide, gallium phosphide, tantalum pentoxide, gallium nitride, sulfur-containing materials, polymers, and other materials with suitable optical properties. It is contemplated that materials and combinations of materials can be used to form the cladding layer 303, encapsulation layer 314, and / or core material layer 302 discussed herein, and that these materials can be selected based on the target optical properties of the one or more optical devices to be manufactured by method 600.

[0049]

[0060] In another embodiment, which can be combined with other embodiments herein, the encapsulation layer 314 can be formed to include an intermediate layer (not shown) extending above the upper surface of the encapsulation layer 314. The intermediate layer can be used to separate the optical structure 110 formed from the encapsulation layer 314 and the core material layer 302 from additional optical structures in a second optical structure material layer (not shown). Thus, optical structures of different optical layers can be formed and stacked on top of the portion 300 shown in FIG. 3E without direct contact with the optical structure 110 or the encapsulation layer 314. Furthermore, the lower the refractive index of the material used for encapsulation, the lower the aspect ratio of the constituent nanostructures (patterned features) of each optical structure. In one embodiment, low aspect ratio features produce thinner optical layers, enabling faster and cleaner etching. In this manner, the systems and methods herein result in a more efficient manufacturing process in terms of time, cost, and complexity.

[0050]

[0061] 3A-3E, the optical structures 110 shown herein are depicted as having a generally square or rectangular cross-section, but it is contemplated that the optical structures may, in other examples, include tapered sidewalls, thus forming a trapezoidal cross-section (not shown). In one example, the trapezoidal cross-section is wider near the top relative to the bottom of the opening.

[0051]

[0062] Therefore, the method 600 uses a negative patterning process to pattern the optical structures 1101-110, including the remaining portions of the core material layer 302. N 3E, PGL substrate 106 includes seven optical structures (i.e., optical structures 1101-1107) disposed on support substrate 301 and each sealed and separated by at least a portion of encapsulation layer 314.

[0052]

[0063] FIG. 7 shows optical structures 1101 to 110 N4A-4F , such as a portion of a PGL substrate 106. Method 700 may include steps 702-718. Method 700 begins at step 702, in which patterned layer 405 is disposed on support substrate 401. Patterned layer 405 defines exposed negative portions of support substrate 401 and corresponds to a structural pattern that, when removed, enables formation of optical structures 110 in subsequent steps.

[0053]

[0064] In an embodiment, as shown in FIGS. 4B and 4C and described in further detail in steps 704-708 below, disposing the patterned layer 405 on the support substrate 401 may include disposing a hard mask 402 on the support substrate 401; disposing a patterned photoresist 404 on the hard mask 402, where the patterned photoresist 404 defines exposed portions of the hard mask 402; and removing the exposed portions of the hard mask 402 to form a patterned hard mask 402 corresponding to the patterned photoresist 404.

[0054]

[0065] In another embodiment, disposing the patterned layer 405 on the support substrate 401 in step 702 can include either disposing a patterned photoresist directly on the support substrate 401 or disposing a photoresist layer on the support substrate 401 and performing a lithography process to pattern and develop the photoresist material. The patterned photoresist defines exposed negative portions of the support substrate 401. The patterned photoresist may enable selective etching of the support substrate 401 beneath the patterned photoresist to protect certain areas of the support substrate 401 from unwanted etching in subsequent processes. In such an embodiment, the method 600 continues with step 710 below to remove the negative structure portions 410 of the support substrate 401 defined by the patterned layer 405.

[0055]

[0066] 4A, in step 704, a hard mask 402 is disposed on a support substrate 401. The hard mask 402 can be disposed on the support substrate 401 using a liquid material injection casting process, a spin-on coating process, a liquid spray coating process, a dry powder coating process, a screen printing process, a doctor blade process, a PVD process, a CVD process, a PECVD process, an FCVD process, an ALD process, or an evaporation process. The hard mask 304 can comprise a material selected from a group of materials including, but not limited to, chromium (Cr), silver (Ag), SiN, SiO, TiN, and carbon (C). In some embodiments, the support substrate 401 comprises a material selected from the group consisting of silica (SiO), boron oxide (BO), and alumina (AlO).

[0056]

[0067] In step 706, as shown in FIG. 4B , a patterned photoresist 404 is disposed on the support substrate 401 and, if present, on the hard mask 402. The patterned photoresist 404 allows for selective etching of materials beneath the patterned photoresist 404 to protect certain areas from unwanted etching in subsequent processes. In one example, the patterned photoresist 404 is formed by disposing a photoresist material on the hard mask 402 and performing a lithography process to pattern and develop the photoresist material. The patterned photoresist 404 defines exposed portions 408 of the hard mask 402 (i.e., openings in the hard mask 402). The exposed portions 408 correspond to the structure pattern 406 that results in the formation of the plurality of optical structures 110. In one example, the patterned photoresist 404 can be disposed on the hard mask 402 using a spin-on coating process. The photoresist material 404 may include, but is not limited to, a photosensitive polymer-containing material.

[0057]

[0068] 4C , in step 708, exposed portions 408 of hard mask 402 are removed. Removal of exposed portions 408 exposes negative structure portions 410 of support substrate 401. Negative structure portions 410 correspond to structure pattern 406 and result in the formation of optical structures 110. In one embodiment, exposed portions 408 are removed by ion etching, RIE, or a selective wet chemical etching process to form a plurality of openings in hard mask 402.

[0058]

[0069] In step 710, the negative structure portions 410 of the support substrate 401 are removed to form the patterned structures 406, as shown in FIG. 4C . In embodiments that can be combined with other embodiments described herein, the negative structure portions 410 of the support substrate 401 can be removed by ion etching, RIE, or a selective wet chemical etching process to form a plurality of trenches 412 in the support substrate 401. In one embodiment, removing the exposed portions 408 in step 708 and the portions of the support substrate 401 in step 712 can be performed simultaneously or sequentially. In some aspects, the hard mask 402 has a lower etch rate than the material of the support substrate 401.

[0059]

[0070] In step 712, the patterned layer 405 is removed. Removing the patterned layer 405 may include removing a hard mask and / or a photoresist layer. In the example shown in FIG. 4D , removing the patterned layer 405 includes removing the hard mask 402 and the patterned photoresist 404. This leaves the support substrate 401 having a plurality of patterned structures 406, each separated by a plurality of trenches 412. In one embodiment, removing the hard mask 402 may include ion etching, RIE, or selective wet chemical etching. Removing the patterned photoresist 404 may include a conventional ashing or etching process.

[0060]

[0071] In step 714, as shown in FIG. 4E, a fill layer 418 is disposed over the support substrate 401 and the patterned structures 406 formed therein. The fill layer 418 may include, but is not limited to, a material selected from the group consisting of SiN, SiO, low refractive index fluoropolymers, hydrogels, and photoresist-containing materials. The fill layer 418 may be disposed over the support substrate 401 and within the plurality of trenches 412 by one or more of PVD, CVD, FCVD, and spin-on coating processes. The flowability of the fill layer 418 allows the fill layer 418 to flow into each of the plurality of trenches 412.

[0061]

[0072] In one embodiment, the fill layer 418 is formed from a material having a refractive index different from that of the PGL substrate 106 within the support substrate 401. In some embodiments, the fill layer 418 has a refractive index between 1.4 and 1.5. In another embodiment, the fill layer 418 is formed from a material having a refractive index greater than that of the support substrate 401. In certain embodiments, the fill layer 418 may be formed from high refractive index materials such as amorphous and crystalline silicon, silicon nitride, titanium dioxide, gallium phosphide, tantalum pentoxide, gallium nitride, sulfur-containing materials, polymers, and other materials with suitable optical properties. It is contemplated that materials and combinations of materials can be used to form the fill layer 418 discussed herein, and these materials can be selected based on the target optical properties of one or more optical devices fabricated in the method 700. In one example, the fill layer 418 has a refractive index between 1.45 and 1.50, while the support substrate 401 has a lower refractive index between 1.40 and 1.44.

[0062]

[0073] In step 716, excess fill layer portions 418A are removed so that the height of fill layer 418 in the plurality of trenches 412 is approximately the same height as the patterned structures 406 of support substrate 401, as shown in FIG. 4F. Excess fill layer 418A may be removed using a chemical mechanical polishing (CMP) process, according to one embodiment. Removal of excess fill layer 418 forms a plurality of optical structures 110 in substrate 401 separated by patterned structures 406.

[0063]

[0074] 4A-4F, the optical structures 110 shown herein are depicted as having a generally square or rectangular cross-section, but it is contemplated that the optical structures may, in other examples, include tapered sidewalls, thus forming a trapezoidal cross-section (not shown). In one example, the trapezoidal cross-section is wider near the top relative to the bottom of the opening.

[0064]

[0075] In step 718, as shown in FIG. 4G, an encapsulation layer 420 is optionally disposed over the support substrate 401 and the plurality of optical structures 110. The encapsulation layer 420 may be formed using one or more of PVD, CVD, FCVD, and spin-on coating processes. In one embodiment, the encapsulation layer 420 is made of a low refractive index material compared to the refractive index of the fill layer 418. In some embodiments, the encapsulation layer 420 has a refractive index between 1.3 and 1.9 (e.g., between 1.40 and 1.44).

[0065]

[0076] Therefore, the method 700 uses a negative patterning process to pattern the optical structures 1101-110, including the remaining portions of the fill layer 418. N 4F and 4G, PGL substrate 106 includes seven optical structures (i.e., optical structures 1101-1107). The seven optical structures include portions of fill layer 418 that are disposed within support substrate 401 and are thus separated by portions of support substrate 401.

[0066]

[0077] FIG. 8 shows optical structures 1101 to 110 N 5A-5E , such as a portion of a PGL substrate 106. Method 800 includes steps 802-808. Method 800 is provided for depositing a refractive index-varying material species on a portion of a support substrate 501 via an ion implantation process. Ion implantation is a surface modification technique that can alter the optical properties of a portion of a surface layer of support substrate 501. Ion implantation allows for precise control of both the dopant composition and penetration depth through selection of the species and energy of the doping ions. In some embodiments, support substrate 501 comprises a material selected from the group consisting of silica (SiO), boron oxide (BO), and alumina (AlO).

[0067]

[0078] 5A, a patterned layer 502 is disposed on a support substrate 501. The patterned layer 502 defines exposed substrate portions 504 of the support substrate 501 (i.e., openings in the patterned layer 502). The patterned layer 502 is configured to allow selective implantation of doping ions into the support substrate 501 disposed below the patterned layer 502 because portions of the patterned layer 502 can act as a mask to block the doping ions from reaching selected portions of the support substrate 501 beneath the patterned layer 502.

[0068]

[0079] The patterned layer 502 may be a patterned photoresist or a patterned hard mask. In one embodiment, the patterned layer 502 may be a patterned photoresist formed from a material including, but not limited to, a polymeric material formed from a phenolic resin, an epoxy resin, or an acrylic resin. The patterned photoresist must be thick enough to reliably absorb ions. Therefore, it is generally necessary to appropriately select the resist film thickness when adjusting the ion energy of the implantation process. In one example, the patterned layer 502 may be formed by depositing a photoresist material on the substrate 501 and performing a lithography process to pattern and develop the photoresist material. In another embodiment, the patterned layer 502 may be a patterned hard mask. The hard mask may include, but is not limited to, a material selected from a group of materials including chromium (Cr), silver (Ag), Si3N4, SiO2, TiN, and carbon (C).

[0069]

[0080] As shown in FIG. 5B, in step 804, an ion implantation process is performed on the support substrate 501. In the ion implantation process, doping ions are accelerated and implanted into the support substrate 501 through the openings in the patterned layer 502. The doping ions will comprise a dopant material that changes the refractive index of the implanted region located within the openings in the patterned layer 502 and may include at least one of Al, P, F, Cl, P, or gases N, Ar, or Kr. As described herein, the doping ions provided in the ion implantation process are generated from a plasma formed by applying high-voltage RF to a processing region of a plasma processing chamber. The plasma dissociated ions are then biased toward the surface of the substrate 106 and implanted to a desired depth from the substrate surface. Once implanted, the doping ions bond with portions of the material of the support substrate 501, inducing a refractive index change in those portions of the PGL substrate 106. In one embodiment, when performing the ion implantation process in method 800, the support substrate 501 is placed on a substrate support pedestal in a plasma processing chamber, and gas is flowed into the plasma processing chamber and ignited to generate a plasma. A bias is then applied to the support substrate 501, causing doping ions generated in the plasma to accelerate toward the surface of the support substrate 501. The bias on the plasma and support substrate 501 causes the doping ions generated in the plasma to be implanted into the support substrate 501 and form part of the support substrate 501. One example of an ion implanter is the VIISTA® Trident, available from Applied Materials, Inc. of Santa Clara, California.

[0070]

[0081] In an embodiment, as shown in FIG. 5C , the ion implantation process employed in step 804 modifies exposed substrate portions 504 of support substrate 501 to form a plurality of optical structures 110. Meanwhile, substrate regions 512 protected by patterned layer 502 are not modified by the ion implantation process. In one aspect, the ion implantation modification relies on ions (light or heavy) implanted into PGL substrate 106. The ions implanted into exposed portions 504 of PGL substrate 106 can be modified to increase or decrease the refractive index. In one embodiment, optical structures 110 formed from the ion implantation process include a refractive index that is higher than the refractive index of PGL support substrate 501 and protected regions 512.

[0071]

[0082] In step 806, as shown in FIG. 5E, the patterned layer 502 is removed to form the substrate 106, which includes a support substrate 501 having alternating optical structures 110 and substrate regions 512 formed therein. Removing the patterned layer 502 may include removing a patterned hard mask or a patterned photoresist. Removing the patterned hard mask may include ion etching, RIE, or selective wet chemical etching. Removing the patterned photoresist may include using an ashing process or an etching process described herein.

[0072]

[0083] In some embodiments, it may be desirable to perform an annealing process on the PGL substrate of substrate 501 to activate the dopant species, remove any damage caused to the optical structure 110 by the implantation process, and / or to better distribute the index-changing dopant material implanted during step 804 of method 800.

[0073]

[0084] 5A-5E are shown herein as having a generally square or rectangular cross-section, it is contemplated that the optical structure may, in other examples, include tapered sidewalls, thus forming a trapezoidal cross-section (not shown). In one example, the trapezoidal cross-section is wider near the top relative to the bottom of the opening.

[0074]

[0085] In step 808, as shown in FIG. 5E, an encapsulation layer 520 is optionally disposed over the substrate 501 and the plurality of optical structures 110. The encapsulation layer 520 may be formed using one or more of PVD, CVD, FCVD, and spin-on coating processes. In one embodiment, the encapsulation layer 520 is made of a low refractive index material having a refractive index lower than that of the implanted portion of the support substrate 501. In some embodiments, the encapsulation layer 520 has a refractive index between 1.3 and 1.9 (e.g., between 1.40 and 1.44).

[0075]

[0086] Thus, the method 800 uses a negative patterning and implantation process to form optical structures 1101-110, including implanted portions of the support substrate 501. N 5E, PGL substrate 106 includes seven optical structures (i.e., optical structures 1101-1107), which include exposed portions 504 formed in support substrate 401.

[0076]

[0087] 9 is a schematic cross-sectional end view of a portion of a photon engine 103 mounted on a package substrate 101 formed using cutting lines CC of FIG. 10, according to an embodiment. As shown in FIG. 9, the photon engine 103 includes a bottom surface 106A of a photonic glass layer substrate 106 disposed on a top surface 101A of the package substrate 101, and includes a plurality of optical structures 1101-110. N extend through the PGL substrate 106. In the illustrated embodiment, a plurality of optical structures 1101-110 extend through the PGL substrate 106. Nare aligned in the XZ plane of the PGL substrate 106. FIG. 9 shows a plurality of optical structures 1101 to 110 formed in a line in a plane that crosses the PGL substrate 106. N 1, a PGL substrate 106 includes a plurality of optical structures 1101 to 110 N Other arrangements of optical structures 1101-110 may be formed. For example, one or more rows of optical structures may be formed and stacked vertically. The stacked rows of optical structures may be formed by one or more of the processes described herein, such as the methods described in connection with FIGS. 3A-8. N The placement of is not intended to limit the scope of the disclosure provided herein.

[0077]

[0088] 10 is a schematic cross-sectional side view of a portion of a photon engine 103 mounted on a package substrate 101, formed using cut lines BB of FIG. 2A , according to one embodiment. As shown, the package substrate 101 includes a plurality of circuit traces 1002 extending from a plurality of corresponding interconnect pads 1004 integrally formed on a top surface 101A of the package substrate 101. In one embodiment, the plurality of circuit traces 1002 form interconnects 104 that electrically connect the photon engine 103 in contact with the plurality of interconnect pads 1004 to the electrical or opto-electrical chip 102. Alternatively, the plurality of circuit traces 1002 may electrically connect the photon engine 103 in contact with the plurality of interconnect pads 1004 to other integrated circuits disposed on the package substrate 101.

[0078]

[0089] In some embodiments, the plurality of vias 1006 extend through a portion of the PGL substrate 106 between the bonding surface 208 and the bottom surface 106A of the PGL substrate 106. When the photon engine 103 is mounted to the package substrate 101, in one embodiment, the plurality of vias 1006 align with and rest in electrical contact with corresponding interconnect pads 1004. The interconnect pads 1004 are exposed on the top surface 101A of the package substrate 101 and are electrically connected to the photon engine 103 through a plurality of circuit traces 1002 formed in the package substrate 101. In another embodiment, the plurality of vias 1006 may alternatively connect the photon engine 103 to one or more other integrated circuits (chips) embedded within or on the package substrate 101.

[0079]

[0090] As shown in FIG. 10 , the SiPho chip 108 may be actively or passively mounted to the coupling surface 208 of the PGL substrate 106, with the side surface 108B of the SiPho chip 108 being “butt-coupled” to the end surface 106B of the PGL substrate 106 at the first interface 107. When the SiPho chip 108 is butt-coupled to the end surface 106B of the PGL substrate 106, the end of the waveguide 108A in the SiPho chip 108 is also butt-coupled to a corresponding end of an optical structure 110 (e.g., optical structure 1103) formed in the PGL substrate 106 at the fourth coupling interface 1008. The coupling between the multiple waveguides 108A and the multiple optical structures 110 at the fourth interface 1008 may affect the loss of the optical signal between the SiPho chip 108 and the PGL substrate 106. Thus, to minimize coupling losses, the one or more fiducial marks 206 (FIG. 2B) described above may be used during mounting of the SiPho chip 108 to assist in the alignment and precise placement of the SiPho chip 108 and the plurality of waveguides 108A and the plurality of optical structures 1101-110 at the fourth interface 1008. N Optimize the butt coupling and minimize the coupling loss.

[0080]

[0091] To connect the SiPho chip 108 to the PGL substrate 106, the SiPho chip 108 further includes a plurality of solder connections 1012 in contact with the plurality of solder balls 1010. The plurality of solder balls 1010 are positioned between the plurality of solder connections 1012 and the ends of each of the plurality of vias 1006 on the bonding surface 208. The plurality of solder balls 1010 electrically connect the SiPho chip 108 to the plurality of vias 1006 formed in the photonic glass layer substrate 106. In one embodiment, the plurality of solder balls 1010 or other interconnect bumps, pillars, or interconnect materials, including planar hybrid bonding techniques, may be used to connect the plurality of solder connections 1012 to the plurality of vias 1006 that extend through the PGL substrate 106 to the substrate 101. In the illustrated embodiment, a plurality of solder balls 1010 and a plurality of vias 1006 connect a plurality of solder connections 1012 to a plurality of interconnect pads 1004 in the substrate 101, thereby electrically connecting the SiPho chip 108 to a plurality of circuit traces 1002 in the package substrate 101 that are connected to the plurality of interconnect pads 1004.

[0081]

[0092] In one embodiment, the bonding surface 208 of the PGL substrate 106 may further include a plurality of recesses (not shown) for encapsulating each of the plurality of solder balls 1010 used to connect the plurality of solder connections 1012 in the SiPho chip 108 to the plurality of vias 1006 in the PGL substrate 106. The recesses may be formed to allow the plurality of solder balls 1010 to expand when planarized so that their contact surfaces are substantially flush with the bonding surface 208. Planarization of the plurality of solder balls 1010 on the bonding surface 208 upon contact with the solder connections 1012 of the SiPho chip 108 helps ensure uniformity in mounting the SiPho chip 108 to the PGL substrate 106 and improves contact reliability of the solder balls 1010.

[0082]

[0093] 10 also includes a cross-sectional view of a portion of fiber connector 112 coupled to a portion of PGL substrate 106 at interface 109, according to one embodiment. In a configuration, fiber connector 112 can be removably connected to a portion of photon engine 103 to enable transmission and reception of optical signals to and from optical structure 110 by using a "butt-coupled" connection configuration.

[0083]

[0094] 11 is a schematic cross-sectional side view of a portion of a photon engine 103 mounted on a package substrate 101, according to an alternative embodiment. In the illustrated embodiment, the SiPho chip 108 may be passively mounted on the photonic glass layer substrate 106 at a second chip mounting area 1106 of the photonic glass layer substrate 106. The second chip mounting area 1106 of the PGL substrate 106 includes a plurality of optical structures 1101-110 extending along a bonding surface 1104 of the PGL substrate 106. N When the SiPho chip 108 is mounted on the second chip mounting area 1106, some of the plurality of waveguides 108A in the SiPho chip 108 are coupled to the plurality of optical structures 1101-110 in the PGL substrate 106. N The plurality of waveguides 108A are evanescently coupled with the surface of the corresponding coupling portion 1102 of each of the plurality of optical structures 110. Evanescent coupling is achieved when two optical waveguides are positioned in close proximity such that the evanescent field generated by one waveguide reaches the other waveguide before substantial decay of the evanescent field occurs. Evanescent coupling of the plurality of waveguides 108A with the plurality of optical structures 110 enables transmission of optical signals between the coupled waveguides.

[0084]

[0095] In one embodiment, the evanescent coupling of the waveguides can be formed as a directional coupler in which the evanescent mode of one waveguide overlaps with the mode of a second waveguide. When the evanescent modes of the waveguides overlap, the evanescent fields generated by each waveguide also overlap, and the evanescent field generated by one guide can excite waves in the other guide. Thus, in one aspect, the coupling strength between the plurality of waveguides 108A and the plurality of optical structures 110 can be sensitive to the distance between the waveguide 108A and the optical structure 110 and / or the length of the coupling portion 1102. Accordingly, the coupling portion 1102 of the waveguide 108A and each contact portion can be sized and shaped to optimize coupling and minimize coupling loss.

[0085]

[0096] Mounting the SiPho chip 108 on the substrate 106 in the chip mounting area 1106 further includes connecting the plurality of solder connections 1012 in the SiPho chip 108 to the plurality of vias 1006 in the PGL substrate 106 using a plurality of solder balls 1010. The plurality of solder balls 1010 connect the plurality of optical structures 1101-110. N The plurality of solder balls 1010 may be positioned on the bonding surface 208 adjacent to the bonding portion 1102 of the SiPho chip 108, and may be aligned between each respective solder connection 1012 and the via 1006. As the contacts of the SiPho chip 108 are mounted on the PGL substrate 106, when the plurality of solder balls 1010 are planarized, the plurality of solder balls 1010 may be aligned with the plurality of optical structures 1101-110. N10A and 10B, the SiPho chip 108 may be sized to be planarized to a height substantially the same as the height of the coupling portion 1102 of the PGL substrate 106. In the illustrated embodiment, a plurality of solder balls 1010 and a plurality of interconnect pads 1004 in contact with the plurality of vias 1006 electrically connect the SiPho chip 108 to a plurality of circuit traces 1002 in the package substrate 101. Additionally, one or more standoff structures 1015 may be used to position, support, and / or assist in aligning the SiPho chip 108 within the chip mount area 204. In one example, the standoff structures 1015 ( FIG. 10 ) are formed to help establish vertical alignment between the waveguide 108A and the optical structure 110. In some embodiments, as shown in FIG. 10 , the PGL substrate 106 may be sized to be planarized to a height substantially the same as the height of the coupling portion 1102 of the PGL substrate 106. In the illustrated embodiment, a plurality of solder balls 1010 and a plurality of interconnect pads 1004 in contact with the plurality of vias 1006 electrically connect the SiPho chip 108 to a plurality of circuit traces 1002 in the package substrate 101. In addition, one or more standoff structures 1015 may be used to position, support, and / or assist in aligning the SiPho chip 108 within the chip mount area 204. In one example, the standoff structures 1015 ( FIG. 10 ) are formed to help establish vertical alignment between the waveguide 108A and the optical structure 110. In some embodiments, as shown in FIG. 10 , the PGL substrate 106 may be sized to be planarized to a height substantially the same as the height of the coupling portion 1102 of the PGL substrate 106. N The SiPho chip 108 includes one or more standoff structures 1015 configured to support the SiPho chip 108 in a direction substantially perpendicular to a plane parallel to the plane in which the SiPho chip 108 extends (e.g., the XY plane) (e.g., the Z direction).

[0086]

[0097] 12 is a schematic cross-sectional side view of a fiber connector 112 portion of photon engine 103, according to an embodiment. Generally, fiber connector 112 is used to removably connect an external fiber cable 120 to photon engine 103. Multiple optical fibers 112A of fiber connector 112 transmit optical signals to and from fiber cable 120 that is plugged into fiber connector 112. Fiber connector 112 is configured to allow external fiber cable 120 to be attached to the optical inputs and outputs of photon engine 103 without the need to actively align fiber cable 120 fiber core-by-fiber core with photon engine 103. In this manner, fiber connector 120 can be formed and configured to be interoperable with a variety of different fiber cable 120 assemblies and standards.

[0087]

[0098] As shown in FIG. 12, light transmitted along the plurality of fibers 112A is reflected by the lens assembly through the plurality of optical structures 1101-110 on the PGL substrate 106. NThe light is then transmitted to and passes through photon engine 103. The lens assembly includes first lens 112B and third lens 112C formed on fiber connector 112 and second lens 1202 formed on substrate 106. In the illustrated embodiment, light from fiber cable 120 is transmitted along fiber 112A toward first lens 112B formed near the end of fiber 112A. First lens 112B directs the light transmitted along fiber 112A to second lens 1202 on PGL substrate 106. Second lens 1202 on PGL substrate 106 then reflects the light and redirects it to third lens 112C on fiber connector 112. The third lens 112C finally reflects the light and redirects it to the optical structure 110 on the PGL substrate 106, which then transmits the light through the photon engine 103.

[0088]

[0099] Briefly, embodiments herein relate to optical silicon photonic devices and methods for fabricating optical silicon photonic devices. The methods described herein enable mass production and manufacturing of optical silicon photonic devices having a plurality of optical structures formed on a photonic glass layer substrate. The optical silicon photonic device further includes a silicon photonic chip mounted on the photonic glass layer substrate and connected to the plurality of optical structures. The plurality of optical structures optically connect the silicon photonic chip to a fiber connector configured to connect to an external fiber and operate to propagate optical signals between the fiber connector and the silicon photonic chip.

[0089]

[0100] While the foregoing is directed to embodiments of the present disclosure, other and additional embodiments of the disclosure may be devised without departing from the basic scope thereof, the scope of which is determined by the claims that follow.

Claims

1. 1. A method for fabricating electronic and photonic devices, comprising: depositing a core material layer on a surface of a substrate including a photonic glass layer (PGL) having a first refractive index, the core material layer having a second refractive index different from the first refractive index; depositing a patterned layer over the core material layer, the patterned layer having an opening formed therein exposing a portion of a surface of the core material layer; removing portions of the core material exposed in the openings of the patterned layer to form a plurality of optical structures, each of the plurality of optical structures including a waveguide configured to transmit light between a first edge and a second edge of the substrate, each of the waveguides of the plurality of optical structures extending in one or more directions between the first edge and the second edge; A method comprising:

2. depositing a cladding layer on the surface of the substrate prior to depositing the core material layer, the cladding layer having a fourth refractive index different from the second refractive index; removing the portion of the core material exposed in the opening followed by removing the patterned layer; depositing an encapsulation layer over the plurality of optical structures, the deposited encapsulation layer having a third refractive index different from the second refractive index; The method of claim 1 further comprising:

3. 3. The method of claim 2, wherein depositing a patterned layer over the core material layer comprises depositing a patterned hard mask or forming a patterned photoresist over the core material layer.

4. depositing a patterned layer over the core material layer; depositing a hard mask over the core material layer; forming a patterned photoresist overlying the hard mask, the patterned photoresist having openings formed therein that expose portions of the hard mask; removing the exposed portion of the hard mask to expose a portion of the core material layer; The method of claim 2 , comprising:

5. The encapsulation layer is Si ３ N ４ , SiO ２ , doped SiO ２ 3. The method of claim 2, wherein the substrate comprises one or more of a low refractive index fluoropolymer, a nanoparticle membrane, a hydrogel, a porous material, and a photoresist-containing material.

6. The method of claim 2 , wherein the first refractive index and the third refractive index are lower than the second refractive index.

7. 10. The method of claim 1, further comprising forming a chip mount area on a surface of the photonic glass layer at the first edge of the substrate, the chip mount area operable to connect a photonic or electronic integrated circuit to the photonic glass layer substrate.

8. 10. The method of claim 1, further comprising forming a fiber connector on a surface of the photonic glass layer at the second edge of the substrate, the fiber connector operable to connect a fiber optic cable to the photonic glass layer substrate.

9. The core material layer may be made of silicon carbide (SiC), silicon oxycarbide (SiOC), titanium dioxide (TiO ２ ), silicon dioxide (SiO ２ ), vanadium (IV) oxide (VOx), aluminum oxide (Al ２ O ３ ), aluminum-doped zinc oxide (AZO), indium tin oxide (ITO), tin dioxide (SnO ２ ), zinc oxide (ZnO), tantalum pentoxide (Ta ２ O ５ ), silicon nitride (Si ３ N ４ ), zirconium dioxide (ZrO ２ ), niobium oxide (Nb ２ O ５ ), cadmium stannate (Cd ２ SnO ４ ), silicon mononitride (SiN), silicon oxynitride (SiON), barium titanate (BaTiO ３ ), diamond-like carbon (DLC), hafnium (IV) oxide (HfO ２ ), lithium niobate (LiNbO ３ 10. The method of claim 1, wherein the material comprises one or more of: silicon carbonitride (SiCN)-containing materials;

10. each of the waveguides of the plurality of optical structures a first end portion extending from the first edge of the substrate, the first end portion of the waveguide including a first cross-sectional dimension; a second end portion extending from the second edge of the substrate, the second end portion of the waveguide including a second cross-sectional dimension, the second cross-sectional dimension being greater than the first cross-sectional dimension; and The method of claim 1 , comprising:

11. 11. The method of claim 10, wherein the first cross-sectional dimension comprises a height dimension that is approximately 1 micron in size and the second cross-sectional dimension comprises a height dimension that is approximately 9 microns in size.

12. 1. A method for fabricating electronic and photonic devices, comprising: depositing a patterned layer over a surface of a substrate including a photonic glass layer, the photonic glass layer having a first refractive index, the patterned layer having openings formed therein exposing portions of the surface of the substrate; removing portions of the substrate exposed in the openings in the patterned layer to form structures in the substrate separated by trenches; removing the patterned layer; depositing a fill layer having a second refractive index different from the first refractive index within the trenches to cover the structures to form a plurality of optical structures, each of the plurality of optical structures comprising a waveguide configured to transmit light between a first edge and a second edge of the substrate, each of the waveguides of the plurality of optical structures extending in one or more directions extending between the first edge and the second edge; A method comprising:

13. The method of claim 12 , wherein excess portions of the fill layer are removed after the fill layer is deposited in the trenches of the substrate overlying the structures.

14. 14. The method of claim 13, further comprising, after excess portions of the fill layer are removed, depositing an encapsulation layer to cover the portions of the fill layer deposited in the structures and the trenches, wherein the deposited encapsulation layer has a third refractive index different from the second refractive index.

15. each of the waveguides of the plurality of optical structures a first end portion extending from the first edge of the substrate, the first end portion of the waveguide including a first cross-sectional dimension; a second end portion extending from the second edge of the substrate, the second end portion of the waveguide including a second cross-sectional dimension, the second cross-sectional dimension being greater than the first cross-sectional dimension; and 13. The method of claim 12, comprising:

16. 1. A method for fabricating electronic and photonic devices, comprising: depositing a patterned layer over a surface of a substrate including a photonic glass layer, the photonic glass layer having a first refractive index, the patterned layer having openings formed therein exposing portions of the surface of the substrate; performing an ion implantation process on the exposed portion of the substrate to implant a plurality of doping ions into the surface of the exposed portion of the substrate, wherein the exposed portion of the substrate containing the plurality of doping ions defines a plurality of optical structures having a second refractive index different from the first refractive index, each of the plurality of optical structures including a waveguide configured to transmit light between a first edge and a second edge of the substrate, each of the waveguides of the plurality of optical structures extending in one or more directions extending between the first edge and the second edge; A method comprising:

17. 17. The method of claim 16, wherein the plurality of doping ions comprises a dopant material selected from the group consisting of Al, P, F, Cl, P, N, Ar, Kr, and combinations thereof.

18. 17. The method of claim 16, further comprising removing the patterned layer after the ion implantation process is completed and depositing an encapsulation layer over the substrate and the plurality of optical structures, the deposited encapsulation layer having a third refractive index different from the second refractive index.

19. 17. The method of claim 16, further comprising forming a chip mount area on a surface of the photonic glass layer at the first edge of the substrate, the chip mount area operable to connect a photonic or electronic integrated circuit to the substrate.

20. 17. The method of claim 16, further comprising forming a fiber connector on a surface of the photonic glass layer at the second edge of the substrate, the fiber connector operable to connect a fiber optic cable to the substrate.

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