Capacitor component and integrated circuit chip package including same

Abstract

The present invention provides a high-capacity capacitor component, and an integrated circuit chip package including the same, comprising: an anodized film body having a plurality of pores; a first electrode layer having a first surface electrode portion formed on the surface of the body and a first pore electrode portion formed on the inner wall of the pores; a dielectric layer having a surface dielectric portion formed on the first surface electrode portion and a pore dielectric portion formed on the first pore electrode portion; and a second electrode layer having a second surface electrode portion formed on the surface dielectric portion and a second pore electrode portion formed on the pore dielectric portion.

Description

[Technical Field]

[0001] The present invention relates to a capacitor component and an integrated circuit chip package including the same. [Background technology]

[0002] Multilayer ceramic capacitors (MLCCs), a type of multilayer chip electronic component, are used in a variety of electronic devices due to their advantages of being compact, high capacitance, and easy to mount. Multilayer ceramic capacitors have a structure in which multiple dielectric layers are alternately arranged with internal electrodes of different polarities between the dielectric layers. Recently, as electronic devices have become smaller, multilayer ceramic capacitors have also become smaller. To achieve this, high-capacity multilayer ceramic capacitors have been realized by thinning the dielectric layers and increasing the number of internal electrode layers to achieve miniaturization.

[0003] The multilayer ceramic capacitor includes a plurality of dielectric layers and first and second internal electrodes formed on the dielectric layers, and is formed by stacking a plurality of dielectric layers on which internal electrodes are formed, and the first and second internal electrodes are arranged to face each other with one dielectric layer sandwiched between them.

[0004] However, since the internal electrodes of such capacitors have a two-dimensional planar shape, there is a limit to how much capacitance can be increased. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Korean Patent Registration No. 10-2192426 [Patent Document 2] Korean Patent Registration No. 10-2189805 Summary of the Invention [Problem to be solved by the invention]

[0006] SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a high-capacity capacitor component and an integrated circuit chip package including the same. [Means for solving the problem]

[0007] In order to achieve the above object, a capacitor component according to the present invention includes an anodized film body having a plurality of pores, a first electrode layer having a first surface electrode portion formed on the surface of the body and a first pore electrode portion formed on the inner wall of the pore, a dielectric layer having a surface dielectric portion formed on the first surface electrode portion and a pore dielectric portion formed on the first pore electrode portion, and a second electrode layer having a second surface electrode portion formed on the surface dielectric portion and a second pore electrode portion formed on the pore dielectric portion.

[0008] The first pore electrode portion is formed only on a part of the inner wall of the pore.

[0009] The first pore electrode portion is formed on the entire inner wall of the pore.

[0010] Furthermore, the depth of the pore dielectric portion inside the pore is thinner than the depth of the first pore electrode portion and deeper than the depth of the second pore electrode portion.

[0011] a first upper electrode layer having a first upper surface electrode portion formed on an upper surface of the body and a first upper pore electrode portion formed on a portion of the upper inner wall of the pore; an upper dielectric layer having an upper surface dielectric portion formed on the first upper surface electrode portion and an upper pore dielectric portion formed on the first upper pore electrode portion; a second upper electrode layer having a second upper surface electrode portion formed on the upper surface dielectric portion and a second upper pore electrode portion formed on the upper pore dielectric portion; a first lower electrode layer having a first lower surface electrode portion formed on a lower surface of the body and a first lower pore electrode portion formed on a portion of the lower inner wall of the pore; a lower dielectric layer having a lower surface dielectric portion formed on the first lower surface electrode portion and a lower pore dielectric portion formed on the first lower pore electrode portion; and a second lower electrode layer having a second lower surface electrode portion formed on the lower surface dielectric portion and a second lower pore electrode portion formed on the lower pore dielectric portion.

[0012] The first upper pore electrode portion and the first lower pore electrode portion are spaced apart from each other.

[0013] The upper and lower pore dielectric portions are spaced apart from each other.

[0014] In addition, the second upper pore electrode portion and the second lower pore electrode portion are spaced apart from each other.

[0015] Meanwhile, an integrated circuit chip package according to the present invention includes a package substrate, a semiconductor chip mounted on the package substrate, a molding part for protecting the semiconductor chip, and a capacitor component provided in or on the package substrate, wherein the capacitor component includes an anodized oxide film body having a plurality of pores, a first electrode layer having first surface electrodes formed on the surface of the body and first pore electrodes formed on inner walls of the pores, a dielectric layer having a surface dielectric part formed on the first surface electrodes and a pore dielectric part formed on the first pore electrodes, and a second electrode layer having second surface electrodes formed on the surface dielectric and second pore electrodes formed on the pore dielectric. [Effects of the Invention]

[0016] The present invention provides a high-capacity capacitor component and an integrated circuit chip package including the same. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a perspective view including a partly cutaway portion of a capacitor component according to a first preferred embodiment of the present invention; [Figure 2] 1 is a cross-sectional view of a capacitor component according to a first preferred embodiment of the present invention. [Figure 3] FIG. 2 is a perspective view of an anodized film body. [Figure 4a] 2A to 2C are diagrams illustrating a method for manufacturing a capacitor component according to the first preferred embodiment of the present invention. [Figure 4b] 2A to 2C are diagrams illustrating a method for manufacturing a capacitor component according to the first preferred embodiment of the present invention. [Figure 4c] 2A to 2C are diagrams illustrating a method for manufacturing a capacitor component according to the first preferred embodiment of the present invention. [Figure 4d] 2A to 2C are diagrams illustrating a method for manufacturing a capacitor component according to the first preferred embodiment of the present invention. [Figure 5] FIG. 4 is a cross-sectional view of a capacitor component according to a second preferred embodiment of the present invention. [Figure 6] FIG. 10 is a cross-sectional view of a capacitor component according to a third preferred embodiment of the present invention. [Figure 7] FIG. 10 is a cross-sectional view of a capacitor component according to a fourth preferred embodiment of the present invention. [Figure 8] 1 is a cross-sectional view of an integrated circuit chip package according to a preferred embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0018] The following merely exemplifies the principles of the present invention. Accordingly, those skilled in the art will be able to embody the principles of the invention and invent various devices that fall within the concept and scope of the invention, even if not explicitly described or shown herein. Furthermore, all conditional terms and embodiments listed herein are expressly intended, in principle, only for the purpose of enabling the concept of the invention to be understood, and should not be understood as being limited to the embodiments and conditions specifically listed in this specification.

[0019] The above objects, features, and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, which will enable those skilled in the art to easily implement the technical ideas of the invention.

[0020] The embodiments described herein will be explained with reference to cross-sectional views and / or perspective views that are idealized exemplary views of the present invention. The thicknesses of films and regions shown in these drawings are exaggerated for the purpose of effectively explaining the technical content. The shapes of the exemplary views may vary due to manufacturing techniques and / or tolerances. Furthermore, the number of molded objects shown in the drawings is only a partial illustration. Therefore, the embodiments of the present invention are not limited to the specific shapes shown in the drawings, and also include changes in shapes that occur during the manufacturing process.

[0021] Capacitor component 100 according to the first embodiment First, a capacitor component 100 according to a first preferred embodiment of the present invention will be described.

[0022] FIG. 1 is a perspective view including a partially cut-away portion of a capacitor component according to a first preferred embodiment of the present invention, FIG. 2 is a cross-sectional view of a capacitor component according to a first preferred embodiment of the present invention, FIG. 3 is a perspective view of an anodized film body, and FIGS. 4a to 4b are diagrams for explaining a method for manufacturing a capacitor component according to a first preferred embodiment of the present invention.

[0023] 1 and 2, a capacitor component 100 includes an anodized body 140, a first electrode layer 110, a dielectric layer 120, and a second electrode layer .

[0024] The anodized film body 140 refers to a film formed by anodizing the base metal M, and the pores P refer to holes formed in the process of anodizing the base metal M to form an anodized film. For example, if the base metal M is aluminum (Al) or an aluminum alloy, an anodized film made of aluminum oxide (Al2O3) is formed on the surface of the base metal M when the base metal M is anodized. However, the base metal M is not limited to these and may include Ta, Nb, Ti, Zr, Hf, Zn, W, Sb, or alloys thereof.

[0025] After anodization, the base metal M is removed, leaving only the anodized film body 140 made of aluminum oxide (Al2O3). The barrier layer is then removed, opening the pores P at the top and bottom. The anodized film body 140 has a plurality of pores P, each having a length of 20 μm to 200 μm and a diameter of 10 nm to 1 μm. The pitch between adjacent pores P is 20 nm to 200 nm. A preferred embodiment of the present invention uses these pores P to significantly improve the capacitance per unit volume of the capacitor component 100.

[0026] The first electrode layer 110 includes a first surface electrode portion 111 formed on the surface of the anodized film body 140, and a first pore electrode portion 113 formed on the inner walls of the pores P. The first surface electrode portion 111 is a portion of the first electrode layer 110 formed on the surface side of the anodized film body 140, and the first pore electrode portion 113 is a portion of the first electrode layer 110 formed on the inner wall side of the pores P. The first surface electrode portion 111 is formed entirely along the surface of the anodized film body 140. The first pore electrode portion 113 is formed along the inner walls of the pores P.

[0027] The first electrode layer 110 may be composed of a metal film made of a first metal, a metal oxide film containing the first metal, a metal nitride film containing the first metal, a metal oxynitride film containing the first metal, or a combination thereof. The first metal may be Ti, Co, Nb, or Sn. In an exemplary embodiment, the first electrode layer 110 may include Ti, Ti oxide, Ti nitride, Ti oxynitride, Co, Co oxide, Co nitride, Co oxynitride, Nb, Nb oxide, Nb nitride, Nb oxynitride, Sn, Sn oxide, Sn nitride, Sn oxynitride, or a combination thereof. For example, the first electrode layer 110 may be composed of TiN, CoN, NbN, SnO2, or a combination thereof.

[0028] The dielectric layer 120 includes a surface dielectric portion 121 formed on the first surface electrode portion 111, and a pore dielectric portion 123 formed on the first pore electrode portion 113. The surface dielectric portion 121 is a portion of the dielectric layer 120 formed on the surface side of the anodized film body 140, and the pore dielectric portion 123 is a portion of the dielectric layer 120 formed on the inner wall side of the pore P. The surface dielectric portion 121 is formed along the surface of the first surface electrode portion 111, and the pore dielectric portion 123 is formed along the surface of the first pore electrode portion 113.

[0029] The dielectric layer 120 can be made of a metal oxide film containing a second metal, which can be Hf, Zr, Nb, Ce, or Ti. In an exemplary embodiment, the dielectric layer 120 can be made of Al2O3, ZrO2, HfO2, Nb2O5, CeO2, or TiO2.

[0030] The second electrode layer 130 includes a second surface electrode portion 131 formed on the surface dielectric portion 121, and a second pore electrode portion 133 formed on the pore dielectric portion 123. The second surface electrode portion 131 is a portion of the second electrode layer 130 formed on the surface side of the anodized film body 140, and the second pore electrode portion 133 is a portion of the second electrode layer 130 formed on the inner wall side of the pore P. The second surface electrode portion 131 is formed along the surface of the surface dielectric portion 121, and the second pore electrode portion 133 is formed along the surface of the pore dielectric portion 123.

[0031] The second electrode layer 130 can be composed of a metal film made of a first metal, a metal oxide film containing the first metal, a metal nitride film containing the first metal, a metal oxynitride film containing the first metal, or a combination thereof. The first metal can be Ti, Co, Nb, or Sn. In an exemplary embodiment, the first electrode layer 110 can include Ti, Ti oxide, Ti nitride, Ti oxynitride, Co, Co oxide, Co nitride, Co oxynitride, Nb, Nb oxide, Nb nitride, Nb oxynitride, Sn, Sn oxide, Sn nitride, Sn oxynitride, or a combination thereof. For example, the first electrode layer 110 can be composed of TiN, CoN, NbN, SnO2, or a combination thereof.

[0032] The capacitor component 100 according to the present invention has a capacitor structure formed by the first surface electrode portion 111, the surface dielectric portion 121, and the second surface electrode portion 131 provided on the surface side of the anodized film body 140, and an additional capacitor structure formed through the configuration of the first pore electrode portion 113, the pore dielectric portion 123, and the second pore electrode portion 133 provided on the inside side of the pore P, thereby significantly improving the capacitance per unit volume.

[0033] On the other hand, the first pore electrode portion 113 is formed only on a part of the inner wall of the pore P. In other words, the first pore electrode portion 113 does not cover the entire inner wall of the pore P, but only a part of it. More specifically, the part of the inner wall of the pore P that is not covered by the first pore electrode portion 113 is the center of the inner wall of the pore P.

[0034] The pore dielectric portion 123 is formed only on a part of the inner wall of the first pore electrode portion 113. In other words, the pore dielectric portion 123 does not cover the entire inner wall of the first pore electrode portion 113, but only a part of it.

[0035] The second pore electrode portion 133 is formed only on a part of the inner wall of the pore dielectric portion 123. In other words, the second pore electrode portion 133 does not cover the entire inner wall of the pore dielectric portion 123, but only a part of it.

[0036] The depth of the pore dielectric portion 123 inside the pore P is shallower than the depth of the first pore electrode portion 113 and deeper than the depth of the second pore electrode portion 133 .

[0037] Referring to FIG. 2, the first electrode layer 110 includes a first upper electrode layer 110a and a first lower electrode layer 110b.

[0038] The first upper electrode layer 110a includes a first upper surface electrode portion 111a formed on the upper surface of the anodic oxide film body 140 and a first upper pore electrode portion 113a formed on a part of the upper inner wall of the pore P.

[0039] The first lower electrode layer 110b includes a first lower surface electrode portion 111b formed on the lower surface of the anodic oxide film body 140 and a first lower pore electrode portion 113b formed on a part of the lower inner wall of the pore P.

[0040] The dielectric layer 120 includes an upper dielectric layer 120a and a lower dielectric layer 120b.

[0041] The upper dielectric layer 120a includes an upper surface dielectric portion 121a formed on the first upper surface electrode portion 111a and an upper pore dielectric portion 123a formed on the first upper pore electrode portion 113a.

[0042] The lower dielectric layer 120b includes a lower surface dielectric portion 121b formed on the first lower surface electrode portion 111b and a lower pore dielectric portion 123b formed on the first lower pore electrode portion 113b.

[0043] The second electrode layer 130 includes a second upper electrode layer 130a and a second lower electrode layer 130b.

[0044] The second upper electrode layer 130a includes a second upper surface electrode portion 131a formed on the upper surface dielectric portion 121a and a second upper pore electrode portion 133a formed on the upper pore dielectric portion 123a.

[0045] The second lower electrode layer 130b includes a second lower surface electrode portion 131b formed on the lower surface dielectric portion 121b and a second lower pore electrode portion 133b formed on the lower pore dielectric portion 123b.

[0046] The first upper pore electrode portion 113a and the first lower pore electrode portion 113b are spaced apart from each other.

[0047] The upper and lower pore dielectric portions 123a and 123b are spaced apart from each other.

[0048] The second upper pore electrode portion 133a and the second lower pore electrode portion 133b are spaced apart from each other.

[0049] Based on the anodized film body 140, a first upper electrode layer 110a, an upper dielectric layer 120a, and a second upper electrode layer 130a are provided on the upper side, and a first lower electrode layer 110b, a lower dielectric layer 120b, and a second lower electrode layer 130b are provided on the lower side, thereby forming two capacitor structures on both sides of the anodized film body 140. These two capacitor structures can be connected in series or in parallel depending on the manner in which the terminals are connected. When a first terminal (not shown) connects the first upper electrode layer 110a and the first lower electrode layer 110b to each other and a second terminal (not shown) connects the second upper electrode layer 130a and the second lower electrode layer 130b to each other, the two capacitor structures are connected in parallel. On the other hand, when a first terminal (not shown) is connected to one of the first upper electrode layer 110a and the second upper electrode layer 130a, and a second terminal (not shown) is connected to one of the first lower electrode layer 110b and the second lower electrode layer 130b, and the remaining one of the first upper electrode layer 110a and the second upper electrode layer 130a is connected to the remaining one of the first lower electrode layer 110b and the second lower electrode layer 130b, the two capacitor structures are connected in series.

[0050] 3 to 4d, a method for manufacturing the capacitor component 100 according to the first preferred embodiment of the present invention will be described below. In the following description of the manufacturing method, the configuration of the capacitor component 100 according to the first embodiment may become clearer.

[0051] The manufacturing method of the capacitor component 100 according to the first embodiment includes the steps of (i) providing an anodized film body 140, (ii) forming a first electrode layer 110 on the surface of the anodized film body 140 and in the pores P, (iii) forming a dielectric layer 120 on the surface of the first electrode layer 110, and (iv) forming a second electrode layer 130 on the surface of the dielectric layer 120.

[0052] First, the step of (i) providing an anodized oxide film body 140 is performed.

[0053] FIG. 3 is a perspective view of the anodized film body 140, and FIG. 4a is a cross-sectional view of the anodized film body 140. As shown in FIG.

[0054] The anodized film body 140 refers to a film formed by anodizing the base metal M, and the pores P refer to holes formed during the process of anodizing the base metal M to form the anodized film. For example, if the base metal M is aluminum (Al) or an aluminum alloy, an anodized film made of aluminum oxide Al2O3 is formed on the surface of the base metal M when the base metal M is anodized. However, the base metal M is not limited to this and may include Ta, Nb, Ti, Zr, Hf, Zn, W, Sb, or alloys thereof. The anodized film formed as described above is vertically divided into a barrier layer without pores P formed therein and a porous layer with pores P formed therein.

[0055] After anodization, the base metal M is removed, leaving only the anodized film body 140 made of aluminum oxide (Al2O3). The barrier layer is then removed to open the top and bottom of the pores P. The pores P have a length of 1 μm to 200 μm and a diameter of 10 nm to 1 μm. The pitch between adjacent pores P is 20 nm to 200 nm.

[0056] In the present invention, the pores P of the anodic oxide film body 140 are used, eliminating the need for a separate step of forming through-holes. The anodic oxide film has a thermal expansion coefficient of 2 to 3 ppm / °C. This means that there is little thermal deformation due to temperature, even in high-temperature environments.

[0057] Next, (ii) a step of forming a first electrode layer 110 on the surface of the anodized film body 140 and in the pores P is performed.

[0058] 4b, a first electrode layer 110 is formed on the anodic oxide film body 140. The first electrode layer 110 can be formed through a deposition process (CVD, PVD, ALD) and can be formed to a thickness of 1 nm to 100 nm.

[0059] The first electrode layer 110 includes a first surface electrode portion 111 formed on the surface of the anodized film body 140, and a first pore electrode portion 113 formed on the inner wall of the pore P. The first pore electrode portion 113 is formed only on a part of the inner wall of the pore P.

[0060] Next, (iii) a step of forming a dielectric layer 120 on the surface of the first electrode layer 110 is performed.

[0061] 4c, a dielectric layer 120 is formed on the surface of the first electrode layer 110. The dielectric layer 120 can be formed through a deposition process (CVD, PVD, ALD) and can be formed to a thickness of 1 nm to 100 nm.

[0062] The dielectric layer 120 includes a surface dielectric portion 121 formed on the first surface electrode portion 111 and a pore dielectric portion 123 formed on the first pore electrode portion 113. The pore dielectric portion 123 is formed only on a portion of the inner wall of the first pore electrode portion 113. Therefore, the depth of the pore dielectric portion 123 is thinner than the depth of the first pore electrode portion 113.

[0063] Next, (iv) a step of forming a second electrode layer 130 on the surface of the dielectric layer 120 is performed.

[0064] 4d, a second electrode layer 130 is formed on the surface of the dielectric layer 120. The second electrode layer 130 can be formed through a deposition process (CVD, PVD, ALD), and can be formed to a thickness of 1 nm to 100 nm.

[0065] The second electrode layer 130 includes a second surface electrode portion 131 formed on the surface dielectric portion 121 and a second pore electrode portion 133 formed on the pore dielectric portion 123. The second pore electrode portion 133 is formed only on a portion of the inner wall of the pore dielectric portion 123. Therefore, the depth of the second pore electrode portion 133 is shallower than the depth of the pore dielectric portion 123.

[0066] The capacitor component 100 is fabricated through the above-described series of processes. However, the pores P may still have spaces even after the second electrode layer 130 is formed. If spaces are still present in the pores P after the second electrode layer 130 is formed, the spaces can provide room for thermal expansion of the first electrode layer 110, the dielectric layer 120, and the second electrode layer 130, and the capacitor component 100 can also be cooled by air cooling through the spaces. Meanwhile, after the second electrode layer 130 is formed, the spaces in the pores P can be filled with a functional material. Here, the functional material can be a metal material or an insulating material.

[0067] Capacitor component 100 according to the second embodiment Next, a second embodiment of the present invention will be described. However, the following description will focus on the distinctive components compared to the first embodiment, and a description of the same or similar components as the first embodiment will be omitted.

[0068] FIG. 5 is a cross-sectional view of a capacitor component 100 according to a second preferred embodiment of the present invention.

[0069] The capacitor component 100 according to the second embodiment differs from the first embodiment in that the first electrode layer 110, the dielectric layer 120, and the second electrode layer 130 are formed on only one side of the anodized film body 140, in that the first electrode layer 110, the dielectric layer 120, and the second electrode layer 130 are formed on both sides, but the remaining configuration is the same.

[0070] Capacitor component 100 according to the third embodiment Next, a third embodiment of the present invention will be described. The following description will focus on the distinctive components compared to the first embodiment, but will omit a description of components that are the same as or similar to those of the first embodiment.

[0071] FIG. 6 is a cross-sectional view of a capacitor component 100 according to a third preferred embodiment of the present invention.

[0072] The capacitor component 100 according to the third embodiment differs from the first embodiment in that the first upper pore electrode portion 113a and the first lower pore electrode portion 113b are connected to each other, in that the first upper pore electrode portion 113a and the first lower pore electrode portion 113b are spaced apart from each other, but the remaining configuration is the same.

[0073] The first upper electrode layer 110a includes a first upper surface electrode portion 111a formed on the upper surface of the anodized film body 140 and a first upper pore electrode portion 113a formed on a part of the upper inner wall of the pore P. The first lower electrode layer 110b includes a first lower surface electrode portion 111b formed on the lower surface of the anodized film body 140 and a first lower pore electrode portion 113b formed on a part of the lower inner wall of the pore P.

[0074] The dielectric layer 120 includes an upper dielectric layer 120a and a lower dielectric layer 120b. The upper dielectric layer 120a includes an upper surface dielectric portion 121a formed on the first upper surface electrode portion 111a and an upper pore dielectric portion 123a formed on the first upper pore electrode portion 113a. The lower dielectric layer 120b includes a lower surface dielectric portion 121b formed on the first lower surface electrode portion 111b and a lower pore dielectric portion 123b formed on the first lower pore electrode portion 113b.

[0075] The second electrode layer 130 includes a second upper electrode layer 130a and a second lower electrode layer 130b. The second upper electrode layer 130a includes a second upper surface electrode portion 131a formed on the upper surface dielectric portion 121a and a second upper pore electrode portion 133a formed on the upper pore dielectric portion 123a. The second lower electrode layer 130b includes a second lower surface electrode portion 131b formed on the lower surface dielectric portion 121b and a second lower pore electrode portion 133b formed on the lower pore dielectric portion 123b.

[0076] The first upper pore electrode portion 113a and the first lower pore electrode portion 113b are connected to each other. The first upper pore electrode portion 113a and the first lower pore electrode portion 113b cover the inner wall of the pore P entirely.

[0077] The upper pore dielectric portion 123a and the lower pore dielectric portion 123b are spaced apart from each other, and the second upper pore electrode portion 133a and the second lower pore electrode portion 133b are spaced apart from each other.

[0078] Capacitor component 100 according to the fourth embodiment Next, a fourth embodiment of the present invention will be described. The following description will focus on distinctive components compared to the first embodiment, but will omit a description of components that are the same as or similar to those of the first embodiment.

[0079] FIG. 7 is a cross-sectional view of a capacitor component 100 according to a fourth preferred embodiment of the present invention.

[0080] The capacitor component 100 according to the fourth embodiment differs from the configuration of the first embodiment in that the first upper pore electrode portion 113a and the first lower pore electrode portion 113b are connected to each other and the upper pore dielectric portion 123a and the lower pore dielectric portion 123b are connected to each other, in that the first upper pore electrode portion 113a and the first lower pore electrode portion 113b are spaced apart and the upper pore dielectric portion 123a and the lower pore dielectric portion 123b are spaced apart; the remaining configuration is the same.

[0081] The first upper electrode layer 110a includes a first upper surface electrode portion 111a formed on the upper surface of the anodized film body 140 and a first upper pore electrode portion 113a formed on a part of the upper inner wall of the pore P. The first lower electrode layer 110b includes a first lower surface electrode portion 111b formed on the lower surface of the anodized film body 140 and a first lower pore electrode portion 113b formed on a part of the lower inner wall of the pore P.

[0082] The dielectric layer 120 includes an upper dielectric layer 120a and a lower dielectric layer 120b. The upper dielectric layer 120a includes an upper surface dielectric portion 121a formed on the first upper surface electrode portion 111a and an upper pore dielectric portion 123a formed on the first upper pore electrode portion 113a. The lower dielectric layer 120b includes a lower surface dielectric portion 121b formed on the first lower surface electrode portion 111b and a lower pore dielectric portion 123b formed on the first lower pore electrode portion 113b.

[0083] The second electrode layer 130 includes a second upper electrode layer 130a and a second lower electrode layer 130b. The second upper electrode layer 130a includes a second upper surface electrode portion 131a formed on the upper surface dielectric portion 121a and a second upper pore electrode portion 133a formed on the upper pore dielectric portion 123a. The second lower electrode layer 130b includes a second lower surface electrode portion 131b formed on the lower surface dielectric portion 121b and a second lower pore electrode portion 133b formed on the lower pore dielectric portion 123b.

[0084] The first upper pore electrode portion 113a and the first lower pore electrode portion 113b are connected to each other. The first upper pore electrode portion 113a and the first lower pore electrode portion 113b cover the inner wall of the pore P entirely.

[0085] The upper pore dielectric portion 123a and the lower pore dielectric portion 123b are connected to each other, and the upper pore dielectric portion 123a and the lower pore dielectric portion 123b entirely cover the first upper pore electrode portion 113a and the first lower pore electrode portion 113b.

[0086] The second upper pore electrode portion 133a and the second lower pore electrode portion 133b are spaced apart from each other.

[0087] Integrated Circuit Chip Packages(1000) FIG. 8 is a cross-sectional view of an integrated circuit chip package 1000 incorporating a capacitor component 100 according to a preferred embodiment of the present invention.

[0088] An integrated circuit chip package 1000 according to a preferred embodiment of the present invention includes a package substrate 1300, a semiconductor chip 1200 mounted on the package substrate 1300, a molding part 1100 that protects the semiconductor chip 1200, and a capacitor component 100 provided in or on the package substrate 1300.

[0089] The semiconductor chip 1200 may be a logic chip including a logic circuit. The logic chip may be a controller that controls a memory chip. In another exemplary embodiment, the semiconductor chip 1200 may be a memory chip. The memory chip may include various forms of memory circuits. The memory circuit may be dynamic random access memory (DRAM), static RAM (SRAM), ferromagnetic RAM (FRAM), phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), read only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable ROM (EPROM), electrically erasable ROM (EEPROM), or a combination thereof.

[0090] The package substrate 1300 may include a plurality of wiring layers 1310 configured to be electrically connected to a plurality of chip pads 1210 included in the semiconductor chip 1200, and an insulating film 1320 for selectively insulating adjacent wiring layers 1310 among the plurality of wiring layers 1310. The plurality of wiring layers 1310 included in the package substrate 1300 may include Al, Cu, Sn, Ni, Au, Pt, or an alloy thereof. A plurality of external connection members 1600 may be connected to the package substrate 1300.

[0091] The package substrate 1300 includes a capacitor component 100. The capacitor component 100 may be configured to be electrically connectable to some of the chip pads 1210 included in the semiconductor chip 1200, or some of the wiring layers 1310 selected from among a plurality of wiring layers 1310 included in the package substrate 1300. The capacitor component 100 may include any one selected from the capacitor components 100 according to the first to third embodiments and capacitor components 100 having various structures modified and changed therefrom within the technical spirit of the present invention.

[0092] Although the present invention has been described above with reference to preferred embodiments thereof, those skilled in the art may implement the present invention in various modified or altered forms without departing from the spirit and scope of the present invention as set forth in the following claims. [Explanation of symbols]

[0093] 100 Capacitor parts 110 1st electrode layer 120 Dielectric layer 130 Second electrode layer 140 Anodized Body

Claims

1. an anodized film body having a plurality of pores; a first electrode layer having first surface electrode portions formed on the surface of the body and first pore electrode portions formed on the inner walls of the pores; a dielectric layer having a surface dielectric portion formed on the first surface electrode portion and a pore dielectric portion formed on the first pore electrode portion; a second electrode layer having a second surface electrode portion formed on the surface dielectric portion and a second pore electrode portion formed on the pore dielectric portion.

2. The capacitor component according to claim 1 , wherein the first pore electrode portion is formed only on a part of the inner wall of the pore.

3. The capacitor component according to claim 1 , wherein the first pore electrode portion is formed on the entire inner wall of the pore.

4. 2. The capacitor component according to claim 1, wherein a depth of the pore dielectric portion within the pore is less than a depth of the first pore electrode portion and greater than a depth of the second pore electrode portion.

5. an anodized film body having a plurality of pores; a first upper electrode layer having a first upper surface electrode portion formed on an upper surface of the body and a first upper pore electrode portion formed on a portion of an upper inner wall of the pore; an upper dielectric layer having an upper surface dielectric portion formed on the first upper surface electrode portion and an upper pore dielectric portion formed on the first upper pore electrode portion; a second upper electrode layer having a second upper surface electrode portion formed on the upper surface dielectric portion and a second upper pore electrode portion formed on the upper pore dielectric portion; a first lower electrode layer having a first lower surface electrode portion formed on a lower surface of the body and a first lower pore electrode portion formed on a part of a lower inner wall of the pore; a lower dielectric layer having a lower surface dielectric portion formed on the first lower surface electrode portion and a lower pore dielectric portion formed on the first lower pore electrode portion; a second lower electrode layer having a second lower surface electrode portion formed on the lower surface dielectric portion and a second lower pore electrode portion formed on the lower pore dielectric portion.

6. The capacitor component of claim 5 , wherein the first upper pore electrode portion and the first lower pore electrode portion are spaced apart from each other.

7. The capacitor component of claim 5 , wherein the upper pore dielectric portion and the lower pore dielectric portion are spaced apart from each other.

8. The capacitor component of claim 5 , wherein the second upper pore electrode portion and the second lower pore electrode portion are spaced apart from each other.

9. A package substrate; a semiconductor chip mounted on the package substrate; a molding part for protecting the semiconductor chip; a capacitor component provided in or on the package substrate, The capacitor component is an anodized film body having a plurality of pores; a first electrode layer having first surface electrode portions formed on the surface of the body and first pore electrode portions formed on the inner walls of the pores; a dielectric layer having a surface dielectric portion formed on the first surface electrode portion and a pore dielectric portion formed on the first pore electrode portion; a second electrode layer having a second surface electrode portion formed on the surface dielectric portion and a second pore electrode portion formed on the pore dielectric portion.

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